Semiconductor device

Abstract

To provide a semiconductor device which achieves microfabrication while suppressing defects. A semiconductor device which achieves miniaturization while maintaining favorable characteristics is provided.SOLUTION: Forming a first resist mask over the first conductive layer using light having wavelengths shorter than or equal to that of 365nm, etching the first conductive layer using the first resist mask to form a second conductive layer having a depressed portion, reducing the size of the first resist mask to form a second resist mask, and etching the second conductive layer using the second resist mask to form source and drain electrodes each having a projecting portion at its periphery, the projecting portion having a tapered shape; A gate insulating layer which is in contact with part of the semiconductor layer is formed over the source electrode and the drain electrode, and a gate electrode is formed over the gate insulating layer so as to overlap with the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of the disclosed invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in such electronic devices. Silicon-based semiconductor materials, oxide semiconductors, etc. are known.

[0003] To achieve faster transistor operation, transistor miniaturization is required. For example, Patent Document 1 describes an oxide semiconductor with a channel layer thickness of about 10 nm or less. Non-Patent Document 1 discloses a thin film transistor using a GaN-based thin film transistor having a channel length of 2 μm to 100 μm. A thin film transistor using an oxide semiconductor having a conductivity of m is disclosed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-21170 [Non-patent literature]

[0005] [Non-Patent Document 1] T. Kawamura, H. Uchiyama, S. Saito, H. Wakana, T. Mine, and M. Hatano, "Low-Voltage Operating Amorphous Oxide TFTs", IDW'09, p. 1689-1692. Summary of the Invention [Problem to be solved by the invention]

[0006] When miniaturizing transistors, defects that occur during the manufacturing process become a major problem. For example, a semiconductor layer of a transistor is formed on wiring such as a source electrode, a drain electrode, or a gate electrode. When forming a semiconductor layer or a gate insulating layer, the wiring has a thickness larger than that of the semiconductor layer. Therefore, as the film thickness of the semiconductor layer or gate insulating layer decreases with miniaturization, This can reduce the coverage of the insulation layer, resulting in disconnections and poor connections.

[0007] In particular, when fabricating fine transistors with short channel lengths (L), the resolution of the pattern is important. To improve the efficiency, light sources for photolithography with wavelengths below i-line (365 nm) are being developed. It is preferable to use short light. However, the i-line is not used as a light source for photolithography. When using this light, the pattern is smaller than when using light with a longer wavelength such as g-line (436 nm). Since it is difficult to form the end of the wiring in a tapered shape, the coating of the thin film formed on the wiring is poor. It is easy to decrease.

[0008] In view of the above, one embodiment of the disclosed invention aims to provide a miniaturized semiconductor device while suppressing defects. Another object of the present invention is to provide a semiconductor device that achieves miniaturization while maintaining good characteristics. It is one of the targets. [Means for solving the problem]

[0009] The semiconductor device according to one embodiment of the present invention includes a wiring (a gate electrode, a source electrode, or a drain electrode) having a large thickness. In the fabrication of the wiring, a protrusion is provided on the periphery of the conductive layer. Chipping, shrinking the resist mask, and etching using the reduced resist mask. In this case, when light with a short wavelength of 365 nm or less is used as the light source for photolithography, Even if the wiring is made of a thin film, the periphery of the wiring can be tapered. The configuration can be adopted.

[0010] One embodiment of the present invention is a method for forming a semiconductor layer, and forming a first conductive layer made of a single layer over the semiconductor layer. A first resist mask is formed on the first conductive layer using light having a wavelength of 365 nm or less. The first conductive layer is etched using the first resist mask to form a second conductive layer having a recess. The first resist mask is reduced to form a second resist mask. The second conductive layer is etched using a resist mask to form a protrusion at the periphery. The source electrode and the drain electrode are formed in a tapered shape. A gate insulating layer is formed on the semiconductor layer so as to be in contact with a part of the semiconductor layer, and the gate insulating layer is overlapped with the semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device, in which a gate electrode is formed at a position corresponding to the gate electrode.

[0011] In one embodiment of the present invention, a first conductive layer is formed, and a thin film having a thickness of 365 nm or less is formed on the first conductive layer. A first resist mask is formed using light of a wavelength, and a first The conductive layer is etched to form a second conductive layer having a recess, and the first resist mask is removed. The second resist mask is formed by reducing the thickness of the second conductive layer. The source electrode and the semiconductor substrate are etched to form a protrusion at the periphery, the protrusion having a tapered shape. A drain electrode is formed, a semiconductor layer is formed on the source electrode and the drain electrode, and the semiconductor layer A gate insulating layer is formed on the semiconductor layer, and a gate electrode is formed on the gate insulating layer at a position where it overlaps with the semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device.

[0012] In the above-described method for manufacturing a semiconductor device, an oxide semiconductor layer is preferably used as the semiconductor layer. I wish.

[0013] Another embodiment of the present invention is a semiconductor layer including at least a channel formation region, a source electrode and a drain electrode each of which is a single layer and is in contact with a part of the a gate insulating layer provided on the gate electrode and in contact with the channel forming region; The channel length of the channel forming region is 2 μm. The source electrode and the drain electrode each have a protrusion on the periphery, and the protrusion is The semiconductor device has a rectangular shape.

[0014] In the semiconductor device, the gate insulating layer has a protruding portion that is in contact with the source The gate electrode and drain electrode may be in contact with each other.

[0015] Alternatively, in the semiconductor device, the semiconductor layer is a source voltage source at least in the protruding portion. The source electrode and drain electrode may be in contact with each other.

[0016] In any of the above semiconductor devices, the protrusion of the source electrode is It may have the same width and thickness as the protrusions on the poles.

[0017] Another embodiment of the present invention is a gate electrode having a single layer and a gate insulating film provided on and in contact with the gate electrode. and a gate insulating layer formed thereon, and at least a channel forming region. a semiconductor layer overlapping the electrode, and a source electrode and a drain electrode each in contact with a part of the semiconductor layer; and the length of the channel forming region in the direction in which carriers flow is less than 2 μm. The gate electrode has a protruding portion on its periphery, and the protruding portion is tapered.

[0018] In the semiconductor device, the gate insulating layer has a gate insulating layer at least at the protruding portion. It may be in contact with an electrode.

[0019] In any of the above semiconductor devices, the semiconductor layer is preferably an oxide semiconductor layer. I wish.

[0020] Here, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. A display device, a memory device, an integrated circuit, and the like can be included in the semiconductor device.

[0021] In this specification, the terms "above" and "below" are used to indicate that the positional relationship of a component is "directly above" or It is not limited to "directly under" the gate electrode. For example, "a gate electrode on a gate insulating layer" If the expression is, it excludes those that include other components between the gate insulating layer and the gate electrode. do not have.

[0022] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the term "electrode" or "wire" may be used to refer to the plural "electrodes" or "wires." " is also included when they are integrally formed.

[0023] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0024] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0025] In this specification, the term "same" is used to mean that the final result does not change significantly. This includes reasonable deviations that may be slightly modified. For example, the thickness of a film formed in the same process The thickness of each film is the same, and variations in the film formation process are allowed. [Effects of the Invention]

[0026] According to one embodiment of the disclosed invention, it is possible to suppress defects or maintain good characteristics while forming fine Therefore, it is possible to provide a semiconductor device that achieves high efficiency.

[0027] According to one embodiment of the disclosed invention, problems associated with miniaturization can be solved, and as a result, As a result, it becomes possible to make the transistor size sufficiently small. By making the size of the semiconductor device sufficiently small, the area occupied by the semiconductor device can be reduced, and the semiconductor This increases the number of semiconductor devices produced, thereby reducing the manufacturing cost of semiconductor devices. In addition, the reduction of the channel length will have the effect of increasing the operating speed and reducing power consumption. It is also possible. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 2] 1A and 1B are a plan view and a cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 5] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 6] 10A to 10C are diagrams showing application examples of a semiconductor device. [Figure 7] 10A to 10C are diagrams showing application examples of a semiconductor device. [Figure 8] 10A to 10C are diagrams showing application examples of a semiconductor device. [Figure 9] 10A to 10C are diagrams illustrating electronic devices using semiconductor devices. [Figure 10] 5A to 5C are cross-sectional views showing the manufacturing process of a sample manufactured in an example. [Figure 11] 1 is a STEM photograph of a conductive layer produced in an example. DETAILED DESCRIPTION OF THE INVENTION

[0029] An example of an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications can be made to the above. The present invention should not be construed as being limited to the description of the embodiment. The configurations according to the embodiments can be combined as appropriate. In the configuration of the present invention, the same parts and parts having similar functions are designated by the same reference numerals, and their repetition The explanation of repetition will be omitted.

[0030] In addition, the position, size, range, etc. of each component shown in the drawings are not actual size for ease of understanding. The position, size, range, etc. may not be shown. Therefore, the disclosed invention may not necessarily be The position, size, range, etc. are not limited to those disclosed in the drawings, etc.

[0031] In this specification, ordinal numbers such as "first," "second," and "third" are used to indicate the composition of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0032] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the disclosed invention and a manufacturing method thereof will be described. This will be described with reference to the drawings.

[0033] <Configuration example of semiconductor device> 1 and 2 show examples of the configuration of a semiconductor device.

[0034] The semiconductor layer included in the transistor described in this embodiment is an amorphous Semiconductors, polycrystalline semiconductors, microcrystalline (semi-amorphous or microcrystalline) In the following, in this embodiment, a semiconductor layer and An example in which an oxide semiconductor layer is used as a transistor is shown. In addition, compared to amorphous silicon, the on-current and It is possible to improve the field effect mobility and suppress the deterioration of the transistor. This allows for a transistor that consumes less power and is capable of high-speed operation. However, the embodiment of the present invention is not limited to this.

[0035] 1A is a plan view of the transistor 160, and FIG. 1B is a plan view of the transistor 160 along line A in FIG. 1A. 1(C) is a cross-sectional view taken along line C1-D1 in FIG. FIG.

[0036] The transistor 160 shown in FIG. 1 has a channel forming region on a substrate 100 having a surface on which the transistor is to be formed. and a layer of the oxide semiconductor layer 144 including at least a region of the oxide semiconductor layer 144. The source electrode 142a and the drain electrode 142b are connected to each other. A gate insulating film is provided on the electrode 142b and is in contact with a channel formation region of the oxide semiconductor layer 144. The channel forming region of the oxide semiconductor layer 144 is formed by interposing the edge layer 146 and the gate insulating layer 146 therebetween. and a gate electrode 148 overlapping the source electrode 142a and the drain electrode 142. b has a step-like difference in the periphery.

[0037] An insulating layer may be provided so as to cover the gate electrode 148 and the like. It may be included as a component of register 160.

[0038] The channel length L of the transistor 160 is preferably less than 2 μm, and more preferably 10 nm or more. It is more preferable that the thickness is 350 nm (0.35 μm) or less. The thickness of the film is 1 nm or more and 50 nm or less, preferably 2 nm or more and 20 nm or less, and more preferably The size is set to 3nm or more and 15nm or less. This will realize high-speed and low-power semiconductor devices. will be done.

[0039] In the cross-sectional view of the transistor 160 in the channel length direction shown in FIG. 42a is a region in contact with the oxide semiconductor layer 144 and another region (a region in contact with the base 100) ) has a protruding portion 145a having a smaller film thickness than the other protruding portion 145a, and the protruding portion 145a has a tapered shape. Similarly, the drain electrode 142b has a region in contact with the oxide semiconductor layer 144. The protrusion 145b has a smaller thickness than the other area (the area in contact with the substrate 100). The protrusion 145b has a tapered shape. Each end of the step has a step-like shape, and the cross section of the step-like shape has a tapered shape. This can also be rephrased as "there is."

[0040] The protrusions 145a and 145b have a taper angle of, for example, 30° or more and 60° or less. The taper angle is defined as the angle at which a layer having a tapered shape (for example, a source electrode) The electrode 142a) was observed from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate 100). In this case, it indicates the inclination angle between the side and bottom surfaces of the layer.

[0041] Generally, the gate insulating layer of a top-gate transistor is connected to the source electrode and the drain electrode. In the region covering the end of the electrode, there is a step (coverage) due to the film thickness of the electrode, and the step In this region, the film thickness is locally smaller than in other regions. In a small region, the breakdown voltage is low, so the electric field is concentrated in that region, causing the transistor to break down. This may cause gate leakage from areas with a small film thickness. There is.

[0042] However, in the transistor 160 shown in FIG. The inner electrode 142b is provided with a protrusion 145a and a protrusion 145b having a small thickness on the periphery thereof. By gradually reducing the thickness of the peripheral film, the coverage of the gate insulating layer 146 is improved. This can prevent disconnection and poor connection. Therefore, it is possible to prevent the formation of a locally thin region. Improve the dielectric breakdown voltage of the transistor 160 and suppress the occurrence of gate leakage. can be done.

[0043] Furthermore, the thickness of the protrusion 145a of the source electrode 142a of the transistor 160 is Similarly, the thickness of the protrusion 145b of the drain electrode 142b is smaller than that of the other regions. That is, in the protrusions 145a and 145b, , the cross-sectional area perpendicular to the flow of charge is smaller. Since resistance is inversely proportional to the cross-sectional area, The protrusions 145a and 145b of the source electrode 142a and the drain electrode 142b The region b is a region with a high resistance compared to the other regions. The high-resistance region of the drain electrode 142a or the high-resistance region of the drain electrode 142b and the channel of the oxide semiconductor layer 144 By contacting the formation region, the electric field between the source and drain can be alleviated. The short channel effect that accompanies the reduction in transistor size can be suppressed.

[0044] Further, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144, or It is desirable that the water be highly purified by supplying sufficient oxygen. Specifically, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 Below Below, preferably 5 x 1018 atoms / cm 3 Less than or equal to 5×10 17 at oms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is determined by the secondary electron Secondary Ion Mass Spectros (SIMS) It is measured by the number of copies.

[0045] In this way, the hydrogen concentration is sufficiently reduced to achieve high purity, and oxygen deficiency is prevented by supplying sufficient oxygen. In the oxide semiconductor layer 144 in which defect levels in the energy gap due to depletion are reduced, The carrier concentration due to donors such as hydrogen is 1×10 12 / cm 3 Less than 1× 10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 It is less than. For example, the off-state current (here, the value per unit channel width (1 μm)) at room temperature (25°C) ) is 100zA (1zA (zeptoampere) is 1 x 10 -21 A) Below 10, preferably In this way, the i-type (intrinsic) or substantially i-type oxide semiconductor By using such a material, the transistor 160 can be provided with excellent off-state current characteristics. .

[0046] As disclosed in Non-Patent Document 1, etc., 19 / cm 3 When using an n-type oxide semiconductor with a large channel length of 2 μm to 100 μm, Although relatively large transistors can be realized, such materials are difficult to fabricate by miniaturization (transistor When used in transistors with channel lengths less than 2 μm, the threshold voltage is significantly reduced. Therefore, it becomes extremely difficult to realize a normally-off transistor. On the other hand, the carrier density of a highly purified, intrinsic, or substantially intrinsic oxide semiconductor is is at least 1 x 10 14 / cm 3 This is less than the problem of normally-on as mentioned above. Since no junction defects occur, it is possible to easily realize transistors with channel lengths of less than 2 μm. is.

[0047] The oxide semiconductor layer 144 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. The oxide semiconductor layer 144 is in a CAAC-OS (C Axis Aligned-Oxide) state. ed Crystalline Oxide Semiconductor) film is preferred.

[0048] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often sized to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image using a microscope, the boundary between the amorphous and crystalline parts in the CAAC-OS film was The grain boundaries in the CAAC-OS film were not clearly observed by TEM. Therefore, the CAAC-OS film is not affected by electron transfer due to grain boundaries. The decrease in mobility is suppressed.

[0049] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 10° to 5°.

[0050] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts near the surface may be higher than that near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0051] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0052] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0053] The transistor 162 shown in FIG. 2 is a variation of the transistor 160. 2A is a plan view of the transistor 162, and FIG. FIG. 2(B) is a cross-sectional view taken along line A2-B2 in FIG. 2(A). 2(A) is a cross-sectional view taken along line C2-D2.

[0054] The transistor 162 is formed on a substrate 100 having a surface on which the transistor is to be formed, and has a channel forming region. and a source region in contact with a part of the oxide semiconductor layer 144. The source electrode 142a and the drain electrode 142b are connected to the source electrode 142a and the drain electrode 142b. a gate insulating layer 146 provided on the oxide semiconductor layer 144 and in contact with a channel formation region of the oxide semiconductor layer 144; and overlaps with the channel formation region of the oxide semiconductor layer 144 with the gate insulating layer 146 interposed therebetween. The source electrode 142a and the drain electrode 142b are disposed at the periphery of the gate electrode 148. , has a step-like difference.

[0055] 1B, the cross-sectional view of the transistor 160 in the channel length direction is similar to that of FIG. In the cross-sectional view of the transistor 162 in the channel length direction shown in FIG. a is a region in contact with the lower surface of the oxide semiconductor layer 144 and a region other than the lower surface of the oxide semiconductor layer 14 4)))))))))))))))))))))))))))))))))))))))))))))))) Similarly, the drain electrode 142b is formed by the oxide semiconductor layer 144. The region in contact with the bottom surface has a larger thickness than the other region (the region not in contact with the oxide semiconductor layer 144). The protruding portion 145b has a small thickness and is tapered.

[0056] In addition, the source electrode 142a or the drain electrode 142b has a protrusion 145a or a protrusion at the periphery. 145b has a step-shaped step, so that the source electrode 142a and the drain electrode 14 The oxide semiconductor layer 144 provided on and in contact with 2b also has a step-like structure.

[0057] The channel length L of the transistor 162 is preferably less than 2 μm, and more preferably 10 nm or more. It is more preferable that the thickness is 350 nm (0.35 μm) or less. The thickness of the film is 1 nm or more and 50 nm or less, preferably 2 nm or more and 20 nm or less, and more preferably The size is set to 3nm or more and 15nm or less. This will realize high-speed and low-power semiconductor devices. will be done.

[0058] The difference between the transistor 162 in FIG. 2 and the transistor 160 in FIG. 1 is that In the transistor 160, the oxide semiconductor layer 144 The source electrode 142a and the drain electrode 142b are connected to a part of the upper surface and the side surface of the On the other hand, in the transistor 162, a part of the bottom surface of the oxide semiconductor layer 144 is in contact with the oxide semiconductor layer 144. They are in contact with the source electrode 142a and the drain electrode 142b, respectively.

[0059] In the transistor 162 shown in FIG. 2, the source electrode 142a and the drain electrode 142b The film thickness of the end portion is set to 145a and 145b. By reducing the thickness stepwise, the coverage of the oxide semiconductor layer 144 and the gate insulating layer 146 is improved. This can prevent disconnection and connection failure. 144 and the gate insulating layer 146, a region with a small thickness is formed locally. This can improve the breakdown voltage of the transistor 162 and The occurrence of gate leakage can be suppressed.

[0060] Furthermore, the thickness of the protrusion 145a of the source electrode 142a of the transistor 162 is Similarly, the thickness of the protrusion 145b of the drain electrode 142b is smaller than that of the other regions. , which is smaller than the other regions, the source electrode 142a and the drain electrode 142b The protruding portions 145a and 145b are regions with a higher resistance than the other regions. The transistor 162 has a high resistance region of the source electrode 142a or the drain electrode 142b. The oxide semiconductor layer 144 is in contact with the channel formation region of the oxide semiconductor layer 144. The electric field can be relaxed, suppressing the short channel effect that accompanies shrinking transistor size. It is possible.

[0061] <Example of transistor manufacturing process> An example of a manufacturing process of a transistor according to this embodiment will be described below with reference to FIGS. 3A to 3C and 4A to 4C. explain.

[0062] <Fabrication process of transistor 160> An example of a method for manufacturing the transistor 160 shown in FIGS. 1A and 1B will be described with reference to FIGS.

[0063] First, an oxide semiconductor layer is formed on a substrate 100 having a surface to be formed. The layer is processed to form the oxide semiconductor layer 144.

[0064] There is no particular limitation on the substrate that can be used for the base 100. It is necessary to have heat resistance to the extent that it can withstand heat treatment. For example, a glass substrate, Substrates such as ceramic substrates, quartz substrates, and sapphire substrates can be used. If it has an edge surface, it can be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor Substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can also be used. It is possible to provide a semiconductor element on the substrate. An undercoat film may be provided on the surface of the insulating film.

[0065] The oxide semiconductor layer 144 is made of at least one material selected from the group consisting of In, Ga, Sn, and Zn. For example, the oxide of a quaternary metal, In-Sn-Ga-Zn-O, is In-Ga-Zn-O oxide semiconductors, which are oxides of ternary metals, and In-S n-Zn-O based oxide semiconductor, In-Al-Zn-O based oxide semiconductor, Sn-Ga-Zn -O-based oxide semiconductors, Al-Ga-Zn-O-based oxide semiconductors, Sn-Al-Zn-O-based oxide semiconductors oxide semiconductors, binary metal oxides such as In-Zn-O oxide semiconductors, Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O based oxide semiconductors, In-Mg-O based oxide semiconductors, and In-Ga-O based materials materials, oxides of single-component metals such as In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, and Zn In addition, the above-mentioned oxide semiconductor may contain In and Ga. Elements other than Sn and Zn, such as SiO2, may also be included.

[0066] For example, the In-Ga-Zn-O oxide semiconductor is a semiconductor containing indium (In), gallium (Ga), and Zn. It means an oxide semiconductor containing Ga and Zn, and the composition ratio is not important. do not have.

[0067] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m A thin film expressed as (m>0) Here, M is one or more selected from Zn, Ga, Al, Mn and Co. For example, M may represent Ga, Ga and Al, Ga and Mn, or Examples of the elements include Ga and Co.

[0068] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, the composition of the target to be used The atomic ratio of In:Zn is 50:1 to 1:2 (converted to molar ratio, In2O3 In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of conversion, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn=1 5:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used to form an In-Zn-O based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0069] The filling rate of the target to be used is 90% or more and 100% or less, preferably 95% or more and 95% or less. The target with a high filling rate is 9.9% or less. This is because the body layer can be made into a dense membrane.

[0070] The thickness of the oxide semiconductor layer 144 is preferably greater than or equal to 3 nm and less than or equal to 30 nm. If the thickness of the compound semiconductor layer 144 is too large (for example, 50 nm or more), the transistor This is because there is a risk of the device becoming normally on.

[0071] The oxide semiconductor layer is formed by a method that is less likely to be contaminated with impurities such as hydrogen, water, hydroxyl groups, or hydrides. For example, it can be produced by sputtering.

[0072] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. In addition, the oxide semiconductor layer may be heated under a mixed atmosphere of hydrogen, water, and hydroxyl groups. To prevent contamination with impurities such as hydrogen, water, hydroxyl groups, and hydrides, It is desirable to use an atmosphere using a high purity gas that has been removed.

[0073] For example, the oxide semiconductor layer can be formed as follows.

[0074] First, the substrate is held in a film-forming chamber maintained under reduced pressure, and the substrate temperature is increased to 200°C for 5 minutes. 00°C or less, preferably more than 300°C and less than 500°C, more preferably more than 350°C and less than 400°C Heat to below 50°C.

[0075] Next, while removing the remaining moisture in the film-forming chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. A high-purity gas removed by the removal of the target was introduced into the chamber, and an oxide semiconductor layer was deposited on the substrate using the target. To remove residual moisture in the deposition chamber, a cryopump or Adsorption type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. It is also desirable that the exhaust means be a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump contains, for example, hydrogen, water, hydroxyl groups, or hydrogen. Because impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of impurities can be reduced.

[0076] When the substrate temperature during film formation is low (for example, 100°C or less), the oxide semiconductor contains hydrogen atoms. It is preferable to heat the substrate at the above-mentioned temperature because there is a risk of contamination with substances containing fluorine. By heating the substrate at the above temperature to form the oxide semiconductor layer, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, the oxide semiconductor layer is formed in a state where the substrate is heated to the above-mentioned temperature. By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be removed. It is possible to sufficiently reduce the concentration of substances. It is also possible to reduce damage caused by sputtering. This can be done.

[0077] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced. The powder adhering to the surface on which the oxide semiconductor layer is to be formed is removed by performing reverse sputtering to generate plasma. It is preferable to remove the particles or dust particles. This method involves applying a voltage to the plate, generating plasma near the substrate, and modifying the surface of the substrate. Instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0078] The oxide semiconductor layer is processed by forming a mask of a desired shape on the oxide semiconductor layer and then applying the mask to the oxide semiconductor layer. The mask can be used to etch the nitride semiconductor layer. It can be formed by using a method such as lithography, or an ink jet method. The mask may be formed by the following method. Etching or wet etching may be used. Of course, these may be used in combination. good.

[0079] In addition, the oxide semiconductor layer 144 (or the oxide semiconductor layer before being processed into islands) is subjected to a heat treatment. By performing the heat treatment, the oxide semiconductor layer 1 is The hydrogen-containing substances contained in 44 can be further removed. In an inert gas atmosphere, 250°C or higher and 700°C or lower, preferably 450°C or higher and 600°C or lower The inert gas atmosphere is nitrogen or rare gas (heterogeneous). The atmosphere is mainly composed of oxygen (sodium, neon, argon, etc.) and does not contain water, hydrogen, etc. For example, nitrogen, helium, or neon introduced into the heat treatment equipment should be used. The purity of rare gases such as argon and argon should be 6N (99.9999%) or higher, preferably 7N ( 99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm pm or less).

[0080] By performing heat treatment to reduce impurities, an oxide semiconductor layer is formed, and A transistor with excellent characteristics can be realized.

[0081] The above-mentioned heat treatment has the effect of removing hydrogen and water. This heat treatment can also be called hydration treatment or dehydrogenation treatment. It can also be performed before processing the semiconductor layer into islands or after forming the gate insulating film. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but also multiple times. good.

[0082] Next, a source electrode and a drain electrode (formed from the same layer as this) are formed on the oxide semiconductor layer 144. The conductive layer 140 for forming the wiring (including the wiring to be formed) is formed in a single layer structure (see FIG. 3(A)). (see).

[0083] The conductive layer 140 can be formed by using a PVD method or a CVD method. The 40 materials include aluminum, chromium, copper, tantalum, titanium, molybdenum, and titanium. An element selected from the group consisting of tin and an alloy containing the above elements can be used. Manganese, magnesium, zirconium, beryllium, neodymium, or scandium Alternatively, a combination of these materials may be used.

[0084] The conductive layer 140 may also be formed using a conductive metal oxide. The materials include indium oxide, tin oxide, zinc oxide, indium oxide tin oxide alloy, indium oxide Indium-zinc oxide alloys, or these metal oxide materials with silicon or silicon oxide It is possible to use a material containing fluorine.

[0085] Next, a resist mask 150a and a resist mask 150b are formed over the conductive layer 140. For example, after applying a resist onto the conductive layer 140, the resist is exposed to an exposure device. A photomask is placed on the resist, and light is projected onto the resist to expose it. The resist mask 150a and the resist mask 150b can be formed by the above method.

[0086] In order to form the channel length of the transistor 160 minutely, a light source of the exposure device is used, which has a wavelength of 3 Light of 65 nm or less can be used. For example, the i-line, which is the spectrum light of a high-pressure mercury lamp, (wavelength 365 nm), or KrF laser light (wavelength 248 nm) or ArF laser light (wavelength Preferably, light having a wavelength in the visible to ultraviolet region, such as 193 nm, can be used.

[0087] After forming the resist mask 150a and the resist mask 150b, the conductive layer is formed using the masks. Layer 140 is half-etched (i.e., etched while conductive layer 140 covers the substrate). The etching is stopped to form a conductive layer 141 having a recess.

[0088] Next, the resist mask 150a and the resist mask 150b are recessed (reduced). Then, a resist mask 152a and a resist mask 152b are formed (see FIG. 3C). To make the resist mask recede (shrink), ashing with oxygen plasma can be performed. By reducing (shrinking) the resist mask, part of the conductive layer 141 is exposed. .

[0089] Next, the conductive layer 141 is etched using the resist masks 152a and 152b. By etching, the source electrode 142a and the drain electrode 142b are formed (FIG. 3( Also, the conductive layer exposed from the resist mask 152a and the resist mask 152b is By etching a part of the conductive layer 141, the source electrode 142a and the drain electrode 14 2b are formed on the periphery thereof with protrusions 145a and 145b.

[0090] As mentioned above, miniaturized transistors (channel lengths less than 2 μm) were fabricated. When using a photolithography light source to improve the resolution of the pattern, It is preferable to use light with a short wavelength of 65 nm or less. When light of 365 nm or less is used for exposing a film, it is difficult to make the pattern end tapered. In the method for manufacturing a semiconductor device described in this embodiment mode, etching of a conductive layer is performed multiple times. By performing this process in several steps, the protrusions 11 of the source electrode 142a and the drain electrode 142b are 45a and protrusion 145b may be tapered.

[0091] The protrusion 145a of the source electrode 142a is the same as the protrusion 145a of the drain electrode 142b. It has the same width and thickness as the protruding portion 145b.

[0092] Next, the oxide semiconductor layer 144 is formed on the source electrode 142a and the drain electrode 142b. A gate insulating layer 146 is formed so as to contact a part of the gate insulating layer 146 .

[0093] The gate insulating layer 146 is formed using an oxide insulating layer from which part of oxygen is released by heating. As an oxide insulating layer from which part of oxygen is released by heating, it is preferable to use an oxide having a stoichiometric ratio of 0.1 to 0.2. It is preferable to use an oxide insulating layer containing more oxygen than the oxide insulating layer containing oxygen. The oxide insulating layer from which a part of the oxygen is released diffuses oxygen into the oxide semiconductor layer 144 by heating. An oxide insulating layer that can be used for the gate insulating layer 146 is typically Silicon oxide layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, oxide Using an aluminum nitride layer, a gallium oxide layer, a hafnium oxide layer, an yttrium oxide layer, etc. It is possible.

[0094] After the gate insulating layer 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 Oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen vacancies in the oxide semiconductor layer 144, thereby forming an i-type (intrinsic) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0095] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be performed. The second heat treatment may also serve as the first heat treatment.

[0096] As described above, the oxide semiconductor layer 144 is formed by the first heat treatment and the second heat treatment. The hydrogen atom-containing material can be highly purified so as to contain as few substances containing hydrogen atoms as possible.

[0097] Next, a conductive layer is formed to form the gate electrode (including the wiring formed in the same layer). The conductive layer is then processed to form a gate electrode 148 (see FIG. 3(E)).

[0098] The gate electrode 148 may be made of molybdenum, titanium, tantalum, tungsten, aluminum, or copper. It is made of metal materials such as neodymium and scandium, or alloy materials containing these as the main components. The gate electrode 148 may have a single layer structure or a multilayer structure. You can do that.

[0099] In this way, the transistor 160 is completed.

[0100] <Fabrication process of transistor 162> An example of a manufacturing process of the transistor 162 shown in FIG. 2 will be described with reference to FIG. The fabrication process of the transistor 162 is largely the same as that of the transistor 160 . Therefore, in the following, explanations of overlapping parts may be omitted.

[0101] First, a conductive layer 140 is formed on a substrate 100 having a surface to be formed (see FIG. 4(A)). .

[0102] Next, a resist mask 150a and a resist mask 150b are formed over the conductive layer 140. Then, the conductive layer 140 is half-etched using the mask (i.e., the conductive layer 140 is (The etching is stopped when layer 140 covers the substrate) to form conductive layer 141 having a recess. (See Figure 4(B)).

[0103] Next, the resist mask 150a and the resist mask 150b are recessed (reduced). Then, a resist mask 152a and a resist mask 152b are formed (see FIG. 4(C)). The conductive layer 141 is etched using the resist masks 152a and 152b. By this, the source electrode 142a having the protrusion 145a on the periphery and the source electrode 142b having the protrusion 145a on the periphery are formed. 5b and a drain electrode 142b (see FIG. 4(D)).

[0104] After the resist masks 152a and 152b are removed, the oxide semiconductor layer is The oxide semiconductor layer is then processed to form an island-shaped oxide semiconductor layer 144. Before forming the oxide semiconductor layer, plasma treatment using a gas such as N 2 O, N 2 , or Ar is performed. Water or the like adhering to the surface on which the oxide semiconductor layer is formed may be removed by this plasma treatment. The polishing process reduces the steps at the periphery of the source electrode 142a and the drain electrode 142b. Since the size can be reduced, the thickness of the source electrode 142a and the drain electrode 142b can be reduced. To further improve the coverage of the oxide semiconductor layer 144, the gate insulating layer 146, and the like to be deposited. In addition, if plasma treatment is performed, the product should not be exposed to the air after the plasma treatment. It is preferable to form an oxide semiconductor layer without using a gate insulating film.

[0105] Next, the oxide semiconductor layer 144 is formed on the source electrode 142a and the drain electrode 142b. Next, a gate insulating layer 146 is formed so as to contact a part of the gate electrode (the same as forming a conductive layer for forming a wiring (including a wiring formed by a layer), and processing the conductive layer; A gate electrode 148 is formed (see FIG. 4(E)).

[0106] In this way, the transistor 162 is completed.

[0107] The source electrode 142a and the drain electrode 142b of the transistor 160 and the transistor 162 are Although the poles 142b each have one protrusion, this is not a limiting embodiment of the present invention. It's not something like that.

[0108] For example, the recession (shrinkage) of the resist mask and the etching using the recessed (shrinkage) resist mask. By performing the etching process multiple times, a thick film is formed around the periphery of the source electrode 142a and the drain electrode 142b. However, a plurality of protruding portions having different film thicknesses may be formed in a stepped manner. When the step is formed, the nth step (n≧1, the protrusion with the smallest film thickness) of the source electrode 142a The protrusion of the nth step of the drain electrode 142b is the same as the protrusion of the nth step of the drain electrode 142b. The film thickness and width are the same. Note that the step shape also applies when multiple surfaces are connected by curved surfaces. In addition, when forming a plurality of protrusions with different film thicknesses, the thickness of each of the plurality of protrusions is Each preferably has a tapered shape.

[0109] Further, a protruding portion may be provided on the periphery of the gate electrode 148. By providing the portion, it is possible to improve the coverage of the insulating layer formed on the gate electrode 148. This allows the gate electrode 148 and the wiring provided on the gate electrode 148 to This prevents the concentration of an electric field in the insulating layer, which is caused by the deterioration of the transistor. However, if a protrusion is provided on the periphery of the gate electrode 148, the breakdown can be prevented. In this case, the gate electrode 148 is a single layer electrode selected from the above-mentioned materials.

[0110] This embodiment can also be applied to a bottom-gate transistor. 1 shows an example of the configuration of a Tom-gate transistor.

[0111] The transistor 170 shown in FIG. 5A includes a gate electrode 149 and a gate A gate insulating layer 146 is provided in contact with the electrode 149, and a gate insulating layer 148 is provided on the gate insulating layer 146. The source electrode 142a and the drain electrode 142b are connected to each other. The oxide film 142a is in contact with a part of the electrode 142b and overlaps with the gate electrode 149 via the gate insulating layer 146. and a compound semiconductor layer 144.

[0112] The channel length L of the transistor 170 is preferably less than 2 μm, and more preferably 10 nm or more. It is more preferable that the thickness is 350 nm (0.35 μm) or less. The thickness of the film is 1 nm or more and 50 nm or less, preferably 2 nm or more and 20 nm or less, and more preferably This will enable the development of semiconductor devices that can operate at high speeds and consume less power. The position is realized.

[0113] The transistor 172 shown in FIG. 5B includes a gate electrode 149 and a gate A gate insulating layer 146 is provided in contact with the electrode 149, and the gate insulating layer 146 is provided between the gate electrode 149 and the gate insulating layer 146. The oxide semiconductor layer 144 overlapping with the electrode 149 and the oxide semiconductor layer 144 contacting a part of the oxide semiconductor layer 144 are connected to each other. The semiconductor device has a source electrode 142a and a drain electrode 142b.

[0114] In the transistor 170 and the transistor 172, the gate electrode 149 is made of the above-mentioned material. and a protrusion 14 having a smaller thickness at the periphery than the other regions. This improves the coverage of the gate insulating layer 146 and prevents disconnection and poor connection. In addition, in the gate insulating layer 146, a region with a locally small film thickness can be prevented. Therefore, the formation of the transistor 170 and the transistor 1 72 dielectric breakdown voltage and suppress the occurrence of gate leakage. The protrusion 147 can be produced in the same manner as the protrusions 145a and 145b. Furthermore, a plurality of protruding portions having different film thicknesses may be formed in a stepped pattern.

[0115] The transistor 170 also has a source electrode 142a and a drain electrode 142b. The oxide semiconductor layer 14 has a protrusion 145a and a protrusion 145b. 4 can improve the covering property.

[0116] In the transistor 172, the periphery of the source electrode 142a and the drain electrode 142b It is not necessary to provide the protrusions 145a and 145b on the protrusion 14. 5a and the protrusion 145b, the insulating layer ( This is preferable because it can improve the coverage of the insulating film (not shown).

[0117] The transistors 160, 162, and 170 shown in this embodiment The transistor 172 has a large-film wiring (gate electrode, source electrode, or drain electrode). By forming a protrusion on the periphery of the wiring, poor coverage of the insulating layer provided in contact with the wiring can be prevented. This prevents the formation of a thin region locally in the insulating layer. This prevents breakdown of the transistor due to the electric field concentrating in the thin film area. It is possible.

[0118] In addition, in the manufacturing process of miniaturized transistors (channel lengths of less than 2 μm), Even when light of 365 nm or less is used for photolithography exposure, the gate electrode, The protrusion formed on the periphery of the source electrode or the drain electrode can be tapered. be.

[0119] Note that the configurations, methods, and the like described in this embodiment may be applied to configurations, methods, and the like described in other embodiments. They can be used in any suitable combination.

[0120] (Embodiment 2) In this embodiment, a storage medium (memory element) is shown as an example of a semiconductor device. In this embodiment, a transistor including an oxide semiconductor described in Embodiment 1 and a transistor including a semiconductor other than an oxide semiconductor are used. A transistor using the above material is formed on the same substrate.

[0121] FIG. 6 shows an example of the configuration of a semiconductor device. FIG. 6(A) shows a cross section of the semiconductor device, and FIG. 6(B) shows a plan view of the semiconductor device. Here, FIG. 6(A) shows the E of FIG. 6(B). 6(C) corresponds to the cross section taken along the lines 1-E2 and F1-F2. An example of a circuit diagram when the device is used as a memory element is shown in FIGS. 6(A) and 6(B). The semiconductor device has a transistor using a first semiconductor material in the lower part and a second semiconductor material in the upper part. In this embodiment, a transistor using the first semiconductor material is The transistor 260 includes a semiconductor material other than an oxide semiconductor. The transistor using the semiconductor material of Embodiment 2 is The transistor 160 is a semiconductor material other than an oxide semiconductor, for example, silicon, Germanium, silicon germanium, silicon carbide, or gallium arsenide may be used. It is preferable to use a single crystal semiconductor. On the other hand, the transistor 160 including an oxide semiconductor can be easily operated at high speed. This characteristic allows for long-term charge retention. The transistor structure described in Embodiment 1 can be used as appropriate for the transistor. do.

[0122] The transistor 260 in FIG. 6 is formed on a substrate 3 comprising a semiconductor material (e.g., silicon). The channel forming region 116 is provided in the first region 01, and the second region 116 is provided so as to sandwich the channel forming region 116. The impurity region 118 is formed by the metal compound region 124 in contact with the impurity region 118, and the channel A gate insulating layer 108 is provided on the gate forming region 116, and a and a gate electrode 109 formed therein.

[0123] The substrate 301 containing a semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. The substrates used include crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Generally, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, it refers to a substrate having a structure in which a material other than silicon is formed on an insulating surface. This also includes substrates with a structure in which a semiconductor layer made of The layer is not limited to a silicon semiconductor layer. In addition, the SOI substrate may be formed on an insulating substrate such as a glass substrate. The term "substrate" also includes a structure in which a semiconductor layer is provided on a substrate via an insulating layer.

[0124] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 260 . Here, the electrode 126 functions as a source electrode or a drain electrode of the transistor 260. In addition, an element isolation insulating layer 106 is provided to surround the transistor 260. An insulating layer 128 is provided to cover the transistor 260. To achieve this, the transistor 260 has a structure without a sidewall insulating layer as shown in FIG. On the other hand, if the characteristics of the transistor 260 are important, it is desirable to A sidewall insulating layer is provided on the side of the electrode 109, and an impurity layer including regions with different impurity concentrations is formed. An area 118 may be provided.

[0125] The transistor 260 can be fabricated using known techniques. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium The transistor 260 using arsenic or the like is characterized by being capable of high-speed operation. Therefore, by using this transistor as a readout transistor, it is possible to read out information. This can be done quickly.

[0126] After forming the transistor 260, processing before forming the transistor 160 and the capacitor element 164 As a process, the insulating layer 128 is subjected to a CMP process to expose the upper surface of the gate electrode 109 . The process for exposing the upper surface of the gate electrode 109 includes etching in addition to CMP. However, in order to improve the characteristics of the transistor 160, an insulating It is desirable to keep the surface of layer 128 as flat as possible.

[0127] After forming the oxide semiconductor layer 144 on the planarized insulating layer 128, the exposed gate electrode 10 9, a conductive layer is provided to cover the electrode 126, the insulating layer 128, the oxide semiconductor layer 144, and the like. Then, the conductive layer is processed in the same manner as in the first embodiment to form the source electrode 142. The source electrode 142a and the drain electrode 142b are formed. The drain electrode 142b is electrically connected to the gate electrode 109 of the transistor 260. It is electrically connected to the electrode 126 of the transistor 260 .

[0128] In the semiconductor device shown in FIG. 6, the source electrode 142 is connected via the gate insulating layer 146. The conductive layer 158 is provided so as to at least partially overlap with the gate electrode 154. It is formed in the same process as the gate electrode 148 and functions as one electrode of the capacitor element 164 .

[0129] An insulating layer 150 is provided on the gate electrode 148 and the conductive layer 158. A wiring 154 is provided on the insulating layer 150, and the wiring 154 is connected to the insulating layer 150, the gate It is connected to the drain electrode 142b through an opening formed in the insulating layer 146 or the like. The wiring 154 overlaps at least a part of the oxide semiconductor layer 144 of the transistor 160. An insulating layer 156 is provided to cover the wiring 154. .

[0130] In the semiconductor device shown in FIG. 6, the transistor 260 and the transistor 160 , are provided so as to overlap at least partially. In particular, the source of the transistor 260 The oxide semiconductor layer 144 is provided so as to partly overlap with the drain region or the gate region. In addition, the wiring 154 preferably overlaps with at least part of the oxide semiconductor layer 144. In addition, the transistor 160 and the capacitor 164 are provided in the same manner as the transistor 2. It is arranged to overlap with 60.

[0131] For example, the conductive layer 158 of the capacitor 164 is slightly different from the gate electrode 109 of the transistor 260. By adopting such a planar layout, For example, a memory device can be manufactured by using the semiconductor device. When configuring a recell, the minimum processing dimension is F, and the area occupied by the memory cell is 15F 2 ~ 25F 2 It is possible to do so.

[0132] FIG. 6C shows an example of a circuit diagram in which the above semiconductor device is used as a memory element. In FIG. 6C, one of the source electrode and the drain electrode of the transistor 160 and the capacitor One of the electrodes of the capacitor 164 and the gate electrode of the transistor 260 are electrically connected. In addition, the first wiring (also called the source line) and the transistor 26 The source electrode of bit line 0 is electrically connected to the second wiring (2nd Line: also called bit line). The third transistor 260 is electrically connected to the drain electrode of the transistor 260. (also called the 3rd Line: first signal line) and the source electrode of the transistor 160. The other of the drain electrodes is electrically connected to a fourth wiring (4th Line). The second signal line and the gate electrode of the transistor 160 are electrically connected to each other. Then, a fifth wiring (also called a word line) and the capacitor element 164 The other electrode is electrically connected.

[0133] The transistor 160 including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 160, the source of the transistor 160 One of the electrodes or drain electrodes of the capacitor 164 and the transistor 260 The potential of the node (hereinafter referred to as node FG) electrically connected to the gate electrode of Furthermore, by having the capacitance element 164, This makes it easier to retain the charge given to the gate FG and to read out the retained information. becomes.

[0134] When storing (writing) information in the semiconductor device, first, the potential of the fourth wiring is set to This sets the potential at which the transistor 160 is turned on, turning the transistor 160 on. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, the charges that give two different potential levels (hereinafter referred to as low level Either a charge or a high level charge is given. The potential of the fourth wiring is set to a potential that turns off the transistor 160. By turning off 160, node FG is in a floating state, so As described above, a predetermined amount of charge is stored in the node FG. By storing and holding information, the memory cell can store information.

[0135] Since the off-state current of the transistor 160 is extremely small, the charge supplied to the node FG is retained for a long time. Therefore, no refresh operation is required or the data is retained for a certain period of time. It is possible to reduce the frequency of cleaning operations extremely, and power consumption can be reduced significantly. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. It is possible.

[0136] When reading out the stored information (reading), a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the potential is held at the node FG. Depending on the amount of charge transferred, transistor 160 assumes different states. If 60 is an n-channel type, when a high level charge is held at node FG, The apparent threshold voltage V of transistor 160 th_H A low-level charge is applied to node FG. The apparent threshold voltage V of transistor 160 when held th_L It became lower Here, the apparent threshold is the voltage at which the transistor 260 is turned on. Therefore, the potential of the fifth wiring is V th _H and V th_L By setting the potential V0 to the intermediate potential between For example, if a high level charge is applied during writing, The potential of the fifth wire is V0 (>V th_H ), transistor 260 is in the "on state" When a low level charge is applied, the potential of the fifth wire becomes V0( <V t h_L ), transistor 260 remains in the "off state." The potential of the wiring is controlled to read out the on / off state of the transistor 260 (the The stored information can be read out by reading out the potential of the wiring 2.

[0137] When the stored information is rewritten, a predetermined amount of electricity is consumed by the rewriting. By supplying a new potential to node FG, which holds the load, node FG is connected to the new information. Specifically, the potential of the fourth wiring is set to a value corresponding to the potential of the fourth wiring when the transistor 160 is in an on state. This turns on the transistor 160. A potential (potential related to new information) is supplied to node FG, and a predetermined amount of charge is accumulated in node FG. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 160. By turning off the transistor 160, the node FG receives the new information. That is, a predetermined amount of charge is stored in the node FG by the first write. While the charge is held, the same operation as the first write (second write) is performed. , it is possible to overwrite the stored information.

[0138] The transistor 160 described in this embodiment has a highly purified and intrinsic oxide semiconductor layer. By using the transistor 144, the off-state current of the transistor 160 can be sufficiently reduced. By using such transistors, it is possible to retain memory contents for an extremely long period of time. In addition, a semiconductor device capable of miniaturizing a channel length (L) can be obtained. By using the sta 160, the integration degree of the semiconductor device can be improved.

[0139] In the semiconductor device described in this embodiment, the transistor 260 and the transistor 1 By overlapping 60, a semiconductor device with a sufficiently high integration density can be realized.

[0140] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0141] (Embodiment 3) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. Here, the central processing unit (CPU) will be described.

[0142] An example of a block diagram of a CPU is shown in Fig. 7. The CPU 1101 shown in Fig. 7 is a timing A control circuit 1102, an instruction analysis decoder 1103, a register array 1104, Address logic buffer circuit 1105, data bus interface 1106, ALU ( Arithmetic logic unit 1107, instruction register 1108, etc. It is composed of:

[0143] These circuits include inverter circuits, resistors, capacitors, and transistors shown in the previous embodiments. By using the transistor described in the above embodiment, This makes it possible to suppress the short channel effect of the transistor and achieve miniaturization.

[0144] Below, we will briefly explain each circuit included in the CPU 1101. The control circuit 1102 receives external commands, converts them into internal information, Also, depending on the internal operation, memory data is read and written. The instruction analysis decoder 1103 converts external instructions into internal instructions. The register array 1104 has a function to temporarily store data. The address logic buffer circuit 1105 has the function of specifying an address in the external memory. The data bus interface 1106 is used to connect to external memory or a device such as a printer. The ALU 1107 has the function of performing calculations. The instruction register 1108 has the function of temporarily storing instructions. The CPU is made up of a combination of these components.

[0145] The transistors shown in the above embodiments are used in at least a part of the CPU 1101. This makes it possible to suppress the short channel effect of the transistor and achieve miniaturization. This allows for a high degree of integration of the CPU 1101.

[0146] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0147] (Fourth embodiment) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. Here, we will explain the semiconductor device that has an image sensor function to read information about an object. An example of the device will be described. Note that in the circuit diagram, a transistor using an oxide semiconductor is To indicate that it is a standard, the OS code may also be added.

[0148] FIG. 8A shows an example of a semiconductor device having an image sensor function. 8(A) is an equivalent circuit of the photosensor, and FIG. 8(B) is a cross-sectional view showing a part of the photosensor.

[0149] One electrode of the photodiode 1202 is connected to the photodiode reset signal line 1212. The other electrode is electrically connected to the gate of the transistor 1204. 1204, one of the source electrode and the drain electrode is connected to the photosensor reference signal line 1218; The other of the source electrode and the drain electrode is the source electrode or the drain electrode of the transistor 1206. The transistor 1206 has a gate electrode electrically connected to one of the electrodes. The other of the source electrode and the drain electrode is connected to a photosensor output signal line 1214. are electrically connected.

[0150] Here, the transistor 1204 and the transistor 1206 shown in FIG. 8A are oxide semiconductors. Here, a transistor using an oxide semiconductor is Therefore, the transistor described in the above embodiment can be used. The transistor can reduce leakage current in the off state to a minimum, Furthermore, the light detection accuracy of the transceiver sensor can be improved. By using a resistor, the short channel effect of the transistor is suppressed and miniaturization is achieved. This allows the area of ​​the photodiode to be increased, improving the light detection accuracy of the photosensor. can be improved.

[0151] FIG. 8B shows a photodiode 1202 and a transistor 120 in the photosensor. 4, a substrate 1222 (TFT substrate) having an insulating surface is provided with a sensor. A photodiode 1202 and a transistor 1204 are provided to function as a photodiode. The substrate 12 is formed on the diode 1202 and the transistor 1204 using an adhesive layer 1228. 24 is provided on the transistor 1204. An insulating layer 1234 and an interlayer insulating A layer 1236 and an interlayer insulating layer 1238 are provided.

[0152] In addition, the gate electrode of the transistor 1204 is electrically connected to the gate electrode of the transistor 1204. The gate electrode 1240 is provided in the same layer. and a metal film provided on the interlayer insulating layer 1236 through an opening provided in the interlayer insulating layer 1236. The photodiode 1202 is electrically connected to the electrode layer 1242. 2, the photodiode 1202 and the transistor 1204 are The electrodes 1240 and 1242 are electrically connected to each other.

[0153] The photodiode 1202 is made up of a first semiconductor layer 1226a, a second semiconductor layer 1226b, and a third semiconductor layer 1226c in this order from the electrode layer 1242 side. The second semiconductor layer 1226b and the third semiconductor layer 1226c are stacked. The photodiode 1202 is electrically connected to the electrode layer 1242 through the first semiconductor layer 1226a. In addition, in the third semiconductor layer 1226c, a The electrode layer 1244 is electrically connected to the electrode layer 1244 .

[0154] Here, the first semiconductor layer 1226a is a semiconductor layer having n-type conductivity, and the second semiconductor layer The layer 1226b is a high-resistance semiconductor layer (I-type semiconductor layer), and the third semiconductor layer 1226c is a A pin-type photodiode in which semiconductor layers having p-type conductivity are stacked is shown as an example.

[0155] The first semiconductor layer 1226a is an n-type semiconductor layer, and is made of an aluminium containing an impurity element that imparts n-type conductivity. The first semiconductor layer 1226a is formed of a ruthenium silicon film. Using semiconductor material gas containing metal elements (e.g., phosphorus (P)), it is formed by plasma CVD method. Silane (SiH4) can be used as the semiconductor material gas. 6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain pure elements, the film is grown by using diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by ion implantation or the like. After the pure element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon film can be formed by LPCVD, vapor phase growth, or The thickness of the first semiconductor layer 1226a is 20 nm or more and 200 nm or less. It is preferable to form it so that the thickness is 1 nm or less.

[0156] The second semiconductor layer 1226b is an i-type semiconductor layer (intrinsic semiconductor layer) and is made of amorphous silicon. The second semiconductor layer 1226b is formed by an arsenic film using a semiconductor material gas. The amorphous silicon film is formed by the plasma CVD method. Or, Si2H6, SiH2Cl2, SiHCl3 The second semiconductor layer 1226b may be formed by LPCV. The second semiconductor layer 1226b may be formed by a deposition method, a vapor deposition method, a sputtering method, or the like. The film thickness is preferably formed to be 200 nm or more and 1000 nm or less.

[0157] The third semiconductor layer 1226c is a p-type semiconductor layer, and is made of an amorphous material containing an impurity element that imparts p-type conductivity. The third semiconductor layer 1226c can be formed of a thick silicon film. Plasma CVD is performed using semiconductor material gases containing impurity elements of the SiO2 group (e.g., boron (B)). Silane (SiH4) can be used as the semiconductor material gas. , Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, An impurity element may be introduced into the amorphous silicon film by ion implantation. After introducing the impurity element by the above method, the impurity element is preferably diffused by heating or the like. In this case, the amorphous silicon film can be formed by LPCVD, vapor phase growth, etc. The third semiconductor layer 1226c may be formed by a deposition method, a sputtering method, or the like. It is preferable to form the film so that the thickness is 50 nm or less.

[0158] In addition, the first semiconductor layer 1226a, the second semiconductor layer 1226b, and the third semiconductor layer 1226c The semiconductor layer may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (ceramic) semiconductor. Semi Amorphous Semiconductor (SAS) ) may be formed using a semiconductor.

[0159] Considering the Gibbs free energy, microcrystalline semiconductors are metastable, intermediate between amorphous and single crystal. In other words, a semiconductor with a third state that is stable in terms of free energy It has a short-range order and lattice distortion. Microcrystalline silicon, a typical example of a microcrystalline semiconductor, is characterized by its Raman scattering. The spectrum shows single-crystal silicon at 520 cm -1 It is shifted to the lower wavenumber side. That is, 520 cm, which indicates single crystal silicon -1 and 480 cm, which indicates amorphous silicon - 1 The Raman spectrum of microcrystalline silicon has a peak between these two. Contains at least 1 atomic % or more of hydrogen or halogen to terminate the bonding bonds. It also contains rare gas elements such as helium, argon, krypton, and neon. By increasing the lattice distortion, the stability is increased and a good microcrystalline semiconductor film can be obtained. .

[0160] This microcrystalline semiconductor film is formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or Alternatively, it can be formed by a microwave plasma CVD device with a frequency of 1 GHz or more. Representative examples include SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, and S It can be formed by diluting silicon hydride such as iF4 with hydrogen. In addition to hydrogen, one or more of helium, argon, krypton, and neon A microcrystalline semiconductor film can be formed by diluting the silicon hydride with a rare gas element. The flow rate ratio of hydrogen to nitrogen is 5 to 200 times, preferably 50 to 150 times, More preferably, it is 100 times. Furthermore, in the gas containing silicon, CH4, C2H6 It is also possible to mix in carbide gases such as GeH4, GeF4, germanium gases such as F2, etc. stomach.

[0161] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type The photodiode exhibits better characteristics when the p-type semiconductor layer side is used as the light receiving surface. The photodiode 1202 receives incident light 1230 from the surface on the plate 1224 side and converts it into an electrical signal. In addition, the semiconductor layer side having the opposite conductivity type to the semiconductor layer side serving as the light receiving surface is Since this light becomes disturbance light, it is preferable to use a conductive film having a light-blocking property for the electrode layer 1242. Alternatively, the n-type semiconductor layer side can be used as the light receiving surface.

[0162] In addition, by irradiating incident light 1230 from the surface on the substrate 1224 side, the transistor 1 The oxide semiconductor layer of the transistor 1204 is irradiated with incident light 12 by the gate electrode of the transistor 1204. 30 can be shaded.

[0163] The insulating layer 1234, the interlayer insulating layer 1236, and the interlayer insulating layer 1238 are made of insulating materials. Depending on the material, the method can be sputtering, SOG, spin coating, dipping, or spraying. - Coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing) etc.), using a doctor knife, roll coater, curtain coater, knife coater, etc. It can be formed.

[0164] The insulating layer 1234 may be made of an inorganic insulating material such as a silicon oxide layer or a silicon oxynitride layer. , silicon nitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum oxynitride layer an oxide insulating layer or nitride insulating layer such as an aluminum nitride layer or an aluminum oxide nitride layer; Single layer or laminated layers can be used. High density microwave (2.45 GHz) Plasma CVD is preferable because it can form a dense, high-quality insulating layer with high dielectric strength.

[0165] The interlayer insulating layer 1236 and the interlayer insulating layer 1238 are planar insulating layers for reducing surface irregularities. The insulating layer 1236 and the insulating layer 1238 are preferably an insulating layer that functions as a film. Heat-resistant materials such as polyimide, acrylic, benzocyclobutene, polyamide, epoxy, etc. In addition to the above organic insulating materials, organic insulating materials having a low dielectric constant can be used. Materials (low-k materials), siloxane resins, PSG (phosphor glass), BPSG (phosphor silicon dioxide) A single layer or a laminate of a material such as a glass substrate can be used.

[0166] The photodiode 1202 detects the incident light 1230 to obtain information about the object. When reading the information of the detected object, a light source such as a backlight is used. can be used.

[0167] In the photosensor described above, the transistor using an oxide semiconductor is The transistor shown in the above embodiment can be used. The photodiode can minimize leakage current in the off state, Detection accuracy can be improved. By doing so, it is possible to suppress the short channel effect of the transistor and achieve miniaturization. This increases the area of ​​the photodiode and improves the light detection accuracy of the photosensor. It is possible.

[0168] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0169] (Embodiment 5) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 9. In this embodiment, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) ), digital cameras, digital video cameras, electronic paper, television equipment (television The semiconductor device is applied to an electronic device such as a television receiver. The following describes the case.

[0170] FIG. 9A shows a notebook personal computer, which includes a housing 601, a housing 602, a display, and a keyboard. The display unit 603, the keyboard 604, etc. At least one of the semiconductor devices is provided. This will enable the realization of a high-speed, low-power consumption notebook personal computer.

[0171] FIG. 9B shows a personal digital assistant (PDA), and a main body 611 includes a display unit 613 and an external An interface 615 and operation buttons 614 are provided. The main body 611 is provided with a stylus 612 for operating the Therefore, for example, a high-speed, low-power portable information terminal can be The end is realized.

[0172] FIG. 9C shows an electronic book 620 equipped with electronic paper, which has a housing 621 and a housing 623. The housing 621 and the housing 623 each include a display unit 62 5 and a display unit 627 are provided. The housing 621 and the housing 623 are connected by a shaft 637. The housing 62 is connected to the shaft 637, and can be opened and closed around the shaft 637. 1 includes a power supply 631, operation keys 633, a speaker 635, etc. At least one of the housings 623 is provided with the semiconductor device described in the above embodiment. This allows, for example, the realization of high-speed, low-power-consumption e-books.

[0173] FIG. 9D shows a mobile phone that is made up of two housings, a housing 640 and a housing 641. Furthermore, the housing 640 and the housing 641 slide and are unfolded as shown in FIG. 9(D). The device can be made compact enough to be portable. The housing 641 includes a display panel 642, a speaker 643, a microphone 644, and operation keys. 645, pointing device 646, camera lens 647, external connection terminal 648, etc. The housing 640 also includes a solar cell 649 for charging the mobile phone, an external The device is also provided with an internal memory slot 650. The antenna is built into the housing 641. At least one of the housing 640 and the housing 641 includes the semiconductor device described in the above embodiment. This allows, for example, a high-speed, low-power-consumption mobile phone to be realized.

[0174] FIG. 9E shows a digital camera, which includes a main body 661, a display unit 667, an eyepiece 663, and an operation unit. It is composed of a switch 664, a display unit 665, a battery 666, etc. The semiconductor device shown in the previous embodiment is provided in 61. This will result in a high-speed, low-power digital camera.

[0175] FIG. 9F shows a television device 670, which includes a housing 671, a display unit 673, a stand 674, and a The television device 670 is operated by a switch provided in the housing 671. The operation can be performed by a switch or a remote control 680. The semiconductor device described in the above embodiment is mounted on the device 680. A high-speed, low-power consumption television device is realized.

[0176] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. As a result, miniaturization of semiconductor devices has led to increased speed and reduced power consumption. An electronic device is obtained. [Example]

[0177] In this example, the conductive layer was processed by applying the manufacturing method of the semiconductor device shown in Embodiment Mode 1. Here is an example.

[0178] In this example, a structure corresponding to the transistor 160 shown in FIG. The method for preparing the sample is shown below.

[0179] First, a silicon oxide layer 402 having a thickness of 300 nm is formed on a glass substrate 400 as an undercoat film. Then, an island-shaped oxide semiconductor layer was formed as a semiconductor layer by sputtering. The oxide semiconductor layer 404 was formed using an In-Ga-Zn-O target. The film was formed by sputtering. The film thickness was 30 nm. A tungsten layer 406 was formed as a conductive layer with a thickness of 100 nm (see FIG. 10(A)). ).

[0180] The resulting tungsten layer 406 is subjected to a first etching using a resist mask 410. A tungsten layer 408 having a recess was formed (see FIG. 10(B1)). The light source used to fabricate the photomask 410 was i-line light with a wavelength of 365 nm. In addition, the etching equipment is ICP (Inductively Coupled Plasma) A dry etching system using a high density plasma source such as LASM was used.

[0181] The first etching was performed with the pressure in the chamber set to 0.67 Pa and the substrate temperature set to 40°C. Apply 3000 W of RF (13.56 MHz) power to the electrode coil and 1 The etching was performed for 10 seconds by applying a power of 40 W. The etching gas was C The mixture gas of F4, Cl2 and O2 was used with flow rates of 55sccm, 45sccm and The flow rate was set to 55 sccm.

[0182] Next, the resist mask 410 was reduced to form a resist mask 412. The reduction of the 410 was performed in the same chamber as the first etching at a pressure of 3.0 Pa. The substrate temperature was set to 40°C, and 2000 W of RF power was applied to the coil of the upper electrode. The electrode was set to 0 W, and O2 gas was flowed at a flow rate of 100 sccm to perform ashing by oxygen plasma. The ashing time was 15 seconds.

[0183] Thereafter, a second etching is performed using the reduced resist mask 412, and a protrusion is formed on the periphery. The tungsten layer 414 having the above structure was obtained (see FIG. 10(C1)). The pressure in the chamber was set to 0.67 Pa, the substrate temperature was set to 40°C, and a 3000 An RF power of 140 W was applied to the electrode on the substrate side, and etching was performed for 15 seconds. The etching gas was a mixture of CF4, Cl2 and O2 at a flow rate of 1000 s. were set to 55 sccm, 45 sccm and 55 sccm, respectively.

[0184] After that, the resist mask 412 was removed (see FIG. 10(D1)).

[0185] As a comparative example, a resist mask 410 was used to oxidize the film by a single etching process. The compound semiconductor layer 404 was exposed, and a tungsten layer 416 was formed (see FIG. 10(B2)). After that, the resist mask 410 was removed (see FIG. 10(C2)).

[0186] FIG. 11(A) shows the end of the tungsten layer 414 (shown in FIG. 10(D1)) after etching. STEM (Scanning Transmission Electron Microscopy) of the area enclosed by the dotted line A CT microscope image is shown.

[0187] FIG. 11B shows a comparative example of a tungsten layer 416 (see FIG. 10C2). The STEM image of the edge of the sample (area surrounded by a dotted line in this figure) is shown.

[0188] As shown in FIG. 11(B), when a resist mask made using i-line is used, tungsten Layer 406 is patterned in a single etching process to form tapered edges. It was shown that the side and bottom surfaces of the tungsten layer 416 were substantially perpendicular to each other. When a thin film is formed on a conductive layer, disconnection or connection failure is likely to occur. There is a concern that this may result in the formation of locally thin regions.

[0189] In addition, as shown in FIG. 11A, by applying the manufacturing method described in Embodiment 1, it is possible to manufacture a semiconductor device using i-line. Even when the resist mask was used, protrusions were formed at the edge of the tungsten layer 414. It was shown that a protrusion 415 was formed. The protrusion 415 had a tapered shape.

[0190] As described above, by applying the method for manufacturing a semiconductor device according to one embodiment of the present invention, Even when light of 365 nm or less is used for the device, the protrusions formed around the edges of the wiring can be removed by taping. It was shown that it is possible to make it into a shape like a bell. [Explanation of symbols]

[0191] 100 base 106 Element isolation insulating layer 108 Gate insulating layer 109 Gate electrode 116 Channel formation region 118 Impurity region 124 Metal compound area 126 electrode 128 Insulating Layer 140 Conductive layer 141 Conductive layer 142a Source electrode 142b Drain electrode 144 Oxide semiconductor layer 145a Protrusion 145b Protrusion 146 Gate insulating layer 147 Protrusion 148 gate electrode 149 gate electrode 150 insulating layer 150a resist mask 150b resist mask 152a Resist mask 152b Resist mask 154 Wiring 156 Insulating Layer 158 Conductive Layer 160 transistors 162 transistors 164 Capacitor 170 transistors 172 transistors 260 transistors 301 Substrate 400 glass substrate 402 silicon oxide layer 404 Oxide semiconductor layer 406 tungsten layer 408 tungsten layer 410 Resist mask 412 Resist mask 414 Tungsten layer 415 Protrusion 416 Tungsten layer 601 Case 602 Case 603 Display section 604 keyboard 611 Main unit 612 Stylus 613 Display section 614 Operation button 615 External Interface 620 e-books 621 Case 623 Case 625 Display section 627 Display section 631 Power supply 633 Operation Key 635 Speaker 637 Shaft 640 chassis 641 Case 642 Display Panel 643 Speaker 644 Microphone 645 Operation Key 646 Pointing Device 647 Camera Lenses 648 External connection terminal 649 Solar Cells 650 external memory slot 661 Main Unit 663 Eyepiece 664 Operation switch 665 Display section 666 Battery 667 Display section 670 Television Equipment 671 Case 673 Display section 675 Stand 680 Remote Controlled Device 1101 CPU 1102 Timing control circuit 1103 Instruction Parsing Decoder 1104 Register Array 1105 Address logic buffer circuit 1106 Data Bus Interface 1107 ALU 1108 Instruction Register 1202 Photodiode 1204 transistor 1206 Transistor 1212 Photodiode reset signal line 1214 Gate signal line 1216 Photo sensor output signal line 1218 Photo sensor reference signal line 1222 board 1224 board 1226a Semiconductor layer 1226b Semiconductor layer 1226c Semiconductor layer 1228 Adhesive layer 1230 Incident light 1234 Insulation layer 1236 Interlayer insulation layer 1238 Interlayer insulation layer 1240 gate electrode 1242 Electrode layer 1244 Electrode layer

Claims

1. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer located above the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region overlapping with the second conductive layer and a region overlapping with the first conductive layer and having a function as the other electrode of the capacitor; a third insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the third conductive layer has the same material as the second conductive layer; the third conductive layer is electrically connected to one of a source region or a drain region of the first transistor; The fifth conductive layer has the same material as the fourth conductive layer.

2. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer located above the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region overlapping with the second conductive layer and a region overlapping with the first conductive layer and having a function as the other electrode of the capacitor; a third insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the third conductive layer has the same material as the second conductive layer; the third conductive layer is electrically connected to one of a source region or a drain region of the first transistor; the fifth conductive layer has the same material as the fourth conductive layer; The fourth conductive layer has a region overlapping with the second conductive layer.

Images