Semiconductor device

Abstract

A semiconductor device with favorable electrical characteristics and a method for manufacturing the semiconductor device are provided.SOLUTION: In a transistor including an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer, n-type buffer layers are formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer, whereby parasitic resistance is reduced and on-state current characteristics of the transistor are improved.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. For example, a transistor is a semiconductor device, and a liquid crystal display including the transistor Electro-optical devices such as light-emitting devices, semiconductor circuits, and electronic equipment are also included in the semiconductor device category. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. do.

[0004] For example, the active layer of a transistor is 18 / cm 3 is less than Amorphous oxides containing indium (In), gallium (Ga), and zinc (Zn) were used. A transistor is disclosed (see Patent Document 1).

[0005] In addition, a transistor using an oxide semiconductor is superior to a transistor using amorphous silicon. It operates faster than a conventional digital camera and can be used to configure display device drive circuits and high-speed memory circuits. . [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0007] For example, transistors used in a driver circuit of a display device are required to operate at high speed. In particular, the higher the resolution of the display, the shorter the time it takes to write the display image. It is desirable that the transistor used in the circuit has a high on-state current and can operate at high speed.

[0008] Therefore, one embodiment of the present invention is a transistor which has high on-state current and can operate at high speed, and a method for fabricating the transistor. Another object of the present invention is to provide a semiconductor device including the transistor. One of the purposes is to provide [Means for solving the problem]

[0009] One embodiment of the present invention disclosed in this specification is a method for manufacturing a semiconductor device using an oxide semiconductor that is a channel formation region of a transistor. A barrier having n-type conductivity is formed between the conductor layer and the metal layer serving as the source electrode or drain electrode. By forming a buffer layer, parasitic resistance is reduced and the on-current characteristics of the transistor are improved. It is something that will raise the bar.

[0010] One embodiment of the present invention disclosed in this specification is a method for manufacturing a semiconductor device comprising: The source electrode layer and the drain electrode layer overlapping with a part of the semiconductor layer and contacting a part of the oxide semiconductor layer are a gate insulating layer formed on the source electrode layer and an oxide layer formed on the gate insulating layer; The semiconductor layer and the drain electrode layer and the oxide semiconductor layer are provided with n-type conductivity. The semiconductor device is characterized in that a buffer layer is formed thereon.

[0011] The source electrode layer and the drain electrode layer may be formed of aluminum, chromium, copper, tantalum, titanium, or the like. A single film or alloy film whose main component is an element selected from silicon, molybdenum, and tungsten, or A laminated film of these can be used.

[0012] The buffer layer may be formed of indium oxide, indium tin oxide, indium zinc oxide, or the like. a metal oxide selected from the group consisting of tin oxide, tin oxide, zinc oxide, and tin zinc oxide; or the metal oxide contains one or more elements selected from aluminum, gallium, and silicon. By using this structure, the source electrode layer and the drain electrode layer can be formed of a material that is known to be a material for the present invention. The parasitic resistance between the electrode layer and the oxide semiconductor layer can be reduced.

[0013] Another embodiment of the present invention disclosed in this specification is a semiconductor device including a semiconductor substrate having an insulating surface and a semiconductor layer formed on the substrate. An oxide semiconductor layer is formed in an island shape on the insulating layer, and an n-type conductive layer is formed on the oxide semiconductor layer. a buffer layer and a metal layer for forming the insulating film, and selectively etching the buffer layer and the metal layer. A source region including the buffer layer and the metal layer is formed so as to overlap a part of the oxide semiconductor layer. and a gate electrode is formed to cover the oxide semiconductor layer, the source region, and the drain region. a gate insulating layer is formed on the gate insulating layer so as to overlap with part of the oxide semiconductor layer; The present invention relates to a method for manufacturing a semiconductor device, and to a method for manufacturing the same. [Effects of the Invention]

[0014] According to one embodiment of the present invention, a semiconductor device using an oxide semiconductor layer as a source electrode layer and a drain electrode layer It is possible to reduce the parasitic resistance between the metal layer and the transistor, which has a high on-current and can operate at high speed. A semiconductor device including a transistor and a manufacturing method thereof can be provided. [Brief explanation of the drawings]

[0015] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating processes in a manufacturing method of a semiconductor device. [Figure 3] FIG. 1 is a plan view illustrating one embodiment of a semiconductor device. [Figure 4] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 5] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 6] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 7] 1A and 1B are diagrams illustrating electronic devices. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] IV characteristics of the transistor before and after applying negative gate BT stress. [Figure 10] Scientific calculation model and electric field strength distribution during negative gate BT stress. [Figure 11] Transistor IV characteristics and current density distribution when negative charge is inserted (at drain voltage +0.1V). [Figure 12] Transistor IV characteristics and current density distribution when negative charge is inserted (drain voltage +3V). [Figure 13] Cross-sectional TEM photograph of a transistor with a buffer layer and its schematic diagram. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that various modifications can be made to the modes and details. It will be easily understood. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used to indicate the same things. The numbers are used in common across different drawings. Also, when referring to the same thing, the hatch pattern is used. Similarly, there are cases where no particular symbol is attached.

[0017] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of the processes or the order of stacking. Furthermore, in this specification, the specific name is not used as a matter for identifying the invention. It does not indicate a title.

[0018] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. Explain.

[0019] As an example of a semiconductor device according to one embodiment of the present invention, a plan view of a top-gate transistor and a A cross-sectional view is shown in FIG. 1. Here, FIG. 1(A) is a top view, and FIG. 1(B) and FIG. 1(C) are These are cross-sectional views taken along the lines AB and CD in FIG. The transistor 151 has a source region and a drain region formed in contact with the upper portion of the semiconductor layer. Therefore, it is called a top gate type and also a top contact type. do.

[0020] The transistor 151 shown in FIG. 1 includes an insulating layer 102, an oxide semiconductor layer 10, and a 6, source electrode layer 108a, drain electrode layer 108b, gate insulating layer 112, gate electrode Here, the oxide semiconductor layer 106, the source electrode layer 108a, and the oxide semiconductor layer 114 are included. Between the semiconductor layer 106 and the drain electrode layer 108b, buffer layers 107a and 107b are provided. In this specification, for ease of explanation, the source electrode layer 107b is formed. 08a and the buffer layer 107a are integrated as the source region, and the drain electrode layer 108b and the buffer layer 107b are sometimes integrated and referred to as the drain region. Also, in this embodiment, the transistor using the oxide semiconductor layer is an n-channel type.

[0021] Note that the transistor 151 may have a configuration as shown in the cross-sectional views of FIGS. 8(A), (B), and (C). FIG. 8(A) shows a configuration in which the film thickness of the channel formation region in the oxide semiconductor layer 106 is formed thin. FIG. 8(B) shows a configuration in which the source electrode layer 108a and the drain electrode layer 108b are formed with a step on the buffer layers 107a and 107b. FIG. 8(C) shows a configuration in which FIGS. 8(A) and 8(B) are combined. The transistors having these configurations have electrical characteristics equivalent to those of the transistor having the configuration shown in the cross-sectional view of FIG. 1(B).

[0022] As the material of the insulating layer 102, silicon oxide, silicon oxynitride, Ga x Al 2-x O 3+y (0 ≦ x ≦ 2, 0 < y < 1, x is a value from 0 or more to 2 or less, y is greater than 0 and less than 1 ) aluminum oxide, gallium oxide, or gallium aluminum oxide represented by, or a mixed material of these can be used. Also, the insulating layer 102 may be a laminate of the aforementioned materials and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride or a mixed material of these. For example, if the insulating layer 102 has a laminated structure of a silicon nitride layer and a silicon oxide layer, it is possible to prevent the entry of moisture from the substrate or the like into the transistor 151. When the insulating layer 102 is formed in a laminated structure, the oxide semiconductor layer 10 ​ The side in contact with 6 is made of silicon oxide, silicon oxynitride, aluminum oxide, or a mixture of these materials. The insulating layer 102 may be an oxide layer such as a silicon dioxide layer or the like. It works.

[0023] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors added to them, It is preferable that the alloy contains gallium (Ga) as well as tin (Sn It is also preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer. stomach.

[0024] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0025] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In-G In-Ga-Zn-O based materials, which are ternary metal oxides (IGZO and (also written as "In-Al-Zn-O"); In-Sn-Zn-O; Sn- Ga-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials materials, In-Hf-Zn-O based materials, In-La-Zn-O based materials, In-Ce-Zn -O-based materials, In-Pr-Zn-O-based materials, In-Nd-Zn-O-based materials, In- Sm-Zn-O based materials, In-Eu-Zn-O based materials, In-Gd-Zn-O based materials materials, In-Tb-Zn-O based materials, In-Dy-Zn-O based materials, In-Ho-Zn -O-based materials, In-Er-Zn-O-based materials, In-Tm-Zn-O-based materials, In- Yb-Zn-O system materials, In-Lu-Zn-O system materials, and quaternary metal oxides n-Sn-Ga-Zn-O based materials, In-Hf-Ga-Zn-O based materials, In-Al -Ga-Zn-O based materials, In-Sn-Al-Zn-O based materials, In-Sn-Hf- Zn-O based materials and In-Hf-Al-Zn-O based materials can be used.

[0026] Here, for example, an In-Ga-Zn-O-based material is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than Ga and Zn may also be included.

[0027] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m (m>0 and m must be an integer. It can be formed by a thin film using a material represented by the formula (I), where M is Zn, It represents one or more metallic elements selected from Ga, Al, Mn, and Co. For example, M As the metal, Ga, Ga and Al, Ga and Mn, Ga and Co, etc. can be used. do.

[0028] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn-O system with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The material or an oxide having a composition close to the material can be used. 1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3: 1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn-O-based material having an atomic ratio of 1000 or an oxide having a composition close to that.

[0029] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0030] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0031] In addition, in a crystalline oxide semiconductor, bulk defects can be further reduced, and the surface By improving the flatness, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface with a thickness of 0.1 nm or less.

[0032] The oxide semiconductor layer and the underlying oxide insulating layer are in contact with each other, whereby the insulating layer 102 and the oxide semiconductor layer The interface state with the oxide semiconductor layer 106 and the oxygen vacancies in the oxide semiconductor layer 106 can be reduced. The reduction in the interface states and oxygen vacancies reduces the time-dependent change in the threshold voltage of the transistor 151. This can reduce the amount of

[0033] The source and drain regions of the transistor 151 are in contact with the oxide semiconductor layer 106. The side to be connected is formed of buffer layers 107a and 107b having n-type conductivity. By forming layers, the oxide semiconductor layer 106, the source electrode layer 108a, and the oxide semiconductor The parasitic resistance between the layer 106 and the drain electrode layer 108b can be reduced, This can increase the on-state current of the transistor and improve the frequency characteristics of the circuit. This effect is particularly noticeable when the channel length of the transistor is 5 μm or less. The reduction in the parasitic resistance is mainly due to the oxide semiconductor layer 106 and the source electrode layer 108a or the drain electrode layer 108b. This occurs due to a reduction in contact resistance with the electrode layer 108b.

[0034] Representative materials that can be used for the buffer layers 107a and 107b having n-type conductivity Examples include indium oxide (In-O-based material), indium tin oxide (In-Sn- O-based materials), indium zinc oxide (In-Zn-O-based materials), tin oxide (Sn-O zinc oxide (Zn-O based materials), tin zinc oxide (Sn-Zn-O based materials) ), as well as aluminum (Al), gallium (Ga), silicon (Si). In addition, titanium oxide (Ti- O-based materials), titanium niobium oxide (Ti-Nb-O-based materials), molybdenum oxide (M oO-based materials), tungsten oxide (WO-based materials), magnesium oxide (Mg -O-based materials), calcium oxide (Ca-O-based materials), gallium oxide (Ga-O-based materials) The above materials may contain nitrogen (N).

[0035] Examples of the metal layer used for the source electrode layer 108a and the drain electrode layer 108b include aluminum. Elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten Metal films containing elements or alloy films containing the above elements (titanium nitride film, molybdenum nitride film, etc.) For example, aluminum films, tungsten nitride films, and laminated films thereof can be used. Titanium, molybdenum, tungsten, etc. are applied to one or both sides of a metal film such as aluminum or copper. Any high melting point metal film or its nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) It may also be configured by laminating a layer of a metal film (stainless steel film, etc.).

[0036] In a structure in which the source electrode and the drain electrode are in contact with the gate insulating layer, the withstand voltage of the gate insulating layer is To prevent a voltage drop, a metal film with a weak oxygen-removing effect is used as the source electrode and drain electrode. The metal film is preferably made of, for example, molybdenum or tungsten. However, when the source electrode and the drain electrode are laminated, At least, the side in contact with the gate insulating layer should be the metal film.

[0037] The gate insulating layer 112 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or silicon nitride oxide. Silicon, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide nium oxide, hafnium oxide, gallium oxide, lanthanum oxide or a mixture of these materials The film can be formed by a plasma CVD method, a sputtering method, or the like. The gate insulating layer 112 is not limited to a single layer, but may be a laminate of the above-mentioned materials.

[0038] Note that the gate insulating layer 112 is formed using an insulating material containing the same kind of component as that of the oxide semiconductor layer. Such a material can maintain a good state of the interface with the oxide semiconductor layer. Here, the term "component of the same kind as the oxide semiconductor layer" refers to a component selected from the constituent elements of the oxide semiconductor layer. For example, when the oxide semiconductor layer is an In-Ga-Zn system When the insulating material is made of oxide semiconductor material, oxide gas is the only insulating material containing the same type of component. Lithium, etc.

[0039] The gate electrode layer 114 may include molybdenum, titanium, tantalum, tungsten, aluminum, etc. Metallic materials such as copper, neodymium, scandium, or nitrides of these, or materials containing these as the main components The gate electrode layer 114 may have a single-layer structure. Alternatively, a laminated structure of the above materials may be used.

[0040] Although not shown, an insulating layer may be provided over the transistor 151. The insulating layer may be made of the same material as the insulating layer 102. In order to electrically connect the gate insulating layer 108a and the drain electrode layer 108b to the wiring, An opening may be formed in the oxide semiconductor layer 106 or the like. A second gate electrode may be provided. Note that the oxide semiconductor layer 106 is processed into an island shape. Although it is preferable to be present, it does not have to be processed into an island shape.

[0041] Next, an example of the manufacturing process of the transistor 151 shown in FIG. 1 will be described.

[0042] First, an insulating layer 102 serving as a base film is formed on a substrate 100 having an insulating surface (see FIG. 2(A ). The insulating layer 102 has a function of preventing the diffusion of impurity elements from the substrate 100, and can be formed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or G a x Al 2-x O 3+y (0≦x≦2, 0<y<1, x is a value from 0 to 2, y is greater than 0 and less than 1) aluminum oxide, gallium oxide, or gallium aluminum oxide selected from the group consisting of aluminum oxide. Also, the base film is not limited to a single layer and may be a laminate of the above-mentioned plurality of films.

[0043] Here, the substrate 100 can be at least one having heat resistance against subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. Also, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium lumianium, or an SOI substrate can also be used.

[0044] Further, a flexible substrate may be used as the substrate 100. Alternatively, a substrate provided with a release layer may be used. In the latter case, after manufacturing a transistor including an oxide semiconductor layer according to the method disclosed below, it can also be transferred to a flexible substrate.

[0045] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm, is formed on the insulating layer 102. An oxide semiconductor film of 100 nm or less is formed.

[0046] As described above, the oxide semiconductor used for the oxide semiconductor film is an oxide semiconductor represented by the chemical formula InMO3(Z nO) m (m>0 and m is not an integer) can be used, where In the example, an In-Ga-Zn-O film is formed by sputtering.

[0047] The film formation target used in the sputtering method has a composition ratio of, for example, In2O3:G The metal oxides used are a2O3:ZnO = 1:1:1 [molar ratio]. Also, In2O3 Metal oxides with a molar ratio of Ga2O3:ZnO=1:1:2 may also be used.

[0048] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, the composition of the target to be used The atomic ratio of In:Zn is 50:1 to 1:2 (converted to molar ratio, InO 3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar number In terms of ratio, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn = 1.5:1 to 15:1 (converted to molar ratio In2O3:ZnO = 3:4 to 15: For example, the target used to form an In-Zn-O oxide semiconductor is an atomic When the numerical ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0049] In addition, when an In-Sn-Zn-O-based material is used as the oxide semiconductor, the target to be used The composition ratio of In:Sn:Zn is preferably 2:1:3 in terms of atomic ratio.

[0050] The filling rate of the film formation target is 90% or more and 100% or less, preferably 95% or more and 100% or less. By using a film formation target with a high filling rate, the oxide semiconductor film formed The conductive film can be a dense film.

[0051] The sputtering gas is a rare gas (typically argon), oxygen, or a rare gas and oxygen. The sputtering gas may contain hydrogen, water, hydroxyl groups, or a mixture of hydrogen and water. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0052] The oxide semiconductor film is preferably formed while the substrate is heated. The substrate is held in the film-forming chamber, and the substrate temperature is set to 100°C or more and 600°C or less, preferably 200°C or less. The impurity concentration in the oxide semiconductor film is reduced by forming the film at a temperature of 200°C or higher and 400°C or lower. It is possible.

[0053] In order to remove residual moisture in the film-forming chamber, an adsorption-type vacuum pump, for example, a cryo- It is preferable to use a pump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo molecular pump with a cold trap added. The film-forming chamber, which is evacuated using a cryopump, contains, for example, hydrogen atoms, chemical compounds containing hydrogen atoms such as water, etc. Since the oxide semiconductor film formed in the film formation chamber is exhausted, the oxide semiconductor film is The concentration of impurities contained in the film can be reduced.

[0054] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions are: direct current (DC) power supply 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, powdery substances (particles, etc.) generated during film formation are This reduces the thickness (also called "film thickness") and makes the film thickness distribution uniform.

[0055] Next, the oxide semiconductor film is subjected to a first photolithography step and an etching step to form an island. The oxide semiconductor layer 106 is then processed into a crystalline oxide semiconductor layer 106 (see FIG. 2B).

[0056] The resist mask used in the photolithography process is formed by an inkjet method. The inkjet method does not require a photomask, which reduces manufacturing costs. It is possible.

[0057] Here, the oxide semiconductor film is etched by dry etching or wet etching. For example, a wet oxide semiconductor film may be used. The etching solution used for etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0058] Next, the oxide semiconductor layer 106 is dehydrated or dehydrogenated by first heat treatment. In the specification, dehydration or dehydrogenation refers only to the elimination of water or hydrogen molecules. This does not only include the elimination of hydrogen atoms and hydroxyl groups, but also includes the elimination of hydrogen atoms and hydroxyl groups.

[0059] Excess hydrogen (including water and a hydroxyl group) is removed by this heat treatment, and the oxide semiconductor layer 106 The impurity level in the energy gap can be reduced. The temperature of the heat treatment is 250°C. or higher than 650°C or lower, preferably 350°C or higher and 500°C or lower, more preferably 390°C or higher The heat treatment time is set to 460°C or less. If the temperature is within the above-mentioned preferable range, the heat treatment can be performed for about one hour. The heat treatment may be carried out in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.). In an atmosphere between 500°C and 750°C (or a temperature below the distortion point of the glass substrate) RTA (Ra) at 650°C for 1 minute to 10 minutes, preferably 650°C for 3 minutes to 6 minutes These heat treatment methods may also be used. The method may be appropriately determined by a practitioner. The heat treatment for hydrogenation is not limited to this timing, but may be performed during the photolithography process or the formation process. It may be performed multiple times before and after the film process. In that case, the heat treatment is performed in an atmosphere containing oxygen. You may also do the following.

[0060] In addition, the heat treatment of the oxide semiconductor is performed on the oxide semiconductor film before it is processed into the island-shaped oxide semiconductor layer. In this case, the photolithography process is carried out after the heat treatment. In addition, if the heat treatment is performed after the oxide semiconductor film is formed, the source electrode layer is formed on the island-shaped oxide semiconductor layer. The deposition may be performed after the drain electrode layer is laminated.

[0061] Next, a buffer layer and a metal layer are formed on the insulating layer 102 and the oxide semiconductor layer 106. The buffer layer and the metal layer can be made of the materials described above. A single layer of indium tin oxide was formed as the thin film and a single layer of tungsten as the metal layer by sputtering. Complete.

[0062] Next, a resist mask is formed on the metal layer by a second photolithography process, and a selective The buffer layer 107a and the source electrode layer 102 that form the source region are selectively etched. 8a, and a buffer layer 107b and a drain electrode layer 108b which constitute the drain region are formed. Then, the resist mask is removed (see FIG. 2(C)).

[0063] Note that when the source and drain regions are formed, the oxide semiconductor layer 106 is etched as little as possible. However, it is preferable to etch only the metal layer and the buffer layer. It is difficult to obtain the etching conditions for the oxide semiconductor during etching of the metal layer and the buffer layer. A part of the conductor layer 106 may be etched to have a shape with a groove (recess). In addition, the source electrode layer 108a is formed on the buffer layers 107a and 107b so as to have a step. A drain electrode layer 108b may be formed.

[0064] Next, a gate insulating layer 112 is formed on the source region, the drain region, and the oxide semiconductor layer 106. Here, silicon oxide is used as the gate insulating layer 112 (see FIG. 2(D)). It is formed by sputtering.

[0065] The gate insulating layer 112 can be formed as a dense, high-quality insulating layer with high dielectric strength. Even if it is formed by high density plasma CVD using microwaves (for example, frequency 2.45 GHz), The oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, which reduces the interface state. It is possible.

[0066] In addition, the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor layer are improved by heat treatment after film formation. In any case, the gate insulating layer 112 has a good film quality. In addition, it is possible to reduce the interface state density with the oxide semiconductor layer and form a good interface. It is preferable to use something that can be used.

[0067] After the gate insulating layer 112 is formed, second heat treatment is preferably performed. The temperature is 250°C or higher and 700°C or lower, preferably 350°C or higher and 600°C or lower, or It is less than the strain point.

[0068] The second heat treatment may be carried out in an oxidizing gas atmosphere or an inert gas atmosphere. It is preferable that the gas does not contain water, hydrogen, etc. Also, the purity of the gas introduced into the heat treatment device 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., It is preferable to keep the concentration of impurities at 1 ppm or less, preferably 0.1 ppm or less.

[0069] In the second heat treatment, the oxide semiconductor layer 106 and the gate insulating layer 112 containing oxygen are in contact with each other. Therefore, oxygen, which is one of the main components of oxide semiconductors, is removed by heating. The oxide semiconductor layer 106 can be supplied with the oxide from the insulating layer 112. Oxygen vacancies in the oxide semiconductor layer 106 and the interface between the oxide semiconductor layer 106 and the gate insulating layer 112 At the same time, defects in the gate insulating layer 112 can also be reduced. can be done.

[0070] The timing of the second heat treatment is not particularly limited as long as it is performed after the gate insulating layer 112 is formed. For example, the second heat treatment may be performed after the gate electrode layer 114 is formed.

[0071] Next, after forming a conductive film, a third photolithography step and an etching step are performed to form a gate electrode. A gate electrode layer 114 is formed (see FIG. 2(E)). A laminate of tantalum nitride and tantalum nitride is formed by sputtering.

[0072] Although not shown in the drawings, an insulating layer may be formed on the gate insulating layer 112 and the gate electrode layer 114. The insulating layer may be a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, Ga x Al 2-x O 3+y (0 ≦ x ≦ 2, 0 < y < 1, where x is a value from 0 to 2 and y is a value greater than 0 and less than 1), such as aluminum oxide, gallium oxide, or gallium aluminum oxide, and an inorganic insulating film can be used.

[0073] Furthermore, a protective insulating layer for improving reliability may be formed on the insulating layer. The protective insulating layer may be an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film.

[0074] In addition, a planarizing insulating film may be formed on the insulating layer or the protective insulating layer to reduce surface unevenness caused by the transistor. As the planarizing insulating film, organic materials such as polyimide, acrylic, and benzocyclobutene can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0075] The transistor 151 is formed through the above steps.

[0076] As described above, a semiconductor device with good electrical characteristics can be provided.

[0077] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0078] (Embodiment 2) A semiconductor device having a display function (a display device) using the transistor described in Embodiment 1 as an example In addition, a part or the whole of a driver circuit including a transistor can be manufactured. The pixel portion and the display portion can be integrally formed on the same substrate to form a system-on-panel.

[0079] In FIG. 3A, a pixel portion 202 provided on a first substrate 201 is surrounded by a A sealant 205 is provided, and the device is sealed with a second substrate 206. In this case, the area other than the area surrounded by the sealing material 205 on the first substrate 201 A scanning line driver circuit 204 and a signal line driver circuit 205 are formed of a single crystal semiconductor or a polycrystalline semiconductor. A signal line driver circuit 203 and a scanning line driver circuit 204 are also mounted. Various signals and potentials given to the pixel portion 202 are transmitted through an FPC (Flexible Printed Circuit). ted circuits) 218a, 218b.

[0080] In FIG. 3B and FIG. 3C, a pixel portion 202 provided on a first substrate 201, A sealing material 205 is provided so as to surround the scanning line driving circuit 204. A second substrate 206 is provided on the display unit 202 and the scanning line driving circuit 204. The element portion 202 and the scanning line driving circuit 204 are connected to the first substrate 201, the sealing material 205, and the second substrate 202. The display element is sealed with the substrate 206. In this case, the area other than the area surrounded by the sealing material 205 on the first substrate 201 A signal line driver circuit 203 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted on the 3B and 3C, a signal line driver circuit 203 and Various signals and potentials applied to the scanning line driver circuit 204 or the pixel portion 202 are transmitted through the FPC 21 It is supplied via 8a.

[0081] In addition, in FIG. 3B and FIG. 3C, the signal line driver circuit 203 is formed separately, and the first However, the present invention is not limited to this configuration. The circuit may be formed separately and mounted, or may be mounted as part of a signal line driver circuit or a scanning line driver circuit. Alternatively, only the wiring may be formed separately and mounted.

[0082] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape Auto The COG method can be used. 3B is an example in which a signal line driver circuit 203 and a scanning line driver circuit 204 are mounted. 3(C) is an example of mounting the signal line driver circuit 203 by the COG method, and FIG. 3(D) is an example of mounting the signal line driver circuit 203 by the TAB method. This is an example in which the signal line driver circuit 203 is implemented by the following.

[0083] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to modules with FPC or TAB tape attached, A module with a printed wiring board at the end of TAB tape, or a display element with a COG method According to the formula, all modules on which ICs (integrated circuits) are directly mounted are also included in the display device. .

[0084] In addition, the pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. For this purpose, the transistor shown as an example in Embodiment 1 can be used.

[0085] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Also includes electronic devices such as electronic ink. A display medium whose contrast changes due to an electrochemical effect can also be used.

[0086] One embodiment of the display device will be described with reference to FIGS. 4 to 6. FIGS. 4 to 6 are the same as those in FIG. 3(B). ) corresponds to a cross section at MN.

[0087] As shown in FIGS. 4 to 6, the semiconductor device has a connection terminal electrode 215 and a terminal electrode 216. The connection terminal electrodes 215 and the terminal electrodes 216 are anisotropically connected to the terminals of the FPC 218. They are electrically connected via a conductive layer 219 .

[0088] The connection terminal electrode 215 is formed of the same conductive layer as the first electrode layer 230, and the terminal electrode 216 is , the source and drain electrodes of transistor 210 and transistor 211 are the same conductor. The conductive layer is formed of a conductive material.

[0089] The pixel portion 202 and the scanning line driver circuit 204 provided on the first substrate 201 are 4 to 6, the pixel portion 202 includes a transistor 21. 0 and a transistor 211 included in the scanning line driver circuit 204 are illustrated.

[0090] In this embodiment, the transistors 210 and 211 are the transistors shown in the first embodiment. The transistors 210 and 211 have excellent electrical characteristics. A display device with high display capabilities can be constructed.

[0091] The transistor 210 provided in the pixel portion 202 is electrically connected to a display element, and The display element is not particularly limited as long as it can display, and various display elements can be used. You can be there.

[0092] FIG. 4 shows an example of a liquid crystal display device using liquid crystal elements as display elements. The liquid crystal element 213 includes a first electrode layer 230, a second electrode layer 231, and a liquid crystal layer 20. 8. In addition, insulating layers 232 and 233 functioning as alignment layers are arranged to sandwich the liquid crystal layer 208. The second electrode layer 231 is provided on the second substrate 206 side, and the first electrode The polar layer 230 and the second electrode layer 231 are laminated with the liquid crystal layer 208 interposed therebetween. Also, a color filter 237 for color display is provided on the opposing substrate side. However, it may be provided on the substrate side where the transistor is formed. , the color filter 237 is not necessary.

[0093] The transistors 210 and 211 are provided in the lower layer with a backlight or the like to protect the channels of the transistors. Light-shielding layers 238a and 238b are provided to block light from being irradiated onto the formation region. There is no restriction on the material that can be used for the layer, as long as it is a material with high light-shielding properties. For example, metal When a layer is used, it can function not only as a light-shielding layer but also as a second gate electrode. This can be done.

[0094] In addition, on the opposing substrate side, the area located above the transistors 210 and 211 is also light-shielded. A layer 236 is provided to protect the transistor from light irradiation. 236 also acts as a black matrix in the display area, improving display quality. It is possible.

[0095] As described above, by blocking the light irradiating the transistors 210 and 211, the oxide semiconductor This can suppress the photodegradation phenomenon that is a problem with transistors that use semiconductors, and can be used for a long period of time. This can suppress the deterioration of the threshold voltage.

[0096] The spacers 235 are columnar spacers obtained by selectively etching an insulating layer. It is provided to control the layer thickness (cell gap) of the liquid crystal layer 208. Spherical spacers may also be used.

[0097] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystal may be a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like. These liquid crystal materials can be in a cholesteric phase, smectic phase, cubic phase, or chromatic phase depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0098] Alternatively, a liquid crystal exhibiting a blue phase may be used, which does not require an alignment layer. It is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, it changes from the cholesteric phase to the isotropic phase. This is the phase that appears just before the transition to the blue phase. Since the blue phase appears only in a narrow temperature range, To improve the temperature range, 5% by weight or more of chiral agent and ultraviolet curing resin are mixed. The liquid crystal composition is then irradiated with ultraviolet light to form a liquid crystal layer. This liquid crystal layer exhibits a blue phase over a wide temperature range. The response speed is short, less than 1 msec. Since no alignment layer is required, the viewing angle dependency is small. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. Therefore, defects and damage to the liquid crystal display device during the manufacturing process can be reduced. In addition, when a blue phase is used, the structure of FIG. However, the present invention is not limited to the above, and may be applied to a structure in which the second electrode layer 231 is formed on the same substrate side as the first electrode layer 230. A so-called transverse electric field mode configuration may also be used.

[0099] The specific resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω· cm or more, more preferably 1 × 10 12 Ω·cm or more. The resistivity value is measured at 20°C.

[0100] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set to be able to hold charge for a certain period of time, taking into consideration factors such as the current. By using a transistor with a semiconductor layer, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0101] The transistor including the highly purified oxide semiconductor layer used in this embodiment has an off state. Therefore, the current value (off-state current value) at the time of the image signal or the like can be reduced. The signal retention time can be extended, and the write interval can also be set longer when the power is on. Therefore, the frequency of refresh operations can be reduced, which is effective in reducing power consumption. To bear fruit.

[0102] In addition, the transistor using the highly purified oxide semiconductor layer used in this embodiment has a relatively low Since a relatively high field effect mobility can be obtained, high speed driving is possible. By using the above transistor in the pixel portion, a high-quality image can be provided. In addition, a driver circuit portion can be formed over the same substrate using the transistor. The number of parts in the liquid crystal display device can be reduced.

[0103] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (Antiferroelectric Liq. uid Crystal) mode can be used.

[0104] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type liquid crystal display device. This is a method of controlling the arrangement of crystal molecules, and when no voltage is applied, In this method, the liquid crystal molecules are aligned vertically. There are several types of vertical alignment modes: However, for example, MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used. Also, pixels can be divided into several It is a multi-layer structure that is divided into regions (sub-pixels) and designed to tilt the molecules in different directions in each region. A method known as domaining or multi-domain design can be used.

[0105] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0106] In addition, multiple light-emitting diodes (LEDs) are used as backlights, and a time-division display system is used. It is also possible to perform field sequential driving. By applying the color drive method, color display can be achieved without using a color filter. This can be done.

[0107] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB ( It is not limited to the three colors R represents red, G represents green, and B represents blue. For example, RGBW (W represents white) or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may also be applied to monochrome display devices. It is also possible to do so.

[0108] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0109] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These carriers are then injected into a layer containing a light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, Light is emitted when the excited state returns to the ground state. This is called a current-excited light-emitting element.

[0110] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0111] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite the substrate. Top emission, bottom emission where light is extracted from the surface on the substrate side, and surface on the substrate side and the opposite side of the substrate There are light emitting devices with a double-sided emission structure that extracts light from the It is possible.

[0112] FIG. 5 shows an example of a light-emitting device using a light-emitting element as a display element. The transistor 43 is electrically connected to the transistor 210 provided in the pixel portion 202. The optical element 243 is configured by a first electrode layer 230, an electroluminescent layer 241, and a second electrode layer 231. Although the laminated structure is used, it is not limited to the configuration shown. The configuration of the light emitting element 243 can be changed appropriately depending on the situation.

[0113] The partition wall 240 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 230 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the inclined surface so as to have a slope.

[0114] The electroluminescent layer 241 may be composed of a single layer or a plurality of layers stacked together. It doesn't matter whether it's

[0115] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 243. A protective layer may be formed on the barrier ribs 231 and 240. Examples of the protective layer include a silicon nitride layer, A silicon nitride oxide layer, a DLC layer, etc. can be formed. A filler 244 is provided in the space sealed by the second substrate 206 and the sealant 205. In this way, the container is airtight and has little degassing, so that it is not exposed to the outside air. Packaging with protective film (laminating film, UV curing resin film, etc.) or cover material It is preferable to encase the compound.

[0116] The filler 244 may be an inert gas such as nitrogen or argon, or may be an ultraviolet curing resin or a heat-curing resin. Hardening resins can be used, such as PVC (polyvinyl chloride), acrylic resin, and polyimide. Mido resin, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (ethylene vinyl acetate) can be used.

[0117] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection layer may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0118] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0119] Electrophoretic display devices come in various forms, but they are primarily composed of positively charged particles and negatively charged particles. A plurality of microcapsules containing a first particle and a second particle having a charge are dispersed in a solvent or solute. By applying an electric field to the microcapsules, The particles are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless). .

[0120] In this way, the electrophoretic display device is a device in which a substance with a high dielectric constant moves to a region with a high electric field. This is a display that utilizes the dielectrophoretic effect.

[0121] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0122] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, a semiconductor, or the like. Conductive materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A material selected from magnetochromic materials, magnetophoretic materials, or a composite material of these materials is used. That's fine.

[0123] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles by generating a potential difference between the electrode layers. do.

[0124] FIG. 6 shows an active matrix electronic paper as one mode of a semiconductor device. The electronic paper is an example of a display device that uses the twisting ball display method.

[0125] The first electrode layer 230 connected to the transistor 210 and the second electrode layer 230 provided on the second substrate 206 Between the second electrode layer 231, there are a black area 255a and a white area 255b, and the liquid A spherical particle 253 is provided that includes a cavity 252 that is filled with a body, and the spherical particle The periphery of the second electrode layer 231 is filled with a filler 254 such as resin. The second electrode layer 231 corresponds to an electrode (counter electrode). The second electrode layer 231 is electrically connected to a common potential line.

[0126] 4 to 6, the first substrate 201 and the second substrate 206 are glass substrates. In addition to the plate, a flexible substrate can also be used, for example, a light-transmitting plastic substrate. As for plastic, FRP (Fiberglass- Reinforced Plastics (PVF) plate, PVF (Polyvinyl Fluoride) film Film, polyester film or acrylic resin film can be used. A sheet with aluminum foil sandwiched between PVF film or polyester film is used. You can also be there.

[0127] The insulating layer 221 can be formed using an inorganic insulating material or an organic insulating material. , acrylic resin, polyimide, benzocyclobutene resin, polyamide, epoxy resin, etc. When the above-mentioned organic insulating material having heat resistance is used, it is suitable for the planarizing insulating layer. In addition to organic insulating materials, low-k materials, siloxane resins, PSG (P BPSG (Boron Pho It is also possible to use sphorus silicate glass. The insulating layer 221 may be formed by stacking a plurality of insulating layers made of these materials. .

[0128] The method for forming the insulating layer 221 is not particularly limited, and may be a sputtering method, a spin coating method, or the like, depending on the material. method, dipping method, spray coating method, droplet ejection method (inkjet method, screen printing method) printing method, offset printing method, etc.), roll coating method, curtain coating method, A coating method or the like can be used.

[0129] A first electrode layer 230 and a second electrode layer 231 (pixel electrode layers, commonly referred to as "electrodes") that apply a voltage to the display element are provided. In the case of a layer (also called a conducting electrode layer or a counter electrode layer), the direction of the light to be extracted is determined by the electrode layer. The transparency or reflectivity can be selected depending on the location and the pattern structure of the electrode layer.

[0130] The first electrode layer 230 and / or the second electrode layer 231 may contain titanium oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium stannate oxide (hereinafter referred to as ITO), indium zinc oxide, and silicon-doped indium tin oxide. A light-transmitting conductive material such as an oxide can be used.

[0131] Either the first electrode layer 230 or the second electrode layer 231 is made of tungsten (W). , Molybdenum (Mo), Zirconium (Zr), Hafnium (Hf), Vanadium (V) , niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel ( Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag ) or its alloys, or its nitrides, and It can be achieved.

[0132] In addition, either the first electrode layer 230 or the second electrode layer 231 is made of a conductive polymer (conductive The conductive layer can be formed using a conductive composition containing a conductive polymer. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Phosphorus or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, or Derivatives and the like are included.

[0133] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0134] As described above, a display device with good display performance can be obtained by using the transistor described in Embodiment 1. Note that the transistor described in Embodiment 1 can provide the above-described display function. Not only semiconductor devices having the above, but also power devices mounted on power supply circuits, LSIs and memories semiconductor integrated circuits such as those mentioned above, and semiconductor devices having an image sensor function for reading information of an object The present invention can be applied to semiconductor devices having various functions such as the above.

[0135] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0136] (Embodiment 3) The semiconductor device of one embodiment of the present invention can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the semiconductor device described in the first or second embodiment include: We will explain about this.

[0137] FIG. 7A shows a notebook personal computer, which includes a main body 301, a housing 302, a display It is composed of a display unit 303, a keyboard 304, and the like.

[0138] FIG. 7B shows a personal digital assistant (PDA), which has a main body 311 including a display unit 313 and an external interface. The device is provided with an interface 315, operation buttons 314, and other accessories for operation. There is a Stylus 312 as an example.

[0139] FIG. 7C shows an example of an electronic book. For example, an electronic book 320 includes a housing 321 and The housing 321 and the housing 322 are made up of a shaft 325. The shaft 325 is an axis around which the opening and closing operation can be performed. This configuration makes it possible to handle it like a paper book.

[0140] A display unit 323 is incorporated in the housing 321, and a display unit 324 is incorporated in the housing 322. The display unit 323 and the display unit 324 may be configured to display successive images, It is also possible to configure the display of different images. For example, a sentence is displayed on the right display unit (display unit 323 in FIG. 7(C)) and a sentence is displayed on the left display unit (display unit 324 in FIG. 7(C)). In C), photographs and pictures can be displayed on the display unit 324).

[0141] 7C shows an example in which an operation unit and the like are provided on the housing 321. 321 includes a power supply 326, operation keys 327, a speaker 328, etc. The page can be turned by pressing the operation key 327. The keyboard is on the same surface as the display unit of the housing. The housing may be provided with a display, a pointing device, etc. It is configured with external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary. good.

[0142] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0143] FIG. 7D shows a mobile phone, which is composed of two housings, housing 330 and housing 331. The housing 331 contains a display panel 332, a speaker 333, a microphone 334, a The device is equipped with an imaging device 336, a camera 337, an external connection terminal 338, etc. The housing 330 also includes a solar cell 340 for charging the portable information terminal, an external memory slot, and 341, etc. The antenna is built into the housing 331.

[0144] The display panel 332 is also equipped with a touch panel, and in FIG. 7(D) an image is displayed. The voltage output from the solar cell 340 is indicated by a dotted line. A boost circuit is also implemented to boost the voltage required for each circuit.

[0145] The display direction of the display panel 332 changes appropriately depending on the usage mode. The camera 337 is located on the same surface as the speaker 32, allowing video calls. 333 and microphone 334 are not limited to voice calls, but also allow video calls, recording, playback, etc. Furthermore, the housing 330 and the housing 331 can be slid and unfolded as shown in FIG. 7(D). The device can be folded from a closed state to an overlapping state, making it possible to miniaturize it for portability.

[0146] The external connection terminal 338 can be connected to various cables such as a charging cable or a USB cable. It is possible to charge the battery and to communicate data with a personal computer. A recording medium can be inserted into the reslot 341 to accommodate the storage and transfer of larger amounts of data.

[0147] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0148] FIG. 7(E) shows a digital video camera, which includes a main body 351, a display unit (A) 357, and an eyepiece. 353, an operation switch 354, a display unit (B) 355, a battery 356, etc. It has been done.

[0149] 7F shows an example of a television device. The television device 360 ​​has a housing The display unit 363 is incorporated in the camera 361. The display unit 363 can display images. Also, here, a configuration in which the housing 361 is supported by a stand 365 is shown. There are.

[0150] The television device 360 ​​can be operated using an operation switch provided on the housing 361 or a separate remote control. This can be done by the remote control unit. A display unit for displaying the information may be provided.

[0151] The television device 360 ​​is configured to include a receiver, a modem, etc. It is possible to receive general television broadcasts, and also to receive them by wired or wireless connection via a modem. By connecting to a communication network, it can be transmitted in one direction (sender to receiver) or two directions ( It is also possible to communicate information between a sender and a receiver, or between receivers.

[0152] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Example]

[0153] In this example, the transistor having the n-type buffer layer described in Embodiment 1 was We fabricated the transistor and compared its electrical characteristics and reliability with those of a conventional transistor. Reveal.

[0154] A transistor having a structure corresponding to that shown in FIG. 8A was manufactured according to the manufacturing method of Embodiment 1. The transistor is configured as a 300 nm thick silicon oxide film as an insulating layer 102, which is a base layer. The oxide semiconductor layer 106 is an In-Ga-Zn -O film, and 5 nm of indium containing silicon (Si) as buffer layers 107a and 107b. Indium tin oxide (ITO) film or indium zinc oxide (IZO) film, source The electrode layer 108a and the drain electrode layer 108b are made of a 100 nm tungsten film, and the gate The insulating layer 112 is a 15 nm silicon oxynitride film, and the gate electrode layer 114 is a gate insulating film. From the edge layer 112 side, a tantalum nitride film of 15 nm and a tungsten film of 135 nm were laminated. .

[0155] Although not shown in FIG. 8A, the gate electrode layer 114 and the gate insulating layer 112 are A 300 nm silicon oxide film was formed by sputtering as an interlayer insulating film on the The source electrode layer 108a and the drain electrode layer 108b are electrically connected to each other through contact holes formed in the interlayer insulating film. As a wiring layer connected to the gate electrode layer 114, a 50 nm titanium A 100 nm thick silicon film, a 100 nm thick aluminum film, and a 5 nm thick titanium film were formed on the wiring layer. This was formed as an extraction electrode when obtaining the electrical characteristics of the transistor.

[0156] First, we fabricated transistors (L = 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, On-resistance of 0.8μm, 0.9μm, 2μm, 3μm, 5μm, 10μm, W=10μm) Based on the data on the L length dependence of the resistance, TLM (Transmission Line Mode The parasitic resistance between the semiconductor layer and the source / drain electrodes was calculated using the transmission line model. In addition, the IV characteristics (drain The field effect mobility was calculated using the following conditions: voltage = 3V, gate voltage = -6V to +6V. are shown in Table 1. Here, the field effect mobility indicates the maximum value within the above gate voltage, Three types of transistors (without buffer layer, with ITO or IZO containing Si as buffer layer) Twelve samples of each type were measured, and the median values ​​are shown.

[0157] [Table 1]

[0158] From the results in Table 1, the transistor with an n-type buffer layer has a semiconductor layer and a source / drain The parasitic resistance between the n-electrodes was reduced by approximately 40%, demonstrating the effectiveness of the n-type buffer layer. As a result, the on-current characteristics are improved and the field effect mobility is improved by about 9% to 10%. The results were also confirmed.

[0159] Furthermore, for a transistor with L / W=3 μm / 50 μm fabricated in the same manner as above, The gate BT (voltage-thermal) stress test was performed. D, +0.1V to the drain, +3V (+2MV / cm) and -3V (-2MV / cm) to the gate m), +9V (+6MV / cm), or -9V (-6MV / cm) at 150°C for 1 hour. The test was carried out under the condition that a voltage was applied for a short time.

[0160] In the above tests, applying +3V, -3V, or +9V to the gate was used to verify the effectiveness of the buffer layer. No difference was observed when no voltage was applied, but when -9V was applied, the on-voltage The degradation of the current (current when the gate voltage is 3 V) is smaller for transistors with a buffer layer. The degradation rate of the on-state current obtained from Figures 9(A), (B), and (C) is shown in 2. Here, the initial on-current is defined as the current value when the gate voltage is 3 V. The on-current after negative gate BT stress is The current value is defined as the difference between the threshold voltages after stress.

[0161] [Table 2]

[0162] From this result, the transistor with a buffer layer has a higher It can be seen that the buffer also has the effect of significantly reducing the degradation rate of the on-state current. As a layer, the degradation rate of the on-current can be suppressed more effectively by using ITO containing Si than by using IZO. It was also found that

[0163] Regarding the results of the negative gate BT stress test (suppression of the decrease in on-current), Scientific calculations were performed to investigate the causes.

[0164] The model used for the scientific calculations is basically the configuration shown in Figure 8(A). Considering the structure, the model without a buffer layer is based on the film loss of the oxide semiconductor layer in the channel formation region. The model with a buffer layer is shown in Fig. 13(A). Based on the results of EM observation, the taper angle of the edge was set to 30°, and the oxide in the channel formation region was The thickness of the semiconductor layer was reduced to 10 nm. This is a schematic diagram of the

[0165] The transistor size is L / W=3 / 50μm, and the gate insulating film (silicon oxynitride The film thickness of the oxide semiconductor is 15 nm, the band gap (Eg) of the oxide semiconductor is 3.15 eV, and the electron The affinity (χ) is 4.3 eV, the dielectric constant is 15, and the electron mobility is 10 cm 2 / Vs was assumed. The oxide semiconductor layer that becomes the channel formation region is a uniform amorphous, n-type buffer The layer is a high concentration (1 × 10 20 / cm 3 We assumed an oxide semiconductor containing n-type donors. The band gap and electron affinity of the buffer layer are determined by the oxide semiconductor layer that becomes the channel formation region. Using the same value, the resistivity is 3×10 -3 The electron mobility value was determined to be Ω·cm The work function of the gate metal is 4.9 eV (assuming tungsten), and the source / drain metal The work function of the device is assumed to be 4.5 eV (assuming molybdenum), and the calculation is based on a Synopsys device. The simulator Sentaurus Device was used.

[0166] Figure 10 shows the negative gate BT stress (gate voltage = -9V) applied to each transistor. The electric field strength distribution diagram when a voltage of +0.1 V and a drain voltage of 150°C are applied is shown. As a result of the calculation, it was found that electric field concentration occurs in a part of the oxide semiconductor layer, as shown by the arrow in the figure. In the figure, OS means an oxide semiconductor layer, and GI means a gate insulating layer. .

[0167] Next, we assume that electron traps are formed by negative gate BT stress and then consider the electric field concentration. Calculations for the case where a negative charge is fixed at the position where the charge is released (the interface between the oxide semiconductor layer and the gate insulating layer). The results are shown in Figures 11 and 12.

[0168] The negative charge has a surface density of 1 x 10 13 cm -2 The IV characteristics with and without negative charge are Calculations were made to see whether the phenomenon of on-current degradation in the negative gate BT stress test could be reproduced. In addition, a negative charge was also inserted at the same position on the source side to ensure symmetry.

[0169] As a result, as shown in FIG. 11, when the drain voltage was +0.1 V, In this model, the on-current is significantly reduced, and the IV characteristics of Figure 9(A) can be reproduced. A decrease in on-current was also observed in the model with a buffer layer in Figure 11. However, the amount is small, and in this respect, the IV characteristics of Figures 9(B) and 9(C) are reproduced. It can be said that this is the case.

[0170] In the current density distribution diagram of Figure 11 (gate voltage = +3V, drain voltage = +0.1V), In the model without a buffer layer, the negative charge repels electrons at the interface of the gate insulating layer, It can be seen that a depletion layer is formed around the charge. This depletion layer exists in the current path. On the other hand, in the model with a buffer layer, the n-type Since electrons are supplied from the buffer layer, the depletion layer is very small even if negative charges exist. This is thought to suppress the decrease in on-state current.

[0171] In the current density distribution diagram of Figure 12 (gate voltage = +3V, drain voltage = +3V), Even in a model without a buffer layer, it was confirmed that current flows by bypassing the depletion layer caused by negative charges. When the drain voltage is high (in the saturated region), the gate is pulled by the drain electric field. Since current flows even at positions far from the insulating layer interface, it is thought that the current flows by bypassing the negative charge. Therefore, when the drain voltage is high, the on-state current due to the negative gate BT stress is It can be said that a decrease in flow is unlikely to occur.

[0172] As a result of the above, the phenomenon of the decrease in on-current after negative gate BT stress shown in Figure 9 is This could be explained by the results of scientific calculations.

[0173] This example can be implemented in appropriate combination with the configurations described in other embodiments. . [Explanation of symbols]

[0174] 100 boards 102 Insulating layer 106 Oxide semiconductor layer 107a Buffer layer 107b Buffer layer 108a Source electrode layer 108b Drain electrode layer 112 Gate insulating layer 114 gate electrode layer 151 transistors 201 Substrate 202 Pixel section 203 Signal line driver circuit 204 Scanning line driving circuit 205 Sealing material 206 Substrate 208 Liquid Crystal Layer 210 Transistor 211 Transistor 213 Liquid crystal element 215 Connection terminal electrode 216 Terminal electrode 218 FPC 218a FPC 218b FPC 219 Anisotropic Conductive Layer 221 Insulating layer 230 Electrode layer 231 Electrode layer 232 Insulating layer 233 Insulating Layer 235 Spacer 236 Light blocking layer 237 Color Filter 238a Light blocking layer 238b Light blocking layer 240 Bulkhead 241 Electroluminescent Layer 243 Light-emitting element 244 Filling material 252 Cavity 253 Spherical particles 254 Filling material 255a black area 255b White area 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 322 Case 323 Display section 324 Display section 325 Shaft 326 Power supply 327 Operation Key 328 speakers 330 cabinet 331 Case 332 Display Panel 333 Speaker 334 Microphone 335 Operation Key 336 Pointing Device 337 Camera 338 External connection terminal 340 solar cells 341 external memory slot 351 Main Unit 353 Eyepiece 354 Operation switch 355 Display section (B) 356 Battery 357 Display section (A) 360 Television Equipment 361 Case 363 Display section 365 Stand

Claims

1. a first conductive film that functions as a gate electrode of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a first film having a region in contact with an upper surface of the oxide semiconductor film and having conductivity; a second film having a region in contact with an upper surface of the oxide semiconductor film and having conductivity; a second conductive film having a region in contact with an upper surface of the first film; a third conductive film having a region in contact with an upper surface of the second film, the second conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the third conductive film contains aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the first film has a first region that does not overlap with the second conductive film; the first region has a region on its upper surface that is not in contact with the second conductive film, the second film has a second region that does not overlap with the third conductive film; the second region has a region on an upper surface thereof that is not in contact with the third conductive film, a side surface of the first region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the first region form a first angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second conductive film form a second angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second region form a third angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the third conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the third conductive film form a fourth angle in a cross-sectional view taken along a channel length direction of the transistor; the first angle is smaller than the second angle; the third angle is smaller than the fourth angle; Semiconductor device.

2. a first conductive film that functions as a gate electrode of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a first film having a region in contact with an upper surface of the oxide semiconductor film and having conductivity; a second film having a region in contact with an upper surface of the oxide semiconductor film and having conductivity; a second conductive film having a region in contact with an upper surface of the first film; a third conductive film having a region in contact with an upper surface of the second film, the first film and the second conductive film function as one of a source electrode and a drain electrode, the second film and the third conductive film function as the other of the source electrode and the drain electrode, the second conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the third conductive film contains aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the first film has a first region that does not overlap with the second conductive film; the first region has a region on its upper surface that is not in contact with the second conductive film, the second film has a second region that does not overlap with the third conductive film; the second region has a region on an upper surface thereof that is not in contact with the third conductive film, a side surface of the first region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the first region form a first angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second conductive film form a second angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second region form a third angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the third conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the third conductive film form a fourth angle in a cross-sectional view taken along a channel length direction of the transistor; the first angle is smaller than the second angle; the third angle is smaller than the fourth angle; Semiconductor device.

3. In claim 1 or claim 2, the oxide semiconductor film contains indium oxide; Semiconductor device.

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