Semiconductor device

Abstract

To provide a semiconductor device having good electrode connection and good device characteristics.SOLUTION: A first conductivity type drift region 13 formed in a surface layer portion of the first main surface 2a and a second main surface 2b on the other side, a plurality of second conductivity type body regions 14 formed in a surface layer portion of the drift region 13, first conductivity type source regions 15 formed in surface layer portions of the body regions 14, a plurality of gate electrodes 11 formed in the first main surface 2a, spaced apart from each other in a first direction X along the first main surface 2a, each extending in a second direction Y intersecting the first direction X, and disposed between the body regions 14, and second conductivity type contact regions 16 formed in the body regions 14 and having a higher impurity concentration than the body regions 14. 2a.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes - The document discloses a semiconductor device having a planar gate type MOS gate structure on the main surface of a p-type semiconductor substrate. A p-type base region is provided in the surface layer of the main surface of the semiconductor substrate. A pair of n-type base regions is provided inside the p-type base region. + Type source region and p + A pair of n-type contact regions are provided. + The type source region is p + The gate insulating film is provided on the main surface of the semiconductor substrate, and a gate electrode is provided on the surface of the gate insulating film. An interlayer insulating film is provided to cover the gate electrode. A barrier metal film is provided to cover the interlayer insulating film. The interlayer insulating film and the gate insulating film have a pair of n-type contact regions. + Type source region and p + A contact opening is formed to expose the n-type contact region. + The barrier metal film is disposed between a pair of gate electrodes provided corresponding to the n-type source regions, respectively. + Type source region and p + The source electrode is formed on the barrier metal film and is in contact with the contact region. The source electrode is made mainly of aluminum and covers the barrier metal film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-197670 Summary of the Invention [Problem to be solved by the invention]

[0004] By arranging unit cells, each including a gate electrode, at high density on a semiconductor substrate, the channel width can be increased and the on-resistance can be reduced. To achieve this, the spacing between the gate electrodes is narrowed. Accordingly, the width of the contact opening becomes narrower, and the aspect ratio of the contact opening formed in the interlayer insulating film increases. The aspect ratio is defined, for example, by the ratio of the depth to the width of the contact opening.

[0005] Aluminum, a typical electrode material, does not necessarily have good filling properties in openings, so when attempting to fill a contact opening with an aluminum electrode film in a high aspect ratio, voids may occur, which may increase the contact resistance between the barrier metal and the electrode film or cause poor contact.

[0006] Therefore, one embodiment of the present invention provides a semiconductor device having good electrode connections and good device characteristics. [Means for solving the problem]

[0007] One embodiment of the present invention provides a semiconductor device including: a semiconductor layer made of SiC single crystal, having a first main surface on one side and a second main surface on the other side; a plurality of gate electrodes spaced apart on the first main surface of the semiconductor layer; a first conductivity type drift region formed in a surface layer portion of the first main surface; a second conductivity type body region formed in the surface layer portion of the drift region in an area spanning a pair of adjacent gate electrodes; and a second conductivity type contact region formed in the body region and having a higher impurity concentration than the body region. An interlayer insulating film formed on the first main surface of the semiconductor layer to cover the gate electrodes; an electrode film formed on the interlayer insulating film; and a tungsten plug disposed between the pair of adjacent gate electrodes. The tungsten plug has a bottom portion in contact with the semiconductor layer and a top portion in contact with the electrode film. The bottom of the tungsten plug is in contact with the contact region.

[0008] This configuration makes it possible to provide a semiconductor device with good electrode connection and excellent device characteristics. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a schematic plan view for explaining the internal wiring structure connected to the gate wiring. [Figure 3] FIG. 3 is an enlarged plan view of region III in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing a specific example of the configuration of the unit cell region, showing the cross-sectional structure taken along line IV-IV in FIG. [Figure 5A] FIG. 5A is a cross-sectional view for explaining the manufacturing process of the semiconductor device. [Figure 5B] FIG. 5B is a cross-sectional view for explaining the manufacturing process of the semiconductor device. [Figure 5C] FIG. 5C is a cross-sectional view for explaining the manufacturing process of the semiconductor device. [Figure 5D] FIG. 5D is a cross-sectional view for explaining the manufacturing process of the semiconductor device. [Figure 6] FIG. 6 corresponds to FIG. 4 and is a cross-sectional view for explaining the structure when a semiconductor layer made of SiC single crystal is applied to the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] As mentioned above, aluminum, a typical electrode material, does not necessarily have good filling properties in openings. Therefore, when attempting to fill a contact opening with an aluminum electrode film in a high aspect ratio, voids may occur, which may increase the contact resistance between the barrier metal and the electrode film or cause poor contact.

[0011] Therefore, the inventors of the present invention have come up with the idea of ​​using tungsten, a metal material with good filling properties in openings. Specifically, a tungsten plug is buried in the contact opening, and an aluminum film is formed on the interlayer insulating film so as to contact the tungsten plug. This solves the above problem.

[0012] However, it has been found that the stress of the tungsten plugs embedded in the contact holes can have adverse effects on devices, specifically, the stress of the tungsten plugs can cause warping of the semiconductor substrate, peeling of films, and changes in device characteristics.

[0013] This problem could be solved by reducing the size of the contact openings and the area of ​​the tungsten plugs embedded in the contact openings. However, this solution would require changing the spacing between gate electrodes and corresponding changes to the layout of the body, source, and contact regions. This means that existing device designs cannot be used at all, and all patterning masks must be newly developed.

[0014] Therefore, one embodiment of the present invention provides a semiconductor device that has good electrode connections and good device characteristics without changing the basic layout.

[0015] One embodiment of the present invention provides a semiconductor device including a semiconductor layer having a first main surface on one side and a second main surface on the other side, a plurality of gate electrodes arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film formed on the first main surface of the semiconductor layer to cover the gate electrodes, an electrode film formed on the interlayer insulating film, and a plurality of tungsten plugs arranged between pairs of adjacent gate electrodes. The plurality of tungsten plugs are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pairs of adjacent gate electrodes face each other. Each tungsten plug has a bottom portion in contact with the semiconductor layer and a top portion in contact with the electrode film.

[0016] According to this configuration, a plurality of contact openings are formed in the interlayer insulating film between a pair of gate electrodes at intervals in the opposing direction. A plurality of tungsten plugs are embedded in the plurality of contact openings. The tungsten plugs have good embedding properties in contact openings. Therefore, even if the gap between the gate electrodes is narrow and the contact openings are correspondingly small, the bottoms of the tungsten plugs make good contact with the semiconductor layer, thereby suppressing or preventing poor contact between them.

[0017] On the other hand, since the multiple tungsten plugs are embedded in the multiple contact openings distributed between a pair of gate electrodes, the stress on the tungsten plugs is small. Therefore, process problems caused by the stress on the tungsten plugs can be avoided, and poor device characteristics can be suppressed or prevented. Furthermore, since the multiple tungsten plugs are distributed between the gate electrodes, there is no need to narrow the spacing between the gate electrodes. Therefore, there is no need to change the basic layout.

[0018] The top of the tungsten plug is in contact with the electrode film formed on the interlayer insulating film, so that the electrode film is electrically connected to the semiconductor layer via the tungsten plug.

[0019] The electrode film may be made of a metal material (e.g., a metal material mainly composed of aluminum) that has a lower fillability for contact openings than tungsten. The electrode film is preferably made of a metal material that has a lower stress than tungsten. This can suppress or prevent degradation of device characteristics due to stress in the electrode film.

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0021] 1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention. In this embodiment, the semiconductor device 1 is an electronic component having a metal-insulator-semiconductor field effect transistor (MISFET).

[0022] The semiconductor device 1 includes a chip-shaped semiconductor layer 2. Specifically, the semiconductor layer 2 has a first main surface 2a on one side and a second main surface 2b on the other side (see FIG. 4). Both the first main surface 2a and the second main surface 2b are flat surfaces. FIG. 1 shows the configuration of the semiconductor device 1 in a plan view seen from a direction perpendicular to the first main surface 2a. In this embodiment, the first main surface 2a and the second main surface 2b are quadrangular, more specifically rectangular. The semiconductor layer 2 has side surfaces 2c, 2d, 2e, and 2f (four flat side surfaces in this embodiment) connecting the first main surface 2a and the second main surface 2b.

[0023] In the following description, for convenience, the direction perpendicular to the first major surface 2a and the second major surface 2b, i.e., the direction parallel to the normal to the first major surface 2a and the second major surface 2b, will be referred to as the "normal direction Z" of the semiconductor layer 2. Also, the view from the normal direction Z will be referred to as the "planar view." Furthermore, for convenience, the direction perpendicular to the normal direction Z and parallel to one side surface 2c will be referred to as the "first direction X," and the direction perpendicular to both the normal direction Z and the first direction X (the direction parallel to the other side surface 2d adjacent to the side surface 2c) will be referred to as the "second direction Y."

[0024] The semiconductor layer 2 includes an active region 3 and an outer region (peripheral region) 4. The active region 3 and the outer region 4 are set on a first main surface 2a of the semiconductor layer 2.

[0025] In plan view, the active region 3 is set in the center of the semiconductor layer 2 and spaced inward from the side surfaces 2c to 2f of the semiconductor layer 2. In plan view, the active region 3 may be set in a quadrangular shape (more specifically, rectangular shape) having four sides parallel to the four side surfaces 2c to 2f of the semiconductor layer 2. In this embodiment, the active region 3 has a recess 3a recessed inward from near the center of one side of the rectangle.

[0026] The outer region 4 is an area outside the active region 3. In plan view, the outer region 4 extends in a band shape along the periphery of the active region 3. In plan view, the outer region 4 surrounds the active region 3. More specifically, the outer region 4 is set to have an endless shape (a quadrangular ring shape) surrounding the active region 3 in plan view. In this embodiment, the outer region 4 has a protrusion 4a that protrudes inward toward the active region 3 so as to align with the recess 3a of the active region 3.

[0027] A film-like source terminal electrode 5 is disposed so as to cover almost the entire active region 3. A source pad region 5a is set in the center of the source terminal electrode 5. The source pad region 5a provides a bonding pad to which a bonding wire is bonded.

[0028] A film-like gate terminal electrode 6 is disposed in the outer region 4. The gate terminal electrode 6 and the source terminal electrode 5 are separated from each other by a gap 7 (a slit-shaped gap in this embodiment), thereby electrically insulating them. The gate terminal electrode 6 includes a gate pad portion 6A disposed so as to align with the protrusion 4a of the outer region 4, and a gate wiring 6B extending from the gate pad portion 6A. The gate wiring 6B is also called a gate finger.

[0029] In this embodiment, the gate pad portion 6A is formed in a rectangular shape in a plan view. A gate pad region 6a is set in the center of the gate pad portion 6A. The gate pad region 6a provides a bonding pad to which a bonding wire is bonded.

[0030] The gate wiring 6B extends in a strip shape along the outer region 4. In this embodiment, two gate wirings 6B are coupled to the gate pad portion 6A. Each gate wiring 6B extends along one side surface 2d of the semiconductor layer 2 and is further bent so as to extend along other side surfaces 2c and 2e adjacent to the side surface 2d, forming an L-shape in a plan view. The tips of the two gate wirings 6B are connected to each other by a connecting gate wiring 6C. The connecting gate wiring 6C extends along the side surface 2f. Therefore, it can be said that the gate wirings 6B and 6C form a single gate wiring that surrounds the active region 3 in a ring shape.

[0031] Fig. 2 is a schematic plan view for explaining the internal wiring structure connected to the gate wirings 6B and 6C. In this embodiment, a planar gate structure is formed on the first main surface 2a of the semiconductor layer 2. Fig. 2 shows a plurality of gate electrodes 11 of the planar gate structure and outer gate electrodes 12 that connect the plurality of gate electrodes 11 to each other.

[0032] A plurality of gate electrodes 11 are formed on the first main surface 2a. Each gate electrode 11 extends linearly, for example, in the second direction Y. The plurality of gate electrodes 11 are arranged in parallel at intervals in the first direction X. Both ends of each gate electrode 11 are coupled and connected to outer gate electrodes 12. The outer gate electrodes 12 are arranged in the outer region 4 along the periphery of the active region 3. In this embodiment, they are formed in a ring-shaped pattern that matches the shapes of the gate wirings 6B and 6C. The gate electrodes 11 and the outer gate electrodes 12 may be integrally formed, for example, by a polysilicon film formed on the first main surface 2a.

[0033] 3 is an enlarged plan view of region III in FIG. 2. A plurality of unit cell regions C are set in the active region 3 on the first main surface 2a of the semiconductor layer 2. The plurality of unit cell regions C are arranged in an array. That is, in this embodiment, the plurality of unit cell regions C are arranged in rows and columns in the first direction X and the second direction Y. That is, a plurality of unit cell regions C are arranged in the first direction X. Furthermore, a plurality of unit cell regions C are arranged in the second direction Y. A gate electrode 11 extends in the second direction Y in each unit cell region C. The plurality of unit cell regions C arranged along the second direction Y share the same gate electrode 11.

[0034] In this specification, for convenience, the boundary of the unit cell region C is set at the middle position in the first direction X of the gate electrode 11, and the boundaries of the unit cell region C are set at multiple positions in the second direction Y, thereby defining a substantially square unit cell region C. However, the definition of the unit cell region C is not limited to this. For example, multiple unit cell regions C aligned in the second direction Y according to the above definition may be collectively defined as one unit cell region.

[0035] A source contact 20 is provided between a pair of gate electrodes 11 adjacent to each other in the first direction X. In this embodiment, the source contact 20 is formed of a tungsten plug, as will be described in detail later. Therefore, hereinafter, the source contact 20 may be referred to as a "tungsten plug 20."

[0036] The source contact 20 connects the source terminal electrode 5 (see FIG. 1 ) to the semiconductor layer 2. In this embodiment, a plurality of (more specifically, two) source contacts 20 are arranged at an interval in the first direction X between a pair of gate electrodes 11 adjacent to each other in the first direction X. In other words, two source contacts 20 are arranged at an interval in the first direction X in the middle of the unit cell region C with respect to the first direction X. Each source contact 20 extends along the gate electrode 11, i.e., along the second direction Y. In this embodiment, the source contact 20 is formed in a strip shape. More specifically, the source contact 20 is formed in a rectangular shape extending linearly along the gate electrode 11. The plurality of (two in this embodiment) source contacts 20 are parallel to each other.

[0037] Both ends of each source contact 20 are located near the boundary in the second direction Y within the unit cell region C. Therefore, the length of the source contact 20 in the second direction Y is shorter than the length of the gate electrode 11.

[0038] Since the unit cell regions C are arranged along the second direction Y, the source contacts 20 are accordingly arranged along the second direction Y. That is, in the region between a pair of adjacent gate electrodes 11, the source contacts 20 are arranged at intervals in the first direction X and at intervals in the second direction Y. In other words, between a pair of adjacent gate electrodes 11, the source contacts 20 are arranged in an array (in this embodiment, in a matrix along the first direction X and the second direction Y).

[0039] If the multiple source contacts 20 aligned along the longitudinal direction of the gate electrode 11, i.e., the second direction Y, are collectively referred to as a source contact, the source contact can also be said to be divided into multiple source contact segments with respect to the second direction Y. Also, if the multiple source contacts aligned along a direction intersecting the gate electrode 11 and along the first main surface 2a, i.e., the first direction X, are collectively referred to as a source contact, the source contact can also be said to be divided into multiple source contact segments with respect to the first direction X. Therefore, in this embodiment, the source contact disposed between the pair of gate electrodes 11 has multiple source contact segments arranged at intervals in the first direction X and the second direction Y. Furthermore, in other words, the source contact disposed between the pair of gate electrodes 11 has multiple source contact segments arranged in an array (in this embodiment, a matrix along the first direction X and the second direction Y).

[0040] A gate contact 10 is arranged on the outer gate electrode 12. In this embodiment, a plurality of gate contacts 10 are provided. The plurality of gate contacts 10 are arranged at intervals in the longitudinal direction of the outer gate electrode 12. Each gate contact 10 is formed in a strip shape extending in the longitudinal direction of the outer gate electrode 12. In this embodiment, each gate contact 10 is rectangular with its long sides parallel to the longitudinal direction of the outer gate electrode 12. In this embodiment, the gate contact 10, like the source contact 20, is formed of a tungsten plug.

[0041] The width of the gate contact 10 is substantially equal to the width of the source contact 20. The width of the gate contact 10 refers to the length perpendicular to the longitudinal direction of the gate contact 10. The width of the source contact 20 refers to the length perpendicular to the longitudinal direction of the source contact 20 (source contact segment).

[0042] 4 is a cross-sectional view showing a specific example of the configuration of the unit cell region, and shows the cross-sectional structure taken along line IV-IV in FIG. - The semiconductor layer 2 includes a p-type drift region 13. A p-type body region 14 is formed in a surface layer portion of the first main surface 2a of the semiconductor layer 2. The body region 14 extends in a strip shape along the second direction Y. An n-type body region 14 is formed on the surface of the body region 14. + A p-type source region 15 is formed. The source region 15 extends in a strip shape along the second direction Y. The source region 15 is exposed on the first main surface 2a. On the first main surface 2a, the periphery of the source region 15 is located inward from the periphery of the body region 14 with a gap therebetween, and the body region 14 is exposed on the first main surface 2a. Directly below the source region 15, a p + A contact region 16 is provided on the source region 15. The contact region 16 extends in a strip shape along the second direction Y. In plan view, the contact region 16 is located inside the source region 15.

[0043] A gate insulating film 17 is formed on the first main surface 2a. In this embodiment, the gate insulating film 17 includes a silicon oxide film. The gate insulating film 17 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0044] A gate electrode 11 is formed on the gate insulating film 17. The gate electrode 11 faces the first main surface 2a via the gate insulating film 17. More specifically, the gate electrode 11 is arranged to face a region of the first main surface 2a that straddles the source region 15, the body region 14, and the drift region 13. One gate electrode 11 faces the first main surface 2a near one edge of the body region 14 in the first direction X. The other gate electrode 11 faces the first main surface 2a near the other edge of the body region 14 in the first direction X. In this way, a pair of gate electrodes 11 adjacent to each other in the first direction X share one body region 14. It can also be said that a pair of body regions 14 adjacent to each other in the first direction X share one gate electrode 11.

[0045] The gate electrode 11 is covered with an interlayer insulating film 30. The interlayer insulating film 30 covers the gate electrode 11 and also covers the gate insulating film 17 in the region between the gate electrodes 11. In this embodiment, the interlayer insulating film 30 includes a first interlayer insulating film 31 and a second interlayer insulating film 32 stacked on the first interlayer insulating film 31. The first interlayer insulating film 31 may be, for example, an undoped silicate glass (USG), i.e., a film made of silicon oxide containing neither phosphorus nor boron (an example of a first insulating material). The second interlayer insulating film 32 may be a film made of boro-phosphosilicate glass (BPSG), i.e., a film made of silicon oxide containing phosphorus and boron (an example of a second insulating material).

[0046] A plurality of contact openings 40 are formed in the interlayer insulating film 30 in the region between the pair of gate electrodes 11, i.e., directly above the body region 14. The plurality of contact openings 40 penetrate the interlayer insulating film 30 and the gate insulating film 17. The plurality of contact openings 40 are arranged at intervals in the direction in which the pair of gate electrodes 11 face each other, i.e., in the first direction X. The arrangement and shape of the contact openings 40 in a plan view follow the arrangement and shape of the source contacts 20 described above. That is, the contact openings 40 extend in a strip shape along the second direction Y.

[0047] Each contact opening 40 includes a first opening 41 formed in the first interlayer insulating film 31 and a second opening 42 formed in the second interlayer insulating film 32. The first opening 41 and the second opening 42 are connected to each other. The opening width of the second opening 42 is larger than the opening width of the first opening 41. The opening width refers to the width of the opening in the upper surface (the surface farther from the first main surface 2a) of each interlayer insulating film 31, 32, and in this case refers to the width along the first direction X.

[0048] The contact opening 40 may have a tapered cross section that narrows toward the first main surface 2a. More specifically, the first opening 41 may have a tapered cross section that narrows toward the first main surface 2a. The second opening 42 may have a tapered cross section that narrows toward the first main surface 2a. The inclination angle of the sidewall of the second opening 42 with respect to the normal direction Z to the first main surface 2a may be larger than the inclination angle of the sidewall of the first opening 41 with respect to the normal direction Z to the first main surface 2a.

[0049] A trench 45 is formed in the first main surface 2a, aligned with the contact opening 40 and communicating with the contact opening 40. The trench 45 is an example of a recess formed in the first main surface 2a of the semiconductor layer 2. The trench 45 penetrates the source region 15 and reaches the contact region 16. That is, the source region 15 is exposed on the sidewall of the trench 45, and the contact region 16 is exposed at the bottom of the trench 45. In this embodiment, the contact region 16 is also exposed on the sidewall of the trench 45 near the bottom.

[0050] A tungsten plug 20 is buried in the space defined by the contact opening 40 and the trench 45. The tungsten plug 20 includes a barrier metal layer 24 and a tungsten layer 25. The barrier metal layer 24 is a thin metal layer formed to cover the inner surfaces of the contact opening 40 and the trench 45. The barrier metal layer 24 defines a groove-shaped space corresponding to the shapes of the contact opening 40 and the trench 45. The tungsten layer 25 is buried in this space. The barrier metal layer 24 mainly suppresses or prevents the material of the tungsten layer 25, i.e., tungsten, from diffusing into the interlayer insulating film 30. The barrier metal layer 24 includes, for example, one or both of Ti and TiN. The barrier metal layer 24 may also be a laminate film formed by stacking a Ti film and a TiN film.

[0051] The tungsten plugs 20 are buried in the contact openings 40, and are therefore arranged in the same manner as the contact openings 40. That is, the plurality of tungsten plugs 20 are arranged in the region between the pair of gate electrodes 11, i.e., directly above the body region 14. The plurality of tungsten plugs 20 penetrate the interlayer insulating film 30. The plurality of tungsten plugs 20 are arranged at intervals in the direction in which the pair of gate electrodes 11 face each other, i.e., in the first direction X.

[0052] The arrangement and shape of the tungsten plugs 20 in plan view conform to the arrangement and shape of the source contacts 20 described above. In other words, the tungsten plugs 20 constitute the source contacts 20. That is, in the above description regarding the arrangement of the source contacts 20, the "source contacts" can be replaced with "tungsten plugs."

[0053] Each tungsten plug 20 includes a first portion 21 disposed in a first opening 41 of the first interlayer insulating film 31, a second portion 22 disposed in a second opening 42 of the second interlayer insulating film 32 (and the corresponding opening in the gate insulating film 17), and a third portion 23 disposed in the trench 45. The first, second, and third portions 21, 22, and 23 are continuous with one another. The width of the second portion 22 is greater than the width of the first portion 21. The width refers to the width at the upper end of each portion (the end farther from the first major surface 2a), and here refers to the width along the first direction X. The width is substantially the same as the opening width of the contact opening 40. The tungsten plug 20 may have a tapered cross section that narrows toward the first major surface 2a. More specifically, the first portion 21 may have a tapered cross section that narrows toward the first major surface 2a. The second portion 22 may have a tapered cross section that narrows toward the first major surface 2a. The inclination angle of the side surface of the second portion 22 with respect to the normal direction Z of the first main surface 2a may be larger than the inclination angle of the side surface of the first portion 21 with respect to the normal direction Z of the first portion 21. The inclination angle refers to the angle formed with respect to the normal direction Z.

[0054] A third portion 23, i.e., a bottom portion, of the tungsten plug 20 is buried in the trench 45 and contacts the semiconductor layer 2. Specifically, the third portion 23 (bottom portion) contacts the source region 15 and the contact region 16. As a result, the tungsten plug 20 is electrically connected to the source region 15, and is also electrically connected to the body region 14 via the contact region 16.

[0055] An electrode film 50 constituting the source terminal electrode 5 is formed so as to cover the interlayer insulating film 30. The electrode film 50 includes a barrier metal layer 51 and a main electrode layer 52 stacked on the barrier metal layer 51.

[0056] The main electrode layer 52 is a metal layer containing aluminum as a main component. Specifically, the main electrode layer 52 may contain at least one of aluminum, copper, an Al-Si-Cu (aluminum-silicon-copper) alloy, an Al-Si (aluminum-silicon) alloy, or an Al-Cu (aluminum-copper) alloy. The main electrode layer 52 may have a single-layer structure containing any one of these conductive materials. The main electrode layer 52 may also have a layered structure in which at least two of these conductive materials are layered in any order.

[0057] The barrier metal layer 51 mainly suppresses or prevents the constituent material of the main electrode layer 52, mainly aluminum, from diffusing into the interlayer insulating film 30. The barrier metal layer 51 contains, for example, one or both of Ti and TiN. The barrier metal layer 51 may be a laminated film in which a Ti film and a TiN film are stacked.

[0058] The electrode film 50 is in contact with the top surface of the tungsten plug 20 exposed in the contact opening 40. As a result, the electrode film 50 is electrically connected to the source region 15 via the tungsten plug 20. The electrode film 50 is also electrically connected to the body region 14 via the tungsten plug 20 and the contact region 16.

[0059] The semiconductor layer 2 has an n-type +The semiconductor substrate 1 has a drain region 18 of a type having a drain electrode 8. The exposed surface of the drain region 18 forms the second main surface 2b. A drain terminal electrode 8 is formed on the second main surface 2b.

[0060] When a control voltage equal to or greater than the threshold voltage is applied to the gate electrode 11 while an appropriate voltage is applied between the source terminal electrode 5 and the drain terminal electrode 8, an inversion layer appears on the surface (channel region) of the body region 14 directly below the gate electrode 11. The inversion layer provides a channel connecting the source region 15 and the drift region 13, thereby establishing conduction between the source terminal electrode 5 and the drain terminal electrode 8. When the control voltage is removed, the channel disappears, and the source / drain is cut off.

[0061] 5A to 5D are cross-sectional views illustrating the manufacturing process of the semiconductor device 1. A body region 14, a source region 15, a contact region 16, and a drain region 18 are formed by known processes such as diffusing impurities into a semiconductor substrate, and a gate insulating film 17 is further formed on the surface of the semiconductor layer 2. Furthermore, a gate electrode 11 and an outer gate electrode 12 are formed on the first main surface 2a of the semiconductor layer 2 by forming and patterning a conductive polysilicon film doped with impurities (such as phosphorus). Then, a first interlayer insulating film 31 and a second interlayer insulating film 32 are formed by, for example, plasma CVD (chemical vapor deposition). Then, a heat treatment (annealing) is performed to flatten the interlayer insulating film 30. This state is shown in FIG. 5A.

[0062] Next, an opening 60 penetrating the interlayer insulating film 30 and the gate insulating film 17 is formed by dry etching (e.g., RIE: Reactive Ion Etching) via a resist mask (not shown). The resist mask is then removed. This state is shown in FIG. 5B. The dry etching is performed, for example, under conditions that anisotropically etch the material (e.g., silicon oxide) of the interlayer insulating film 30 and the gate insulating film 17. Therefore, the opening has an inner side surface 61 that is approximately perpendicular to the first main surface 2a.

[0063] Next, trenches 45 are formed in the first main surface 2a of the semiconductor layer 2 by dry etching (e.g., RIE) using the interlayer insulating film 30 as a mask. This state is shown in FIG. 5C. The dry etching is performed under conditions that anisotropically etch the material (e.g., silicon) of the semiconductor layer 2. Therefore, the trenches 45 have inner side surfaces 46 that are approximately perpendicular to the first main surface 2a. Meanwhile, etching of the interlayer insulating film 30 progresses in the lateral direction (the direction parallel to the first main surface 2a), so that the openings 60 are widened.

[0064] Because the first interlayer insulating film 31 and the second interlayer insulating film 32 are made of different materials, their lateral etching rates are different. Accordingly, the opening widths of the first interlayer insulating film 31 and the second interlayer insulating film 32 are different, and the inclination angles of their inner surfaces are also different. Specifically, the opening width of the second opening 42 formed in the second interlayer insulating film 32 is greater than the opening width of the first opening 41 formed in the first interlayer insulating film 31. Furthermore, the inclination angle of the inner surface of the second opening 42 is greater than the inclination angle of the inner surface of the first opening 41. Here, the "inclination angle" refers to the angle that the inner surface forms with respect to the normal direction Z to the first main surface 2a.

[0065] Next, a barrier metal layer 24 is formed by, for example, CVD. Furthermore, a tungsten film 65 is formed by, for example, CVD. The tungsten film 65 penetrates into the contact opening 40 via the barrier metal layer 24 and is buried in the trench 45 formed in the semiconductor layer 2. This state is shown in FIG.

[0066] Next, the tungsten film 65 is etched back to remove the tungsten film 65 on the interlayer insulating film 30 outside the contact opening 40. As a result, the tungsten plug 20 embedded in the contact opening 40 is obtained.

[0067] Thereafter, a barrier metal layer 51 covering the surfaces of the interlayer insulating film 30 and the tungsten plug 20 is formed by, for example, sputtering. Furthermore, a main electrode layer 52 is formed on the barrier metal layer 51 by, for example, sputtering, thereby forming an electrode film 50. This electrode film 50 is separated into a gate terminal electrode 6 and a source terminal electrode 5.

[0068] An electrode film 50 is also formed on the second main surface 2b of the semiconductor layer 2 to serve as the drain terminal electrode 8. In this way, the configuration shown in FIG.

[0069] If necessary, a passivation film (not shown) is formed on the surface of the electrode film 50. Openings that expose the pad regions of the gate terminal electrode 6 and the source terminal electrode 5 are formed in the passivation film.

[0070] As described with reference to FIG. 3 , the gate contact 10 has substantially the same width as the source contact 20. The configuration of the gate contact 10 is substantially the same as the configuration of the source contact 20. That is, the gate contact 10 is composed of a tungsten plug embedded in the interlayer insulating film 30. More specifically, a contact opening is formed in the interlayer insulating film 30 directly above the outer gate electrode 12. This contact opening is formed in the same process as the contact opening 40 for the source contact 20, and reaches the outer gate electrode 12 through the interlayer insulating film 30. In the same process as forming the tungsten plug 20 for the source contact 20, a tungsten plug for the gate contact 10 is embedded in the interlayer insulating film 30 directly above the outer gate electrode 12. This tungsten plug has a top portion that contacts the region of the gate terminal electrode 6 in the electrode film 50 and a bottom portion that contacts the outer gate electrode 12.

[0071] As described above, the semiconductor device 1 of this embodiment includes a semiconductor layer 2 having a first main surface 2a on one side and a second main surface 2b on the other side, a plurality of gate electrodes 11 arranged at intervals on the first main surface 2a of the semiconductor layer 2, an interlayer insulating film 30 formed on the first main surface 2a of the semiconductor layer 2 so as to cover the gate electrodes 11, an electrode film 50 formed on the interlayer insulating film 30, and a plurality of tungsten plugs 20 arranged between pairs of adjacent gate electrodes 11. The plurality of tungsten plugs 20 are respectively embedded in a plurality of contact openings 40 formed in the interlayer insulating film 30 at intervals in the direction in which the pairs of adjacent gate electrodes 11 face each other. Each tungsten plug 20 has a bottom portion in contact with the semiconductor layer 2 and a top portion in contact with the electrode film 50.

[0072] According to this configuration, a plurality of contact openings 40 are formed in the interlayer insulating film 30 between a pair of gate electrodes 11 at intervals in the opposing direction. A plurality of tungsten plugs 20 are embedded in the plurality of contact openings 40. The tungsten plugs 20 have good embedding properties in the contact openings 40. Therefore, even if the gap between the gate electrodes 11 is narrow and the contact openings 40 are correspondingly small, the bottoms of the tungsten plugs 20 make good contact with the semiconductor layer 2, thereby suppressing or preventing poor contact therebetween.

[0073] On the other hand, because the multiple tungsten plugs 20 are embedded in the multiple contact openings 40 that are distributed between a pair of gate electrodes 11, the stress on the tungsten plugs 20 is small. This makes it possible to avoid process problems caused by the stress on the tungsten plugs 20, and suppress or prevent defects in device characteristics. Furthermore, because the multiple tungsten plugs 20 are distributed between the gate electrodes 11, there is no need to narrow the spacing between the gate electrodes 11. This means that there is no need to change the basic layout. Furthermore, because problems such as substrate warpage caused by the stress on the tungsten plugs 20 can be avoided, this method can also be applied to thin wafer processes.

[0074] The top of the tungsten plug 20 contacts the electrode film 50 formed on the interlayer insulating film 30. Therefore, the electrode film 50 is electrically connected to the semiconductor layer 2 via the tungsten plug 20.

[0075] In this way, a semiconductor device 1 having good electrode connections and good device characteristics can be provided without changing the basic layout.

[0076] In this embodiment, a plurality of gate electrodes 11 are arranged at intervals in a first direction X along the first main surface 2a of the semiconductor layer 2. Each gate electrode 11 extends in a second direction Y that intersects (is perpendicular to) the first direction X. A plurality of contact openings 40 are arranged at intervals in the first direction X. Each contact opening 40 extends in the second direction Y. A plurality of tungsten plugs 20 are arranged at intervals in the first direction X so as to be aligned with the contact openings 40. Each tungsten plug 20 extends in the second direction Y.

[0077] With this configuration, the contact openings 40 extend along the gate electrode 11 extending in the second direction Y, and the tungsten plugs 20 accordingly extend along the gate electrode 11. Meanwhile, the contact openings 40 are arranged at intervals in the first direction X, and the tungsten plugs 20 are accordingly arranged at intervals in the first direction X. In this way, a semiconductor device 1 with good electrode connection can be provided without changing the basic layout, while reducing the stress on the tungsten plugs 20.

[0078] In this embodiment, the length of the tungsten plug 20 in the second direction Y is smaller than the length of the gate electrode 11 in the second direction Y. This further reduces the stress on the tungsten plug 20, thereby providing a semiconductor device 1 with excellent device characteristics.

[0079] In this embodiment, the multiple tungsten plugs 20 are arranged in an array between a pair of adjacent gate electrodes 11 along the first direction X and the second direction Y. This allows the multiple tungsten plugs 20 to be evenly dispersed between the pair of gate electrodes 11, thereby further reducing the stress on the tungsten plugs 20 and contributing to improved device characteristics.

[0080] If the plurality of tungsten plugs 20 aligned in the second direction Y along the gate electrode 11 are considered as a single tungsten plug 20, then in this embodiment, each tungsten plug 20 can be said to be divided into a plurality of plug segments in the second direction Y. This reduces the stress on the tungsten plug 20 in the second direction Y, thereby improving the device characteristics.

[0081] In this embodiment, a recess (trench 45 in this embodiment) continuing to the contact opening 40 is formed in the first main surface 2a of the semiconductor layer 2. The bottom of the tungsten plug 20 contacts the semiconductor layer 2 within the recess (trench 45 in this embodiment). This configuration ensures a sufficient contact area between the tungsten plug 20 and the semiconductor layer 2, thereby ensuring reliable electrical connection therebetween. This makes it possible to provide a semiconductor device 1 with good electrode connection.

[0082] In this embodiment, the interlayer insulating film 30 includes a first interlayer insulating film 31 made of a first insulating material in contact with the gate electrode 11, and a second interlayer insulating film 32 made of a second insulating material different from the first insulating material and covering the first interlayer insulating film 31. More specifically, in this embodiment, the first insulating material is silicon oxide containing neither phosphorus nor boron (e.g., USG), and the second insulating material is silicon oxide containing phosphorus and boron (e.g., BPSG). Accordingly, in this embodiment, the contact opening 40 has a first opening 41 penetrating the first interlayer insulating film 31 and a second opening 42 penetrating the second interlayer insulating film 32.

[0083] In this embodiment, the opening width of the second opening 42 is larger than the opening width of the first opening 41. Accordingly, the first portion 21 of the tungsten plug 20 embedded in the first opening 41 of the first interlayer insulating film 31 is narrow, and the second portion 22 embedded in the second opening 42 of the second interlayer insulating film 32 is wide. This improves the embedding of the tungsten plug 20 into the contact opening 40. Furthermore, the top portion of the tungsten plug 20 that contacts the electrode film 50 has a large area, ensuring reliable electrical connection therebetween. On the other hand, the tungsten plug 20 is narrow near the first main surface 2a of the semiconductor layer 2, allowing it to be connected to the semiconductor layer 2 in the narrow region between the gates.

[0084] The opening width of the first opening 41 refers to the width of the first opening 41 at the surface of the first interlayer insulating film 31 (the surface farther from the semiconductor layer 2). Similarly, the opening width of the second opening 42 refers to the width of the second opening 42 at the surface of the second interlayer insulating film 32 (the surface farther from the semiconductor layer 2). In this case, the width refers mainly to the width in the first direction X. However, the width of the second opening 42 may also be wider than the width of the first opening 41 in the second direction Y.

[0085] In this embodiment, the contact opening 40 has a tapered cross section that narrows toward the first main surface 2a of the semiconductor layer 2. This improves the embedding property of the tungsten plug 20, thereby ensuring reliable electrode connection.

[0086] The interval between adjacent gate electrodes 11 is, for example, 1 μm or more and 3 μm or less. More specifically, the interval between adjacent gate electrodes 11 includes one or more of the following ranges: 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, and 2.5 μm or more and 3.0 μm or less. In such cases, the use of tungsten plugs 20 in particular can ensure reliable electrode connection.

[0087] The ratio (aspect ratio) of the opening width (e.g., width in the first direction X) of contact opening 40 in the surface of interlayer insulating film 30 to the depth of contact opening 40 from the surface of interlayer insulating film 30 to first main surface 2a is, for example, not less than 1 and not more than 5. More specifically, the ratio (aspect ratio) includes one or more ranges of not less than 1 and not more than 1.5, not more than 1.5 and not more than 2, not more than 2.5, not more than 2.5 and not more than 3, not more than 3.5, not more than 3.5 and not more than 4, not more than 4.5 and not more than 4.5, and not more than 4.5 and not more than 5. In such cases, the use of tungsten plug 20 in particular can ensure reliable electrode connection.

[0088] In this embodiment, the electrode film 50 is made of a metal material that has lower stress than tungsten. For example, the electrode film 50 includes a metal layer whose main component is aluminum. Such a metal layer has a lower embeddability in the contact opening 40 than tungsten, but also has lower stress than tungsten. This makes it possible to suppress or prevent degradation of device characteristics due to stress in the electrode film 50, and to achieve reliable electrode connection.

[0089] In this embodiment, the semiconductor layer 2 includes a drift region 13 of a first conductivity type (n-type in this embodiment), a body region 14 of a second conductivity type (p-type in this embodiment) formed in a surface layer portion of the first main surface 2a of the semiconductor layer 2 and extending across a pair of adjacent gate electrodes 11, a first conductivity type region (source region 15) formed in the body region 14, and a second conductivity type region (contact region 16) formed in the body region 14 and having a higher impurity concentration than the body region 14. Each tungsten plug 20 is in contact with the first conductivity type region (source region 15) and the second conductivity type region (contact region 16). This allows the tungsten plug 20 to commonly connect the electrode film 50 to the source region 15 and the body region 14.

[0090] Although one embodiment of the present invention has been described above, the present invention can be embodied in other forms. For example, in the above embodiment, an example was described in which the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0091] In the above embodiment, the positions in the second direction Y of the multiple source contacts 20 (tungsten plugs 20) aligned in the first direction X are equal, but this arrangement is not necessarily required. That is, the positions in the second direction Y of the multiple source contacts 20 (tungsten plugs 20) that are different in the first direction X may be different.

[0092] Furthermore, in the above-described embodiment, the source contacts 20 (tungsten plugs 20) are arranged in two rows between a pair of adjacent gate electrodes 11, but they may be arranged in three or more rows.

[0093] Furthermore, in the above-described embodiment, each source contact 20 (tungsten plug 20) is formed in a strip shape (rectangular shape) extending in the second direction Y, but, for example, each source contact 20 (tungsten plug 20) may be formed in a dot shape in plan view, the lengths of which are approximately equal in the first direction X and the second direction Y. Such dot-shaped source contacts 20 (tungsten plugs 20) may be arranged in a dispersed manner between a pair of adjacent gate electrodes 11.

[0094] In the above-described embodiment, silicon was exemplified as the material for the semiconductor layer 2, but for example, as shown in Fig. 6, a semiconductor device 1 (SiC semiconductor device) having a semiconductor layer 2 (i.e., a SiC semiconductor layer) made of silicon carbide (specifically, SiC single crystal) may be employed. Fig. 6 corresponds to Fig. 4 and is a cross-sectional view for explaining a structure in which a semiconductor layer 2 made of SiC single crystal is applied to the semiconductor device 1. In the following, the same reference numerals are used for the structures already mentioned, and explanations thereof will be omitted.

[0095] The semiconductor layer 2 is preferably made of hexagonal SiC single crystal. Hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of the atomic arrangement. Of the multiple polytypes, the semiconductor layer 2 is preferably made of 4H-SiC single crystal. Of course, the SiC single crystal of the semiconductor layer 2 may be made of a polytype other than 4H-SiC single crystal.

[0096] The first and second main surfaces 2a and 2b of the semiconductor layer 2 are preferably formed by the c-plane of a SiC single crystal. The c-plane is the (0001) plane (silicon plane) and (000-1) plane (carbon plane) of a SiC single crystal. In this case, it is particularly preferable that the first main surface 2a is formed by the (0001) plane and the second main surface 2b is formed by the (000-1) plane. Of course, the first main surface 2a may be formed by the (000-1) plane and the second main surface 2b may be formed by the (0001) plane.

[0097] The first direction X may be set in the m-axis direction of the SiC single crystal, and the second direction Y may be set in the a-axis direction of the SiC single crystal. In this case, in the above description, "first direction X" may be replaced with "m-axis direction" and "second direction Y" may be replaced with "a-axis direction." Conversely, the first direction X may be set in the a-axis direction and the second direction Y may be set in the m-axis direction. In this case, in the above description, "first direction X" may be replaced with "a-axis direction" and "second direction Y" may be replaced with "m-axis direction."

[0098] 6 shows an example in which the first direction X is set to the m-axis direction and the second direction Y is set to the a-axis direction. The a-axis direction corresponds to the [11-20] direction and [-1-120] direction of the SiC single crystal. The m-axis direction corresponds to the [1-100] direction and [-1100] direction of the SiC single crystal.

[0099] The first main surface 2a and the second main surface 2b may have an off angle θ that is inclined at an angle of 10° or less in the off direction with respect to the c-plane of the SiC single crystal. The off direction is preferably the a-axis direction. In this case, the c-axis of the SiC single crystal is inclined by the off angle θ with respect to the normal direction Z of the semiconductor layer 2. The c-axis of the SiC single crystal is in the normal direction to the c-plane.

[0100] The off angle θ may be set in the range of more than 0° to 2°, 2° to 4°, 4° to 6°, 6° to 8°, or 8° to 10°. The off angle θ is preferably set in the range of more than 0° to 5°. The off angle θ may be set in the range of, for example, 3.0° to 4.5°. In this case, the off angle θ is preferably 3.0° to 3.5°, or 3.5° to 4.0°. The off angle θ may be set in the range of, for example, 1.5° to 3.0°. In this case, the off angle θ is preferably 1.5° to 2.0°, or 2.0° to 2.5°. Of course, a semiconductor layer 2 without an off angle θ may be employed.

[0101] When the semiconductor layer 2 has an off-angle θ tilted toward the a-axis direction, it is preferable that the first direction X is set to the m-axis direction and the second direction Y is set to the a-axis direction, as shown in Fig. 6. In this case, the trenches 45 are formed so as to extend in the a-axis direction and be spaced apart in the m-axis direction in accordance with the pattern of the multiple source contacts 20 (tungsten plugs 20).

[0102] That is, the wall surfaces of trench 45 are defined by the m-plane, a-plane, and c-plane of the SiC single crystal. The m-plane is a plane in the SiC single crystal that is perpendicular to the m-axis direction (i.e., a plane extending along the a-axis direction). The a-plane is a plane in the SiC single crystal that is perpendicular to the a-axis direction (i.e., a plane extending along the m-axis direction). The c-plane is specifically a silicon plane. The long sidewalls of trench 45 that extend in the a-axis direction are formed by the m-plane. Furthermore, the short sidewalls of trench 45 that extend in the m-axis direction are formed by the a-plane. Furthermore, the bottom wall of trench 45 is formed by the c-plane to which an off-angle θ has been introduced.

[0103] In this structure, the longitudinal sidewalls of trench 45 extend in the a-axis direction (i.e., the off-axis direction), which coincides with the tilt direction of the off-angle θ, so the tilt due to the off-angle θ is suppressed. On the other hand, the lateral sidewalls of trench 45 extend in the m-axis direction, which is perpendicular to the tilt direction of the off-angle θ, so that an inclined surface extending along the c-axis direction is formed due to the off-angle θ. However, because the width of the lateral sidewalls of trench 45 is extremely small compared to the width of the longitudinal sidewalls of trench 45, the inclined surface introduced into the lateral sidewalls of trench 45 is limited.

[0104] This can prevent the formation of a slope on the wall surface of trench 45 due to the off-angle θ, thereby allowing contact opening 40 to appropriately communicate with trench 45. As a result, the tungsten plug 20 can be embedded more easily in contact opening 40 (trench 45).

[0105] Below are examples of features extracted from this specification and drawings.

[0106] By arranging unit cells, each including a gate electrode, at high density on a semiconductor substrate, the channel width can be increased and the on-resistance can be reduced. To achieve this, the spacing between the gate electrodes is narrowed. Accordingly, the width of the contact opening becomes narrower, and the aspect ratio of the contact opening formed in the interlayer insulating film increases. The aspect ratio is defined, for example, by the ratio of the depth to the width of the contact opening.

[0107] Aluminum, a typical electrode material, does not necessarily have good fillability in openings. Therefore, when attempting to fill a contact opening with an aluminum electrode film in a high aspect ratio, voids may occur, which may increase the contact resistance between the barrier metal and the electrode film or cause poor contact. Therefore, the following provides a semiconductor device that has good electrode connection and excellent device characteristics.

[0108] [A1] A SiC semiconductor device (1) including: a SiC semiconductor layer (2) having a first main surface (2a) on one side and a second main surface (2b) on the other side; a plurality of gate electrodes (11) arranged at intervals on the first main surface (2a) of the SiC semiconductor layer (2); an interlayer insulating film (30) formed on the first main surface (2a) of the SiC semiconductor layer (2) so as to cover the gate electrodes (11); an electrode film (50) formed on the interlayer insulating film (30); and a plurality of tungsten plugs (20) embedded in a plurality of contact openings (40) formed in the interlayer insulating film (30) at intervals in a direction in which the pair of gate electrodes (11) face each other, between adjacent pairs of the gate electrodes (11), the tungsten plugs having a bottom portion in contact with the SiC semiconductor layer (2) and a top portion in contact with the electrode film (50). This configuration makes it possible to provide a SiC semiconductor device with good electrode connection and excellent device characteristics.

[0109] [A2] The SiC semiconductor device (1) according to A1, wherein the plurality of gate electrodes (11) are spaced apart in the m-axis direction of the SiC single crystal, each gate electrode (11) extending in the a-axis direction of the SiC single crystal, the plurality of contact openings (40) are spaced apart in the m-axis direction, each contact opening (40) extending in the a-axis direction, and the plurality of tungsten plugs (20) are spaced apart in the m-axis direction so as to be aligned with the contact openings (40), and each tungsten plug (20) extends in the a-axis direction.

[0110] [A3] The SiC semiconductor device (1) according to A2, wherein the length of the tungsten plug (20) in the a-axis direction is smaller than the length of the gate electrode (11) in the a-axis direction.

[0111] [A4] The SiC semiconductor device (1) according to A2 or A3, wherein the plurality of tungsten plugs (20) are arranged in an array between the pair of adjacent gate electrodes (11) along the m-axis direction and the a-axis direction.

[0112] [A5] The SiC semiconductor device (1) according to A2, wherein each tungsten plug (20) is divided into a plurality of plug segments in the a-axis direction.

[0113] [A6] The SiC semiconductor device (1) according to A1, wherein the plurality of gate electrodes (11) are spaced apart in the a-axis direction of the SiC single crystal, each gate electrode (11) extending in the m-axis direction of the SiC single crystal, the plurality of contact openings (40) are spaced apart in the a-axis direction, each contact opening (40) extending in the m-axis direction, and the plurality of tungsten plugs (20) are spaced apart in the a-axis direction so as to be aligned with the contact openings (40), and each tungsten plug (20) extends in the m-axis direction.

[0114] [A7] The SiC semiconductor device (1) according to A6, wherein the length of the tungsten plug (20) in the m-axis direction is smaller than the length of the gate electrode (11) in the m-axis direction.

[0115] [A8] The SiC semiconductor device (1) according to A6 or A7, wherein the plurality of tungsten plugs (20) are arranged in an array between the pair of adjacent gate electrodes (11) along the a-axis direction and the m-axis direction.

[0116] [A9] The SiC semiconductor device (1) according to A6, wherein each tungsten plug (20) is divided into a plurality of plug segments in the m-axis direction.

[0117] [A10] The SiC semiconductor device (1) according to any one of A1 to A9, wherein a recess (45) communicating with the contact opening (40) is formed in the first main surface (2a) of the SiC semiconductor layer (2), and the bottom of the tungsten plug (20) is in contact with the SiC semiconductor layer (2) within the recess (45).

[0118] [A11] The SiC semiconductor device (1) according to any one of A1 to A10, wherein the interlayer insulating film (30) includes a first interlayer insulating film (31) made of a first insulating material in contact with the gate electrode (11), and a second interlayer insulating film (32) made of a second insulating material different from the first insulating material and covering the first interlayer insulating film (31).

[0119] [A12] The SiC semiconductor device (1) according to A11, wherein the first insulating material is silicon oxide containing neither phosphorus nor boron, and the second insulating material is silicon oxide containing phosphorus and boron.

[0120] [A13] The SiC semiconductor device (1) according to A11 or A12, wherein the contact opening (40) has a first opening (41) penetrating the first interlayer insulating film (31) and a second opening (42) penetrating the second interlayer insulating film (32), and the opening width of the second opening (42) is larger than the opening width of the first opening (41).

[0121] [A14] The SiC semiconductor device (1) according to any one of A1 to A13, wherein the contact opening (40) has a tapered cross section narrowing toward the first main surface (2a) of the SiC semiconductor layer (2).

[0122] [A15] The SiC semiconductor device (1) according to any one of A1 to A13, wherein the distance between adjacent gate electrodes (11) is 1 μm or more and 3 μm or less.

[0123] [A16] The SiC semiconductor device (1) according to any one of A1 to A15, wherein a ratio of an opening width of the contact opening (40) on the surface of the interlayer insulating film (30) to a depth of the contact opening (40) from the surface of the interlayer insulating film (30) to the first main surface (2a) is 1 or more and 5 or less.

[0124] [A17] The SiC semiconductor device (1) according to any one of A1 to A16, wherein the electrode film (50) is made of a metal material having a lower stress than tungsten.

[0125] [A18] The SiC semiconductor device (1) according to any one of A1 to A17, wherein the electrode film (50) includes a metal layer containing aluminum as a main component.

[0126] [A19] The SiC semiconductor device (1) according to any one of A1 to A18, wherein the SiC semiconductor layer (2) includes a drift region (13) of a first conductivity type, a body region (14) of a second conductivity type formed in a surface layer portion of the first main surface (2a) of the SiC semiconductor layer (2) and formed in a range spanning the pair of adjacent gate electrodes (11), a first conductivity type region (15) formed in the body region (14), and a second conductivity type region (16) formed in the body region (14) and having a higher impurity concentration than the body region (14), and each tungsten plug (20) is in contact with the first conductivity type region (15) and the second conductivity type region (16).

[0127] [A20] The SiC semiconductor device (1) according to any one of A1 to A19, wherein the first main surface (2a) has an off angle of 10° or less.

[0128] In addition, various design modifications can be made within the scope of the claims. [Explanation of symbols]

[0129] 1: semiconductor device, 2: semiconductor layer, 5: source terminal electrode, 6: gate terminal electrode, 8: drain terminal electrode, 10: gate contact, 11: gate electrode, 12: outer gate electrode, 13: drift region, 14: body region, 15: source region, 16: contact region, 17: gate insulating film, 18: drain region, 20: source contact (tungsten plug), 21: first portion, 22: second portion, 23: third portion, 24: barrier metal layer, 25: tungsten layer, 30: interlayer insulating film, 31: first interlayer insulating film, 32: second interlayer insulating film, 40: contact opening, 41: first opening, 42: second opening, 45: trench, 50: electrode film (source terminal electrode), 65: tungsten film

Claims

1. a semiconductor layer having a first major surface on one side and a second major surface on the other side; a drift region of a first conductivity type formed in a surface layer portion of the first main surface; a plurality of second conductivity type body regions formed in a surface layer portion of the drift region; a first conductivity type source region formed in a surface layer portion of the body region; a plurality of gate electrodes formed on the first main surface of the semiconductor layer, the gate electrodes being spaced apart in a first direction along the first main surface, each extending in a second direction intersecting the first direction, and the plurality of gate electrodes being arranged between the body regions; a second conductivity type contact region formed in the body region and having a higher impurity concentration than the body region; an interlayer insulating film formed on the first main surface of the semiconductor layer so as to cover the gate electrode; an electrode film formed on the interlayer insulating film; a plurality of source contact plugs embedded in contact openings formed in the interlayer insulating film between adjacent pairs of the gate electrodes, the source contact plugs each having a bottom portion in contact with the semiconductor layer and a top portion in contact with the electrode film, and extending in the second direction; a bottom of the source contact plug contacting the contact region.

2. the contact opening has a first opening formed in a region of the interlayer insulating film on the first main surface side, and a second opening formed in a region of the interlayer insulating film closer to the electrode film than the first opening, a sidewall of the first opening and a sidewall of the second opening are both inclined with respect to a normal direction of the first main surface, The opening width of the second opening is larger than the opening width of the first opening, 2. The semiconductor device according to claim 1, wherein an inclination angle of the sidewall of said second opening relative to the normal to said first main surface is different from an inclination angle of the sidewall of said first opening relative to the normal to said first main surface.

3. The semiconductor device according to claim 2 , wherein the length of said source contact plug in said second direction is smaller than the length of said gate electrode in said second direction.

4. a plurality of the source contact plugs are formed at intervals in the first direction, 4. The semiconductor device according to claim 2, wherein the plurality of source contact plugs are arranged in an array between the pair of adjacent gate electrodes along the first direction and the second direction.

5. a plurality of the source contact plugs are formed at intervals in the first direction, 4. The semiconductor device according to claim 2, wherein the plurality of source contact plugs are arranged at intervals in both the first direction and the second direction.

6. The semiconductor device according to claim 2 , wherein the source contact plug is divided into a plurality of plug segments in the second direction.

7. a recess communicating with the contact opening is formed in the first main surface of the semiconductor layer; 7. The semiconductor device according to claim 1, wherein a bottom of said source contact plug is in contact with said semiconductor layer within said recess.

8. 2. The semiconductor device according to claim 1, wherein the interlayer insulating film includes a first interlayer insulating film made of a first insulating material in contact with the gate electrode, and a second interlayer insulating film made of a second insulating material different from the first insulating material and covering the first interlayer insulating film.

9. 9. The semiconductor device according to claim 8, wherein said first insulating material is silicon oxide containing neither phosphorus nor boron, and said second insulating material is silicon oxide containing phosphorus and boron.

10. 10. The semiconductor device according to claim 8, wherein the contact opening has a first opening penetrating the first interlayer insulating film and a second opening penetrating the second interlayer insulating film, and the opening width of the second opening is larger than the opening width of the first opening.

11. 11. The semiconductor device according to claim 1, wherein the contact opening has a tapered cross section that narrows toward the first main surface of the semiconductor layer.

12. a top surface of the source contact plug is located above an upper surface of the gate electrode in a cross-sectional view; 12. The semiconductor device according to claim 1, wherein a bottom surface of the source contact plug is located lower than a lower surface of the gate electrode in a cross-sectional view.

13. a plurality of the source contact plugs are formed at intervals in a direction in which the pair of gate electrodes face each other; 13. The semiconductor device according to claim 1, wherein the distance between adjacent gate electrodes is 1 μm or more and 3 μm or less.

14. 14. The semiconductor device according to claim 1, wherein a ratio of an opening width of the contact opening on the surface of the interlayer insulating film to a depth of the contact opening from the surface of the interlayer insulating film to the first main surface is 1 or more and 5 or less.

15. 15. The semiconductor device according to claim 1, wherein the electrode film is made of a metal material having a lower stress than tungsten.

16. 16. The semiconductor device according to claim 1, wherein the electrode film includes a metal layer containing aluminum as a main component.

17. a planar gate structure including the drift region, the body region, the source region, the plurality of gate electrodes, and the contact region; 17. The semiconductor device according to claim 1, wherein the source contact plug is in contact with the source region and the contact region.

18. a trench is formed in the first main surface, the trench communicating with the contact opening and penetrating the source region to reach the contact region; 18. The semiconductor device according to claim 1, wherein the source contact plug is buried in the trench and contacts the source region on a sidewall of the trench.

19. 19. The semiconductor device according to claim 1, wherein the first main surface has an off-angle of 10 degrees or less.

20. 11. The semiconductor device according to claim 2, wherein the first opening and the second opening are connected to each other, and the sidewall of the contact opening does not have a portion parallel to the first main surface.

Images