Semiconductor device

Abstract

To provide a highly reliable semiconductor device in which occurrence of void, bleed and bowing is suppressed sufficiently in the manufacturing process.SOLUTION: The semiconductor device includes a substrate, a first chip arranged on the substrate, a plurality of raising pieces arranged around the first chip on the substrate, an adhesive piece embedding the first chip and at least a part of the raising pieces, and a second chip arranged so as to cover the first chip in a state of being adhered to the adhesive piece.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] As electronic devices become more multifunctional, stacked MCPs (Multi Chip Packages), which have higher capacity due to the stacking of semiconductor elements in multiple layers, are becoming more common. Examples of stacked MCPs include wire-embedded and chip-embedded semiconductor packages. The adhesive film used to manufacture wire-embedded semiconductor packages is called FOW (Film Over Wire). The adhesive film used to manufacture chip-embedded semiconductor packages is called FOD (Film Over Die). One example of a chip-embedded semiconductor package is one in which a controller chip is placed in the bottom layer and embedded with a film-like adhesive (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-175459 Summary of the Invention [Problem to be solved by the invention]

[0004] However, as chip-embedded semiconductor devices become smaller and thinner, and as their functionality and speed increase, the area of ​​the controller chip tends to increase while the area of ​​the chips stacked on it tends to decrease. In other words, the area occupied by the controller chip relative to the stacked chips tends to increase. There is also a trend toward requiring even thinner stacked chips. Along with these trends, the following issues are becoming more pronounced. · Voids remain around the controller chip after bonding. - The adhesive used to embed the controller chip overflows onto the board (bleeding occurs). Insufficient removal of resin from the controller chip causes the chip placed on top of it to warp in the cry direction (the occurrence of bowing). Note that warping in the cry direction means that the chip warps in an upward convex shape (see Figure 12(d)).

[0005] Although some voids can be eliminated by the pressure curing process after compression bonding, if the voids are too large, they may not be eliminated. Voids can cause separation between the chip and the substrate or package cracks during reflow. Bleeding can contaminate the surrounding wire bonding pads or chips, causing deterioration of wire bonding. Bowing can make multi-tiered chip stacking difficult or cause semiconductor elements to peel off due to residual stress.

[0006] To solve these problems, various improvements have been made to the composition to control the fluidity of film-like adhesives. However, increasing the fluidity of the film to reduce voids and bowing after bonding tends to increase bleeding. On the other hand, decreasing the fluidity of the film to reduce bleeding results in an increase in voids and bowing. As such, there is a trade-off between voids and bowing and bleeding, and it is becoming difficult to improve these problems solely through material improvements. Furthermore, even when process conditions such as bonding temperature or bonding load are changed, for example, high temperature and high load bonding tends to reduce voids but increase bleeding, making it difficult to simultaneously improve the above problems.

[0007] The present disclosure has been made in consideration of the above circumstances and provides a method for manufacturing a semiconductor device using a film on adhesive (FOD) for embedding chips, which can sufficiently suppress the occurrence of voids, bleeding, and bowing. The present disclosure also provides a semiconductor device with excellent reliability in which the occurrence of voids, bleeding, and bowing during the manufacturing process is sufficiently suppressed. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the following steps. (A) A step of placing a first chip on a substrate. (B) A step of arranging a plurality of padding pieces on the substrate around the first chip or around the area where the first chip is to be arranged. (C) A step of preparing a chip with an adhesive piece, the chip comprising a second chip and an adhesive piece provided on one surface of the second chip. (D) A step of applying a pressing force to the chip with the adhesive piece toward the substrate so that the first chip and at least a portion of the padding piece are embedded in the adhesive piece. The steps (A), (B) and (C) may be performed in any combination and order.

[0009] The present inventors have investigated methods for suppressing the occurrence of voids, bleed, and bowing during the manufacturing process of semiconductor devices and discovered that voids and bleed occur due to bowing during the process of pressure-bonding a second chip to a first chip. FIGS. 12(a) to 12(f) are cross-sectional views schematically illustrating a conventional process of pressure-bonding a chip to a controller chip. FIG. 12(a) shows a state in which a substrate 10 is placed on a hot plate H and a controller chip Tc (first chip) is fixed to the substrate 10 with adhesive pieces Ac. An adhesive-piece-attached chip 31 (a stack of adhesive pieces A1 and chip T1 (second chip)) is placed above the controller chip Tc, ready for pressure-bonding. FIG. 12(b) shows a state in which the bottom surface of the adhesive piece A1 is in contact with the top surface of the controller chip Tc. FIG. 12(c) shows a state in which the adhesive piece A1 begins to melt on the top surface of the controller chip Tc. FIG. 12(d) shows a state in which bowing occurs in chip T1. Figure 12(e) shows a state in which the edge portion of the adhesive piece A1 is in contact with the surface of the substrate 10. Figure 12(f) shows a state in which the thermocompression bonding of the chip T1 is completed. As shown in Figure 12(f), bowing (warping in the cry direction) occurs in the chip T1, and voids V and bleed B occur in the adhesive piece A1. In response to this, the inventors have discovered a new finding that, as shown in Figures 13(a) to 13(c), if bowing does not occur in the chip T1, voids and bleed can also be suppressed.

[0010] The padding piece placed on the substrate in step (B) is intended to prevent bowing of the second chip. In step (D), a pressing force is applied to the chip with the adhesive piece toward the substrate so that the first chip and at least a portion of the padding piece are embedded in the adhesive piece, thereby preventing bowing of the second chip (see FIG. 9). This also prevents the occurrence of voids and bleeding.

[0011] From the viewpoint of efficiently carrying out step (B), a transfer film including a base film and a plurality of protruding pieces provided on the surface of the base film may be used. That is, step (B) may include transferring a plurality of protruding pieces provided on the surface of the base film onto the surface of the substrate.

[0012] As described above, some voids can be eliminated by the pressure curing step after pressure bonding. That is, if the adhesive strips are made of a thermosetting resin composition, a step of curing the adhesive strips by heating in a pressurized atmosphere may be carried out after step (D). By carrying out this step, voids can be further reduced.

[0013] According to the inventors' investigations, when the shape of the second chip is rectangular in plan view and the ratio B / A of the length B of the long side to the length A of the short side of the rectangle is 2 or greater, conventional crimping methods are prone to open voids and bleeding due to bowing of the second chip. Open voids do not disappear even after the pressure curing process described above, and should be avoided. In contrast, according to the manufacturing method of the present disclosure, even when the shape of the second chip is rectangular in plan view and the ratio B / A of the length B of the long side to the length A of the short side of the rectangle is 2 or greater, the padding piece prevents the short sides of the second chip from bending downward in step (D), thereby suppressing bowing of the second chip and thereby suppressing open voids and bleeding.

[0014] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a first chip arranged on the substrate, a plurality of protrusions arranged on the substrate around the first chip, an adhesive piece embedding the first chip and at least a portion of the protrusions, and a second chip arranged to cover the first chip while being adhered to the adhesive piece.

[0015] The semiconductor device is manufactured by the manufacturing method described above, for example. This semiconductor device has excellent reliability because the occurrence of voids, bleeding, and bowing during the manufacturing process is sufficiently suppressed.

[0016] In the semiconductor device, the second chip may be spaced apart from the plurality of padding pieces, and an adhesive (the adhesive pieces) may be filled between the second chip and the plurality of padding pieces. Also, the second chip may be spaced apart from the first chip, and an adhesive (the adhesive pieces) may be filled between the second chip and the first chip.

[0017] The padding piece may have a multi-layer structure including, for example, a dummy chip and an adhesive piece. The padding piece may have a multi-layer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers. The padding piece may have a two-layer structure including a first layer and a second layer. The second layer may be, for example, an adhesive piece and may be made of a cured product of a thermosetting resin composition. The first layer may correspond to the intermediate layer.

[0018] The first chip may be wire-bonded to the substrate or may be flip-chip bonded. [Effects of the Invention]

[0019] According to the present disclosure, there is provided a method for manufacturing a semiconductor device using a film on adhesive (FOD) for embedding chips, which method can sufficiently suppress the occurrence of voids, bleeding, and bowing. Also, according to the present disclosure, there is provided a semiconductor device having excellent reliability in which the occurrence of voids, bleeding, and bowing during the manufacturing process is sufficiently suppressed. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating one embodiment of a semiconductor device according to the present disclosure. [Figure 2] 2(a) and 2(b) are plan views schematically showing examples of the positional relationship between a chip and a plurality of padding pieces. [Figure 3]FIG. 3(a) is a plan view schematically showing an example of a laminated film for producing a padding piece, and FIG. 3(b) is a cross-sectional view taken along line bb in FIG. 3(a). [Figure 4] FIG. 4 is a cross-sectional view that schematically shows a step of bonding the adhesive layer and the laminated film shown in FIG. 3(b). [Figure 5] 5(a) to 5(d) are cross-sectional views that schematically show the process of producing the padding piece. [Figure 6] 6(a) and 6(b) are cross-sectional views each showing a schematic example of a chip with an adhesive piece. [Figure 7] 7A to 7C are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. [Figure 8] 8A to 8C are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. [Figure 9] 9A to 9C are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. [Figure 10] 10A to 10C are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view schematically showing an example of a transfer film used to arrange a padding piece on the surface of a base material. [Figure 12] 12(a) to 12(f) are cross-sectional views that schematically show a conventional thermocompression bonding process. [Figure 13] 13(a) to 13(c) are cross-sectional views that schematically show that voids and bleeding are also suppressed, assuming that bowing does not occur in the chip to be compressed. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In the following embodiments, components (including steps, etc.) are not essential unless otherwise specified. In the following description, identical or equivalent parts are given the same reference numerals, and duplicate explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. The sizes of the components in each figure are conceptual, and the dimensional ratios of the drawings are not limited to the ratios shown.

[0022] The numerical values ​​and ranges in this specification do not limit the present disclosure. In this specification, numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In numerical ranges described in stages in this specification, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another numerical range described in stages.

[0023] First Embodiment [Semiconductor Devices] FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device according to this embodiment. The semiconductor device 100 shown in this figure is, for example, a three-dimensional NAND memory. The semiconductor device 100 includes a substrate 10, a controller chip Tc (first chip) disposed on the surface of the substrate 10, a plurality of padding pieces R disposed around the controller chip Tc on the substrate 10, an adhesive piece A1 embedding the entire controller chip Tc and at least a portion of the padding piece R, a chip T1 (second chip) disposed so as to cover the controller chip Tc while being adhered to the adhesive piece A1, five chips T2, T3, T4, T5, and T6 stacked on the surface of the chip T1, wires Wa and Wb electrically connecting the chips to electrodes 10a and 10b on the surface of the substrate 10, and a sealing layer 50 sealing them. An adhesive piece A2 is disposed between the chips T1 and T2, an adhesive piece A3 is disposed between the chips T2 and T3, and an adhesive piece A4 is disposed between the chips T3 and T4. An adhesive piece A5 is placed between chips T4 and T5, and an adhesive piece A6 is placed between chips T5 and T6.

[0024] The substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing warpage of the semiconductor device 100, the thickness of the substrate 10 is, for example, 90 to 300 μm, and may be 90 to 210 μm.

[0025] The controller chip Tc is adhered to the substrate 10 by adhesive pieces Ac and is electrically connected to the electrodes 10a by wires Wa. The shape of the controller chip Tc in a plan view is, for example, rectangular (square or oblong). The length of one side of the controller chip Tc is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm. The thickness of the controller chip Tc is, for example, 20 to 150 μm, and may be 30 to 100 μm. The thickness of the adhesive pieces Ac is, for example, 5 to 40 μm, and may be 10 to 25 μm. The sum of the thickness of the controller chip Tc and the thickness of the adhesive pieces Ac (the distance from the upper surface of the substrate 10 to the upper surface of the controller chip Tc) is, for example, 25 to 190 μm, and may be 40 to 125 μm.

[0026] The protrusions R are disposed on the substrate 10 around the controller chip Tc. The protrusions R serve to suppress bowing of the chip T1 when the chip T1 is pressure-bonded (see FIG. 9). The protrusions R in this embodiment have a three-layer structure including a pair of surface layers R1, R1 and an intermediate layer R2 disposed therebetween. The length of one side of the protrusions R in plan view is, for example, 12 mm or less, and may be 2 to 10 mm or 3 to 8 mm.

[0027] The total thickness of the padding piece R may be equal to the sum of the thickness of the controller chip Tc and the thickness of the adhesive piece Ac, and may be, for example, 25 to 190 μm, 40 to 125 μm, or 40 to 115 μm. The ratio of the total thickness of the padding piece R to the sum of the thickness of the controller chip Tc and the thickness of the adhesive piece Ac may be, for example, 0.8 to 1.2, or 0.9 to 1.1, or, for example, 0.5 to 1.2, or 0.8 to 1.1. When this ratio is within these ranges, a sufficiently uniform pressing force can be applied to the chip T1 during the compression bonding process of the chip T1 (see FIG. 9). This suppresses bowing of the chip T1, and as a result, the occurrence of voids and bleeding can also be suppressed. This ratio may be less than 1.0, or may be 0.95 or less, or 0.90 or less. A relatively thin padding piece R can suppress bleeding of the adhesive piece A1 onto the surface of the padding piece R. The adhesive strip A1 that protrudes onto the surface of the pad R may contaminate the wire bonding pad (not shown) of the chip T1 in subsequent processes, which may cause a decrease in the reliability of the wire bonding.

[0028] The thickness of the surface layer R1 is, for example, 5 to 40 μm or 5 to 50 μm, and may be 5 to 25 μm or 5 to 20 μm. The thicknesses of the two surface layers R1, R1 may be the same or different. The surface layer R1 is made of a thermosetting resin composition. The thermosetting resin composition can be in a semi-cured (B-stage) state and then in a fully cured (C-stage) state by a subsequent curing treatment. The thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer (e.g., acrylic resin), and may further contain an inorganic filler, a curing accelerator, etc. as necessary. The compositions of the two surface layers R1, R1 may be the same or different.

[0029] The thickness of the intermediate layer R2 is, for example, 5 to 75 μm or 5 to 90 μm, and may be 10 to 75 μm or 10 to 50 μm. The intermediate layer R2 is preferably made of a material with sufficiently high mechanical strength. Specific examples of such materials include resins such as polyimide and polyethylene terephthalate (PET), and metals such as copper and aluminum. The tensile modulus of the material constituting the intermediate layer R2 is, for example, 8.0 MPa or more, and may be 9.0 MPa or more, or 10.0 MPa or more. When the intermediate layer R2 is made of a resin material, the intermediate layer R2 is made of a material different from the resin material constituting the surface layer R1. By having multiple layers made of different materials in the padding piece, it is possible to assign functions to each layer, and the padding piece can have higher functionality than one made of multiple layers of the same material.

[0030] As shown in FIG. 2(a), two protrusions R (rectangular in shape) may be arranged at positions corresponding to the short sides of the chip T1 in a plan view, or as shown in FIG. 2(b), one protrusion R (square in shape, four in total) may be arranged at positions corresponding to each corner of the chip T1 in a plan view. From the viewpoint of suppressing bleeding, it is preferable that the multiple protrusions R are not entirely covered by the chip T1; that is, it is preferable that each protrusion R is arranged so that a portion of each protrusion R protrudes outward from the chip T1 in a plan view. It is preferable that the four corners of the chip T1 are balanced and cover at least a portion of each protrusion R. This configuration can more effectively suppress both bowing and bleeding.

[0031] (Method of making the raised piece) An example of a method for producing the raised piece R will be described. The surface layer R1 shown in FIG. 1 is in a state after the thermosetting resin composition that constitutes it has hardened. On the other hand, the surface layer S1 and the surface layer P1 obtained by cutting it into individual pieces are in a state before the thermosetting resin composition contained therein has completely hardened (see FIGS. 3(b) and 5(b)).

[0032] First, a laminated film 20 shown in FIGS. 3(a) and 3(b) is prepared. The laminated film 20 includes a base film 1, an adhesive layer 2, and a three-layer film 15F. The base film 1 is, for example, a polyethylene terephthalate film (PET film). The adhesive layer 2 is formed into a circular shape by punching or the like (see FIG. 3(a)). The adhesive layer 2 is made of, for example, an ultraviolet-curing adhesive. The adhesive layer 2 has the property of decreasing its adhesiveness when irradiated with ultraviolet light. The three-layer film 15F is formed into a circular shape by punching or the like, and has a smaller diameter than the adhesive layer 2 (see FIG. 3(a)).

[0033] The three-layer film 15F is composed of a pair of surface layers S1, S1 made of thermosetting resin layers and an intermediate layer M sandwiched therebetween. The thickness of the surface layer S1 is substantially the same as that of the above-mentioned surface layer R1, and may be, for example, 5 to 40 μm, 5 to 25 μm, or 5 to 20 μm. The thickness of the intermediate layer M is the same as that of the above-mentioned intermediate layer R2, and may be, for example, 5 to 75 μm, 10 to 75 μm, or 10 to 50 μm. The tensile modulus of the intermediate layer M may be, for example, 8.0 MPa or more, 9.0 MPa or more, or 10.0 MPa or more. When the tensile modulus of the intermediate layer M is 8.0 MPa or more, the intermediate layer R2 functions like a spring plate in the step of picking up the lifting piece R (see FIG. 5(d)), thereby achieving excellent pick-up performance. The upper limit of the tensile modulus of the intermediate layer M is approximately 15 MPa in view of the ease of material availability. Examples of materials constituting the intermediate layer M include polyimide and polyethylene terephthalate (PET). The intermediate layer M may be a layer made of a thermosetting resin composition or a photocurable resin composition that has been cured so that the tensile modulus falls within the above range.

[0034] The laminate film 20 can be produced, for example, by bonding a first laminate film having a base film 1 and an adhesive layer 2 thereon with a second laminate film having a cover film 3 and a three-layer film 15F thereon (see FIG. 4). The first laminate film is obtained through a process of forming an adhesive layer on the surface of the base film 1 by coating, and then processing the adhesive layer into a predetermined shape (e.g., a circle) by punching or the like. The second laminate film is obtained through a process of forming a surface layer S1 on the surface of the cover film 3 (e.g., a PET film or a polyethylene film) by coating, forming an intermediate layer M on the surface of the surface layer S1, forming a surface layer S1 on the surface of the intermediate layer M by coating, and then processing the adhesive film formed through these processes into a predetermined shape (e.g., a circle) by punching or the like. When using the laminate film 20, the cover film 3 is peeled off at an appropriate time.

[0035] As shown in FIG. 5(a), a dicing ring DR is attached to the laminate film 20. That is, the dicing ring DR is attached to the adhesive layer 2 of the laminate film 20, and the three-layer film 15F is placed inside the dicing ring DR. The three-layer film 15F is then diced into individual pieces (see FIG. 5(b)). This results in a large number of raised pieces R being obtained from the three-layer film 15F. Thereafter, for example, the adhesive layer 2 is irradiated with ultraviolet light to reduce the adhesive force between the adhesive layer 2 and the raised pieces R. After the ultraviolet light irradiation, as shown in FIG. 5(c), the inner region of the dicing ring DR on the base film 1 is pushed up by the ring Ra, thereby applying tension to the base film 1 and separating the raised pieces R from each other.

[0036] Next, as shown in FIG. 5(d), the lifting piece R is pushed up by a push-up jig 42 to peel the lifting piece R from the adhesive layer 2, and then the lifting piece R is picked up by suction using a suction collet 44. The three-layer film 15F before dicing or the lifting piece R before picking up may be heated to promote the curing reaction of the thermosetting resin. By appropriately curing the lifting piece R at the time of picking up, excellent pick-up properties can be achieved. The cuts for singulation are preferably formed up to the outer edges of the lifting piece R. The diameter of the three-layer film 15F may be, for example, 300 to 310 mm or 300 to 305 mm. The shape of the three-layer film 15F in plan view is not limited to the circle shown in FIG. 3(a) and may be rectangular (square or oblong).

[0037] Although a three-layered protrusion R is illustrated here, the protrusion may be a two-layered structure in which one of the two surface layers R1, R1 is absent. For example, the protrusion may be a two-layered structure consisting of a first layer in contact with the surface of the substrate 10 and a second layer provided on the surface of the first layer. The first layer corresponds to the surface layer R1 described above, and its material and physical properties may be similar to those of the surface layer R1. The second layer corresponds to the intermediate layer R2 described above, and its material and physical properties may be similar to those of the intermediate layer R2. The thickness of the two-layered protrusion is, for example, 25 to 190 μm, or may be 40 to 125 μm or 40 to 115 μm. The protrusion R may also be a laminate of a dummy chip (first layer) and an adhesive piece (second layer) provided on one side of the dummy chip. Protrusions of these configurations can be fabricated through a dicing process and a pick-up process.

[0038] The chip T1 is, for example, a memory chip. In plan view, the chip T1 has a larger area than the controller chip Tc. The chip T1 is disposed on the substrate 10 via an adhesive piece A1 so as to cover the entire controller chip Tc. In plan view, the shape of the chip T1 is, for example, rectangular (square or oblong). The length of one side of the chip T1 is, for example, 12 mm or less, and may be 6 to 10 mm, or 2 to 4 mm. When these chips are rectangular, the ratio B / A of the length B of the long side to the length A of the short side is, for example, 1.5 to 4, 1.8 to 3.5, or 2.1 to 3.2. The thickness of the chip T1 is, for example, 10 to 170 μm, and may be 10 to 30 μm. These chips have a complex circuit layer (upper surface side in FIG. 1) and a relatively thin semiconductor layer (lower surface side in FIG. 1). As the ratio of the thickness of the semiconductor layer to the total thickness of the chip decreases, the chip becomes more susceptible to warping in the smile direction. For example, if this ratio is 80% or less, smile warpage is likely to occur. Smile warpage means that the chip warps in a downward convex shape.

[0039] The chip T1 and the adhesive piece A1 have substantially the same size in plan view (see FIG. 6(a)). The chip with adhesive piece 31 shown in FIG. 6(a) is a laminate of the adhesive piece A1 (before hardening) and the chip T1. The chip with adhesive piece 31 can be obtained by singulating a laminate of an adhesive film (FOD) for embedding a chip and a semiconductor wafer.

[0040] As shown in FIG. 1, the chip T1 is spaced apart from the multiple padding pieces R in the thickness direction of the semiconductor device 100. The chip T1 is also spaced apart from the controller chip Tc in the thickness direction of the semiconductor device 100. This configuration can suppress the occurrence of bowing of the chip T1 and ensure a sufficient distance from the upper surface of the controller chip Tc to the lower surface of the chip T1. Adhesive pieces A1 are filled between the chip T1 and the multiple padding pieces R. Adhesive pieces A1 are also filled between the chip T1 and the controller chip Tc.

[0041] Chips T2, T3, T4, T5, and T6 are, for example, memory chips, similar to chip T1. The planar shape, size, and thickness of chips T2, T3, T4, T5, and T6 may be similar to those of chip T1. The planar size of chip T2 and adhesive piece A2 are substantially the same (see FIG. 6(b)). The adhesive piece-attached chip 32 shown in FIG. 6(b) is a laminate of adhesive piece A2 (before hardening) and chip T2. The adhesive piece-attached chip 32 can be obtained by singulating a laminate of a die bonding film and a semiconductor wafer. This die bonding film may be thinner than the above-mentioned adhesive film for embedding chips (FOD). In addition to the adhesive piece-attached chip 32, adhesive piece-attached chips 33, 34, 35, and 36, each including chips T3, T4, T5, and T6, are also obtained by dicing.

[0042] [Method of manufacturing semiconductor device] The semiconductor device 100 is manufactured through the following steps. (A) A step of placing a controller chip Tc on a substrate 10 (see FIG. 7). (B) A step of arranging a plurality of padding pieces R around the controller chip Tc on the substrate 10 (see FIG. 8). It should be noted that the step (A) may be performed first and then the step (B), or the step (B) may be performed first and then the step (A). When the step (B) is performed first and then the step (A), in the step (B), a plurality of padding pieces R may be arranged around the area on the substrate 10 where the controller chip Tc is to be arranged. (C) A step of preparing an adhesive piece-attached chip 31 (see FIG. 6(a)). Step (C) may be performed at any timing as long as it is performed before step (D). (D) A process of applying a pressing force to the chip 31 with adhesive pieces toward the substrate 10 so that the entire controller chip Tc and a part of each of the padding pieces R are embedded in the adhesive pieces A1 (see FIG. 9). Step (D) may be performed, for example, on a hot plate. The temperature conditions for thermocompression bonding are, for example, 80 to 150° C., and may be 90 to 130° C. The pressure for thermocompression bonding is, for example, 0.05 to 0.5 MPa, and may be 0.1 to 0.3 MPa. (E) A step of sequentially stacking a plurality of chips with adhesive pieces 32 to 36 on the surface of the chip T1 (see FIG. 10). (F) A step of sealing the chips, wires, etc. on the surface of the substrate 10 with a sealing material.

[0043] In step (D), when applying a pressing force to the chip 31 with adhesive pieces toward the substrate 10, the presence of multiple padding pieces R around the controller chip maintains the flat shape of the chip T1, thereby suppressing the occurrence of bowing. That is, by pressing the chip T1 so that the entire controller chip Tc and portions of each padding piece R arranged at positions corresponding to the peripheral edge of the chip T1 are embedded in the adhesive pieces A1, a sufficiently uniform pressing force is applied to the chip T1 (see FIG. 9). This makes it possible to suppress bowing of the chip T1, and as a result, the occurrence of voids and bleeding can also be suppressed.

[0044] Although the embodiments of the present disclosure have been described in detail above, the present invention is not limited to the above embodiments. For example, in the above embodiments, the controller chip Tc is connected to the substrate 10 by wires Wa, but the controller chip Tc may be flip-chip connected to the substrate 10. Furthermore, in the above embodiments, the three-dimensional NAND memory in which the controller chip is embedded is illustrated, but the padding piece may be applied to other semiconductor devices in which other chips are embedded.

[0045] In the above embodiment, the case where the lifting pieces R are manufactured through the dicing process and the pick-up process has been exemplified, but the lifting pieces may be arranged on the substrate 10 using a transfer film. Fig. 11 is a cross-sectional view showing a schematic example of a transfer film. The transfer film 60 shown in Fig. 11 includes a base film 61 and a plurality of lifting pieces R provided on the surface of the base film 61.T Equipped with raised piece R T The transfer film 60 is made of, for example, a thermosetting resin composition. By preparing such a transfer film 60 in advance, a plurality of raised pieces R can be collectively formed on the surface of the substrate 10 by, for example, heat pressing. T It is possible to place [Industrial Applicability]

[0046] According to the present disclosure, there is provided a method for manufacturing a semiconductor device using a film on adhesive (FOD) for embedding chips, which method can sufficiently suppress the occurrence of voids, bleeding, and bowing. Also, according to the present disclosure, there is provided a semiconductor device having excellent reliability in which the occurrence of voids, bleeding, and bowing during the manufacturing process is sufficiently suppressed. [Explanation of symbols]

[0047] 1...base film, 2...adhesive layer, 3...cover film, 10...substrate, 10a...electrode, 10b...electrode, 15F...three-layer film, 20...laminated film, 31, 32, 33, 34, 35, 36...chip with adhesive piece, 50...sealing layer, 60...transfer film, 61...base film, 100...semiconductor device, A1, A2, A3, A4, A5, A6, Ac...adhesive piece, DR...dicing ring, P1, R1, S1...surface layer, R, R T ...raising piece, M, R2...intermediate layer, T1...chip (second chip), T2, T3, T4, T5, T6...chip, Tc...controller chip (first chip), Wa, Wb...wire.

Claims

1. A substrate; a first chip disposed on the substrate; a plurality of padding pieces disposed on the substrate around the first chip; an adhesive piece that embeds the first chip and at least a portion of the padding piece; a second chip attached to the adhesive piece and arranged to cover the first chip; Equipped with A semiconductor device in which the raised piece has a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers, and the material of the intermediate layer is one selected from the group consisting of polyimide and polyethylene terephthalate.

2. A substrate; a first chip disposed on the substrate; a plurality of padding pieces disposed on the substrate around the first chip; an adhesive piece that embeds the first chip and at least a portion of the padding piece; a second chip attached to the adhesive piece and arranged to cover the first chip; Equipped with A semiconductor device in which the second chip has a square or rectangular shape in plan view, and one of the padding pieces is disposed at each position corresponding to a corner of the second chip.

3. A substrate; a first chip disposed on the substrate; a plurality of padding pieces disposed on the substrate around the first chip; an adhesive piece that embeds the first chip and at least a portion of the padding piece; a second chip attached to the adhesive piece and arranged to cover the first chip; Equipped with In a plan view, the second chip has a rectangular shape, and the two padding pieces are disposed at positions corresponding to the short sides of the second chip.

4. A substrate; a first chip disposed on the substrate; a plurality of padding pieces disposed on the substrate around the first chip; an adhesive piece that embeds the first chip and at least a portion of the padding piece; a second chip attached to the adhesive piece and arranged to cover the first chip; Equipped with The second chip has a rectangular shape in a plan view, A semiconductor device in which the ratio B / A of the length B of the long side of the rectangle to the length A of the short side of the rectangle is 2 or more.

5. the second chip is spaced apart from the plurality of padding pieces; 5. The semiconductor device according to claim 1, wherein the adhesive pieces are filled between the second chip and the plurality of padding pieces.

6. the second chip is spaced apart from the first chip; 6. The semiconductor device according to claim 1, wherein the adhesive piece is filled between the second chip and the first chip.

7. 7. The semiconductor device according to claim 1, wherein the padding piece has a multi-layer structure including a dummy chip and an adhesive piece.

8. The semiconductor device according to any one of claims 1 to 7, wherein the raised piece has a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers.

9. 9. The semiconductor device according to claim 1, wherein the first chip is flip-chip connected to the substrate.

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