Insulated gate semiconductor device

Abstract

To provide an insulated gate semiconductor device which can be further improved.SOLUTION: A main electrode region of a first conductivity type having a high impurity concentration in contact with the first side wall surface of the trench, a base region of a second conductivity type in contact with a lower surface of the main electrode region and the first side wall surface, a drift layer of the first conductivity type having a lower impurity concentration than the main electrode region in contact with a lower surface of the base region and the first side wall surface, a gate protection-region of the second conductivity type having a higher impurity concentration than the base region in contact with the second side wall surface and the bottom surface of the trench, and a base contact region of the second conductivity type separated from the trench and in contact with the gate protection-region and having a higher impurity concentration than the base region.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to an insulated gate semiconductor device having an insulated gate electrode structure in a trench and a method for manufacturing the same. [Background technology]

[0002] Trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) are expected to have reduced on-resistance compared to planar-gate MOSFETs due to a smaller cell pitch. For trench-gate MOSFETs made of wide-bandgap semiconductors such as silicon carbide (SiC), a structure using the a-plane (11-20) for the sidewall of the trench has been proposed (see Patent Documents 1 to 3). In Patent Documents 1 to 3, an n-type source region and a p-type base region are provided on one sidewall of the trench, and the sidewall is used as a current path.

[0003] Insulated gate semiconductor devices such as trench gate MOSFETs that use wide bandgap semiconductors as materials have been required to have further improvements in their structures and manufacturing methods. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2017 / 0077251 [Patent Document 2] Patent No. 6105032 specification [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-163047 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above problems, an object of the present invention is to provide an insulated gate semiconductor device and a method for manufacturing the same that can achieve further improvements in insulated gate semiconductor devices. [Means for solving the problem]

[0006] One aspect of the present invention is an insulated gate semiconductor device in which a plurality of trenches are arranged in a chip structure, each trench having both side walls defined by a first sidewall surface that forms a first inclination angle with respect to a reference plane of the chip structure and a second sidewall surface that faces the first sidewall surface and forms a second inclination angle with respect to the reference plane that is different from the first inclination angle, the semiconductor device including: (a) a first unit cell having an insulated gate electrode structure in a first trench included in the plurality of trenches, the first unit cell including a first conductivity type main electrode region in contact with the first sidewall surface of the first trench; a second conductivity type base region in contact with a lower surface of the main electrode region and the first sidewall surface; and a second conductivity type base region in contact with a lower surface of the base region and the first sidewall surface, the first conductivity type base region having a lower impurity density than the main electrode region; The gist of the present invention is that the present invention is an insulated gate semiconductor device comprising: (a) a first unit cell having a gate protection region of a second conductivity type in contact with a drift layer of a first type and a second sidewall surface and bottom surface of the first trench, the gate protection region having a higher impurity density than the base region; and (b) a second unit cell having an insulated gate electrode structure in a second trench included in the plurality of trenches, the second unit cell being embedded in an upper part of the drift layer and having an operation suppression region of the second conductivity type in contact with the first sidewall surface and second sidewall surface of the second trench and having a higher impurity density than the base region, the second unit cell being arranged to include the second trench located at one end of an array of the plurality of trenches.

[0007] Another aspect of the present invention is summarized as an insulated gate semiconductor device including: (a) an insulated gate electrode structure disposed inside a trench having sidewalls defined by a first sidewall surface that forms a first inclination angle with respect to a reference plane of a chip structure and a second sidewall surface that faces the first sidewall surface and forms a second inclination angle with respect to the reference plane that is different from the first inclination angle; (b) a main electrode region of a first conductivity type in contact with the first sidewall surface of the trench; (c) a base region of a second conductivity type in contact with a lower surface of the main electrode region and the first sidewall surface; (d) a drift layer of the first conductivity type that has a lower impurity density than the main electrode region and that is in contact with a lower surface of the base region and the first sidewall surface; (e) a gate protection region of the second conductivity type that is in contact with the second sidewall surface and a bottom surface of the trench and has a higher impurity density than the base region; and (f) a main electrode in contact with the main electrode region, the insulated gate electrode structure including a Schottky barrier diode formed by the drift layer and the main electrode located between adjacent unit cells.

[0008] Another aspect of the present invention is summarized as an insulated gate semiconductor device comprising: (a) an insulated gate electrode structure disposed inside a trench having sidewalls defined by a first sidewall surface that forms a first inclination angle with respect to a reference plane of a chip structure and a second sidewall surface that faces the first sidewall surface and forms a second inclination angle with respect to the reference plane that is different from the first inclination angle; (b) a main electrode region of a first conductivity type and with a high impurity density in contact with the first sidewall surface of the trench; (c) a base region of a second conductivity type in contact with a lower surface of the main electrode region and the first sidewall surface; (d) a drift layer of the first conductivity type that has a lower impurity density than the main electrode region and that is in contact with a lower surface of the base region and the first sidewall surface; (e) a gate protection region of the second conductivity type that is in contact with the second sidewall surface and bottom surface of the trench and has a higher impurity density than the base region; and (f) a base contact region of the second conductivity type that is spaced from the trench and in contact with the gate protection region and has a higher impurity density than the base region.

[0009] Another aspect of the present invention is summarized as an insulated gate semiconductor device in which a plurality of striped unit cells are arranged, each unit cell including: (a) a drift layer of a first conductivity type; (b) a base region of a second conductivity type provided on the drift layer; (c) a main electrode region of the first conductivity type provided on an upper portion of the base region and having a higher impurity density than the drift layer; (d) an insulated gate electrode structure provided inside a striped trench so that one sidewall surface of the main electrode region and the base region are in contact with each other; and (e) a gate protection region of the second conductivity type provided in a striped pattern on the drift layer so as to be in contact with a bottom surface and the other sidewall surface of the trench, the gate protection region having a higher impurity density than the base region, and the structure in which a common base region is sandwiched between the trenches of adjacent unit cells and the structure in which a common gate protection region is sandwiched between the trenches of adjacent unit cells are alternately repeated, and the gate protection regions are arranged intermittently along the longitudinal direction of the trench.

[0010] Another aspect of the present invention is summarized as a method for manufacturing an insulated gate semiconductor device, including: (a) forming a base region of a second conductivity type on a drift layer of a first conductivity type; (b) forming a main electrode region of the first conductivity type on an upper portion of the base region, the main electrode region having a higher impurity concentration than the drift layer; (c) forming a trench reaching the drift layer, the trench having both side walls defined by a first sidewall surface that forms a first inclination angle with respect to a reference plane of a chip structure in which the main electrode region is formed and a second sidewall surface that faces the first sidewall surface and forms a second inclination angle with respect to the reference plane that is different from the first inclination angle, thereby exposing the main electrode region and the base region at the first sidewall surface; (d) forming a gate protection region of the second conductivity type in contact with the bottom surface and the first sidewall surface of the trench by obliquely implanting ions into the bottom surface and the first sidewall surface of the trench; and (e) forming an insulated gate electrode structure inside the trench. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide an insulated gate semiconductor device and a method for manufacturing the same that can achieve further improvements in insulated gate semiconductor devices. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view showing an example of an insulated gate semiconductor device according to a first embodiment. [Figure 2] 2 is a vertical cross-sectional view of the insulated gate semiconductor device according to the first embodiment as seen from the AA direction in FIG. 1. FIG. [Figure 3] 2 is a vertical cross-sectional view of the insulated gate semiconductor device according to the first embodiment as seen from the BB direction in FIG. 1. [Figure 4] FIG. 2 is a schematic diagram for explaining the plane orientation of the sidewall surface of a trench. [Figure 5] FIG. 2 is a schematic diagram for explaining the plane orientation of the sidewall surface of a trench. [Figure 6] 1 is a graph showing the relationship between the plane orientation of the sidewall surface of a trench and the gate voltage and mobility. [Figure 7] FIG. 3 is a cross-sectional view of a main portion showing another example of the insulated gate semiconductor device according to the first embodiment. [Figure 8] FIG. 3 is a cross-sectional view of a main portion showing another example of the insulated gate semiconductor device according to the first embodiment. [Figure 9] FIG. 3 is a cross-sectional view of a main portion showing another example of the insulated gate semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a main part of an example of an insulated gate semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a cross-sectional view of a main portion showing another example of an insulated gate semiconductor device according to the second embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a main portion showing another example of an insulated gate semiconductor device according to the second embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a main portion showing another example of an insulated gate semiconductor device according to the second embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a main part of an example of an insulated gate semiconductor device according to a third embodiment. [Figure 15] 10A to 10C are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to a third embodiment. [Figure 16]16A to 16C are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to the third embodiment, following FIG. 15. [Figure 17] 17A to 17C are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to the third embodiment, following FIG. 16. [Figure 18] 18A to 18C are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to the third embodiment, following FIG. 17. [Figure 19] 19A to 19C are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to the third embodiment, following FIG. 18. [Figure 20] 20A to 20C are cross-sectional views illustrating steps in the example of the method for manufacturing the insulated gate semiconductor device according to the third embodiment, following FIG. 19. [Figure 21] 21A to 21C are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to the third embodiment, following FIG. 20. [Figure 22] 22A to 22D are cross-sectional views illustrating steps in an example of a method for manufacturing an insulated gate semiconductor device according to the third embodiment, following FIG. 21. [Figure 23] 23A to 23C are cross-sectional views illustrating steps in the example of the method for manufacturing the insulated gate semiconductor device according to the third embodiment, following FIG. 22. [Figure 24] FIG. 10 is a cross-sectional view of a main portion showing another example of an insulated gate semiconductor device according to the third embodiment. [Figure 25] FIG. 10 is a cross-sectional view of a main portion showing another example of an insulated gate semiconductor device according to the third embodiment. [Figure 26] FIG. 10 is a cross-sectional view of a main portion showing another example of an insulated gate semiconductor device according to the third embodiment. [Figure 27] FIG. 10 is a cross-sectional view showing a main part of an example of an insulated gate semiconductor device according to a fourth embodiment. [Figure 28] 28 is a horizontal cross-sectional view of the insulated gate semiconductor device according to the fourth embodiment as seen from the AA direction in FIG. 27. FIG. [Figure 29] 29 is a vertical cross-sectional view of the insulated gate semiconductor device according to the fourth embodiment as seen from the CC direction in FIG. 28. FIG. [Figure 30] 28 is another horizontal cross-sectional view of the insulated gate semiconductor device according to the comparative example, seen from the direction AA in FIG. 27. [Figure 31] 28 is another horizontal cross-sectional view of the insulated gate semiconductor device in accordance with the fourth embodiment as seen from the AA direction in FIG. 27. FIG. [Figure 32] 28 is another horizontal cross-sectional view of the insulated gate semiconductor device in accordance with the fourth embodiment as seen from the AA direction in FIG. 27. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, first to fourth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0014] In this specification, the term "first main electrode region" refers to a semiconductor region that becomes either the source region or the drain region in a field-effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), the term refers to a semiconductor region that becomes either the emitter region or the collector region. Also, in a static induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), the term refers to a semiconductor region that becomes either the anode region or the cathode region. In a FET or SIT, the term "second main electrode region" refers to a semiconductor region that becomes either the source region or the drain region, but that does not become the first main electrode region. In an IGBT, the term refers to a region that becomes either the emitter region or the collector region, but that does not become the first main electrode region. In a SI thyristor or a GTO, the term refers to a region that becomes either the anode region or the cathode region, but that does not become the first main electrode region. Thus, if the "first main electrode region" is the source region, the "second main electrode region" refers to the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. In an FET or the like, the functions of the "first main electrode region" and the "second main electrode region" can be interchanged by exchanging the bias relationship. Furthermore, in this specification, when the term "main electrode region" is simply used, it comprehensively means either the first main electrode region or the second main electrode region.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are read as being converted to left and right, and if it is rotated 180 degrees and observed, up and down are read as being reversed. The following description will exemplify a case where the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the "+" or "-" attached to "n" or "p" indicates a semiconductor region with a relatively higher or lower impurity density, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the same "n" and "n" are attached to semiconductor regions, this does not necessarily mean that the impurity densities of the respective semiconductor regions are strictly the same. Furthermore, it is technically and logically self-evident that the components and regions to which the limitations of "first conductivity type" and "second conductivity type" are added in the following description mean components and regions made of semiconductor materials even if there is no particular explicit limitation. Also, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0016] 1, the insulated gate semiconductor device (MISFET) according to the first embodiment has a chip structure including an array of a plurality of unit cells C1-C3, ..., C4-C6, each having a plurality of trenches 10a-10c, ..., 10d-10f of the same shape. Note that in the insulated gate semiconductor device according to the first embodiment, the number of trenches and the number of unit cells are not particularly limited. The insulated gate semiconductor device according to the first embodiment can be configured as a power semiconductor device that can pass a large current by further arranging a plurality of these unit cells to form a multi-channel structure.

[0017] In FIG. 1, the planar pattern of the trenches 10a-10c, ..., 10d-10f is schematically shown by dashed lines. The trenches 10a-10c, ..., 10d-10f are striped and extend parallel to one another. In a direction perpendicular to the longitudinal direction of the trenches 10a-10c, ..., 10d-10f (the parallel direction of the trenches 10a-10c, ..., 10d-10f), the unit cells C1-C3 are located on the left periphery of the array structure, and the unit cell C1 is located at one end of the array structure. The unit cells C4-C6 are located on the right periphery of the array structure, and the unit cell C6 is located at the other end of the array structure.

[0018] Figure 2 is a vertical cross-sectional view of unit cells C1 to C3 in the left peripheral portion shown in Figure 1, viewed from the direction AA. As shown in Figure 2, the insulated gate semiconductor device according to the first embodiment includes a drift layer 1 of a first conductivity type (n-type), and base regions 3a and 3b of a second conductivity type (p-type) arranged on the drift layer 1. The drift layer 1 and base regions 3a and 3b are each composed of an epitaxially grown layer made of SiC.

[0019] The upper portions of the base regions 3a and 3b are provided with n-type impurity layers having a higher impurity density than the drift layer 1. + First main electrode regions (source regions) 4a to 4d of a p-type are selectively provided. The source regions 4a and 4c are in contact with the base regions 3a and 3b, respectively. The source regions 4b and 4d are not used as current paths, so they may not be provided. On the drift layer 1, p-type impurity regions with a higher impurity density than the base regions 3a and 3b are provided. + Gate protection regions 2a and 2b are selectively provided. The upper surfaces of the gate protection regions 2a and 2b are located at the same horizontal level as the upper surfaces of the source regions 4a to 4d. The gate protection region 2a contacts the source regions 4b and 4c and the base region 3b.

[0020] The trenches 10a to 10c are provided so as to extend from the upper surfaces of the source regions 4a to 4d to the drift layer 1. While FIG. 2 illustrates an example in which both sidewall surfaces of the trenches 10a to 10c are parallel to the vertical direction, this is not limiting. For example, both sidewall surfaces of the trenches 10a to 10c may be inclined so as to taper downward. Furthermore, although the trenches 10a to 10c each have a flat bottom surface, they may also have a curved surface, and the corners of the bottom surface may have curvature.

[0021] One sidewall surface (a first sidewall surface described later) of trench 10b contacts the source region 4a and base region 3a, and the other sidewall surface (a second sidewall surface described later) contacts the source region 4b and gate protection region 2b. One sidewall surface of trench 10d contacts the source region 4c and base region 3b, and the other sidewall surface contacts the source region 4d and gate protection region 2b. Although the bottom surfaces of trenches 10b and 10d are in contact with the drift layer 1 and gate protection regions 2a and 2b, respectively, the entire bottom surfaces of trenches 10b and 10d may be covered with the gate protection regions 2a and 2b, respectively. On the other hand, both sidewall surfaces and the bottom surface of trench 10a are covered with p + The gate protection regions 2a and 2b are covered with an operation suppression region 2x. The operation suppression region 2x contacts the source region 4a and the base region 3a. The operation suppression region 2x is provided at the same depth as the gate protection regions 2a and 2b.

[0022] Gate insulating films 5a to 5c are provided on the bottom and sidewall surfaces of the trenches 10a to 10c. As the gate insulating films 5a to 5c, in addition to a silicon oxide film (SiO2 film), any one of a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (YO3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, or a composite film obtained by laminating two or more of these films can be used.

[0023] Gate electrodes 6a-6c are buried inside the trenches 10a-10c with gate insulating films 5a-5c interposed therebetween, thereby forming an insulated gate electrode structure (5a, 6a), (5b, 6b), (5c, 6c). The gate electrodes 6a-6c can be made of a polysilicon layer (doped polysilicon layer) doped with a high impurity concentration, such as phosphorus (P).

[0024] A first main electrode (source electrode) 8 is disposed on the gate electrodes 6a-6c via an interlayer insulating film 7. A non-doped silicon oxide film (SiO2 film) containing no phosphorus (P) or boron (B), known as "NSG," can be used as the interlayer insulating film 7. However, the interlayer insulating film 7 may also be a phosphorus-doped silicon oxide film (PSG), a boron-doped silicon oxide film (BSG), a boron- and phosphorus-doped silicon oxide film (BPSG), a silicon nitride film (Si3N4), or the like. The source electrode 8 is electrically connected to the source regions 4a, 4c and the gate protection regions 2a, 2b. The source electrode 8 is disposed separately from the gate surface electrode (not shown) located at the back of the page.

[0025] For example, the source electrode 8 can be made of an aluminum (Al) film. The gate surface electrode can be made of the same material as the source electrode 8. Although not shown, a source contact layer and a barrier metal layer that serve as an underlying metal may be disposed below the source electrode 8. For example, if the source contact layer is made of nickel silicide (NiSi x ) film, and the barrier metal layer can be composed of a titanium nitride (TiN) film.

[0026] The bottom surface of the drift layer 1 is provided with n +A second main electrode region (drain region) 9 having a shaped cross section is disposed on the bottom surface of the drain region 9. The drain region 9 is composed of a semiconductor substrate (SiC substrate) made of SiC. A second main electrode (drain electrode) 11 is disposed on the bottom surface of the drain region 9. The drain electrode 11 may be, for example, a single layer film made of gold (Au), or a metal film laminated in the order of Al, nickel (Ni), and Au, and may further be laminated on the bottom layer with a metal film such as molybdenum (Mo) or tungsten (W), or an alloy layer formed by depositing nickel (Ni) and titanium (Ti) and reacting them with SiC.

[0027] On the other hand, a vertical cross-sectional view of unit cells C4 to C6 located in the right peripheral portion shown in FIG. 1, viewed from the BB direction, corresponds to FIG. 3. As shown in FIG. 3, p-type base regions 3c to 3e are disposed on an n-type drift layer 1. Above the base regions 3c to 3e, n + The source regions 4e, 4g, and 4h are in contact with the base regions 3c to 3e, respectively. The source regions 4f, 4h, and 4j are not used as current paths, so they may not be provided. + Gate protection regions 2c to 2e are selectively provided. The upper surfaces of the gate protection regions 2c to 2e are located at the same horizontal level as the upper surfaces of the source regions 4e to 4j. The gate protection region 2c contacts the source region 4g and the base region 3d. The gate protection region 2d contacts the source region 4i and the base region 3e.

[0028] Trenches 10d-10f are provided so as to extend from the upper surfaces of the source regions 4e-4j to the drift layer 1. One sidewall surface of trench 10d contacts the source region 4e and base region 3c, and the other sidewall surface contacts the source region 4f and gate protection region 2c. One sidewall surface of trench 10e contacts the source region 4g and base region 3d, and the other sidewall surface contacts the source region 4h and gate protection region 2d. One sidewall surface of trench 10f contacts the source region 4i and base region 3e, and the other sidewall surface contacts the source region 4j and gate protection region 2e. Although a case where the bottom surfaces of trenches 10d-10f contact the drift layer 1 and gate protection regions 2c-2e, respectively, is illustrated, the entire bottom surfaces of trenches 10d-10f may be covered with the gate protection regions 2c-2e, respectively.

[0029] Gate electrodes 6d-6f are buried inside the trenches 10d-10f with gate insulating films 5d-5f interposed therebetween, forming an insulated gate electrode structure (5d, 6d), (5e, 6e), (5f, 6f). A source electrode 8 is disposed on the gate electrodes 6d-6f with an interlayer insulating film 7 interposed therebetween. The source electrode 8 is electrically connected to the source regions 4e, 4g, 4h and the gate protection regions 2c-2e. An n-type semiconductor layer 1 is disposed on the underside of the drift layer 1 so as to contact the drift layer 1. + A drain region 9 is disposed on the bottom surface of the semiconductor substrate 1. A drain electrode 11 is disposed on the bottom surface of the drain region 9.

[0030] 4 to 6, the plane orientations used for the sidewall surfaces of the trenches 10a to 10c, ..., 10d to 10f shown in Figures 1 to 3 will be described. The chip structure in which the trenches 10a to 10c, ..., 10d to 10f shown in Figures 1 to 3 are formed is, for example, as shown in Figure 4. <0001> The off-angle θ1 is approximately 4° to 8° in the <11-20> direction relative to the (c-axis) direction. The off-angle θ1 is the angle between the reference plane of the chip structure and a plane (basal plane) perpendicular to the c-axis, which is the (0001) plane (Si plane) or the (000-1) plane (C plane). The solid lines L1 on the side of the chip structure schematically represent the Si plane. Consider providing a trench T1 and a trench T2 perpendicular to trench T1 in this chip structure. The sidewall surfaces S1 and S2 of trench T1 use the m-plane, which is the (1-100) plane perpendicular to the (0001) plane. Because the sidewall surfaces S1 and S2 of trench T1 are actually tapered, both sidewall surfaces S1 and S2 of trench T1 are m-planes inclined approximately 9° toward the Si plane.

[0031] Figure 5 shows a chip structure with a trench T2. As shown in Figure 5, the opposing sidewall surfaces S3 and S4 of trench T2 are both a-planes, which are (11-20) planes. In Figure 5, dashed lines L2 and L3 parallel to the a-plane are shown. In this case, because the semiconductor wafer has an off-axis angle θ1, the inclination angle θ2 of one sidewall surface S3 of trench T2 relative to the a-plane is different from the inclination angle θ3 of the other sidewall surface S4 relative to the a-plane. For example, when the off-axis angle θ1 is 4°, the inclination angle θ2 of the sidewall surface S3 of trench T2 relative to the a-plane on the Si-face side is 5°, and the inclination angle θ4 of the sidewall surface S4 of trench T2 relative to the a-plane on the Si-face side is 13°. Figure 6 shows the relationship between gate voltage and electron mobility for an m-plane inclined 9° toward the Si-face side, an a-plane inclined 5° toward the Si-face side, and an a-plane inclined 13° toward the Si-face side. As can be seen from Figure 6, the electron mobility is highest for the a-plane tilted at 5° toward the Si surface, followed by the m-plane tilted at 9° toward the Si surface, and finally the a-plane tilted at 13° toward the Si surface.

[0032] In the insulated gate semiconductor device according to the first embodiment, the a-plane, which has a relatively small inclination angle θ2 toward the Si-plane and high electron mobility, is used as the sidewall surface of trenches 10b-10c, ..., 10d-10f shown in Figures 1 to 3 that contacts source regions 4a, 4c, 4e, 4g, and 4i and base regions 3a-3e, and is utilized as a current path. This a-plane is defined as a "first sidewall surface" that forms a first inclination angle θ2 with respect to the reference plane (a-plane) of the chip structure.

[0033] 1 to 3, the a-plane, which has a relatively large inclination angle θ3 toward the Si-plane and low electron mobility, is used as the sidewall surface of the trenches 10b to 10c, ..., 10d to 10f that contacts the source regions 4b, 4d, 4f, 4h, and 4j and the gate protection regions 2a to 2e. This a-plane is defined as a "second sidewall surface" that faces the first sidewall surface, forms a second inclination angle θ3 with respect to the reference plane (a-plane) that is different from the first inclination angle θ2, and has lower electron mobility than the first sidewall surface. In this way, both sidewalls of the trenches 10b to 10c, ..., 10d to 10f are defined as a "first sidewall surface" and a "second sidewall surface."

[0034] During operation of the insulated gate semiconductor device in accordance with the first embodiment, a positive voltage is applied to the drain electrode 11, and a positive voltage equal to or greater than the threshold is applied to the gate electrodes 6a-6f. As a result, inversion layers (channels) are formed in the base regions 3a-3e on the gate electrodes 6b-6f sides of the base regions 3a-3e in the unit cells C2-C6, excluding the unit cell C1 located at one end of the array of unit cells C1-C3, ..., C4-6, resulting in an ON state. In the ON state, a current flows from the drain electrode 11 to the source electrode 8 via the drain region 9, the drift layer 1, the inversion layers in the base regions 3a-3e, and the source regions 4a, 4c, 4e, 4g, and 4i. On the other hand, when the voltage applied to the gate electrodes 6a-6f is less than the threshold, no inversion layers are formed in the base regions 3a-3e, resulting in an OFF state, and no current flows from the drain electrode 11 to the source electrode 8. On the other hand, in unit cell C1 located at one end of the array of unit cells C1 to C3, ... C4 to C6, both sidewalls and the bottom of trench 10a are covered with operation suppression region 2x, so that operation of unit cell C1 is suppressed when the insulated gate semiconductor device of the first embodiment is in operation.

[0035] In the unit cell C1 located at the end of the array structure of the unit cells C1 to C3, ..., C4 to 6, the pattern of the trench 10a is relatively easily broken. In contrast, in the insulated gate semiconductor device according to the first embodiment, in the unit cell C1 located at the end of the array structure of the unit cells C1 to C3, ..., C4 to 6, the bottom and both sidewalls of the trench 10a are p + The unit cell C1 is covered with the mold operation suppression region 2x. This suppresses the operation of the unit cell C1 even if the pattern of the trench 10a is broken, thereby improving reliability.

[0036] 7, in the unit cell C6 located at the other end of the array structure of the unit cells C1 to C3, . . . C4 to C6, the bottom and both sidewalls of the trench 10f are also p + The unit cell C6 may be covered with a mold operation suppression region 2y. The operation suppression region 2y contacts the bottom and sidewall surface of the trench 10e of the unit cell C5 adjacent to the unit cell C6. The operation suppression region 2y is a semiconductor region common to the gate protection region of the unit cell C5, and also functions as the gate protection region of the unit cell C5. According to the structure shown in FIG. 7, even if the patterns of the trenches 10a and 10f of the unit cells C1 and C6 located at both ends of the array structure of the unit cells C1 to C3, ..., C4 to C6 are broken, the operation of the unit cells C1 and C6 is suppressed, thereby improving reliability.

[0037] 8, in two unit cells C1 and C2 located at the ends of the array structure of unit cells C1 to C3, . . . C4 to C6, the bottoms and both sidewalls of trenches 10a and 10b are p + The unit cells C1 to C3, ..., C4 to C6 may be covered with a mold operation suppression region 2x. This suppresses the operation of the unit cells C1 and C2 even if the patterns of the trenches 10a and 10b of the two unit cells C1 and C2 located at the ends of the array structure of the unit cells C1 to C3, ..., C4 to C6 are broken, thereby improving reliability.

[0038] Furthermore, as shown in FIG. 9, in two unit cells C5 and C6 located at the other end of the array structure of the unit cells C1 to C3, . . . C4 to C6, the bottoms and both sidewalls of the trenches 10e and 10f are also p + The unit cell C5 may be covered with a mold operation suppression region 2y. The operation suppression region 2y contacts the bottom and sidewall surface of the trench 10d of the unit cell C4 adjacent to the unit cell C5. The operation suppression region 2y is a semiconductor region common to the gate protection region of the unit cell C4 and also functions as the gate protection region of the unit cell C4. According to the structure shown in FIGS. 8 and 9, even if the patterns of the trenches 10a, 10b and trenches 10e, 10f are broken in the unit cells C1, C2 and C5, C6 located at both ends of the array structure of the unit cells C1 to C3, ..., C4 to C6, the operation of the unit cells C1, C2 and C5, C6 is suppressed, thereby improving reliability.

[0039] The trench 10a of one unit cell C0 at one end of the array structure of unit cells C1 to C3, . . . C4 to C6 shown in FIG. + The structure covered with the operation suppression region 2x of the type and the trenches 10e and 10f of the two unit cells C5 and C6 at the other end of the array structure of the unit cells C1 to C3, . . . C4 to C6 shown in FIG. + Furthermore, the trenches 10a and 10b of the two unit cells C0 at one end of the array structure of the unit cells C1 to C3, ..., C4 to C6 shown in FIG. + The trench 10f of one unit cell C6 at the other end of the array structure of unit cells C1 to C3, . . . C4 to C6 shown in FIG. 7 is p + It may be combined with a structure covered with a mold motion suppression region 2y.

[0040] (Second embodiment) As shown in FIG. 10, the insulated gate semiconductor device according to the second embodiment includes a drift layer 1 of a first conductivity type (n-type) and a second conductivity type (p-type) semiconductor layer selectively provided on the drift layer 1. +The drift layer 1 includes base regions 3a and 3b of the first conductivity type. Main electrode regions (source regions) 4a to 4d of the first conductivity type are provided above the base regions 3a and 3b and have a higher impurity concentration than the drift layer 1. Note that 4b and 4d are not used as current paths and may therefore not be provided.

[0041] Trenches 10a and 10b are provided so as to penetrate through the source regions 4a to 4d. One sidewall surface of trench 10a contacts source region 4a and base region 3a, and the other sidewall surface contacts source region 4b. One sidewall surface of trench 10b contacts source region 4c and base region 3b, and the other sidewall surface contacts source region 4d.

[0042] In the insulated gate semiconductor device according to the second embodiment, the a-plane, which has relatively high electron mobility, is used as the sidewall surfaces of trenches 10a and 10b facing source regions 4a and 4c and base regions 3a and 3b. On the other hand, the a-plane, which has relatively low electron mobility, is used as the sidewall surfaces of trenches 10a and 10b facing source regions 4b and 4d. That is, the sidewall surfaces of trenches 10a and 10b facing source regions 4a and 4c and base regions 3a and 3b are first sidewall surfaces, and the sidewall surfaces of trenches 10a and 10b facing source regions 4b and 4d are second sidewall surfaces.

[0043] Inside the trenches 10a and 10b, insulated gate electrode structures (5a, 6a) and (5b, 6b) each consisting of a gate insulating film 5a and a gate electrode 6a and a gate electrode 6b are provided. On the drift layer 1, a second conductivity type (p + Gate protection regions 2a to 2c (type) are selectively provided. Gate protection region 2a contacts source region 4a and base region 3a. Gate protection region 2b contacts the bottom and sidewall surfaces of trench 10a and also contacts source region 4b. Gate protection region 2c contacts the bottom and sidewall surfaces of trench 10b and also contacts source region 4d.

[0044] A first main electrode (source electrode) 8 is disposed on the gate electrodes 6a and 6b via an interlayer insulating film 7. The source electrode 8 contacts the source regions 4a and 4c and the gate protection regions 2a to 2c. + A second main electrode region (drain region) 9 is disposed on the bottom surface of the drain region 9. A second main electrode (drain electrode) 11 is disposed on the bottom surface of the drain region 9.

[0045] The insulated gate semiconductor device according to the second embodiment has a Schottky barrier diode D1 (schematically shown by a circuit symbol in FIG. 10) formed by a drift layer 1 and a source electrode 8 between unit cells each including trenches 10a and 10b. The Schottky barrier diode D1 functions as a free wheeling diode (FWD). In the structure shown in FIG. 10, a Schottky junction of the Schottky barrier diode D1 is formed by the source electrode 8 and the upper surface of the drift layer 1, which is located at the same horizontal level as the upper surfaces of the source regions 4a to 4d. Other configurations and basic operations of the insulated gate semiconductor device according to the second embodiment are similar to those of the insulated gate semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0046] In the insulated gate semiconductor device according to the second embodiment, the Schottky barrier diode D1 is built-in, eliminating the need for an external FWD and reducing the number of components.

[0047] 11, the configuration of the Schottky barrier diode D2 is different from that of the insulated gate semiconductor device according to the second embodiment shown in FIG. + Gate protection regions 2a to 2c and p +A base contact region 2f is selectively provided. The source electrode 8 has a protruding portion 8a buried to the same depth as the bottom surfaces of the trenches 10a, 10b so as to be sandwiched between the gate protection region 2b and the base contact region 2f. A Schottky junction is formed between the bottom surface of the protruding portion 8a of the source electrode 8 and the drift layer 1, thereby constituting a Schottky barrier diode D2.

[0048] 12, the configuration of the Schottky barrier diode D3 is different from that of the insulated gate semiconductor device according to the second embodiment shown in FIG. + Insulated gate protection regions 2a-2c are selectively provided. The source electrode 8 has a protruding portion 8a buried to the same depth as the bottom surfaces of the trenches 10a, 10b so as to be sandwiched between the gate protection region 2b and the base region 3b. A Schottky junction is formed between the side surface of the protruding portion 8a of the source electrode 8 and the drift layer 1, thereby configuring a Schottky barrier diode D3. According to the modified example of the insulated gate semiconductor device of the second embodiment shown in FIG. 12, a Schottky junction is formed between the side surface of the protruding portion 8a of the source electrode 8 and the drift layer 1. Therefore, the width W1 of the gate protection region 2b can be reduced while maintaining the area of ​​the Schottky barrier diode D3, and the chip size can be reduced.

[0049] 13, the configuration of the Schottky barrier diode D3 is different from that of the insulated gate semiconductor device according to the second embodiment shown in FIG. + Gate protection regions 2a to 2c and p +A base contact region 2f is selectively provided. The source electrode 8 has a protruding portion 8a embedded in the drift layer 1 to the same depth as the bottom surfaces of the trenches 10a and 10b so as to be sandwiched between the drift layer 1 and the base contact region 2f. The bottom surface of the protruding portion 8a contacts the drift layer 1 and the base contact region 2f. A stepped Schottky junction is formed by the region from the lower surface of the source electrode 8 to the side surface and bottom surface of the protruding portion 8a of the source electrode 8 and the drift layer 1. According to the modification of the insulated gate semiconductor device according to the second embodiment shown in FIG. 13, the area of ​​the Schottky barrier diode D4 can be increased, enabling a reduction in the forward voltage.

[0050] (Third embodiment) 14, the insulated gate semiconductor device according to the third embodiment includes a drift layer 1 of a first conductivity type (n-type), and base regions 3a and 3b of a second conductivity type (p-type) selectively provided on the drift layer 1. The upper portions of the base regions 3a and 3b are doped with the first conductivity type (n-type) at a higher impurity density than the drift layer 1. + Main electrode regions (source regions) 4a to 4c (type) are provided. Note that the source region 4b is not used as a current path and may not be provided. A trench 10 is provided from the upper surfaces of the source regions 4a to 4c, penetrating the source regions 4a and 4b to reach the drift layer 1. One sidewall surface of the trench 10 contacts the source region 4a and the base region 3a, and the other sidewall surface contacts the source region 4b.

[0051] In the insulated gate semiconductor device according to the third embodiment, the a-plane, which has relatively high electron mobility, is used as the sidewall surface of trench 10 facing source region 4a and base region 3a. That is, the sidewall surface of trench 10 facing source region 4a and base region 3a is the first sidewall surface, and the sidewall surface of trench 10 facing source region 4b is the second sidewall surface.

[0052] An insulated gate electrode structure (5, 6) is provided inside the trench 10. A first main electrode (source electrode) 8 is disposed on the gate electrode 6 via an interlayer insulating film 7. The source electrode 8 contacts the source regions 4a and 4c. An n-type electrode 8 is disposed on the lower surface of the drift layer 1 so as to contact the drift layer 1. + A second main electrode region (drain region) 9 is disposed on the bottom surface of the drain region 9. A second main electrode (drain electrode) 11 is disposed on the bottom surface of the drain region 9.

[0053] On the drift layer 1, a second conductivity type (p + A gate protection region 2 (p-type) is selectively provided. The gate protection region 2 is a region formed in a self-aligned manner by obliquely implanting p-type impurities into the sidewall and bottom surfaces of the trench 10 during the manufacture of the insulated gate semiconductor device according to the third embodiment. The gate protection region 2 has an L-shaped cross-sectional pattern and contacts the bottom and sidewall surfaces of the trench 10.

[0054] On the drift layer 1, a second conductivity type (p + In the third embodiment, base contact regions 2h and 2i (type) are selectively provided. The base contact region 2h is in contact with the source region 4a and the base region 3a. The base contact region 2i is in contact with the source regions 4b and 4c, the base region 3b, and the gate protection region 2. For example, the impurity density of the gate protection region 2 may be higher than that of the base contact regions 2h and 2i, or may be the same as that of the base contact regions 2h and 2i. The other configurations and basic operations of the insulated gate type semiconductor device of the third embodiment are similar to those of the insulated gate type semiconductor device of the first embodiment, and therefore, redundant explanations will be omitted.

[0055] In the insulated gate semiconductor device of the third embodiment, by providing the gate protection region 2 so as to contact the bottom and sidewall surfaces of the trench 10, electric field concentration at the bottom of the trench 10 can be suppressed and the gate insulating film 5 at the bottom of the trench 10 can be protected.

[0056] Next, a method for manufacturing an insulated gate semiconductor device according to the third embodiment will be described using a trench gate MISFET as an example, with reference to Figures 15 to 23. Note that the method for manufacturing a trench gate MISFET described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the spirit of the claims.

[0057] First, n-type impurities such as nitrogen (N) are added. + A semiconductor substrate (SiC substrate) of this type is prepared. For example, the SiC substrate is a 4H-SiC substrate, and has an off-angle of 4°. + Using a SiC substrate as a drain region 9, an n-type drift layer 1 and a p-type base region 3 are epitaxially grown in this order on the upper surface of the drain region 9, as shown in FIG.

[0058] Next, a photoresist film is applied to the upper surface of the base region 3, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as N are implanted in multiple stages. After removing the ion implantation mask, a new photoresist film is applied to the base region 3 using photolithography, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. After removing the ion implantation mask, a heat treatment is performed to activate the implanted n-type impurity ions and p-type impurity ions. As a result, as shown in FIG. 16, p-type impurity ions are formed in the upper part of the drift layer 1, exposed at the upper surfaces of the base regions 3a and 3b. + The base contact regions 2h and 2i are selectively formed. + The source regions 4, 4c are selectively formed.

[0059] Next, a photoresist film 31 is applied to the upper surfaces of the source regions 4, 4c and the base contact regions 2h, 2i, and then patterned using photolithography. Using the patterned photoresist film 31 as an etching mask, portions of the source region 4, base region 3a, base contact region 2i, and drift layer 1 are selectively removed by dry etching such as reactive ion etching (RIE). As a result, as shown in FIG. 17, trenches 10 are selectively formed so as to reach the top of the drift layer 1. One sidewall surface of the trench 10 is a first sidewall surface, which exposes the source region 4a and base region 3a. The other sidewall surface of the trench 10 is a second sidewall surface, which exposes the base contact region 2i. The bottom surface of the trench 10 exposes the drift layer 1 and base contact region 2i.

[0060] 18, using the photoresist film 31 as an ion implantation mask, p-type impurities are ion-implanted obliquely into the sidewall and bottom surfaces of the trench 10 on the side of the base contact region 2i. After removing the photoresist film 31 used as the ion implantation mask, the implanted p-type impurity ions are activated by heat treatment. As a result, as shown in FIG. 19, the gate protection region 2 having an L-shaped cross-sectional pattern is formed in a self-aligned manner so as to be exposed on the sidewall and bottom surfaces of the trench 10.

[0061] Next, as shown in FIG. 20, a gate insulating film 5 such as an SiO2 film is formed on the bottom and sidewall surfaces of the trench 10 and on the upper surfaces of the source regions 4a-4c and the base contact regions 2h, 2i by thermal oxidation, chemical vapor deposition (CVD), or the like. Next, a polysilicon layer (doped polysilicon layer) doped with impurities such as phosphorus (P) at a high impurity density is deposited by CVD or the like so as to fill the trench 10. Thereafter, the polysilicon layer and the gate insulating film 5 on the upper surfaces of the source regions 4a-4c and the base contact regions 2h, 2i are removed by etch-back, chemical mechanical polishing (CMP), or the like. As a result, as shown in FIG. 21, a gate electrode 6 made of a polysilicon layer is buried in the trench 10, forming an insulated gate electrode structure (5, 6).

[0062] Next, an interlayer insulating film 7 is deposited on the upper surface of the insulated gate electrode structure (5, 6) by a CVD method or the like. Then, as shown in FIG. 22, a portion of the interlayer insulating film 7 is selectively removed by photolithography and dry etching. As a result, a source contact hole is opened in the interlayer insulating film 7. Although not shown, a gate contact hole is also opened in the interlayer insulating film 7 at a location different from the source contact hole so as to expose a portion of the gate surface electrode connected to the gate electrode 6.

[0063] Next, a metal layer such as an Al film is deposited by sputtering or the like. The metal layer such as the Al film is patterned using photolithography and RIE or the like to form patterns of a source electrode 8 and a gate surface electrode (not shown), as shown in FIG. 23. As a result, the patterns of the source electrode 8 and the gate surface electrode are separated. Next, as shown in FIG. 14, a drain electrode 11 made of Au or the like is formed on the entire lower surface of the drain region 9 by sputtering or vapor deposition or the like. In this way, an insulated gate semiconductor device according to an embodiment of the present invention is completed.

[0064] According to the method for manufacturing an insulated gate semiconductor device in accordance with the third embodiment, after forming trench 10, p-type impurity ions are obliquely implanted, thereby forming gate protection region 2 in contact with the bottom and sidewall surfaces of trench 10 in a self-aligned manner. This makes it possible to easily realize the insulated gate semiconductor device shown in FIG.

[0065] 24 differs from the insulated gate semiconductor device according to the third embodiment shown in Fig. 14 in that the side surface of the end of gate protection region 2 that contacts the bottom surface of trench 10 is inclined relative to the vertical direction. The end of gate protection region 2 that contacts the bottom surface of trench 10 is inclined parallel to a line connecting position P1 of the upper end of trench 10 and position P2 of the end of gate protection region 2 that contacts the bottom surface of trench 10.

[0066] 24, for example, trench 10 is formed so as to expose drift layer 1 at its sidewall and bottom surfaces, away from base contact region 2i. Then, ions are implanted obliquely into the sidewall and bottom surfaces of trench 10 so that the region where the end of gate protection region 2 is to be formed does not overlap with base contact region 2i. This makes it possible to form gate protection region 2 in a self-aligned manner, with the side surfaces of the end contacting the bottom surface of trench 10 being inclined.

[0067] 25 differs from the insulated gate semiconductor device shown in FIG. 14 in that the bottom surface of the gate protection region 2 is shallower than the bottom surface of the base contact region 2i. A method for manufacturing the insulated gate semiconductor device according to the third embodiment shown in FIG. 25 includes, for example, forming a trench 10 spaced apart from the base contact region 2i so that the drift layer 1 is exposed at its sidewall and bottom surfaces. Then, by obliquely implanting ions into the sidewall and bottom surfaces of the trench 10, the gate protection region 2 can be formed in a self-aligned manner at a position shallower than the bottom surface of the base contact region 2i.

[0068] 26 shows a modification of the insulated gate semiconductor device according to the third embodiment. The insulated gate semiconductor device shown in FIG. 26 has n-type MOSFETs on the undersides of the base contact regions 2h and 2i and the base region 3a. + This semiconductor device differs from the insulated gate semiconductor device shown in FIG. 14 in that it includes n-type current spreading layers (CSLs) 12a and 12b. By providing the current spreading layers 12a and 12b, it is possible to reduce the on-resistance. The current spreading layers 12a and 12b can be formed by ion implantation of n-type impurities such as nitrogen (N) into the drift layer 1. Alternatively, the current spreading layers may be provided only on the lower surfaces of the base contact regions 2h and 2i.

[0069] (Fourth embodiment) As shown in FIG. 27, the insulated gate semiconductor device according to the fourth embodiment has an arrangement structure of a plurality of striped unit cells C1 to C4, each having four striped trenches 10a to 10d. The insulated gate semiconductor device according to the fourth embodiment includes a drift layer 1 of a first conductivity type (n-type), and base regions 3a and 3b of a second conductivity type (p-type) arranged on the drift layer 1. The upper portions of the base regions 3a and 3b are doped with the first conductivity type (n-type) at a higher impurity density than the drift layer 1. + Main electrode regions (source regions) 41 and 43 of the same type are provided.

[0070] Trenches 10a to 10d are provided from the upper surfaces of the source regions 41 and 43 to reach the drift layer 1. The trenches 10a and 10b sandwich the source region 41 and the base region 3a and contact both ends of the source region 41 and the base region 3a, respectively. The trenches 10c and 10d sandwich the source region 43 and the base region 3b and contact both ends of the source region 43 and the base region 3b, respectively.

[0071] Inside the trenches 10a to 10d, insulated gate electrode structures (5a, 6a), (5b, 6b), (5c, 6c), and (5d, 6d) each consisting of gate insulating films 5a to 5d and gate electrodes 6a to 6d are provided. A first main electrode (source electrode) 8 is disposed on the gate electrodes 6a to 6d via an interlayer insulating film 7. An n-type electrode 8 is disposed on the lower surface of the drift layer 1 so as to contact the drift layer 1. + A second main electrode region (drain region) 9 is disposed on the bottom surface of the drain region 9. A second main electrode (drain electrode) 11 is disposed on the bottom surface of the drain region 9.

[0072] On the drift layer 1, a second conductivity type (p + Gate protection regions 21, 22a, and 23 (type) are selectively provided. Gate protection region 21 contacts the bottom and sidewall surfaces of trench 10a. Gate protection region 22a contacts the bottom and sidewall surfaces of trench 10b and also contacts the bottom and sidewall surfaces of trench 10c. Gate protection region 23 contacts the bottom and sidewall surfaces of trench 10d.

[0073] In the insulated gate semiconductor device according to the fourth embodiment, the a-plane is used as both sidewall surfaces of trenches 10a-10d. For example, the a-plane, which has relatively high electron mobility, is used as the sidewall surface of trench 10a facing the gate protection region 21, the sidewall surface of trench 10b facing the source region 41 and base region 3a, the sidewall surface of trench 10c facing the gate protection region 22a, and the sidewall surface of trench 10d facing the source region 42 and base region 3b, and these are designated as first sidewall surfaces. On the other hand, the a-plane, which has relatively low electron mobility, is used as the sidewall surface of trench 10a facing the source region 41 and base region 3a, the sidewall surface of trench 10b facing the gate protection region 22a, the sidewall surface of trench 10c facing the source region 42 and base region 3b, and the sidewall surface of trench 10d facing the gate protection region 23, and these are designated as second sidewall surfaces. Alternatively, the first and second sidewall surfaces of the trenches 10a to 10d may be reversed from the above.

[0074] In the insulated gate semiconductor device according to the fourth embodiment, the (1-100) m-plane may be used as the sidewalls of trenches 10a to 10d. When the m-plane is used, the inclination angles of both sidewalls of trenches 10a to 10d relative to the reference plane (m-plane) are the same, and therefore the electron mobility on both sidewalls of trenches 10a to 10d is the same.

[0075] The insulated gate semiconductor device according to the fourth embodiment alternates between a structure in which a common base region 3a and source regions 41, 43 are sandwiched between trenches 10a, 10b of adjacent unit cells C1, C2 and between trenches 10c, 10d of adjacent unit cells C3, C4, and a structure in which a common gate protection region 22a is sandwiched between trenches 10b, 10c of adjacent unit cells C2, C3. The other configuration of the insulated gate semiconductor device according to the fourth embodiment is the same as that of the insulated gate semiconductor device according to the first embodiment, so redundant description will be omitted.

[0076] During operation of the insulated gate semiconductor device in accordance with the fourth embodiment, a positive voltage is applied to drain electrode 11, and a positive voltage equal to or greater than the threshold is applied to gate electrodes 6a to 6d. This forms inversion layers (channels) on both side surfaces of base regions 3a and 3b, resulting in an ON state. In the ON state, current flows from drain electrode 11 to source electrode 8 via drain region 9, drift layer 1, inversion layers on both side surfaces of base regions 3a and 3b, and source regions 41 and 43. On the other hand, when the voltage applied to gate electrodes 6a to 6d is less than the threshold, no inversion layers are formed on both side surfaces of base regions 3a and 3b, resulting in an OFF state, and no current flows from drain electrode 11 to source electrode 8.

[0077] FIG. 28 shows a planar layout of FIG. 27 as viewed from the AA direction, which horizontally cuts the source regions 41 and 43. The cross-sectional view of FIG. 28 as viewed from the BB direction corresponds to FIG. 27. As shown in FIG. 28, the planar patterns of the source regions 41 and 43 and the gate electrodes 6a to 6d are striped and extend parallel to each other. Furthermore, the gate protection regions 22a and 22b are intermittently provided at predetermined intervals along the longitudinal direction of the source regions 41 and 43 and the gate electrodes 6a to 6d. The source regions 42a and 42b are provided between the gate protection regions 22a and 22b. The spacing W3 between the gate protection regions 22a and 22b is preferably equal to or smaller than the spacing (JFET width) W2 between the junction field effect transistor (JFET) regions sandwiched between the gate protection regions 21 and 22a shown in FIG. 27. The cross-sectional view of FIG. 28 as viewed from the CC direction corresponds to FIG. 29. As shown in FIG. 29, a base region 3c is provided below the source region 42a.

[0078] Here, an insulated gate semiconductor device according to a comparative example will be described. In the insulated gate semiconductor device according to the comparative example, as shown in FIG. 30, gate protection region 22 has a planar pattern extending along the longitudinal direction of trenches 10a-10d. In contrast, in the insulated gate semiconductor device according to the fourth embodiment, gate protection regions 22a and 22b are provided intermittently, so that the space between gate protection regions 22a and 22b can be used as source regions 42a and 42b. This allows the channel to be increased and the on-resistance to be reduced.

[0079] 29, a Schottky barrier diode may be formed by the source region 42a and the source electrode 8 in the area of ​​the planar pattern of the source region 42a, without providing the base region 3c below the source region 42a. That is, a Schottky barrier diode may be provided in each area between the gate protection regions 22a and 22b.

[0080] 31, gate protection regions 21a, 21b sandwiched between trenches 10a, 10b (see FIG. 27) may be provided intermittently along the longitudinal direction of trenches 10a, 10b. Gate protection regions 21a, 21b are provided alternately with source regions 41a, 41b. Furthermore, gate protection regions 23a, 23b sandwiched between trenches 10c, 10d (see FIG. 27) may be provided intermittently along the longitudinal direction of trenches 10c, 10d. Gate protection regions 23a, 23b are provided alternately with source regions 43a, 43b.

[0081] 31, the arrangement of the gate protection regions 21a, 21b, the arrangement of the gate protection regions 22a, 22b, and the arrangement of the gate protection regions 23a, 23b may be provided at the same positions in a direction perpendicular to the longitudinal direction of the trenches 10a to 10d (see FIG. 27) (the parallel direction of the trenches 10a to 10d). In the parallel direction of the trenches 10a to 10d, the gate protection regions 21a, 22a, 23a and the gate protection regions 21a, 22a, 23a are arranged at the same positions. In addition, in the parallel direction of the trenches 10a to 10d, the source regions 41a, 42a, 43a and the source regions 41b, 42b, 43b are arranged at the same positions.

[0082] 32, the arrangement of the gate protection regions 21a, 21b, the arrangement of the gate protection regions 22a, 22b, and the arrangement of the gate protection regions 23a, 23b may be shifted in the parallel direction of the trenches 10a to 10d. The gate protection regions 21a, 22a, 23a and the gate protection regions 21b, 22b, 23b are shifted in the parallel direction of the trenches 10a to 10d. Furthermore, the source regions 41a, 42a, 43a and the source regions 41b, 42b, 43b are shifted in the parallel direction of the trenches 10a to 10d.

[0083] (Other embodiments) As described above, the present invention has been described with reference to the first to fourth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0084] In the first to fourth embodiments of the present invention, a MISFET having an insulated gate electrode structure in a trench is exemplified, but the present invention is not limited to this and can be applied to insulated gate semiconductor devices having various insulated gate electrode structures, such as an IGBT having an insulated gate electrode structure in a trench. As a trench gate IGBT, the n-type MISFET shown in FIGS. 2 and 3 can be used. + The n-type source regions 4a to 4j are used as emitter regions. +Instead of the drain region 9 of the type, a p + A structure in which a collector region of the same type is provided may be used.

[0085] Furthermore, in the embodiments of the present invention, an insulated gate semiconductor device using SiC has been exemplified, but the present invention can also be applied to an insulated gate semiconductor device using a semiconductor (wide bandgap semiconductor) having a hexagonal crystal system and a wider band gap than Si, such as gallium nitride (GaN), aluminum nitride (GaN), or indium nitride (InN). [Explanation of symbols]

[0086] 1...Drift layer 2,2a,2b,2c,2d,2e,21,21a,21b,22a,22b,23,23a,23b...Gate protection area 2g, 2h, 2i...Base contact area 2x,2y…Movement suppression area 3,3a,3b,3c,3d,3e...Base area 4,4a,4b,4c,4d,4e,4f,4g,4h,4i,4j,41,41a,41b,42a,42b,43,43a,43b...Source area 5, 5a, 5b, 5c, 5d, 5e, 5f...Gate insulating film 6, 6a, 6b, 6c, 6d, 6e, 6f...gate electrodes 7...Interlayer insulating film 8...Source electrode 8a...Convex part 9...Drain region 10a, 10b, 10c, 10d, 10e, 10f...Trench 11...Drain electrode 12a, 12b...current diffusion layer 31...Photoresist film

Claims

1. an insulated gate electrode structure disposed inside a trench having sidewalls defined by a first sidewall surface that forms a first inclination angle with respect to a reference plane of the chip structure and a second sidewall surface that faces the first sidewall surface and forms a second inclination angle with respect to the reference plane that is different from the first inclination angle; a main electrode region of a first conductivity type and having a high impurity concentration in contact with a first sidewall surface of the trench; a second conductivity type base region in contact with a lower surface of the main electrode region and the first sidewall surface; a drift layer of a first conductivity type having a lower impurity density than the main electrode region, the drift layer being in contact with a lower surface of the base region and the first sidewall surface; a gate protection region of a second conductivity type, the gate protection region being in contact with the second sidewall surface and the bottom surface of the trench and having a higher impurity concentration than the base region; a base contact region of a second conductivity type, which is spaced apart from the trench and in contact with the gate protection region, and has a higher impurity density than the base region; 1. An insulated gate semiconductor device comprising:

2. 3. The insulated gate semiconductor device according to claim 2, wherein the impurity concentration of the gate protection region is higher than the impurity concentration of the base contact region.

3. 3. The insulated gate semiconductor device according to claim 1, wherein a side surface of the end of the gate protection region that contacts the bottom surface of the trench is inclined parallel to a straight line connecting an upper end of the first sidewall surface of the trench and the end of the gate protection region that contacts the bottom surface of the trench.

4. 4. The insulated gate semiconductor device according to claim 1, wherein the bottom surface of the gate protection region is shallower than the bottom surface of the base contact region.

5. 5. The insulated gate semiconductor device according to claim 1, wherein the trench is a stripe-shaped trench.

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