Modular stacked silicon package assembly

Abstract

To provide a chip package assembly and a method of manufacturing the same in which a design / construction preparation period is shortened at a reasonable cost and modularity is improved.SOLUTION: The chip package assembly 100 includes an input / output integrated circuit die (I / OIC die) 104, a functional IC die 106, a chiplet 112, and a substrate 134. The functional IC die is stacked on a surface of the I / OIC die, and the chiplet is disposed between the substrate and the I / OIC die. The substrate has substrate circuitry communicatively coupled to the functional circuitry of the functional IC die via the first chiplet and the I / OIC die in the chip package assembly. This allows easy integration with a wide variety of chiplet options, while also allowing easy changes to the configuration of the stack, allowing chip package assembly designs to be assembled from existing components and developed with little cost and in a short period of time.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Technical Field FIELD OF THE INVENTION Embodiments of the present invention relate generally to chip package assemblies, and more particularly to chip package assemblies comprising chiplets interfaced with one or more integrated circuit dies through redistribution layers. [Background technology]

[0002] background In particular, electronic devices such as tablets, computers, copiers, digital cameras, smartphones, control systems, automated teller machines, data centers, artificial intelligence systems, and machine learning systems often employ electronic components that utilize chip-package assemblies to achieve greater functionality and higher component density. Traditional chip packaging methods often utilize a package substrate along with a through-silicon-via (TSV) interposer substrate to achieve multiple The IC die may include memory devices, logic devices, or other IC devices.

[0003] The complexity of chip package design makes it particularly difficult to meet market needs in a timely manner. Packages employing large monolithic IC dies often require long design and build times, resulting in significant costs. These attributes are particularly undesirable in markets such as data centers, artificial intelligence, and machine learning applications, which require faster design lead times and reduced costs. Furthermore, as application requirements change ever more rapidly, the ability to quickly and cost-effectively meet evolving market demands has become extremely challenging.

[0004] Therefore, there is a need for chip package assemblies that offer improved modularity while allowing for shorter lead times for design and construction at a reasonable cost compared to traditional monolithic solutions. Summary of the Invention [Problem to be solved by the invention]

[0005] overview A chip package assembly and method for making the same is provided that provides a modular chip stack that can be matched with a variety of separate chiplets. The use of a modular stack with a simple I / O interface allows for easy integration with a wide variety of chiplet options while allowing for easy changes to the stack configuration, allowing a large number of different chip package assembly designs to be assembled from previously developed or more efficiently developed components, resulting in a much faster pace of development at a fraction of the cost. [Means for solving the problem]

[0006] In one example, the chip package assembly includes an input / output integrated circuit (I / O IC) die, a functional IC die, a first chiplet, and a substrate. The I / O IC die has a first surface and a second surface. The functional IC die is stacked on the first surface of the I / O IC die. The substrate has a first surface and a second surface. and a second surface. The first chiplet is disposed between the substrate and the I / O IC die. The substrate has substrate circuitry communicatively coupled to functional circuitry of the functional IC die through the first chiplet and the I / O IC die within the chip package assembly.

[0007] In another example, a chip package assembly is provided that includes an input / output integrated circuit (I / O IC) die, a first redistribution layer (RDL), a first functional IC die, a first chiplet, and a substrate. The IC I / O die has a first surface and a second surface. The functional IC die is stacked on the first surface of the I / O IC die. The first RDL couples the second surface of the I / O IC die to the first chiplet. The substrate has a first surface and a second surface. The first chiplet is disposed between the substrate and the I / O IC die. The substrate has substrate circuitry communicatively coupled to functional circuitry of the functional IC die via the first RDL, the first chiplet, and the I / O IC die within the chip package assembly. The first RDL has circuitry that directly connects the I / O circuitry of the I / O IC die to the substrate circuitry while bypassing the first chiplet. A dielectric fill layer is laterally disposed around the I / O IC die and the functional IC die.

[0008] In yet another embodiment, a method for fabricating a chip package assembly is provided, the method including: (a) forming a die stack including a plurality of integrated circuit (IC) dies and an I / O IC die having exposed contacts, (b) forming a first redistribution layer (RDL) on the exposed contacts of the I / O IC die, (c) bonding chiplets to the first RDL, and (d) bonding the chiplets to a substrate.

[0009] BRIEF DESCRIPTION OF THE DRAWINGS So that the above-mentioned features of the present invention may be understood in detail, a more particular description of the invention briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention, since the invention may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view illustrating a chip package assembly in which chiplets are coupled to a chip stack by a redistribution layer of the chip package assembly. [Figure 2] 2 is a partial cross-sectional view of the chip package assembly of FIG. 1, showing a portion of a redistribution layer of the chip package assembly. [Figure 3] FIG. 1 is a flow diagram illustrating a method for fabricating a chip package assembly in which chiplets are bonded to a chip stack by a redistribution layer of the chip package assembly. [Figure 4A] 5A-5C are schematic cross-sectional views illustrating the chip package assembly at various stages of the method of FIG. 4. [Figure 4B] 5A-5C are schematic cross-sectional views illustrating the chip package assembly at various stages of the method of FIG. 4. [Figure 4C] 5A-5C are schematic cross-sectional views illustrating the chip package assembly at various stages of the method of FIG. 4. [Figure 4D] 5A-5C are schematic cross-sectional views illustrating the chip package assembly at various stages of the method of FIG. 4. [Figure 4E] 5A-5C are schematic cross-sectional views illustrating the chip package assembly at various stages of the method of FIG. 4. [Figure 4F] 5A-5C are schematic cross-sectional views illustrating the chip package assembly at various stages of the method of FIG. 4. [Figure 5] FIG. 10 is a schematic cross-sectional view illustrating another chip package assembly in which chiplets are coupled to a chip stack by a redistribution layer of the chip package assembly. [Figure 6] FIG. 10 is a schematic cross-sectional view illustrating another chip package assembly in which chiplets are coupled to a chip stack by a redistribution layer of the chip package assembly. [Figure 7] 7 is a schematic top view of the chip package assembly of FIG. 6 showing an exemplary geometric arrangement of auxiliary elements arranged around the chip stack. [Figure 8]FIG. 10 is a schematic cross-sectional view illustrating yet another chip package assembly in which chiplets are coupled to a chip stack by a redistribution layer of the chip package assembly. DETAILED DESCRIPTION OF THE INVENTION

[0011] For ease of understanding, wherever possible, the same reference numerals have been used to indicate identical elements that are common to multiple figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.

[0012] Detailed Description A chip package assembly and method for fabricating the same are provided, including a modular chip stack that can be matched with one or more chiplets. Using one or more chiplets with a scalable modular chip stack allows for a large number of different chip package assembly designs to be efficiently introduced to the market, resulting in a much faster pace of development at a fraction of the cost. The modularity of the chip package assembly is enabled by utilizing a simple input / output integrated circuit (I / O IC) die at the bottom of the chip stack. A redistribution layer (RDL) is used to couple the I / O IC die to one or more chiplets in the chip stack. This allows the I / O IC die to use nearly any combination of functional (i.e., memory or logic) I / C die within the chip stack, thereby maintaining the same connection footprint as the RDL. The versatility of RDL fabrication allows for a variety of chiplets to be used with a single I / O IC die design. As a result, the I / O IC die / RDL interface allows many different combinations of functional IC dies to be matched with many different chiplets without having to design and tape out an entire chip package assembly for every new application.

[0013] In the examples described below, a chip package assembly includes a chip stack interconnected with chiplets using a redistribution layer (RDL). The chip stack may be provided as a single subcomponent of a chip package assembly that can be beneficially utilized in other chip package assemblies. Furthermore, the chip stack and RDL combined as a chip stack / RDL assembly may also be provided as a single subcomponent of a chip package assembly that can be beneficially utilized in other chip package assemblies using various chiplets. In some examples, at least one chiplet is embedded in a chiplet layer with conductive signal feedthroughs for efficient ground and power routing. The chiplet layer is configured to connect directly to the chip stack / RDL assembly to provide a modular assembly technique that enables the use of various chip stacks and / or chiplets without significant development and design costs between configurations.

[0014] Beneficially, the configurations and techniques described above and further detailed below provide a modular and scalable chip package assembly, resulting in significant improvements in cost and development time for creating the chip package assembly compared to conventional large-scale monolithic die solutions.

[0015] 1 , a schematic cross-sectional view of a chip package assembly 100 is shown. The chip package assembly 100 includes a chip stack 102 coupled to chiplets 112 by a redistribution layer (RDL) 116. The chip package assembly 100 also includes a package substrate 134. The chiplets 112 are disposed on a chiplet layer 110 that also includes a plurality of conductive signal feedthroughs 114. The circuitry 120 of the RDL 116 is configured to connect package substrate circuitry 142 of the package substrate 134 and the circuitry of the chiplets 112 with the circuitry of the chip stack 102 within the chip package assembly 100.

[0016] The chip stack 102 is embedded in a mold compound 144. The chip stack 102 and the mold compound 144, together with the RDL 116, form a chip stack / RDL assembly 146. The chip stack / RDL assembly 146 is mechanically and electrically connected directly to the chiplet layer 110 and, through the chiplet layer 110, to the package substrate 134.

[0017] Chip stack 102 includes at least one input / output integrated circuit (I / O IC) die 104 and at least one functional IC die 106. Although three functional IC dies 106 are shown stacked vertically atop I / O IC die 104 in FIG. 1 , the total number of functional IC dies 106 can range from one to as many as can fit within chip package assembly 100. Additionally, although a single IC chip stack 102 is shown in FIG. 1 , additional IC chip stacks may be disposed laterally on a common package substrate 134 and connected to the common package substrate 134 by one or more chiplet layers 110 via common or separate RDLs 116.

[0018] The I / O IC die 104 generally includes routing circuitry for coupling the circuitry 120 of the RDL 116 to the circuitry of the functional IC die 106 in the IC chip stack 102. The I / O IC die 104 is a simple silicon device that allows data movement between multiple complex silicon devices (i.e., the functional IC die 106). The I / O IC die 104 includes control inputs that select / enable data to be input from one or more complex silicon devices (e.g., the functional IC die 106) and then flexibly distributed to one or more complex silicon devices. The I / O IC die 104 is typically a single chip, since the I / O IC die circuitry performs little or no processing of data transferred between functional IC die 106 or between the functional IC die 106 and the circuitry 120 of the RDL 116. The circuitry of IC die 104 is separate from the functional IC die 106 to which it connects, so the circuitry of I / O IC die 104 is not orders of magnitude more complex than that of functional IC die 106.

[0019] In one example, the circuitry of the I / O IC die 104 includes only routing circuitry. In another example, the circuitry of the I / O IC die 104 includes mux and demux circuitry. The circuitry of the I / O IC die 104 may additionally include clocking circuitry. Simple routing circuitry may be present in the circuitry of the I / O IC die 104 to the extent necessary to route signals through the I / O IC die 104 between functional IC die 106 and between circuitry of the functional IC die 106 and circuitry 120 of the RDL 116.

[0020] As described above, one or more functional IC dies 106 are stacked on the I / O IC die 104. One or more of the functional IC dies 106 utilized in the chip stack 102 may be a processor, such as a field programmable gate array (FPGA). Functional IC dies 106 may include, but are not limited to, programmable logic devices, memory devices such as high bandwidth memory (HBM), optical devices, processors, or other IC logic structures. One or more of the functional IC dies 106 may optionally include photodetectors, lasers, light sources, etc. 1, the functional IC die 106 furthest from the I / O IC die 104 is a logic die having math processor circuitry (also known as a math engine) for accelerating machine learning mathematical operations in hardware such as autonomous vehicles, artificial intelligence, and data center neural network applications. In one example, the functional IC die 106 in the stack 102 may include block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic, and other memory devices. configurable logic elements (CLEs), etc. It is contemplated that the functional IC dies 106 comprising chip stack 102 can be of the same type or different types, including types other than FPGA dies.

[0021] The mold compound 144 is disposed on the outside of the functional IC dies 104, 106 and provides additional rigidity to the package assembly 100 while protecting the interconnects 108 between the functional IC dies 104, 106. The mold compound 144 may be a polymeric material, such as an epoxy-based material, or other suitable material.

[0022] Each functional IC die 106 includes a bottom surface and a top surface. The bottom surface of a functional IC die 106 is bonded to the top surface of the next lower functional IC die 106 in the IC chip stack 102. The bottom surface of the lowest functional IC die 106 in the IC chip stack 102 is bonded to the top surface of an I / O IC die 104. The functional IC die 106 and the I / O IC die 104 are mechanically and electrically coupled to each other via interconnects 108, which may be solderless hybrid joints and / or solder connections.

[0023] The bottom surface of the I / O IC die 104 is bonded to the top surface of the RDL 116. The circuitry of the I / O IC die 104 is mechanically and electrically bonded to the circuitry 120 of the RDL 116 through interconnects 108, such as solderless hybrid joints, or via solder connections. The bottom surface of the RDL 116 is bonded to the top surface of the chiplet layer 110 via interconnects 130, which may be solderless hybrid joints and / or solder connections.

[0024] As described above, chiplet layer 110 includes conductive signal feedthroughs 114 and chiplets 112. Conductive signal feedthroughs 114 and chiplets 112 are embedded in mold compound 132. Conductive signal feedthroughs 114 are generally conductive paths that run between the top and bottom surfaces of chiplet layer 110. Mold compound 132 is a dielectric fill layer that provides electrical insulation between feedthroughs 114 and rigidity to chiplet layer 110.

[0025] Chiplets 112 are integrated circuit blocks configured to enable the functionality of chip stack 102 or other chiplets disposed within chip package assembly 100. Chiplets 112 may contain, among other things, physical layer (PHY) circuitry, high-bandwidth memory circuitry, a processor, serial deserializers (SerDes), and other memory circuits. ), a high-speed serial bus, an analog-to-digital converter, a digital-to-analog converter, a video codec circuit, an electrical-to-optical converter, a memory subsystem, a processor subsystem, flash memory, and circuitry comprising one or more of a power conditioning / distribution system, or an optical-to-electrical converter. Chiplet 112 may also be configured as or part of a high-bandwidth memory (HBM) device. The top surface of chiplet 112 is coupled to the bottom surface of RDL 116 via interconnects 130, and the bottom surface of chiplet 112 is coupled to the top surface 136 of package substrate 134 via dummy balls 124. Alternatively, in embodiments in which chiplet 112 includes TSVs, balls 124 may be active to connect circuitry of chiplet 112 and / or RDL 116 to circuitry 142 of package substrate 134. Dummy balls 124 are coupled from the top surface 136 of package substrate 134 The dummy balls 124 serve to provide adequate and uniform spacing from the surface of the chiplet 112, thereby reducing stress on the solder interconnects 148 that couple the feedthrough 114 to the package substrate circuitry 142 of the package substrate 134 when exposed to a wide temperature range. The spacing provided by the dummy balls 124 allows underfill 150 to be placed between the package substrate 134 and the chiplet layer 110, thereby protecting the solder interconnects 148 and the dummy balls 124 while increasing the rigidity of the chip package assembly 100.

[0026] Chiplet 112 may optionally include through-silicon vias to allow power, ground, and / or data signals to pass straight through chiplet 112. In the example shown in FIG. 1 , chiplet 112 does not include through-silicon vias because all inputs and outputs of chiplet 112 are routed through active surface 126 via interconnects 130, while all power, ground, and / or data signals are routed through signal feedthroughs 114 directly between circuitry 120 of RDL 116 and package substrate circuitry 142 of package substrate 134.

[0027] The bottom surface 138 of the package substrate 134 is coupled to a printed circuit board (PCB, not shown) by solder balls 140 or other suitable electrical connections. The solder balls 140 provide electrical signals such as data, ground, and power through package substrate circuitry 142 of the package substrate 134 to the chiplet layer 110, and ultimately through circuitry 120 of the RDL 116 and circuitry of the I / O IC die 104 to circuitry of the functional IC die 106.

[0028] As mentioned above, the circuitry of the I / O IC die 104 is connected to the circuitry 120 of the RDL 116. Further details of the connection between the I / O IC die 104 and the RDL 116 are shown in Figure 2. The RDL 116 also contacts the bottom surface 152 of the mold compound 144.

[0029] Referring to the partial cross-sectional view of FIG. 2 , the I / O IC die 104 includes contact pads 202, where circuitry 204 of the I / O IC die 104 terminates. The contact pads 202 are exposed on the bottom surface of the I / O IC die 104. Interconnects 154 are formed on the pads 202. The interconnects 154 are also electrically and mechanically connected to circuitry 120 of the RDL 116. The top surface of the RDL 116 is fabricated directly on the bottom surface of the I / O IC die 104 and the bottom surface 152 of the mold compound 144. Alternatively, the RDL 116 may be formed on the surface of the chiplet 112. The RDL 116 includes at least three layers of metal and dielectric that are patterned to create circuitry 120 of the RDL 116. In one example, the traces comprising circuitry 120 formed by patterned metal lines 210 and vias 212 are directly connected within dielectric layer 214 to interconnects 154 exposed below the bottom of I / O IC die 104 without solder connections. In such an embodiment, the spacing between contact pads 202 can have a much finer pitch than connections utilizing solder interconnects. The traces comprising circuitry 120 terminate and are exposed at the bottom surface of RDL 116, facilitating electrical and mechanical connection with the circuitry and conductive signal feedthroughs 114 of the underlying chiplet 112. For example, circuitry 120 of RDL 116 is connected via interconnects 130 to contact pads 206 exposed on the active surface 126 of chiplet 112. Circuitry 120 of RDL 116 is also connected to conductive signal feedthroughs 114 via interconnects 118.

[0030] 3 is a flow diagram illustrating a method 300 for fabricating a chip package assembly in which a chip stack is bonded to chiplets via RDLs, such as the chip package assembly 100 described above with particular reference to FIGS. 1 and 2. FIGS. 4A-4F illustrate the method 300 of FIG. 4A-4E are schematic cross-sectional views illustrating chip package assembly 100 at various stages of method 300. Note that the orientation of dies 104, 106 and other components shown in Figures 4A-4E is 180 degrees different from the orientation shown in Figure 1. In other words, dies 104, 106 and other components shown in Figures 4A-4E are upside down compared to those shown in Figure 1.

[0031] 4A , the method 300 begins at operation 302 by attaching a chip stack 102, including at least one I / O IC die 104 and at least one functional die 106, to a carrier 400. The carrier 400 is utilized only during the initial fabrication operations and is therefore removably attached to the chip stack 102 before mounting the chip stack 102 and the later-fabricated RDL 116 to a substrate, such as the package substrate 134, to complete fabrication of the chip package assembly 100. In one example, the top surface 402 of the chip stack 102 is attached to the carrier 400 using a releasable pressure-sensitive adhesive.

[0032] Interconnects 154 are shown extending from a surface of I / O IC die 104 (i.e., a surface of the top functional IC die 106 facing away from adjacent functional IC die 106). Interconnects 154 may be made by patterning and plating or by another technique. Interconnects 154 may alternatively be formed at a later stage in method 300.

[0033] In operation 304, mold compound 144 is disposed around dies 104, 106 and in contact with carrier 400, as shown in FIG. 4B. Mold compound 144 extends beyond the bottom surface of I / O IC die 104 to initial surface 440. Interconnects 154 are generally below initial surface 440 and are encapsulated by mold compound 144. Mold compound 144 may be spun, dispensed, overmolded, or deposited by another suitable method. In operation 304, mold compound 144 fills the gap spaces defined between adjacent dies 104, 106.

[0034] Optionally, in operation 304, at least one or more auxiliary elements may be embedded in the mold compound 144 adjacent to the chip stack 102. The auxiliary elements embedded in the mold compound may be a dummy die, a capacitor, an inductor, or a chiplet. In some examples, multiple auxiliary elements are embedded in the mold compound 144 adjacent to the chip stack 102. When multiple auxiliary elements are embedded in the mold compound 144, each auxiliary element may be the same type of auxiliary element, or one or more of the auxiliary elements may be different types of auxiliary elements.

[0035] Alternatively, if an auxiliary element is utilized, the auxiliary element may be bonded to the RDL 116 at a later stage after depositing the mold compound 114. That is, the auxiliary element does not have to be embedded within the mold compound 114, but may be bonded to the RDL 116 at a later time.

[0036] In operation 306, initial surface 440 of mold compound 144 and distal ends of interconnects 154 are ground, mechanically removed, or otherwise removed to form bottom surface 152 of mold compound 144, as shown in FIG. 4C. Operation 306 forms distal ends of interconnects 154 flush with bottom surface 152 of mold compound 144.

[0037] In operation 308, the RDL 116 is fabricated directly on the bottom surface 152 of the molding compound 144 without solder connections, as shown in FIG. The redistribution layer 116 is fabricated by depositing at least three or more dielectric layers 214, on which metal paths formed from the metal lines 210 and vias 212 form the circuits 120 of the redistribution layer 116.

[0038] 4E, the carrier 400 is removed and the RDL 116 is electrically and mechanically connected to the chiplet layer 110 using the interconnects 118, 130. The chiplet layer 110 may be oriented such that the active surface 126 of the chiplet 112 is positioned opposite and electrically connected to the RDL 116. Alternatively, the chiplet layer 110 may be oriented such that the silicon surface 128 of the chiplet 112 is positioned opposite the RDL 116, thereby coupling the circuitry 120 of the RDL 116 to through-silicon vias exposed on the surface of the chiplet 112.

[0039] In operation 312, the package substrate 134 is electrically and mechanically connected to the chiplet layer 110 using interconnects that use solder interconnects 148, as shown in Figure 4E. In the example of Figure 4E, the active surface 126 of the chiplet 112 faces the RDL 116 such that the circuitry of the chiplet 112 is mechanically and electrically coupled to the circuitry 120 of the RDL 116 by interconnects 130 or other suitable connections, and there is an electrical connection between the conductive signal feedthroughs 114 of the chiplet layer 110 and the package substrate circuitry 142 of the package substrate 134 by solder interconnects 148 or other suitable connections. Alternatively, as shown in FIG. 4F , the active surface 126 of the chiplet 112 faces away from the RDL 116 so that interconnects 130 are used to couple the circuitry 120 of the RDL 116 to through-silicon vias 450 formed through the chiplet 112, and solder interconnects 148 are used to connect the conductive signal feedthroughs 114 of the chiplet layer 110 to the circuitry 120 of the RDL 116.

[0040] In operation 312, package substrate 134 is coupled to chiplet layer 110 of chiplets 112 having active surfaces 126 facing RDL 116 by interconnects 148, as shown in FIG. 1. Operation 312 may also include coupling package substrate 134 to chiplet layer 110 by dummy (or functional) balls 124. In examples where chiplets 112 include through-silicon vias, the vias may be electrically and mechanically coupled to package substrate circuitry 142 of package substrate 134 by solder interconnects 148 or other suitable connections.

[0041] Alternatively, the RDL 116 may be fabricated on the chiplet layer 110 and then attached to the chip stack 102 using solder or other connections.

[0042] 5 shows a schematic cross-sectional view of a chip package assembly 500 in which a chip stack 102 is coupled to chiplets 460 by a redistribution layer (RDL) 116. The chip stack 102 and redistribution layer RDL 116 are configured as described above to form a chip stack / RDL assembly 146. The chip stack / RDL assembly 146 is mounted to a chiplet layer 510 that includes chiplets 460.

[0043] Chiplet layer 510 is configured essentially the same as chiplet layer 110, except that chiplets 460 disposed in chiplet layer 510 have active surfaces 126 that face the package substrate 134 on which chiplet layer 510 is mounted. Silicon surfaces 128 of chiplets 460 face and are bonded to RDL 116.

[0044] More specifically, chiplet 460 is configured essentially the same as chiplet 112, except that chiplet 460 includes a plurality of through-silicon vias 450. The through-silicon vias 450 are coupled to the circuitry (142; not shown in FIG. 5 ) of the package substrate 134 on the silicon side 128 of the chiplet 460 by interconnects 502, which may be solderless hybrid joints and / or solder connections. The through-silicon vias 450 are coupled to the circuitry 120 of the RDL 116 on the active side 126 of the chiplet 460 by interconnects 130, which may be solderless hybrid joints and / or solder connections. In the example shown in FIG. 5 , at least some of the plurality of through-silicon vias 450 are configured to transmit power and / or ground signals between the RDL 116 and the package substrate 134.

[0045] Because the interconnects 502 are spaced much closer together than the interconnects 148, the package substrate circuit 142 at a portion 550 of the package substrate 134 where the interconnects 502 connect to the chiplets 460 has a much finer pitch than the circuit at a portion 552 of the package substrate 134 where the interconnects 148 connect to the feedthroughs 114.

[0046] For example, when the active surface 126 of the chiplet 460 is mounted to the package substrate 134, the pitch of the contact pads of the package substrate 134 and the pitch of the contact pads 206 of the chiplet 460 in portion 550 can be 130 μm or less, such as 54 μm or less, which facilitates high-density signal transmission. The pitch of the contact pads in portion 552 of the package substrate 134 and the pitch of the conductive signal feedthroughs 114 of the chiplet layer 510 are greater than 200 μm, which allows for more cost-effective fabrication of the region of the chiplet layer 510 surrounding (i.e., outside) the chiplet 460.

[0047] 6 shows a schematic cross-sectional view of a chip package assembly 600 in which a chip stack 102 is coupled to chiplets 460 by a redistribution layer (RDL) 116. The chip stack 102 and redistribution layer RDL 116 are configured as described above to form a chip stack / RDL assembly 646. The chip stack / RDL assembly 646 is mounted to a chiplet layer 510 that includes chiplets 460. The chiplet layer 510 is fabricated as described above with reference to FIG.

[0048] 1 , except that the chip stack / RDL assembly 646 includes at least one auxiliary element 602 disposed in the mold compound 144 of the chip stack / RDL assembly 646. The auxiliary element 602 may provide additional functionality, improve performance, or inhibit warpage of the chip package assembly 600.

[0049] Alternatively, one or more or all of the auxiliary elements 602 may be coupled to the RDL 116 without being embedded in the mold compound 144. That is, the auxiliary elements 602 are outside of the mold compound 144, which allows the auxiliary elements 602 to be coupled to the RDL 116 at various stages of the assembly method, as desired.

[0050] 6, two auxiliary elements 602 are shown encapsulated within the mold compound 144. It is contemplated that the number of auxiliary elements 602 that may be utilized in the chip package assembly 600 may range from one to as many as can fit within the mold compound 144. The tops of the auxiliary elements 602 may be ground or fabricated to be flush with the top surface of the mold compound 144 and the exposed top surface of the top functional IC die 106. Alternatively, the tops of one or more of the auxiliary elements 602 may be flush with the top of the chip stack 102 and / or one or more of the other auxiliary elements 602. The auxiliary element 602 does not have to be flush. The auxiliary element 602 is coupled to the RDL 116 via interconnects 604. The interconnects 604 may be solderless hybrid joints and / or solder connections, solder and / or other types of joining materials, such as epoxy. In some examples, the interconnects 604 simply mechanically secure the auxiliary element 602 to the RDL 116. In other examples, the interconnects 604 serve to electrically and mechanically connect circuitry within the auxiliary element 602 to the circuitry 120 of the RDL 116.

[0051] In one example, at least one of the auxiliary elements 602 is a dummy die dispersed within the mold compound 144 in an arrangement that reduces stresses due to temperature changes and mismatches between the coefficients of thermal expansion of the components stacked within the chip package assembly 600.

[0052] In another example, at least one of the auxiliary elements 602 is a capacitor. Auxiliary elements 602 configured as capacitors, such as deep trench capacitors, may be utilized in conjunction with auxiliary elements 602 having other types of configurations. The capacitor circuit formed in the auxiliary element 602 is electrically and mechanically coupled to the circuit 120 of the RDL 116 by interconnects 604. In one example, the deep trench capacitor circuit of the auxiliary element 602 is coupled to a power rail of the circuit 120 of the RDL 116.

[0053] In another example, at least one of the auxiliary elements 602 is an inductor. Auxiliary elements 602 configured as inductors may be utilized in conjunction with auxiliary elements 602 having other types of configurations. The inductor circuit formed in the auxiliary element 602 is electrically and mechanically coupled to the circuit 120 of the RDL 116 by interconnects 604.

[0054] In another example, at least one of the auxiliary elements 602 is a chiplet. Auxiliary elements 602 configured as chiplets may be utilized with auxiliary elements 602 having other types of configurations. The chiplet circuitry formed in the auxiliary element 602 is electrically and mechanically coupled to the circuitry 120 of the RDL 116 by interconnects 604. The chiplet circuitry of the auxiliary element 602 may be configured as one or more of a physical layer (PHY) circuit, a high-bandwidth memory circuit, a processor, a serial / deserializer (SerDes), a high-speed serial bus, an analog-to-digital converter, a digital-to-analog converter, a video codec circuit, an electrical-to-optical converter, a memory subsystem, a processor subsystem, flash memory, and a power conditioning / distribution system or an optical-to-electrical converter, among others.

[0055] 7 is a schematic top view of the chip package assembly 600 of FIG. 6 illustrating an exemplary geometric arrangement of auxiliary elements 602 disposed about the chip stack 102. The auxiliary elements 602 are generally disposed in a region 706 of the mold compound 144 defined between an outermost edge 702 of the chip stack 102 and an outermost edge 704 of the mold compound 144. The region 706 generally defines the boundary of the chip stack 102.

[0056] In one example, a single support element 602 is disposed in the region 706 between two adjacent edges 702 and 704. In another example, multiple support elements 602 are disposed in the region 706 between two adjacent edges 702 and 704. Two or more support elements 602 may be disposed in the region 706, with at least two support elements 602 separated by a chip stack 102. In another example, one or more support elements 602 are disposed in the region 706 between each pair of adjacent edges 702, 704 that define the boundaries of the chip stack 102. In the example shown in FIG. 7, four support elements 602 overlap the intersection of two adjacent edges 702 of the chip stack 102, further enhancing the chip package assembly 600's resistance to warpage. The support elements 602 also may be disposed in the region 706 between the chip stack 102. The auxiliary element 602 may have a planar area that is much smaller than the planar area of ​​the functional IC die 106 of the stack 102. The auxiliary element 602 may have a length-to-width aspect ratio that is much larger than the length-to-width aspect ratio of the functional IC die 106 of the chip stack 102. The high aspect ratio of the auxiliary element 602 provides a more efficient fit between adjacent edges 702 and 704 as well as rigidity to the chip package assembly 600.

[0057] Although the auxiliary element 602 is illustrated as being incorporated into a chip package assembly 600 having a structure similar to that of the chip package assembly 500, one or more of the auxiliary elements 602 described above may be incorporated into the mold compound 144 of any of the chip package assemblies described herein, among other chip package assemblies that utilize a mold compound to define the boundaries of one or more IC dies.

[0058] FIG. 8 is a schematic cross-sectional view illustrating yet another chip package assembly 800 in which chiplets 460 are coupled to a chip stack 102 by a first redistribution layer (RDL) 116 of the chip package assembly 800. The chip stack 102 and the first RDL 116 are configured as described above with reference to FIGS. 1, 2, and 6 to form a chip stack / RDL assembly 646. The chip stack / RDL assembly 646 is mounted to a chiplet layer / RDL assembly 800. The chiplet layer / RDL assembly 800 includes a second RDL 830 formed directly on the chiplet layer 510. Because the chiplet layer 510 includes the chiplets 460, a portion of the second RDL 830 is formed directly on the chiplet 460. The chiplet layer 510 may be fabricated as described above with reference to FIG. 5.

[0059] Chip stack / RDL assembly 646 is essentially the same as the chip stack / RDL assembly described above with reference to Figure 6. Auxiliary elements 602 may provide additional functionality, improve performance, or inhibit warpage of chip package assembly 600.

[0060] Chip package assembly 800 may be fabricated as described in FIG. 6 with reference to chip package assembly 600, except that chiplet layer 510 is coupled to package substrate 134 via second redistribution layer (RDL) 820. Second RDL 830 is fabricated as described in FIG. 2 with reference to RDL 116 to form circuitry 802 that electronically couples the circuitry of chiplet layer 510 (i.e., the circuitry of chiplets 460 and feedthroughs 114) to package substrate circuitry 142 of package substrate 134.

[0061] The circuitry 802 of the second RDL 830 may optionally include conductive vias 804 that extend linearly through the second RDL 830. Such conductive vias 804 may be configured to route power and / or ground directly through the second RDL 830. Additionally, the conductive vias 804 may be vertically aligned with the conductive vias 450 formed in the chiplet 460 such that power and / or ground may be routed directly through the second RDL 830 and the chiplet 460 to the first RDL 116.

[0062] A portion of the circuit 802 of the second RDL 830 is directly coupled to the conductive feedthrough 114 of the chiplet layer 510. A portion of the circuit 802 of the second RDL 830 is directly coupled to the circuit of the chiplet 460 by interconnects 502, which may be solderless hybrid joints and / or solder connections. A portion of the circuit 802 of the second RDL 830 is directly coupled to the package substrate circuit 142 of the package substrate by interconnects 830, which may be solderless hybrid joints and / or solder connections. A portion of the circuit 802 of the second RDL 830 is directly coupled to the package substrate circuit 142 of the package substrate 134 by interconnects 148, such as solder bumps. The gap space between the package substrate 134 and the second RDL 830, the interconnects 830, protects the interconnects 148, 830. The chip package assembly 800 may be filled with underfill 806 to solidify the chip package assembly 800 .

[0063] Thus, a chip package assembly and method for fabricating the same has been described that utilizes a modular chip stack that can be matched with one or more chiplets. Advantageously, because the chip stack is built on a simple I / O IC die, a wide variety of functional dies can be utilized while maintaining the same output interface of the chip stack through the I / O IC die, thereby enabling modular, flexible designs that can be rapidly designed and developed with minimal cost and time. Furthermore, the use of chiplets allows for the use of scalable, modular chip stacks with a wide variety of different chiplets, further enhancing the flexibility to rapidly design and develop a wide range of vast chip package assembly designs at a fraction of the cost and time required to develop conventional designs. Thus, modular chip package assemblies offer excellent scalability, low development costs, and very attractive development times.

[0064] In addition to the appended claims, the disclosed technology can be illustrated in the following non-limiting examples.

[0065] Example 1: A chip package assembly including: an input / output integrated circuit (I / O IC) die having a first surface and a second surface; a functional IC die stacked on the first surface of the I / O IC die; a first chiplet having circuitry coupled to circuitry of the I / O IC die; and a substrate having a first surface and a second surface, the first chiplet being disposed between the substrate and the I / O IC die, the substrate having substrate circuitry communicatively coupled to functional circuitry of the functional IC die via the first chiplet and the I / O IC die within the chip package assembly.

[0066] Example 2: The chip package assembly of Example 1, further including a first redistribution layer (RDL) coupling the second surface of the I / O IC die to the first chiplet.

[0067] Example 3: The chip package assembly of Example 2, further including circuitry that connects I / O circuitry of the I / O IC die directly to substrate circuitry while bypassing the first chiplet.

[0068] Example 4: The chip package assembly of Example 3, further including a first dielectric fill layer disposed laterally around the first chiplet, and conductive vias disposed in the first dielectric fill layer to provide electrical connections between the I / O circuitry and the substrate circuitry.

[0069] Example 5: The chip package assembly of Example 4, wherein the first chiplet further includes a solder connection that mechanically and electrically couples the first chiplet to the substrate.

[0070] Example 6: The chip package assembly of Example 2, further including a second RDL coupling the substrate to the active side of the first chiplet.

[0071] Example 7: The chip package assembly of Example 6, wherein the first chiplet further includes a conductive via disposed through a first chiplet substrate of the first chiplet, the conductive via coupling the circuitry of the first chiplet to the first RDL.

[0072] Example 8: An example embodiment in which a first chiplet further includes a conductive via disposed through a first chiplet substrate of the first chiplet, the conductive via coupling circuitry of the first chiplet to first RDL circuitry of the first RDL and substrate circuitry of the substrate. 2. Chip package assembly.

[0073] Example 9: The chip package assembly of Example 4, further including a second dielectric fill layer laterally disposed around the I / O IC die and the functional IC die, and a circuit element disposed in the second dielectric fill layer, the circuit element being coupled to the first RDL circuitry of the first RDL.

[0074] Example 10: The chip package assembly of Example 9, wherein the circuit element is a capacitor.

[0075] Example 11: The chip package assembly of example 10, wherein the capacitor is a deep trench capacitor coupled to a power rail in a first RDL circuit of the first RDL.

[0076] Example 12: The chip package assembly of Example 4, further including a second dielectric fill layer laterally disposed around the I / O IC die and the functional IC die, and a second chiplet disposed in the second dielectric fill layer laterally offset from the first chiplet, the second chiplet having second chiplet circuitry coupled to the first RDL circuitry of the first RDL.

[0077] Example 13: The chip package assembly of Example 12, wherein the second chiplet is one of the plurality of chiplets having chiplet circuitry coupled to the first RDL circuitry of the first RDL.

[0078] Example 14: The chip package assembly of Example 12, wherein the second chiplet circuitry includes one or more of a physical layer (PHY) circuit, a high-bandwidth memory circuit, a processor, a serial / deserializer (SerDes), a high-speed serial bus, an analog-to-digital converter, a digital-to-analog converter, a video codec circuit, an electrical-to-optical converter, a memory subsystem, a processor subsystem, flash memory, and a power conditioning / distribution system, or an optical-to-electrical converter.

[0079] Example 15: The chip package assembly of example 1, wherein the first chiplet does not include a through-silicon via.

[0080] Example 16: The chip package assembly of Example 1, wherein the first chiplet circuit of the first chiplet further includes one or more of a physical layer (PHY) circuit, a high-bandwidth memory circuit, a processor, a serial / deserializer (SerDes), a high-speed serial bus, an analog-to-digital converter, a digital-to-analog converter, a video codec circuit, an electrical-to-optical converter, a memory subsystem, a processor subsystem, flash memory, and a power conditioning / distribution system, or an optical-to-electrical converter.

[0081] Example 17: The chip package assembly of example 1, wherein the I / O IC die further includes a mux circuit and a demux circuit.

[0082] Example 18: The chip package assembly of Example 1, further including a plurality of IC dies stacked on the first IC die, wherein a second IC die of the plurality of IC dies positioned farthest from the first IC die is a processor.

[0083] Example 19: A chip package assembly, comprising: an input / output integrated circuit (I / O IC) die having a first surface and a second surface; and a metal layer stacked on the first surface of the I / O IC die. a first redistribution layer (RDL) coupling a second surface of the I / O IC die to the first chiplet; and a substrate having a first surface and a second surface, the first chiplet being disposed between the substrate and the I / O IC die, the substrate having substrate circuitry communicatively coupled to functional circuitry of the functional IC die through the first RDL, the first chiplet, and the I / O IC die within the chip package assembly, the chip package assembly further including circuitry connecting I / O circuitry of the I / O IC die directly to the substrate circuitry while bypassing the first chiplet, and a dielectric fill layer laterally disposed around the I / O IC die and the functional IC die.

[0084] Example 20: The chip package assembly of Example 19, further including a circuit element or a second chiplet disposed in the dielectric fill layer laterally offset from the first chiplet, the circuit element being coupled to the first RDL circuit of the first RDL.

[0085] Example 21: The chip package assembly of Example 19, wherein the first chiplet circuit of the first chiplet further includes one or more of a physical layer (PHY) circuit, a high-bandwidth memory circuit, a processor, a serial / deserializer (SerDes), a high-speed serial bus, an analog-to-digital converter, a digital-to-analog converter, a video codec circuit, an electrical-to-optical converter, a memory subsystem, a processor subsystem, flash memory, and a power conditioning / distribution system, or an optical-to-electrical converter.

[0086] Example 22: The chip package assembly of Example 19, wherein the first chiplet has a smaller planar area than the I / O IC die.

[0087] Example 23: The chip package assembly of example 19, wherein the first chiplet does not include a through-silicon via.

[0088] Example 24: The chip package assembly of example 19, wherein the I / O IC die further includes a mux circuit and a demux circuit.

[0089] Example 25: The chip package assembly of example 19, wherein the IC die positioned farthest from the I / O IC die among the plurality of IC dies is a processor.

[0090] Example 26: The chip package assembly of Example 19, wherein the first chiplet further includes a solder connection that mechanically and electrically couples the first chiplet to the substrate.

[0091] Example 27: The chip package assembly of Example 19, further including a second RDL bonding the substrate to the active side of the first chiplet.

[0092] Example 28: The chip package assembly of Example 27, wherein the first chiplet further includes a conductive via disposed through a first chiplet substrate of the first chiplet, the conductive via coupling the circuitry of the first chiplet to the first RDL.

[0093] Example 29: The chip package assembly of Example 19, wherein the first chiplet further includes a conductive via disposed through a first chiplet substrate of the first chiplet, the conductive via coupling the circuitry of the first chiplet to the first RDL circuitry of the first RDL and to the substrate circuitry of the substrate.

[0094] Example 30: Method for making a chip package assembly, forming a die stack including multiple integrated circuit (IC) dies and an I / O IC die having exposed contacts. forming a first redistribution layer (RDL) over exposed contacts of the I / O IC die; bonding a chiplet to the first RDL; and bonding the chiplet to a substrate.

[0095] Example 31: The method of example 30, further comprising forming a second RDL on the chiplet opposite the first RDL.

[0096] Example 32: The method of example 30, further comprising electrically connecting the first RDL to the I / O IC die while bypassing the circuitry of the chiplet.

[0097] Example 33: The method of example 30, further comprising forming a first dielectric fill layer around the I / O IC die.

[0098] Example 34: The method of Example 33, further comprising electrically coupling circuit elements disposed in the first dielectric fill layer to the first RDL laterally outside of the I / O IC die.

[0099] Example 35: The method of Example 33, further comprising electrically coupling a second chiplet disposed in the first dielectric fill layer to the first RDL laterally outside the I / O IC die.

[0100] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of which is determined by the appended claims.

Claims

1. 1. A chip package assembly comprising: an input / output integrated circuit (I / O IC) die having a first surface and a second surface; a functional IC die stacked on the first surface of the I / O IC die; a first chiplet having circuitry coupled to circuitry of the I / O IC die; a substrate having a first surface and a second surface, the first chiplet being disposed between the substrate and the I / O IC die, the substrate having substrate circuitry communicatively coupled within the chip package assembly to functional circuitry of the functional IC die via the first chiplet and the I / O IC die.

2. The chip package assembly of claim 1 , further comprising a first redistribution layer (RDL) coupling the second surface of the I / O IC die to the first chiplet.

3. The chip package assembly of claim 2 further comprising circuitry that connects I / O circuitry of said I / O IC die directly to said substrate circuitry while bypassing said first chiplet.

4. a first dielectric fill layer disposed laterally around the first chiplet; 4. The chip package assembly of claim 3, further comprising: conductive vias disposed in the first dielectric fill layer to provide electrical connections between the I / O circuitry and the substrate circuitry.

5. The first chiplet comprises: The chip package assembly of claim 4 , further comprising a solder connection mechanically and electrically coupling the first chiplet to the substrate.

6. a second dielectric fill layer laterally disposed around the I / O IC die and the functional IC die; and an auxiliary element disposed in the second dielectric fill layer, the auxiliary element being coupled to a first RDL circuit of the first RDL, the auxiliary element being a capacitor, a dummy structure or a chiplet.

7. a second dielectric fill layer laterally disposed around the I / O IC die and the functional IC die; a second chiplet disposed laterally offset from the first chiplet in the second dielectric fill layer, the second chiplet having a second chiplet circuit coupled to a first RDL circuit of the first RDL.

8. 8. The chip package assembly of claim 7, wherein the second chiplet is one of a plurality of chiplets having chiplet circuitry coupled to the first RDL circuitry of the first RDL.

9. The chip package assembly of claim 1 , wherein the first chiplet does not include through-silicon vias.

10. The chip package assembly of claim 1 , wherein the I / O IC die further includes a mux circuit and a demux circuit.

11. 2. The chip package assembly of claim 1, further comprising a plurality of IC dies stacked on the first IC die, wherein a second IC die of the plurality of IC dies positioned farthest from the first IC die is a processor.

12. 1. A chip package assembly comprising: an input / output integrated circuit (I / O IC) die having a first surface and a second surface; a plurality of functional integrated circuit (IC) dies stacked on the first surface of the I / O IC die; a first chiplet; and a first redistribution layer (RDL) coupling the second surface of the I / O IC die to the first chiplet; a substrate having a first surface and a second surface, the first chiplet being disposed between the substrate and the I / O IC die, the substrate having substrate circuitry communicatively coupled to functional circuitry of the functional IC die via the first RDL, the first chiplet, and the I / O IC die within the chip package assembly, the chip package assembly further comprising: circuitry that connects I / O circuitry of the I / O IC die directly to the substrate circuitry while bypassing the first chiplet; a dielectric fill layer laterally disposed around the I / O IC die and the functional IC die.

13. The first chiplet circuitry of the first chiplet may include physical layer (PHY) circuitry, high-bandwidth memory circuitry, a processor, a serial deserializer (SerDes), a high-speed serial bus, an analog-to-digital converter, a digital 13. The chip package assembly of claim 1 or 12, further comprising one or more of a digital-to-analog converter, a video codec circuit, an electrical-to-optical converter, a memory subsystem, a processor subsystem, flash memory, a high-bandwidth memory, and a power conditioning / distribution system or an optical-to-electrical converter.

14. The chip package assembly of claim 2 or 12, further comprising a second RDL coupling the substrate to an active side of the first chiplet.

15. 13. The chip package assembly of claim 2 or 12, wherein the first chiplet further includes conductive vias disposed through the first chiplet, the conductive vias coupling circuitry of the first chiplet to first RDL circuitry of the first RDL and to the substrate circuitry of the substrate.

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