Peak current load control circuit

Abstract

To provide a peak current load control circuit.SOLUTION: The circuit includes a reference voltage adjustment circuit configured to generate a reference voltage control signal according to the constant current mode signal and / or the constant voltage mode signal of the primary-side control chip, and a peak load detection module configured to adjust a reference voltage for peak load detection according to the reference voltage control signal, perform peak load detection on the primary-side control chip according to the reference voltage, and adjust a control mode of the primary-side control chip, where the control mode includes a constant current loop control mode and a constant voltage loop control mode. The reference voltage adjustment circuit controls and adjusts the reference voltage for detecting the peak load of the primary-side control chip according to the constant current mode signal and / or the constant voltage mode signal of the primary-side control chip, so as to control the switching of the control mode of the primary-side control chip and improve the stability of the output voltage when detecting the peak current load of the primary-side regulation charger.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on March 31, 2022, application number 202210331067.8, entitled "Peak Current Load Control Circuit," and a Chinese patent application filed with the China Patent Office on March 31, 2022, application number 202220729267.4, entitled "Peak Current Load Control Circuit," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the technical field of power electronics, and in particular to peak current load control circuits. [Background technology]

[0003] In smart speaker applications, when deep bass is played, the instantaneous output of the smart speaker is several times higher than the output during normal playback. Taking the Tmall Genie X5 speaker as an example, the rated output displayed on the charger is 12V 2A (24W), but when deep bass is played, the peak output current reaches 3.8A, resulting in an instantaneous output of 45.6W. At such a high instantaneous output, the charger's output voltage drops significantly, causing the smart speaker to shut down and restart.

[0004] Therefore, the issue that needs to be resolved now is how to prevent smart speakers from shutting down and restarting due to a significant drop in the charger's output voltage during momentary high output, and how to improve the stability of the charger's output voltage. Summary of the Invention

[0005] The object of the present invention is to provide a peak current load control circuit to prevent load shedding and restart caused by a significant drop in the charger output voltage during instantaneous high output power, and to improve the stability of the charger output voltage.

[0006] In order to solve the above technical problems, the peak current load control circuit provided in the present invention comprises: a reference voltage adjusting circuit for generating a reference voltage control signal according to the constant current mode signal and / or the constant voltage mode signal of the primary side control chip; and a peak load detection module for adjusting a reference voltage for peak load detection based on the reference voltage control signal, performing peak load detection for the primary side control chip based on the reference voltage, and adjusting a control mode of the primary side control chip, wherein the control modes include a constant current loop control mode and a constant voltage loop control mode, the reference voltages include an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times (k is greater than 1) the overcurrent protection reference voltage.

[0007] Optionally, the reference voltage adjusting circuit is specifically used to generate, based on the constant current mode signal and / or the constant voltage mode signal, a first control signal corresponding to the peak load reference voltage when the primary side control chip is in the constant current loop control mode, and a second control signal corresponding to the overcurrent protection reference voltage when the primary side control chip is in the constant voltage loop control mode and the reference voltage is the peak load reference voltage, wherein the reference voltage control signal includes the first control signal and the second control signal.

[0008] Optionally, the reference voltage adjustment circuit comprises: a constant current adjusting circuit that generates the first control signal after the primary side control chip enters the constant current loop control mode according to a constant current mode start signal and a constant current mode end signal corresponding to the constant current mode signal, the reference voltage is the peak load reference voltage, and generates the second control signal after the primary side control chip exits the constant current loop control mode.

[0009] Optionally, the constant current adjusting circuit includes a first AND gate element, a first RS flip-flop, a D flip-flop, and a paraphase amplifier; wherein the first input terminal of the first AND gate element is connected to the output terminal of the constant current mode end signal, the second input terminal of the first AND gate element is connected to the Q output terminal of the D flip-flop, the output terminal of the first AND gate element is connected to the R input terminal of the first RS flip-flop, the S input terminal of the first RS flip-flop is connected to the output terminal of the constant current mode start signal, the Q output terminal of the first RS flip-flop is connected to the D input terminal of the D flip-flop, the clock input terminal of the D flip-flop is connected to the output terminal of the turn-on pulse signal that drives the primary side control chip to turn on the cycle, the Q output terminal of the D flip-flop is connected to the input terminal of the paraphase amplifier, and the output terminal of the paraphase amplifier is connected to the input terminal of the reference voltage control signal of the peak load detection module.

[0010] Optionally, the first RS flip-flop includes a first NOR gate element and a second NOR gate element; wherein the first input terminal of the first NOR gate element is connected to the output terminal of the constant current mode start signal, the second input terminal of the first NOR gate element is connected to the output terminal of the second NOR gate element, the output terminal of the first NOR gate element is connected to the first input terminal of the second NOR gate element, the second input terminal of the second NOR gate element is connected to the output terminal of the first AND gate element, and a common terminal connecting the output terminal of the second NOR gate element and the second input terminal of the first NOR gate element is connected to the D input terminal of the D flip-flop as the Q output terminal of the first RS flip-flop.

[0011] Optionally, the reference voltage control signals include a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to a middle-high reference voltage, and a fourth control signal corresponding to a middle-low reference voltage, wherein the peak load reference voltage is greater than the middle-high reference voltage, greater than the middle-low reference voltage, and greater than the overcurrent protection reference voltage; Correspondingly, the reference voltage adjusting circuit is specifically used to generate the fourth control signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, generate the second control signal when the reference voltage is the mid-low reference voltage and the primary side control chip is in the constant voltage loop control mode, generate the third control signal when the reference voltage is the mid-low reference voltage and the primary side control chip is in the constant current loop control mode, generate the fourth control signal when the reference voltage is the mid-high reference voltage and the primary side control chip is in the constant voltage loop control mode, generate the first control signal when the reference voltage is the mid-high reference voltage and the primary side control chip is in the constant current loop control mode, and generate the third control signal when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant voltage loop control mode based on the constant current mode signal and / or the constant voltage mode signal.

[0012] Optionally, the peak current load control circuit further comprises: The inverter includes a timing circuit that counts the peak load duration and / or the overcurrent protection duration, and outputs a peak load protection restart control signal when the peak load duration reaches a first threshold value and / or outputs an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold value.

[0013] Optionally, the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, and the timing circuit is specifically used for counting the peak load duration and the overcurrent protection duration based on a constant current mode signal of the primary side control chip, and outputting the peak load protection restart control signal when the peak load duration reaches the first threshold and outputting the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold, wherein the peak load duration is a maintenance time when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode, and the overcurrent protection duration is a maintenance time when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode or when the reference voltage is the peak load reference voltage.

[0014] Optionally, the timing circuit comprises a peak load timing circuit and an overcurrent protection timing circuit, among which: the overcurrent protection timing circuit includes a second AND gate element, a second RS flip-flop, and a first timer, a first input terminal of the second AND gate element is connected to the output terminal of the reference voltage control signal of the reference voltage adjusting circuit, a second input terminal of the second AND gate element is connected to the output terminal of a constant current mode end delay signal corresponding to the constant current mode signal, an output terminal of the second AND gate element is connected to the R input terminal of the second RS flip-flop, an S input terminal of the second RS flip-flop is connected to the output terminal of a constant current mode start signal corresponding to the constant current mode signal, and a Q output terminal of the second RS flip-flop is connected to the enable terminal of the first timer, the output terminal of the first timer is used as the output terminal of the overcurrent protection timing circuit to output the overcurrent protection restart control signal when the duration of the received enable signal reaches the second threshold, and the turn-on delay signal is a pulse signal that is generated after a predetermined number of cycles of a turn-on pulse signal have passed after the constant current mode control mode is terminated; The peak load timing circuit includes a third AND gate element and a second timer, a first input terminal of the third AND gate element is connected to the output terminal of the constant current mode signal, a second input terminal of the third AND gate element is connected to the output terminal of a paraphase signal corresponding to the reference voltage control signal, and an output terminal of the third AND gate element is connected to the enable terminal of the second timer, and the output terminal of the second timer is used as the output terminal of the peak load timing circuit to output the peak load protection restart control signal when the duration of the received enable signal reaches the first threshold.

[0015] Optionally, the reference voltage control signals include a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to a middle-high reference voltage, and a fourth control signal corresponding to a middle-low reference voltage, wherein the peak load reference voltage is greater than the middle-high reference voltage, greater than the middle-low reference voltage, and greater than the overcurrent protection reference voltage; Correspondingly, the timing circuit is specifically used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary side control chip, and output the peak load protection restart control signal when the peak load duration reaches the first threshold value, and output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold value, wherein the peak load duration is the maintenance time when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode, and the overcurrent protection duration is the maintenance time when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, or when the reference voltage is the middle-low reference voltage, the middle-high reference voltage, or the peak load reference voltage.

[0016] The peak current load control circuit provided by the present invention includes: a reference voltage adjusting circuit for generating a reference voltage control signal according to a constant current mode signal and / or a constant voltage mode signal of the primary control chip; and a peak load detection module for adjusting a reference voltage for peak load detection according to the reference voltage control signal, and performing peak load detection for the primary control chip according to the reference voltage, and adjusting the control mode of the primary control chip, wherein the control modes include a constant current loop control mode and a constant voltage loop control mode, the reference voltages include an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times (k is greater than 1) the overcurrent protection reference voltage.

[0017] From this, it can be seen that the present invention installs a reference voltage adjustment circuit to control and adjust the reference voltage of the peak load detection of the primary control chip according to the constant current mode signal and / or constant voltage mode signal of the primary control chip, thereby controlling the switching of the constant current loop control mode and constant voltage loop control mode of the primary control chip, thereby avoiding the load shedding restart caused by the obvious drop in output voltage of the primary regulated charger when the output voltage is momentarily high, and improving the stability of the output voltage when the primary regulated charger detects a peak current load.

[0018] In order to more clearly explain the technical methods in the embodiments of the present invention or the prior art, the following briefly introduces drawings that need to be used in the embodiments or the prior art. However, the drawings in the following description are only embodiments of the present invention, and it is obvious that a person skilled in the art can obtain other drawings based on the drawings provided on the premise that no creative work is performed. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a block diagram of a peak current load control circuit provided in an embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram of the control mode switching principle of the primary side control chip. [Figure 3] FIG. 3 is a schematic diagram of a two-position reference voltage switching peak load detection provided in an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram of a peak load detection four-position reference voltage switch provided in an embodiment of the present invention. [Figure 5] FIG. 5 is a schematic diagram of a reference voltage adjusting circuit in a peak current load control circuit provided in an embodiment of the present invention. [Figure 6] FIG. 6 is a schematic diagram of an overcurrent protection timing circuit in a peak current load control circuit provided in an embodiment of the present invention. [Figure 7] FIG. 7 is a schematic diagram of a peak load timing circuit in a peak current load control circuit provided in an embodiment of the present invention. [Figure 8] FIG. 8 is a schematic diagram of the sequence of related signals of the constant current mode signal in the peak current load control circuit provided in the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention, but it is clear that the described embodiments are only some embodiments of the present invention and not all embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present invention without performing creative work fall within the protection scope of the present invention.

[0021] Referring to FIG. 1, it is a block diagram of a peak current load control circuit provided in an embodiment of the present invention. The peak current load control circuit includes: a reference voltage adjusting circuit 10 for generating a reference voltage control signal according to the constant current mode signal and / or the constant voltage mode signal of the primary side control chip; and a peak load detection module 20 for adjusting the reference voltage of peak load detection based on the reference voltage control signal, and performing peak load detection for the primary side control chip based on the reference voltage, and adjusting the control mode of the primary side control chip, wherein the control modes include a constant current loop control mode and a constant voltage loop control mode, the reference voltages include an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times (k is greater than 1) the overcurrent protection reference voltage.

[0022] The principle behind whether a load in a primary side regulation (PSR) system is controlled by a CV (constant voltage) loop or a CC (constant current) loop is that the load weight is detected in real time based on the load capacitance determined by the reference voltage (VrefCC) corresponding to the constant current point. If the load can be moved, the CV loop controls the entire PSR system, but if the load cannot be moved, the CC loop controls the entire PSR system. As shown in Figure 2, section A to B belongs to the constant voltage CV section, and the output of the primary side regulation system is controlled by the CV loop. Section B to C belongs to the constant current CC section. Since the CV loop cannot move the load in this section, the system output is controlled by the CC loop.

[0023] Specifically, the peak load detection module 20 can adopt the following formula for peak load detection on the primary side control chip:

[0024]

number

[0025] In the above formula, Iout is the average output current of the CC loop control of the primary control chip, Np is the number of turns in the primary coil of the transformer, Ns is the number of turns in the secondary coil of the transformer, Rcs is the resistance value of the peak current sampling resistor, and VrefCC is the reference voltage, that is, the reference voltage of the CC loop control.

[0026] In other words, the peak load detection module 20, based on the reference voltage (VrefCC) controlled and adjusted by the reference voltage adjustment circuit 10, can perform peak load detection for the primary control chip using a method that is the same as or similar to the peak load detection method in the prior art, and can adjust and switch the constant current loop control mode or constant voltage loop control mode adopted by the primary control chip.

[0027] In response to this, the peak load detection module 20 of this embodiment adjusts the reference voltage of peak load detection according to the reference voltage control signal sent by the connected reference voltage adjustment circuit 10, thereby adjusting and switching the load capacity of the primary control chip, and also adjusting the control mode of the primary control chip, i.e., switching between constant current loop control mode and constant voltage loop control mode, according to the current load weight situation, thereby improving the stability of the output voltage of the primary regulation charger.

[0028] It should be noted that the specific settings and values ​​of the reference voltage for peak load detection in this embodiment can be set by the designer based on the actual application scenario and user needs. For example, the reference voltage can include a reference voltage (i.e., OCP reference voltage) corresponding to the overcurrent protection (OCP) output current point (i.e., OCP point, points A and D in FIG. 3) and a reference voltage (i.e., peak load reference voltage) corresponding to the peak load output current point (i.e., Pk Load point, points B and C in FIG. 3). Correspondingly, the reference voltage control signal sent by the reference voltage adjusting circuit 10 to the peak load detection module 20 can include a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, where Pk Load / OCP=k, i.e., the peak load reference voltage is k times the overcurrent protection reference voltage, where k is greater than 1. In other words, when k is large, if the output current for the load is between the OCP point and the Pk Load point, peak load detection can be controlled at two positions, the overcurrent protection reference voltage (VrefCCL) and the peak load reference voltage (VrefCCH), and the reference voltage (VrefCC) that determines the constant current point can be switched between VrefCCL and VrefCCH. Correspondingly, the peak load detection module 20 can also switch the control mode of the primary control chip between a constant current loop control mode (CC Mode) and a constant voltage loop control mode (CV Mode), which prevents the output voltage from dropping excessively compared to peak load detection with a fixed reference voltage as in the prior art.

[0029] Furthermore, in this embodiment, the reference voltage (VrefCC) that determines the constant current point can include a preset reference voltage between the overcurrent protection reference voltage and the peak load reference voltage. Increasing the number of VrefCC positions further improves ripple during the control mode switching process of the primary control chip, so the more VrefCC positions there are, the better the ripple performance. For example, if the number of preset reference voltages between the overcurrent protection reference voltage and the peak load reference voltage is two, the reference voltage (VrefCC) can include four positions: a peak load reference voltage (VrefCCH), an overcurrent protection reference voltage (VrefCCL), a mid-high reference voltage (VrefCCMHigh), and a mid-low reference voltage (VrefCCMLow). Of these, VrefCCH > VrefCCMHigh > VrefCCMLow > VrefCCL. As shown in Figure 4, when ΔVrefCC between two adjacent positions is the same, by setting VrefCC in four positions, it is possible to make the ΔVrfCC that changes between two adjacent positions each time VrefCC is only 1 / 3 of the VrefCC of the original two positions, thereby improving the ripple.

[0030] The constant current mode signal of the primary control chip in this embodiment may be a signal of the constant current loop control mode adopted by the primary control chip, such as the CCMode signal in Figure 8, that is, when the control mode of the primary control chip is the constant current loop control mode, the CCMode signal is high, and when the control mode of the primary control chip is the constant voltage loop control mode, the CCMode signal is low. The constant voltage mode signal of the primary control chip may be a signal of the constant voltage loop control mode adopted by the primary control chip, for example, when the control mode of the primary control chip is the constant current loop control mode, the constant voltage mode signal may be low, and when the control mode of the primary control chip is the constant voltage loop control mode, the constant voltage mode signal may be high.

[0031] Accordingly, the reference voltage adjusting circuit 10 of this embodiment can control the reference voltage for peak load detection adjusted by the peak load detection module 20 by generating a reference voltage control signal based on the constant current mode signal and / or the constant voltage mode signal.

[0032] For example, if the reference voltage for peak load detection includes a peak load reference voltage and an overcurrent protection reference voltage, the reference voltage adjusting circuit 10 can specifically generate a first control signal corresponding to the peak load reference voltage when the primary control chip is in constant current loop control mode based on the constant current mode signal and / or the constant voltage mode signal, and generate a second control signal corresponding to the overcurrent protection reference voltage when the primary control chip is in constant voltage loop control mode and the reference voltage is the peak load reference voltage, where the reference voltage control signal includes the first control signal and the second control signal. As shown in FIG. 3, the constant current point corresponding to the overcurrent protection reference voltage (VrefCCL) is the OCP point, and the constant current point corresponding to the peak load reference voltage (VrefCCH) is the Pk Load point. 1) When the load is lower than the OCP point, i.e., below point A, the output current of the PSR device is below the OCP point determined by VrefCCL and operates in the CV section. That is, the PSR device control mode is CV Mode (constant voltage loop control mode).

[0033] 2) When the load is higher than the OCP point but lower than the Pk Load point, i.e., when the load is between points A and B, the load capacitance determined by VrefCCL cannot drive this load. The peak load detection module 20 switches the control mode of the primary control chip from CV Mode to CC Mode (i.e., constant current loop control mode). At this time, the reference voltage adjustment circuit 10 controls the peak load detection module 20 to switch the reference voltage from VrefCCL to VrefCCH, thereby increasing the load capacitance of the PSR device from the OCP point to the Pk Load point. After switching to VrefCCH, the PSR device can drive a load between A and B. The peak load detection module 20 switches the control mode of the primary control chip from CC Mode to CV Mode. At this time, the reference voltage adjustment circuit 10 controls the peak load detection module 20 to switch the reference voltage from VrefCCH to VrefCCL, thereby reducing the load capacitance of the PSR system from the Pk Load point to the OCP point. After this, the above process is repeated, and the reference voltage (VrefCC) that determines the constant current point is switched between VrefCCH and VrefCCL.

[0034] 3) If the load is higher than the Pk Load point, that is, if the load is between points B and C, the load capacitance of the PSR device will be switched to the Pk Load point determined by VrefCCH. At this time, the PSR device cannot drive the load, VrefCC will be stable at VrefCCH, and the control mode of the primary side control chip will remain in CC Mode.

[0035] 4) If the load continues to change and falls below the Pk Load point, that is, if the load is between points C and D, repeat the process in 2) above.

[0036] 5) If the load continues to change and falls below the OCP point, i.e., if the load is lower than point D, VrefCC will stabilize at VrefCCL, and the control mode of the primary side control chip will remain in CV Mode.

[0037] Accordingly, the specific circuit structure of the reference voltage adjusting circuit 10 in this embodiment can be set by the designer based on the practical scenario and user needs. When the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, the reference voltage adjusting circuit 10 can include a constant current adjusting circuit, which can be used to generate a first control signal after the primary control chip enters the constant current loop control mode based on a constant current mode start signal and a constant current mode end signal corresponding to the constant current mode signal, and to generate a second control signal after the primary control chip exits the constant current loop control mode when the reference voltage is the peak load reference voltage. The constant current mode start signal corresponding to the constant current mode signal can be a pulse signal at the start of the constant current loop control mode (CC Mode), such as the CCMode_beginpulse signal in FIG. 8, and the constant current mode end signal corresponding to the constant current mode signal can be a pulse signal at the end of the constant current loop control mode, such as the CCMode_endpulse signal in FIG. 8. Correspondingly, the reference voltage adjustment circuit 10 may further include a signal conversion circuit that converts the constant current mode signal of the primary side control chip into a constant current mode start signal and a constant current mode end signal, and the constant current adjustment circuit can generate a reference voltage control signal according to the constant current mode start signal and constant current mode end signal output by the signal conversion circuit.

[0038] Specifically, as shown in FIG. 5, when the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, the above-mentioned constant current adjustment circuit can include a first AND gate element 11 (and2, i.e., a two-input AND gate element), a first RS flip-flop 12 (two nor2, i.e., an RS flip-flop composed of two-input NOR gate elements), a D flip-flop 13 (DFF), and a paraphase amplifier 14. The first input terminal of the first AND gate element 11 is connected to the output terminal of the constant current mode end signal, the second input terminal of the first AND gate element 11 is connected to the Q output terminal of the D flip-flop 13, the output terminal of the first AND gate element 11 is connected to the R input terminal of the first RS flip-flop 12, the S input terminal of the first RS flip-flop 12 is connected to the output terminal of the constant current mode start signal, the Q output terminal of the first RS flip-flop 12 is connected to the D input terminal of the D flip-flop 13, and the clock input terminal (clk) of the D flip-flop 13 is connected to the cycle turn of the primary side control chip. The D flip-flop 13 has a Q output connected to the input of a paraphase amplifier 14, the output of which is connected to the reference voltage control signal input of the peak load detection module 20. The Q output of the D flip-flop 13 is ...

[0039] Correspondingly, by connecting the second input terminal of the first AND gate element 11 to the Q output terminal of the D flip-flop 13, the constant current adjustment circuit can be used to generate a reference voltage control signal based on the input constant current mode start signal and constant current mode end signal. Also, by connecting the second input terminal of the first AND gate element 11 to the input terminal of the peak load reference voltage usage status signal, the constant current adjustment circuit can be used to generate a reference voltage control signal based on the input constant current mode start signal, constant current mode end signal, and peak load reference voltage usage status signal. This embodiment does not impose any limitations on this.

[0040] Correspondingly, this embodiment does not limit the specific circuit configuration of the first RS flip-flop 12. As shown in FIG. 5, the first RS flip-flop 12 may include a first NOR gate element and a second NOR gate element, of which the first input terminal of the first NOR gate element is connected to the output terminal of the constant current mode start signal, the second input terminal of the first NOR gate element is connected to the output terminal of the second NOR gate element, the output terminal of the first NOR gate element is connected to the first input terminal of the second NOR gate element, the second input terminal of the second NOR gate element is connected to the output terminal of the first AND gate element 11, and the common terminal connecting the output terminal of the second NOR gate element and the second input terminal of the first NOR gate element is connected to the D input terminal of the D flip-flop 13 as the Q output terminal of the first RS flip-flop 12.

[0041] For example, when the reference voltage for peak load detection includes a peak load reference voltage, an overcurrent protection reference voltage, a middle-low reference voltage, and a middle-high reference voltage between the overcurrent protection reference voltage and the peak load reference voltage, the reference voltage control signal can include a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the middle-high reference voltage, and a fourth control signal corresponding to the middle-low reference voltage. The reference voltage adjusting circuit 10 specifically generates the fourth control signal according to the constant current mode signal and / or the constant voltage mode signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode. It can be used to generate a second control signal when the reference voltage is a medium-low reference voltage and the primary control chip is in a constant voltage loop control mode, to generate a third control signal when the reference voltage is a medium-low reference voltage and the primary control chip is in a constant current loop control mode, to generate a fourth control signal when the reference voltage is a medium-high reference voltage and the primary control chip is in a constant voltage loop control mode, to generate a first control signal when the reference voltage is a medium-high reference voltage and the primary control chip is in a constant current loop control mode, and to generate a third control signal when the reference voltage is a peak load reference voltage and the primary control chip is in a constant voltage loop control mode.

[0042] As shown in Figure 4, the constant current point for the overcurrent protection reference voltage (VrefCCL) is the OCP point, the constant current point for the peak load reference voltage (VrefCCH) is the Pk Load point, the constant current point for the mid-low reference voltage (VrefCCMLow) is the B point, and the constant current point for the mid-high reference voltage (VrefCCMHigh) is the C point. The peak load detection reference voltage (VrefCC) can be switched among four positions: VrefCCL, VrefCCMLow, VrefCCMHigh, and VrefCCH. 1) VrefCCL → VrefCCMLow: When a CC Mode trigger is detected under VrefCCL, VrefCC can be switched from VrefCCL to VrefCCMLow. 2) VrefCCMLow → VrefCCL: When the end of CC Mode (i.e., a CV Mode trigger) is detected under VrefCCMLow, VrefCC switches from VrefCCMLow to VrefCCL, since the PSR device can drive the current load under VrefCCMLow. 3) VrefCCMLow→VrefCCMHigh: When a CC Mode trigger is detected under the VrefCCMLow state, VrefCCMLow is insufficient to drive the current load, so VrefCC is switched from VrefCCMLow to VrefCCMHigh. 4) VrefCCMHigh→VrefCCMLow: When an end of CC Mode is detected under the VrefCCMHigh state, VrefCCMHigh is able to drive the current load, so VrefCC can be switched from VrefCCMHigh to VrefCCMLow. 5) VrefCCMHigh→VrefCCH: When a CC Mode trigger is detected under the VrefCCMHigh state, VrefCCMHigh is insufficient to drive the current load, so VrefCC can be switched from VrefCCMHigh to VrefCCH.6) VrefCCH → VrefCCMHigh: When the end of CC Mode is detected under the VrefCCH state, VrefCCH can drive the current load, so VrefCC can be switched from VrefCCH to VrefCCMHigh. 7) When the end of CV Mode is detected under the VrefCCL state, VrefCCL can drive the current load, so VrefCC can maintain VrefCCL.

[0043] Correspondingly, when the reference voltage includes an overcurrent protection reference voltage, a peak load reference voltage, a medium-low reference voltage, and a medium-high reference voltage, the specific circuit structure of the reference voltage adjusting circuit 10 can be set using a method similar to that of the reference voltage adjusting circuit 10 in which the reference voltage includes two positions, namely, the overcurrent protection reference voltage and the peak load reference voltage, and no limitations are imposed in this embodiment.

[0044] Furthermore, the peak current load control circuit provided in this embodiment includes a timing circuit for counting the peak load duration and / or the overcurrent protection duration, and outputting a peak load protection restart control signal when the peak load duration reaches a first threshold and / or outputting an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold to restart the charger system, wherein the peak load duration may be equal to or longer than the duration of a constant current point (such as Pk Load point) at which the current required by the load corresponds to a peak load reference voltage, and the overcurrent protection duration may be equal to or longer than the duration of a constant current point (such as OCP point) at which the current required by the load corresponds to an overcurrent protection reference voltage.

[0045] Correspondingly, the timing circuit can specifically be used to count the peak load duration and the overcurrent protection duration, and to trigger the PSR device to restart the peakload protection by outputting a peakload protection restart control signal when the peak load duration reaches a first threshold, and to trigger the PSR device to restart the OCP protection by outputting an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold.

[0046] For example, the reference voltage control signal includes a first control signal corresponding to a peak load reference voltage and a second control signal corresponding to an overcurrent protection reference voltage. The timing circuit can be specifically used to count the peak load duration and the overcurrent protection duration according to the constant current mode signal of the primary side control chip, and output the peak load protection restart control signal when the peak load duration reaches a first threshold value, and output the overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold value, where the peak load duration is the maintenance time when the reference voltage is the peak load reference voltage and the primary side control chip is in constant current loop control mode, and the overcurrent protection restart control signal is output when the peak load duration reaches a second threshold value. The protection duration is the maintenance time when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in constant current loop control mode or when the reference voltage is the peak load reference voltage. As shown in FIG. 3, the timing circuit starts counting the overcurrent protection duration (i.e., OCP count) at point A and ends counting the overcurrent protection duration at point D. If the overcurrent protection duration is equal to or greater than a second threshold (e.g., 1.5 s), it triggers the OCP protection restart of the PSR device. If the overcurrent protection duration is below the second threshold, it allows the PSR device to continue operating. The timing circuit starts counting the peak load duration (i.e., PK Load count) at point B and ends counting the peak load duration at point C. If the peak load duration is equal to or greater than a first threshold (e.g., 150 ms), it triggers the peak load protection restart of the PSR device. If the peak load duration is below the first threshold, it allows the PSR device to continue operating. In other words, as shown by the output current on the left side of Figure 3, when the output current of the PSR device exceeds the OCP point, an OCP count begins. If the PK Load point is reached during this time, another PK Load count begins. However, unless the duration of the PK Load count reaches 150 ms, a restart of peak load protection cannot be triggered; at this time, the OCP count is still ongoing, and after it reaches 1.5 s, OCP protection is triggered.As shown by the output current on the right side of Figure 3, when the output current of the PSR device exceeds the OCP point, an OCP count will start. If the PK Load point is reached during this time, another PK Load count will start. If the duration of the PK Load count reaches 150ms, a restart of the peak load protection will be triggered. At this time, the OCP count will end at the same time, but it is less than 1.5s.

[0047] For example, when the reference voltage control signal includes a first control signal corresponding to a peak load reference voltage, a second control signal corresponding to an overcurrent protection reference voltage, a third control signal corresponding to a middle-high reference voltage, and a fourth control signal corresponding to a middle-low reference voltage, the timing circuit can specifically be used to count the peak load duration and the overcurrent protection duration according to the constant current mode signal of the primary side control chip, and output a peak load protection restart control signal when the peak load duration reaches a first threshold, and output an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold, and the peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode. The overcurrent protection duration is the maintenance time when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in constant current loop control mode, or when the reference voltage is the medium-low reference voltage, the medium-high reference voltage, or the peak load reference voltage. As shown in FIG. 4, the timing circuit starts counting the overcurrent protection duration (i.e., OCP count) at point A and ends counting the overcurrent protection duration at point F. If the overcurrent protection duration is equal to or greater than a second threshold (e.g., 1.5 s), it triggers the OCP protection restart of the PSR device, and if the overcurrent protection duration is below the second threshold, it allows the PSR device to continue operating. The timing circuit starts counting the peak load duration (i.e., PK Load count) at point D and ends counting the peak load duration at point E. If the peak load duration is equal to or greater than a first threshold (e.g., 150 ms), it triggers the peak load protection restart of the PSR device, and if the peak load duration is below the first threshold, it allows the PSR device to continue operating.

[0048] That is, as shown in Figure 4, at point A, the load exceeds the OCP point, VrefCCL changes to VrefCCMLow, and Tocp (i.e., the overcurrent protection period) counting begins. In the A to B section, VrefCC switches between VrefCCL and VrefCCMLow to detect the load. In the B to C section, VrefCC switches between VrefCCMLow and VrefCCMHigh to detect the load. In the C to D section, VrefCC first switches between VrefCCMHigh and VrefCCH, then between VrefCCMLow and VrefCCMHigh, and finally between VrefCCMHigh and VrefCCH. In the section D to E, Tpeakload (i.e., peak load duration) is counted in this section; in the section E to F, VrefCC first switches between VrefCCH and VrefCCMHigh, and after it falls below the constant current point corresponding to VrefCCMHigh, it switches between VrefCCMHigh and VrefCCMLow, and after it falls below the constant current point corresponding to VrefCCMLow, it switches between VrefCCMLow and VrefCCL; after the load falls below the OCP point, VrefCC stabilizes at VrefCCL and exits Tocp counting.

[0049] Correspondingly, the specific circuit structure of the above-mentioned timing circuit can be set by the designer himself / herself based on the practical scenario and user needs. For example, the timing circuit can include a peak load timing circuit and an overcurrent protection timing circuit, of which the peak load timing circuit can be used to count the peak load duration and output the peak load protection restart control signal when the peak load duration reaches a first threshold, and the overcurrent protection timing circuit can be used to count the overcurrent protection duration and output the overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold.

[0050] Specifically, when the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, as shown in FIG. 6, the overcurrent protection timing circuit may include a second AND gate element 21 (and2), a second RS flip-flop 22 (two nor2) and a first timer 23 (Time Counter1), where the first input terminal of the second AND gate element 21 is connected to the output terminal of the reference voltage control signal of the reference voltage adjusting circuit 10 (such as the output terminal of the paraphase amplifier 14 in FIG. 5), the second input terminal of the second AND gate element 21 is connected to the output terminal of the constant current mode end delay signal (CV_EN_12Pulse) corresponding to the constant current mode signal, the output terminal of the second AND gate element 21 is connected to the R input of the second RS flip-flop 22, the S input terminal of the second RS flip-flop 22 is connected to the output terminal of the constant current mode start signal corresponding to the constant current mode signal, and the Q output terminal of the second RS flip-flop 22 is connected to the first timer 23. The output terminal of the first timer 23 is connected to the enable terminal of the first timer 23, and serves as the output terminal of an overcurrent protection timing circuit for outputting a peak load protection restart control signal (Tocp_pro) when the duration of the received enable signal reaches the second threshold value. The turn-on delay signal is a pulse signal generated after a predetermined number of cycles of turn-on pulse signals have continued after the constant current mode control mode has ended, for example, CV_EN_12Pulse in FIG. 8, that is, a pulse signal generated after 12 turn-on pulse signals (i.e., CV mode switching pulse signals, for example, the PFM signal in FIG. 5) have been continuously counted after the CCMode has ended.

[0051] Specifically, when the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, as shown in FIG. 7, the peak load timing circuit can include a third AND gate element 31 (and2) and a second timer 32 (Time Counter2), where the first input terminal of the third AND gate element 31 is connected to the output terminal of the constant current mode signal, the second input terminal of the third AND gate element 31 is connected to the output terminal of the paraphase signal corresponding to the reference voltage control signal (such as the input terminal of the paraphase amplifier 14 in FIG. 5), and the output terminal of the third AND gate element 31 is connected to the enable terminal of the second timer 32, and the output terminal of the second timer 32 is used as the output terminal of the peak load timing circuit to output a peak load protection restart control signal (Tpeakload_pro) when the duration of the received enable signal reaches a first threshold.

[0052] In this embodiment, the embodiment of the present invention uses the reference voltage adjusting circuit 10 to control the peak load detection reference voltage of the primary control chip according to the constant current mode signal and / or constant voltage mode signal of the primary control chip, thereby controlling the switching between the constant current loop control mode and the constant voltage loop control mode of the primary control chip, thereby avoiding the load shedding restart caused by the obvious drop in the output voltage of the primary regulated charger when the output voltage is momentarily high, and improving the stability of the output voltage when the primary regulated charger detects a peak current load.

[0053] Each embodiment of the specification is described in a progressive manner, with the emphasis being on the differences between each embodiment and the other embodiments, and reference may be made to the same or similar parts between the embodiments.

[0054] The peak current load control circuit provided by the present invention has been introduced in detail above. While specific examples are used in this text to describe the principles and embodiments of the present invention, the explanation of the above examples is merely intended to aid in understanding the method and core concept of the present invention. Therefore, it should be noted that those skilled in the art may make minor improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the claims of the present invention.

Claims

1. a reference voltage adjusting circuit for generating a reference voltage control signal according to the constant current mode signal and / or the constant voltage mode signal of the primary side control chip; a peak load detection module for adjusting a reference voltage of peak load detection according to the reference voltage control signal, and for performing peak load detection for the primary side control chip according to the reference voltage, and for adjusting a control mode of the primary side control chip, wherein the control modes include a constant current loop control mode and a constant voltage loop control mode, the reference voltages include an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times (k is greater than 1) the overcurrent protection reference voltage. Peak current load control circuit.

2. 2. The peak current load control circuit of claim 1, wherein the reference voltage adjusting circuit is specifically used to generate a first control signal corresponding to the peak load reference voltage when the primary side control chip is in the constant current loop control mode based on the constant current mode signal and / or the constant voltage mode signal, and to generate a second control signal corresponding to the overcurrent protection reference voltage when the primary side control chip is in the constant voltage loop control mode and the reference voltage is the peak load reference voltage, wherein the reference voltage control signal includes the first control signal and the second control signal.

3. The reference voltage adjustment circuit a constant current adjusting circuit, which generates the first control signal after the primary side control chip enters the constant current loop control mode according to a constant current mode start signal and a constant current mode end signal corresponding to the constant current mode signal, the reference voltage is the peak load reference voltage, and generates the second control signal after the primary side control chip exits the constant current loop control mode; 3. The peak current load control circuit of claim 2.

4. the constant current adjusting circuit includes a first AND gate element, a first RS flip-flop, a D flip-flop, and a paraphase amplifier; wherein a first input terminal of the first AND gate element is connected to the output terminal of the constant current mode end signal, a second input terminal of the first AND gate element is connected to the Q output terminal of the D flip-flop, an output terminal of the first AND gate element is connected to the R input terminal of the first RS flip-flop, an S input terminal of the first RS flip-flop is connected to the output terminal of the constant current mode start signal, a Q output terminal of the first RS flip-flop is connected to the D input terminal of the D flip-flop, a clock input terminal of the D flip-flop is connected to the output terminal of a turn-on pulse signal for driving the primary side control chip to turn on a cycle, a Q output terminal of the D flip-flop is connected to the input terminal of the paraphase amplifier, and an output terminal of the paraphase amplifier is connected to the input terminal of the reference voltage control signal of the peak load detection module.

4. The peak current load control circuit of claim 3.

5. the first RS flip-flop includes a first NOR gate element and a second NOR gate element; wherein a first input terminal of the first NOR gate element is connected to an output terminal of the constant current mode start signal, a second input terminal of the first NOR gate element is connected to an output terminal of the second NOR gate element, an output terminal of the first NOR gate element is connected to a first input terminal of the second NOR gate element, a second input terminal of the second NOR gate element is connected to an output terminal of the first AND gate element, and a common terminal connecting the output terminal of the second NOR gate element and the second input terminal of the first NOR gate element is connected to a D input terminal of the D flip-flop as a Q output terminal of the first RS flip-flop.

5. The peak current load control circuit of claim 4.

6. the reference voltage control signals include a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to a middle-high reference voltage, and a fourth control signal corresponding to a middle-low reference voltage, wherein the peak load reference voltage is greater than the middle-high reference voltage, greater than the middle-low reference voltage, and greater than the overcurrent protection reference voltage; Correspondingly, the reference voltage adjusting circuit is specifically used to generate the fourth control signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, to generate the second control signal when the reference voltage is the mid-low reference voltage and the primary side control chip is in the constant voltage loop control mode, to generate the third control signal when the reference voltage is the mid-low reference voltage and the primary side control chip is in the constant current loop control mode, to generate the fourth control signal when the reference voltage is the mid-high reference voltage and the primary side control chip is in the constant voltage loop control mode, to generate the first control signal when the reference voltage is the mid-high reference voltage and the primary side control chip is in the constant current loop control mode, and to generate the third control signal when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant voltage loop control mode.

2. The peak current load control circuit of claim 1.

7. The inverter further includes a timing circuit that counts the peak load duration and / or the overcurrent protection duration, and outputs a peak load protection restart control signal when the peak load duration reaches a first threshold value, and / or outputs an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold value.

7. A peak current load control circuit according to claim 1.

8. 8. The peak current load control circuit of claim 7, wherein the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage; the timing circuit is specifically used to count the peak load duration and the overcurrent protection duration according to the constant current mode signal of the primary side control chip, and output the peak load protection restart control signal when the peak load duration reaches the first threshold value and output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold value; wherein the peak load duration is a maintenance time when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode; and the overcurrent protection duration is a maintenance time when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode or when the reference voltage is the peak load reference voltage.

9. The timing circuit includes a peak load timing circuit and an overcurrent protection timing circuit, among which: the overcurrent protection timing circuit includes a second AND gate element, a second RS flip-flop, and a first timer, a first input terminal of the second AND gate element is connected to the output terminal of the reference voltage control signal of the reference voltage adjusting circuit, a second input terminal of the second AND gate element is connected to the output terminal of a constant current mode end delay signal corresponding to the constant current mode signal, an output terminal of the second AND gate element is connected to the R input terminal of the second RS flip-flop, an S input terminal of the second RS flip-flop is connected to the output terminal of a constant current mode start signal corresponding to the constant current mode signal, and a Q output terminal of the second RS flip-flop is connected to the enable terminal of the first timer, the output terminal of the first timer is used as the output terminal of the overcurrent protection timing circuit to output the overcurrent protection restart control signal when the duration of the received enable signal reaches the second threshold, and the turn-on delay signal is a pulse signal that is generated after a predetermined number of cycles of a turn-on pulse signal have passed after the constant current mode control mode is terminated; the peak load timing circuit includes a third AND gate element and a second timer, a first input terminal of the third AND gate element is connected to an output terminal of the constant current mode signal, a second input terminal of the third AND gate element is connected to an output terminal of a paraphase signal corresponding to the reference voltage control signal, and an output terminal of the third AND gate element is connected to an enable terminal of the second timer, and the output terminal of the second timer is used as an output terminal of the peak load timing circuit to output the peak load protection restart control signal when the duration of the received enable signal reaches the first threshold.

9. The peak current load control circuit of claim 8.

10. the reference voltage control signals include a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to a middle-high reference voltage, and a fourth control signal corresponding to a middle-low reference voltage, wherein the peak load reference voltage is greater than the middle-high reference voltage, greater than the middle-low reference voltage, and greater than the overcurrent protection reference voltage; Correspondingly, the timing circuit is specifically used to count the peak load duration and the overcurrent protection duration according to the constant current mode signal of the primary side control chip, and output the peak load protection restart control signal when the peak load duration reaches the first threshold, and output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold, wherein the peak load duration is a maintenance time when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode, and the overcurrent protection duration is a maintenance time when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, or when the reference voltage is the middle-low reference voltage, the middle-high reference voltage, or the peak load reference voltage.

8. The peak current load control circuit of claim 7.

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