Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component excellent in mountability and capable of suppressing the occurrence of a short circuit.SOLUTION: The first main surface AA has a first exposed surface F1 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The second main surface AB has a second exposed surface F2 which is a region exposed from the first external electrode 3A and the second external electrode 3B. The rectangular ratio of the first exposed surface F1 when viewed in the lamination direction T is higher than the rectangular ratio of the outer edge of the first external electrode 3A when viewed in the widthwise direction W and higher than the rectangular ratio of the outer edge of the second external electrode 3B when viewed in the widthwise direction W. The rectangular ratio of the second exposed face F2 when viewed in the lamination direction T is higher than the rectangular ratio of the outer edge of the first external electrode 3A when viewed in the widthwise direction W and higher than the rectangular ratio of the outer edge of the second external electrode 3B when viewed in the widthwise direction W.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors have been known as conventional multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end surfaces of the laminate (see, for example, Patent Document 1).

[0003] A challenge facing multilayer ceramic capacitors is how to improve the ease of mounting the capacitors on a substrate. According to Patent Document 1, the ease of mounting the multilayer ceramic capacitors has been improved by improving the mounting agent used during mounting. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-237137 Summary of the Invention [Problem to be solved by the invention]

[0005] However, it is believed that there is room for improvement in the mountability of multilayer ceramic capacitors from the structural aspects of the multilayer ceramic capacitors. Furthermore, when improving the structure of multilayer ceramic capacitors, it is believed that the risk of short circuits occurring should also be taken into consideration.

[0006] An object of the present invention is to provide a multilayer ceramic electronic component that is easy to mount and can suppress the occurrence of short circuits. [Means for solving the problem]

[0007] The present invention provides a multilayer ceramic electronic component comprising: an inner layer portion including alternately stacked ceramic layers and internal electrodes; a pair of outer layer portions sandwiching the inner layer portion in a stacking direction; a laminate having first and second main surfaces opposing each other in the stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first main surface is formed by the first external electrode and the The second main surface has a first exposed surface which is a region exposed from the second external electrode, and the second main surface has a second exposed surface which is a region exposed from the first external electrode and the second external electrode, the rectangularity of the first exposed surface when viewed in the stacking direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction, and the rectangularity of the second exposed surface when viewed in the stacking direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic electronic component that is excellent in mountability and can suppress the occurrence of short circuits. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along a first internal electrode of the multilayer ceramic capacitor. [Figure 5] FIG. 2 is a cross-sectional view taken along a second internal electrode of the multilayer ceramic capacitor. [Figure 6] FIG. 6 is an enlarged view of a portion VI in FIG. 4. [Figure 7] 1 is a plan view of a multilayer ceramic capacitor viewed from a first main surface side in the lamination direction. [Figure 8] 3 is a plan view of the multilayer ceramic capacitor as viewed in the width direction from a first side surface side. FIG. [Figure 9] 3 is a plan view of the multilayer ceramic capacitor viewed from the second main surface side in the lamination direction. FIG. [Figure 10] 4 is a plan view of the multilayer ceramic capacitor as viewed in the width direction from the second side surface side. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described with reference to Figures 1 to 10. The multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic component.

[0011] (Multilayer ceramic capacitor 1) As shown in FIG. 1, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a so-called two-terminal structure. The multilayer ceramic capacitor 1 includes a laminate 2, a first external electrode 3A, and a second external electrode 3B. The laminate 2 is substantially rectangular and has six outer surfaces. The laminate 2 includes an inner layer portion 11 in which dielectric layers 14 serving as ceramic layers and internal electrodes 15 are stacked. The first external electrode 3A and the second external electrode 3B may be collectively referred to as the "external electrodes 3."

[0012] In this specification, the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the length direction L. The direction perpendicular to both the length direction L and the stacking direction T is referred to as the width direction W.

[0013] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T is referred to as the first main surface AA and the second main surface AB, a pair of outer surfaces on both sides in the width direction W is referred to as the first side surface BA and the second side surface BB, and a pair of outer surfaces on both sides in the length direction L is referred to as the first end surface CA and the second end surface CB. The first main surface AA and the second main surface AB may be collectively referred to as "each main surface A." The first side surface BA and the second side surface BB may be collectively referred to as "each side surface B." The first end surface CA and the second end surface CB may be collectively referred to as "each end surface C."

[0014] A cross section parallel to the length direction L and width direction W is referred to as an “LW cross section.” Figures 4 and 5 show LW cross sections along the surface of the internal electrode 15 on the first main surface AA side.

[0015] (Laminate 2) The laminate 2 has an inner layer portion 11 and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T. The portions where three outer surfaces of the laminate 2 intersect are referred to as "corner portions." The portions where two outer surfaces of the laminate 2 intersect are referred to as "ridge portions."

[0016] (Inner layer 11) 2 and 3, the inner layer portion 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0017] The dielectric layer 14 is formed of a dielectric ceramic containing BaTiO as a main component, for example, and may contain a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like as a secondary component.

[0018] The internal electrodes 15 are formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. The internal electrodes 15 include a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. As shown in FIG. 4, the first internal electrodes 15A are exposed only at the first end face CA. As shown in FIG. 5, the second internal electrodes 15B are exposed only at the second end face CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately.

[0019] The first internal electrode 15A has a first opposing portion 15Aa and a first lead portion 15Ab. The first opposing portion 15Aa is a portion of the first internal electrode 15A that faces the second internal electrode 15B adjacent to it in the stacking direction T. The first opposing portion 15Aa is located in the center between the end faces C. The first lead portion 15Ab is a portion of the first internal electrode 15A that is led out from the first opposing portion 15Aa toward the first end face CA. The first lead portion 15Ab is exposed at the first end face CA. The first lead portion 15Ab is connected to the external electrode 3.

[0020] The second internal electrode 15B has a second opposing portion 15Ba and a second lead portion 15Bb. The second opposing portion 15Ba is a portion of the second internal electrode 15B that faces the adjacent first internal electrode 15A (first opposing portion 15Aa). The second opposing portion 15Ba is located in the center between the end faces C. The second lead portion 15Bb is a portion of the second internal electrode 15B that is led out from the second opposing portion 15Ba toward the second end face CB. The second lead portion 15Bb is exposed at the second end face CB. The second lead portion 15Bb is connected to the external electrode 3.

[0021] The first internal electrode 15A and the second internal electrode 15B may be collectively referred to as the "internal electrode 15." The first opposing portion 15Aa and the second opposing portion 15Ba may be collectively referred to as the "opposing portion 15a." The first lead portion 15Ab and the second lead portion 15Bb may be collectively referred to as the "lead portion 15b." A gap V is formed in the internal electrode 15 (see FIG. 6). The gap V is a portion of the internal electrode 15 where no metal is disposed.

[0022] (Outer layer part 12) The outer layer portion 12 is formed of the same material as the dielectric layer 14 of the inner layer portion 11. Note that the outer layer portion 12 does not have an internal electrode 15 disposed thereon.

[0023] (External electrode 3) The first external electrode 3A is provided on the first end face CA. The first external electrode 3A covers not only the first end face CA but also part of the main face A and part of the side face B. The first external electrode 3A is connected to the first internal electrode 15A.

[0024] The second external electrode 3B is provided on the second end face CB. The second external electrode 3B covers not only the second end face CB but also part of the main face A and part of the side face B. The second external electrode 3B is connected to the second internal electrode 15B.

[0025] The external electrodes 3 each include a base electrode layer 31 disposed on the surface of the laminate 2 and a plating layer 32 disposed on the base electrode layer 31 .

[0026] The base electrode layer 31 is a baked layer containing, for example, a conductive metal and glass. The conductive metal is, for example, nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), gold (Au), an Ag-Pd alloy, or the like, and is preferably Cu.

[0027] The plating layer 32 is made of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and Sn, or an alloy containing such a metal. The plating layer 32 includes, for example, a first plating layer 321 disposed on the base electrode layer 31 and a second plating layer 322 disposed on the first plating layer 321.

[0028] The first plating layer 321 is, for example, a Ni plating layer. The second plating layer 322 is, for example, a Sn (tin) plating layer. The plating layer 322 may have a single layer structure.

[0029] As shown in FIGS. 1 and 7 to 10, the first main surface AA has a first exposed surface F1, which is a region exposed by the first external electrode 3A and the second external electrode 3B. The second main surface AB has a second exposed surface F2, which is a region exposed by the first external electrode 3A and the second external electrode 3B. The "rectangle ratio" is the value obtained by dividing the area inside the outline by the area of ​​the rectangle that circumscribes the outline to the smallest extent. The rectangular ratio of the first exposed surface F1 when viewed in the stacking direction T is higher than the rectangular ratio of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangular ratio of the outer edge of the second external electrode 3B when viewed in the width direction W. The rectangular ratio of the second exposed surface F2 when viewed in the stacking direction T is higher than the rectangular ratio of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangular ratio of the outer edge of the second external electrode 3B when viewed in the width direction W.

[0030] 1 and 8, the outer edge of the first external electrode 3A when viewed in the width direction W from the first side face BA side is shown as the "outer edge OWA," and the outer edge of the second external electrode 3B when viewed in the width direction W from the first side face BA side is shown as the "outer edge OWB." In Fig. 8, the rectangle circumscribing the outer edge OWA is shown as the "rectangle E1," and the rectangle circumscribing the outer edge OWB is shown as the "rectangle E2."

[0031] The first side surface BA has a third exposed surface F3 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The second side surface BB has a fourth exposed surface F4 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The rectangularity of the third exposed surface F3 when viewed in the width direction W is higher than the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W. The rectangularity of the fourth exposed surface when viewed in the width direction W is higher than the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W.

[0032] The first exposed surface F1, the second exposed surface F2, the third exposed surface F3, and the fourth exposed surface F4 may be collectively referred to as "exposed surface F."

[0033] The rectangularity of the first exposed surface F1 when viewed in the stacking direction T is higher than the rectangularity of the outer edge of the multilayer ceramic capacitor 1 when viewed in the width direction W. The rectangularity of the second exposed surface F2 when viewed in the stacking direction T is higher than the rectangularity of the outer edge of the multilayer ceramic capacitor 1 when viewed in the width direction W.

[0034] In FIG. 10, a rectangle circumscribing the outer edge of the multilayer ceramic capacitor 1 when viewed in the width direction W from the second side surface BB side is illustrated as a "rectangle E3."

[0035] Of the internal electrode 15, the line coverage of a portion 51A that overlaps with the boundary line (referred to as the "first boundary line 41A") between the first external electrode 3A and the first exposed surface F1 when viewed in the stacking direction T is 70% or less. Of the internal electrode 15, the line coverage of a portion 51B that overlaps with the boundary line (referred to as the "second boundary line 41B") between the second external electrode 3B and the first exposed surface F1 when viewed in the stacking direction T is 70% or less. The line coverage will be described in detail later.

[0036] The first internal electrode 15A overlaps, for example, the first boundary line 41A and the second boundary line 41B. The line coverage of a portion 51A of the first internal electrode 15A that overlaps with the first boundary line 41A when viewed in the stacking direction T is 70% or less. The line coverage of a portion 51B of the first internal electrode 15A that overlaps with the second boundary line 41B when viewed in the stacking direction T is 70% or less.

[0037] The second internal electrode 15B overlaps with, for example, the first boundary line 41A and the second boundary line 41B. The line coverage of a portion 51A of the second internal electrode 15B that overlaps with the first boundary line 41A when viewed in the stacking direction T is 70% or less. The line coverage of a portion 51B of the second internal electrode 15B that overlaps with the second boundary line 41B when viewed in the stacking direction T is 70% or less.

[0038] The first boundary line 41A and the second boundary line 41B may be collectively referred to as the "boundary line 41."

[0039] The surface coverage of the portion of the internal electrode 15 that overlaps with the first external electrode 3A when viewed in the stacking direction T is 70% or less. The surface coverage of the portion of the internal electrode 15 that overlaps with the second external electrode 3B when viewed in the stacking direction T is 70% or less. The surface coverage will be described in detail later.

[0040] The first internal electrode 15A overlaps with, for example, the first external electrode 3A and the second external electrode 3B. The surface coverage of the portion of the first internal electrode 15A that overlaps with the first external electrode 3A when viewed in the stacking direction T is 70% or less. The surface coverage of the portion of the first internal electrode 15A that overlaps with the second external electrode 3B when viewed in the stacking direction T is 70% or less.

[0041] The second internal electrode 15B overlaps with, for example, the first external electrode 3A and the second external electrode 3B. The surface coverage of the portion of the second internal electrode 15B that overlaps with the first external electrode 3A when viewed in the stacking direction T is 70% or less. The surface coverage of the portion of the second internal electrode 15B that overlaps with the second external electrode 3B when viewed in the stacking direction T is 70% or less.

[0042] 4 and 5, the portion of the laminate 2 that overlaps with the first boundary line 41A is indicated by a virtual line 51A, and the portion of the laminate 2 that overlaps with the second boundary line 41B is indicated by a virtual line 51B. The portion of the internal electrode 15 that overlaps with the first external electrode 3A is indicated by a virtual line 52A, and the portion of the internal electrode 15 that overlaps with the second external electrode 3B is indicated by a virtual line 52B.

[0043] The dimension of the multilayer ceramic capacitor 1 in the length direction L is 1 mm or more. The dimension of the multilayer ceramic capacitor 1 in the width direction W is 0.5 mm or more. The dimension of the multilayer ceramic capacitor 1 in the stacking direction T is 0.5 mm or more.

[0044] (Measurement method) Next, the method for measuring each value will be described.

[0045] <External dimensions of laminate> The lengthwise dimension L of the multilayer ceramic capacitor 1, the widthwise dimension W of the multilayer ceramic capacitor 1, and the dimension T of the multilayer ceramic capacitor 1 are each measured using a micrometer.

[0046] <Rectangle ratio> An image of the multilayer ceramic capacitor 1 is obtained using a digital microscope. In the obtained image, the area inside the outline and the area of ​​the rectangle with the smallest area circumscribing the outline are calculated. The rectangularity ratio is calculated based on the obtained area value and the following formula (1).

[0047] Rectangle ratio = (area inside the contour / area of ​​the rectangle circumscribing the contour) (1)

[0048] The rectangularity of the first external electrode 3A as viewed in the width direction W is the average value of the rectangularity of the first external electrode 3A in an image of the multilayer ceramic capacitor 1 viewed in the width direction W from the first side face BA side and the rectangularity of the first external electrode 3A in an image of the multilayer ceramic capacitor 1 viewed in the width direction W from the second side face BB side. The rectangularity of the outer edge of the multilayer ceramic capacitor 1 as viewed in the width direction W is the average value of the rectangularity of the outer edge of the multilayer ceramic capacitor 1 in an image of the multilayer ceramic capacitor 1 viewed in the width direction W from the first side face BA side and the rectangularity of the outer edge of the multilayer ceramic capacitor 1 in an image of the multilayer ceramic capacitor 1 viewed in the width direction W from the second side face BB side.

[0049] <Coverage> The method for measuring the surface coverage and line coverage will be described using the surface coverage and line coverage related to the first internal electrode 15A and the first external electrode 3A as an example.

[0050] <Line Coverage> A method for measuring the line coverage of the portion 51A of the first internal electrode 15A that overlaps with the first boundary line 41A when viewed from the stacking direction T will be described.

[0051] As shown in Fig. 4, the internal electrode 15 closest to the first principal surface AA and the dielectric layer 14 are peeled off by electrolytic peeling to expose the LW cross section where the first internal electrode 15A is exposed. The LW cross section where the first internal electrode 15A is exposed is observed by SEM, and the line coverage of the portion of the first internal electrode 15A that overlaps with the first boundary line 41A is measured. The line coverage indicates the proportion of metal in the portion of the internal electrode that is considered to be a line.

[0052] Three target areas M1A are set as the target areas for measuring line coverage. Each target area M1A is square in shape. Each target area M1A is placed at a position that includes a portion of the first internal electrode 15A that overlaps with the first boundary line 41A. The target areas M1A are placed at equal intervals in the width direction W. The distance between the target areas M1A on both ends in the width direction W and each end of the first internal electrode 15A in the width direction W is set to be the same as the distance between adjacent target areas M1A.

[0053] As shown in Figure 6, within the target area M1A, the length of the line segment of the portion 51A of the first internal electrode 15A that overlaps with the first boundary line 41A (referred to as the "total length within the range") and the length of the portion of the line segment where metal is disposed (referred to as the "length of the metal portion within the range") are measured. The line coverage of the target area M1A is calculated using the following formula (2). Note that the portion of the internal electrode 15 where metal is disposed is the portion of the internal electrode 15 where no void V is formed.

[0054] Line coverage (%) = (length of metal part within range / total length within range) × 100 (2)

[0055] The line coverage of each target area M1A is calculated, and the value obtained by averaging the line coverage of each target area M1A is set as the line coverage of the portion of the first internal electrode 15A that overlaps with the first boundary line 41A.

[0056] <Surface coverage> A method for measuring the surface coverage of the portion of the first internal electrode 15A that overlaps with the first external electrode 3A when viewed from the stacking direction T will be described.

[0057] The LW surface where the first internal electrode 15A is exposed is observed by SEM, and the surface coverage of the portion overlapping with the first external electrode 3A as viewed from the stacking direction T is measured. The surface coverage indicates the proportion of the metal in the region of the internal electrode 15 that is considered to be the surface.

[0058] Three target areas M2A are set as the measurement target areas for surface coverage. Each target area M2A is square in shape. The target areas M2A are arranged at equal intervals in the width direction W. The distance between the target areas M2A on both ends in the width direction W and each end of the first internal electrode 15A in the width direction W is the same as the distance between adjacent target areas M2A. Each target area M2A is arranged at a position where the center in the length direction L of each target area M2A overlaps with the center in the length direction L of the portion of the first internal electrode 15A that overlaps with the first external electrode 3A when viewed in the stacking direction T.

[0059] The area of ​​the target area M2A (referred to as the "total area") and the area of ​​the part of the target area M2A where metal exists (referred to as the "metal part area") are measured. The surface coverage of the target area M2A is calculated using the following formula (3).

[0060] Surface coverage (%) = (metal area / total area) × 100 (3)

[0061] The surface coverage of each target area M2A is calculated. The value obtained by averaging the surface coverage of each target area M2A is set as the surface coverage of the portion of the first internal electrode 15A that overlaps with the first external electrode 3A when viewed from the stacking direction T.

[0062] The line coverage of the portion of the first internal electrode 15A that overlaps with the second boundary line 41B when viewed in the stacking direction T is also measured in the same manner as the line coverage of the portion of the first internal electrode 15A that overlaps with the first boundary line 41A when viewed in the stacking direction T. The surface coverage of the portion of the first internal electrode 15A that overlaps with the second external electrode 3B when viewed in the stacking direction T is also measured in the same manner as the surface coverage of the portion of the first internal electrode 15A that overlaps with the first external electrode 3A when viewed in the stacking direction T.

[0063] The line coverage and surface coverage associated with the second internal electrode 15B are also measured in the same manner as the line coverage and surface coverage associated with the first internal electrode 15A. For example, when measuring the line coverage and surface coverage associated with the second internal electrode 15B and the second external electrode 3B, the LW surface on which the second internal electrode 15B is exposed is exposed, and multiple target areas M1B for measuring the line coverage and multiple target areas M2B for measuring the surface coverage are set on the second internal electrode 15B, as shown in Fig. 5. The line coverage of the portion of the second internal electrode 15B that overlaps with the first boundary line 41A as viewed in the stacking direction T is also measured in the same manner as the line coverage of the portion of the second internal electrode 15B that overlaps with the second boundary line 41B as viewed in the stacking direction T. The surface coverage of the portion of the second internal electrode 15B that overlaps with the first external electrode 3A when viewed in the stacking direction T is also measured in the same manner as the surface coverage of the portion of the second internal electrode 15B that overlaps with the second external electrode 3B when viewed in the stacking direction T.

[0064] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0065] A dielectric sheet for the dielectric layer 14 and a conductive paste for the internal electrode 15 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0066] A conductive paste for the internal electrodes 15 is printed in a predetermined pattern on a dielectric sheet by, for example, screen printing or gravure printing. This prepares a dielectric sheet on which a pattern of the first internal electrode 15A is formed and a dielectric sheet on which a pattern of the second internal electrode 15B is formed. When the printing method is screen printing, the level of coverage of the internal electrodes 15 can be adjusted for each electrode or region by adjusting the mesh used in the screen printing and the film thickness of the conductive paste for the internal electrodes 15. For example, the coverage of the internal electrodes 15 can be increased by adjusting the mesh and increasing the film thickness of the conductive paste for the internal electrodes 15. When the printing method is gravure printing, the level of coverage of the electrodes can be adjusted by adjusting the area and volume of the openings in the gravure plate for each electrode or region. The area and volume of the openings can be adjusted, for example, by laser drawing.

[0067] A predetermined number of dielectric sheets on which no internal electrode patterns are printed are stacked to form the portion that will become the outer layer portion 12 on the first main surface AA side. A dielectric sheet on which a pattern of a first internal electrode 15A and a dielectric sheet on which a pattern of a second internal electrode 15B are printed are stacked in this order on top of that to form the portion that will become the inner layer portion 11. A predetermined number of dielectric sheets on which no internal electrode patterns are printed are stacked on top of this portion that will become the outer layer portion 12 on the second main surface AB side. In this way, a laminated sheet is produced. The laminated sheet is pressed in the stacking direction by means of a hydrostatic press or the like to produce a laminated block.

[0068] Next, the laminated block is cut in the length direction L and the width direction W. By cutting the laminated block to a predetermined size, laminated chips are cut out. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0069] The laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrodes 15, but is preferably 900°C or higher and 1400°C or lower.

[0070] A conductive paste that will become the base electrode layer 31 is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 31 is a baked layer. The conductive paste containing a glass component and a metal is applied to the laminate 2 by a method such as dipping.

[0071] Dipping is performed so that the base electrode layer 31 on the first end face CA side extends from the first end face CA to parts of the first principal face AA and the second principal face AB. Dipping is also performed so that the base electrode layer 31 on the second end face CB side extends from the second end face CB to parts of the first principal face AA and the second principal face AB. Simultaneously, dipping is also performed so that the base electrode layer on the first end face CA side extends to parts of the first side face BA and the second side face BB. Dipping is also performed so that the base electrode layer 31 on the second end face CB side extends to parts of the first side face BA and the second side face BB.

[0072] Here, the edges of the portions of the conductive paste disposed on each of the principal surfaces A and each of the side surfaces B are shaped into straight lines using a blade or the like. This increases the rectangularity ratio of the portions of each of the principal surfaces A and each of the side surfaces B that are not covered by the baked layer. When shaping the edges of the portions of the conductive paste disposed on each of the principal surfaces A and each of the side surfaces B, a blade is pressed against the conductive paste in the length direction L, thereby straightening the edges of the conductive paste and raising the conductive paste. This allows the contour of the base electrode layer 31 to be rounded, thereby further reducing the rectangularity ratio of the base electrode layer 31, which serves as the base of the external electrode 3, when viewed in the width direction W.

[0073] Thereafter, a baking process is performed to form the base electrode layer 31. The baking temperature at this time is preferably 700°C or higher and 950°C or lower. The laminated chip before firing and the conductive paste applied to the laminated chip may be simultaneously fired. In this case, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 14 as the ceramic material to be added. In this case, a conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously baked to form the laminate 2 with the baked layer formed thereon.

[0074] The edges of the base electrode layer 31 located on each of the principal surfaces A and each of the side surfaces B may be filed with a file or the like to form straight lines. This increases the rectangularity of the portions of each of the principal surfaces A and each of the side surfaces B that are not covered by the baked layer. The edges of the base electrode layer 31 may be shaped before or after the baking process, or may be shaped before or after the baking process. The relatively large external dimensions of the multilayer ceramic capacitor 1 make it easier to process the base electrode layer 31.

[0075] Thereafter, a plating layer is formed on the surface of the base electrode layer 31. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0076] In this manner, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0077] (Effects of the embodiment) According to this embodiment, the following effects can be obtained.

[0078] According to this embodiment, the first main surface AA has a first exposed surface F1 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The second main surface AB has a second exposed surface F2 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The rectangularity of the first exposed surface F1 when viewed in the stacking direction T is higher than the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W. The rectangularity of the second exposed surface F2 when viewed in the stacking direction T is higher than the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W.

[0079] According to this configuration, the rectangularity of the external electrodes 3 when viewed in the width direction W is low, making it easier to ensure a space for solder to flow between the external electrodes 3 and the substrate. In addition, the surfaces of the external electrodes 3 can be formed smoothly, making it easier for the solder to wet and rise along the surfaces of the external electrodes 3. Therefore, by reducing the rectangularity of the external electrodes 3 when viewed in the width direction W, it is possible to ensure a shape that makes it easy for the solder to wet and rise. This makes it easier for solder fillets to be properly formed on the external electrodes 3, improving the mountability of the multilayer ceramic capacitor 1.

[0080] By increasing the rectangularity of the exposed surface when viewed in the stacking direction T, it is possible to easily ensure the shortest distance between the first external electrode 3A and the second external electrode 3B, thereby making it possible to prevent short circuits from occurring between the external electrodes 3.

[0081] According to this embodiment, the first side surface BA has a third exposed surface F3 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The second side surface BB has a fourth exposed surface F4 that is a region exposed from the first external electrode 3A and the second external electrode 3B. The rectangularity of the third exposed surface F3 when viewed in the width direction W is higher than the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W. The rectangularity of the fourth exposed surface when viewed in the width direction W is higher than the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W, and is also higher than the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W.

[0082] According to this configuration, by increasing the rectangularity of the third exposed surface F3 or by increasing the rectangularity of the fourth exposed surface F4, it is possible to easily ensure the shortest distance between the external electrodes 3 on each side surface B. This further reduces the occurrence of short circuits. In addition, by decreasing the rectangularity of the outer edge of the first external electrode 3A when viewed in the width direction W or by decreasing the rectangularity of the outer edge of the second external electrode 3B when viewed in the width direction W, it is possible to ensure space between the external electrode 3 and the substrate and form a smooth surface for the external electrode 3. This makes it easier for solder to wet and rise onto the external electrode 3, thereby allowing appropriate formation of solder fillets for the external electrode 3.

[0083] According to this embodiment, the rectangularity ratio of the first exposed surface F1 when viewed in the stacking direction T is higher than the rectangularity ratio of the outer edge of the multilayer ceramic capacitor 1 when viewed in the width direction W. The rectangularity ratio of the second exposed surface F2 when viewed in the stacking direction T is higher than the rectangularity ratio of the outer edge of the multilayer ceramic capacitor 1 when viewed in the width direction W.

[0084] According to this configuration, by increasing the rectangularity of the first exposed surface F1, it is possible to easily ensure the shortest distance between the external electrodes 3. This makes it possible to suppress the occurrence of short circuits between the external electrodes 3. Furthermore, by reducing the rectangularity of the outer edges of the multilayer ceramic capacitor 1 when viewed in the width direction W, it is possible to easily ensure an appropriate space between the laminate 2 and the mounting substrate and to make it easier for solder to wet and rise along the smooth surfaces of the external electrodes 3. This further improves the mountability of the multilayer ceramic capacitor 1.

[0085] According to this embodiment, the line coverage of a portion 51A of the internal electrode 15 that overlaps with the boundary line between the first external electrode 3A and the first exposed surface F1 (i.e., the first boundary line 41A) when viewed in the stacking direction T is 70% or less. The line coverage of a portion 51B of the internal electrode 15 that overlaps with the boundary line between the second external electrode 3B and the first exposed surface F1 (i.e., the second boundary line 41B) when viewed in the stacking direction T is 70% or less.

[0086] Because the first exposed surface F1 has a high degree of rectangularity, the boundary line between the first exposed surface F1 and the external electrode 3 is likely to be linear. If the boundary line between the first exposed surface F1 and the external electrode 3 extends linearly, it is thought that when the multilayer ceramic capacitor 1 is warped, stress is likely to concentrate in a portion of the inside of the laminate 2 that overlaps with the boundary line 41 between the first exposed surface F1 and the external electrode 3 when viewed from the stacking direction T. This could cause delamination or the like in the laminate 2, starting from that portion.

[0087] However, with this configuration, the line coverage of the internal electrodes 15 is set low in the portions of the laminate 2 where stress is likely to concentrate. The lower the line coverage of the internal electrodes 15, the more the adhesive strength between the internal electrodes 15 and the dielectric layers 14 can be improved. This makes it possible to suppress the occurrence of delamination.

[0088] According to this embodiment, the surface coverage of the portion of the internal electrode 15 that overlaps with the first external electrode 3A when viewed in the stacking direction T is 70% or less. The surface coverage of the portion of the internal electrode 15 that overlaps with the second external electrode 3B when viewed in the stacking direction T is 70% or less.

[0089] Because the first exposed surface F1 has a high degree of rectangularity, the boundary line between the first exposed surface and the external electrode 3 tends to be linear. In this case, when the multilayer ceramic capacitor 1 bends, stress tends to concentrate in the area inside the laminate 2 that overlaps with the boundary line 41 as viewed in the stacking direction T, and delamination and other problems are likely to occur starting from this area. However, delamination can be suppressed by reducing the surface coverage of the internal electrodes 15 located in the area that overlaps with the external electrode 3 as viewed in the stacking direction T to 70% or less.

[0090] According to this embodiment, the length of the multilayer ceramic capacitor 1 is 1 mm or more. The width of the multilayer ceramic capacitor 1 is 0.5 mm or more. The dimension of the multilayer ceramic capacitor 1 in the lamination direction is 0.5 mm or more.

[0091] Even in such a large-sized multilayer ceramic capacitor 1, solder fillets can be appropriately formed on the external electrodes 3 to improve mountability, while the shortest distance between the first external electrode 3A and the second external electrode 3B can be secured to prevent short circuits.

[0092] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0093] For example, in the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 14 made of a dielectric ceramic are used as ceramic layers has been described as an example of a multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramic as ceramic layers, thermistors using semiconductor ceramic as ceramic layers, and inductors using magnetic ceramic as ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ceramics such as ferrite.

[0094] The present invention also includes the following combinations:

[0095] <1> a laminate having an inner layer portion including alternately stacked ceramic layers and internal electrodes, a pair of outer layer portions sandwiching the inner layer portion in a stacking direction, a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first main surface has a region exposed from the first external electrode and the second external electrode. the second main surface has a second exposed surface that is a region exposed from the first external electrode and the second external electrode, the rectangularity of the first exposed surface when viewed in the stacking direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction, and the rectangularity of the second exposed surface when viewed in the stacking direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction.

[0096] <2> the first side surface has a third exposed surface which is a region exposed from the first external electrode and the second external electrode, the second side surface has a fourth exposed surface which is a region exposed from the first external electrode and the second external electrode, the rectangularity of the third exposed surface when viewed in the width direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction, the rectangularity of the fourth exposed surface when viewed in the width direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction, <1> The multilayer ceramic electronic component according to claim 1.

[0097] <3> a rectangularity ratio of the first exposed surface when viewed in the stacking direction is higher than a rectangularity ratio of an outer edge of the multilayer ceramic electronic component when viewed in the width direction, and a rectangularity ratio of the second exposed surface when viewed in the stacking direction is higher than a rectangularity ratio of an outer edge of the multilayer ceramic electronic component when viewed in the width direction. <1> or <2> The multilayer ceramic electronic component according to claim 1.

[0098] <4> a line coverage of a portion of the internal electrode that overlaps with a boundary line between the first external electrode and the first exposed surface when viewed in the stacking direction is 70% or less, and a line coverage of a portion of the internal electrode that overlaps with a boundary line between the second external electrode and the first exposed surface when viewed in the stacking direction is 70% or less; <1> ~ <3> 10. The multilayer ceramic electronic component according to claim 9, wherein the multilayer ceramic electronic component is a multilayer ceramic electronic component.

[0099] <5> a surface coverage of a portion of the internal electrode that overlaps with the first external electrode when viewed in the stacking direction is 70% or less, and a surface coverage of a portion of the internal electrode that overlaps with the second external electrode when viewed in the stacking direction is 70% or less; <1> ~ <4> 10. The multilayer ceramic electronic component according to claim 9, wherein the multilayer ceramic electronic component is a multilayer ceramic electronic component.

[0100] <6> the dimension of the multilayer ceramic electronic component in the length direction is 1 mm or more, the dimension of the multilayer ceramic electronic component in the width direction is 0.5 mm or more, and the dimension of the multilayer ceramic electronic component in the stacking direction is 0.5 mm or more; <1> ~ <5> 10. The multilayer ceramic electronic component according to claim 9, wherein the multilayer ceramic electronic component is a multilayer ceramic electronic component. [Explanation of symbols]

[0101] 1. Multilayer ceramic capacitors (multilayer ceramic electronic components) 2. Laminate 3A 1st external electrode 3B 2nd external electrode 10 Effective layer 14 Dielectric layer (ceramic layer) 15 Internal electrode 41A Boundary line between first external electrode and first exposed surface 41B Boundary line between second external electrode and first exposed surface AA First principal surface AB Second principal surface BA 1st side BB 2nd side CA 1st end face CB 2nd end face F1 1st exposed surface F2 2nd exposed surface F3 3rd exposed surface F4 4th exposed surface OWA: Outer edge of the first external electrode 3A when viewed in the width direction W OWB: Outer edge of the second external electrode 3B when viewed in the width direction W

Claims

1. a laminate having an inner layer portion including alternately stacked ceramic layers and internal electrodes, a pair of outer layer portions sandwiching the inner layer portion in a stacking direction, a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; A multilayer ceramic electronic component comprising: the first main surface has a first exposed surface that is a region exposed from the first external electrode and the second external electrode, the second main surface has a second exposed surface that is a region exposed from the first external electrode and the second external electrode, a rectangularity ratio of the first exposed surface when viewed in the stacking direction is higher than a rectangularity ratio of an outer edge of the first external electrode when viewed in the width direction, and is also higher than a rectangularity ratio of an outer edge of the second external electrode when viewed in the width direction; a rectangularity ratio of the second exposed surface when viewed in the stacking direction is higher than a rectangularity ratio of the outer edge of the first external electrode when viewed in the width direction, and is also higher than a rectangularity ratio of the outer edge of the second external electrode when viewed in the width direction.

2. the first side surface has a third exposed surface that is a region exposed from the first external electrode and the second external electrode, the second side surface has a fourth exposed surface that is a region exposed from the first external electrode and the second external electrode, a rectangularity ratio of the third exposed surface when viewed in the width direction is higher than a rectangularity ratio of an outer edge of the first external electrode when viewed in the width direction, and is also higher than a rectangularity ratio of an outer edge of the second external electrode when viewed in the width direction; 2. The multilayer ceramic electronic component according to claim 1, wherein the rectangularity of the fourth exposed surface when viewed in the width direction is higher than the rectangularity of the outer edge of the first external electrode when viewed in the width direction, and is also higher than the rectangularity of the outer edge of the second external electrode when viewed in the width direction.

3. a rectangularity ratio of the first exposed surface when viewed in the stacking direction is higher than a rectangularity ratio of an outer edge of the multilayer ceramic electronic component when viewed in the width direction; 2. The multilayer ceramic electronic component according to claim 1, wherein a rectangularity ratio of the second exposed surface when viewed in the stacking direction is higher than a rectangularity ratio of an outer edge of the multilayer ceramic electronic component when viewed in the width direction.

4. a line coverage of a portion of the internal electrode that overlaps a boundary line between the first external electrode and the first exposed surface as viewed in the stacking direction is 70% or less; 2. The multilayer ceramic electronic component according to claim 1, wherein a line coverage of a portion of the internal electrode that overlaps a boundary line between the second external electrode and the first exposed surface when viewed in the stacking direction is 70% or less.

5. a surface coverage of a portion of the internal electrode that overlaps with the first external electrode when viewed in the stacking direction is 70% or less; 2. The multilayer ceramic electronic component according to claim 1, wherein a surface coverage of a portion of said internal electrodes that overlaps with said second external electrodes when viewed in the stacking direction is 70% or less.

6. the dimension of the multilayer ceramic electronic component in the length direction is 1 mm or more; the dimension of the multilayer ceramic electronic component in the width direction is 0.5 mm or more; 2. The multilayer ceramic electronic component according to claim 1, wherein the dimension of the multilayer ceramic electronic component in the stacking direction is 0.5 mm or more.

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