Parallel inverter device

Abstract

To provide a parallel inverter device operated in parallel capable of substantially equally distributing a load to each inverter circuit without having a common signal line between the inverter circuits.SOLUTION: The parallel inverter device comprises a plurality of inverter circuits connected in parallel, each inverter circuit comprising an output voltage detection circuit for detecting an output voltage of the parallel inverter device, a reactor current detection circuit for detecting a reactor current of an LC filter, a feedback control circuit for controlling the inverter circuit based on a signal of the output voltage and a signal of the reactor current, and a disturbance observer 2 for outputting an estimated value of a load current from values of a current and a voltage for estimating the load current in the feedback control circuit.SELECTED DRAWING: FIG. 2B

Description

[Technical Field]

[0001] The present invention relates to a parallel inverter device that is operated in parallel and can share the load almost equally among the inverter circuits without using a common signal line between the inverter circuits. [Background technology]

[0002] In inverter devices that output AC power, multiple inverter circuits may be connected in parallel to increase output capacity in response to various usage patterns. Connecting inverter circuits in parallel can cause slight variations in the AC voltage magnitude and frequency of each inverter circuit, resulting in current flowing from the output of one inverter circuit to the output of another inverter circuit, creating a problem of cross current (also known as circulating current).

[0003] It has been pointed out that the occurrence of cross currents not only disrupts the load sharing between inverter circuits, resulting in insufficient output capacity and issues with load responsiveness, but also causes large cross currents to flow due to the low output impedance of parallel inverter devices, which has a significant adverse effect on output voltage control characteristics.

[0004] Conventionally, various methods have been proposed to prevent the occurrence of such cross currents (for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6690071 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-102421 [Patent Document 3] Special Publication No. 6-40704 Summary of the Invention [Problem to be solved by the invention]

[0006] To prevent cross currents, one method is to connect the inverter circuits with a common signal line and operate them in parallel, but this poses reliability issues due to timing discrepancies caused by signal delays and noise interference on the common signal line.

[0007] One method for preventing cross current without a common signal line is to insert a bidirectional switch into the inverter output (see, for example, Patent Document 1), but this has the problem of increasing power loss.

[0008] There is a method for preventing cross current without a common signal line by calculating and controlling the phase difference between the output reactive current and the load current (for example, Patent Document 2), but this poses a problem that is difficult to address when the phase of the load current varies.

[0009] One method is to install an output voltage / current sensor for each inverter circuit (for example, Patent Document 3), but there is a problem in that when detecting electrical quantities at the same location, slight errors between the sensors can affect each other's output voltage control.

[0010] The present invention has been made in view of the above circumstances, and provides a parallel inverter device that is operated in parallel and can share the load almost equally among the inverter circuits without having a common signal line between the inverter circuits. [Means for solving the problem]

[0011] In order to solve the above problems, the present invention provides a parallel inverter device that is operated in parallel and can share the load approximately equally among the inverter circuits, the parallel inverter device comprising a plurality of inverter circuits that are each made up of a plurality of semiconductor switches and LC filters and connected in parallel, each of the inverter circuits comprising an output voltage detection circuit that detects the output voltage of the parallel inverter device, a reactor current detection circuit that detects the reactor current of the LC filter, a feedback control circuit that controls the inverter circuits based on a signal of the output voltage and a signal of the reactor current, and a disturbance observer that outputs an estimated value of the load current from current and voltage values ​​to estimate the load current for control of the feedback control circuit.

[0012] In the parallel inverter device according to the present invention, the estimated value of the load current calculated by the load current estimation may be input via a high-pass filter.

[0013] In the parallel inverter device according to the present invention, a PWM output command value of the inverter circuit can be stored when the output voltage is zero, and the PWM command value can be averaged every half cycle to calculate a circulating current compensation value. [Effects of the Invention]

[0014] The parallel inverter device of the present invention solves the problem of reduced reliability by eliminating the need for a common signal line between the inverter circuits, and also realizes parallel operation with excellent load responsiveness while automatically and approximately equalizing the load sharing between the inverter circuits without prior adjustment. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a basic circuit diagram of a parallel inverter device (with two inverter circuits) according to the present embodiment. [Figure 2A] FIG. 1 is a first basic control block diagram of a feedback control circuit in INV1 of the present embodiment. [Figure 2B] FIG. 2 is a diagram showing a second basic control block diagram of a feedback control circuit in INV1 of the present embodiment and a disturbance observer. [Figure 3A] FIG. 1 is a first basic control block diagram of a feedback control circuit in INV2 of the present embodiment. [Figure 3B] FIG. 10 is a diagram showing a second basic control block diagram of a feedback control circuit in INV2 of the present embodiment and a disturbance observer. [Figure 4] FIG. 2 is a diagram illustrating an example of a basic control block diagram of a disturbance observer. [Figure 5] FIG. 2 is a circuit diagram of a resistive load for adjusting an output voltage detection value according to the present embodiment. [Figure 6]FIG. 1 is a basic circuit diagram of a parallel inverter device having three or more inverter circuits. [Figure 7] FIG. 10 is a schematic diagram for explaining a method for calculating a circulating current compensation value. [Figure 8] FIG. 10 is a diagram showing experimental waveforms of the output voltage, output current, and output filter reactor current when switching from parallel operation to single unit operation. [Figure 9] FIG. 10 is a diagram showing experimental waveforms of the output voltage, output current, and output filter reactor current when switching from single-unit operation to parallel operation. [Figure 10] FIG. 10 is a diagram showing waveforms of experimental results of an output voltage, an output current, and an output filter reactor current in the case where circulating current compensation is not performed. [Figure 11] 10A and 10B are diagrams showing waveforms of experimental results of an output voltage, an output current, and an output filter reactor current when circulating current compensation is provided. DETAILED DESCRIPTION OF THE INVENTION

[0016] A preferred embodiment of the parallel inverter device of the present invention will be described below with reference to the drawings. In the following description, for the sake of simplicity, only symbols may be used. Furthermore, for the sake of convenience, different names or simplified names may be used for the same symbols.

[0017] FIG. 1 is a basic circuit diagram of a parallel inverter device 1 of this embodiment. The parallel inverter device 1 of this embodiment includes multiple inverter circuits, but FIG. 1 shows a configuration including two inverter circuits INV1 and INV2. In INV1, multiple semiconductor switches Q1 to Q4 are full-bridge connected, and an LC filter consisting of a filter reactor Lf1 and a filter capacitor Cf1 is connected. In INV2, multiple semiconductor switches Q5 to Q8 are full-bridge connected, and an LC filter consisting of a filter reactor Lf2 and a filter capacitor Cf2 is connected. INV1 and INV2 are connected in parallel with their output sections coupled, and do not have a common signal line connecting the inverter circuits together.

[0018] The control methods for INV1 and INV2 are similar, and the control method for INV1 will be described below with reference to Figures 2A and 2B. The feedback control circuit and disturbance observer 2 for INV2 are shown in Figures 3A and 3B, and their configurations and functions are similar to those of the feedback control circuit and disturbance observer 2 for INV1 shown in Figures 2A and 2B, so their description will be omitted.

[0019] 2A and 2B show the estimated load current io1_est and the output filter capacitor current icf1 calculated based on the disturbance observer 2. * 10 shows the minor loop control of the output filter reactor current iLf1 obtained by the above and the output voltage control by the second controller 4 as the major loop.

[0020] INV1 includes an output voltage detection circuit that detects the output voltage Vo of the parallel inverter device 1 and a reactor current detection circuit that detects the reactor current iLf1 of the LC filter, and a feedback control circuit shown in Figures 2A and 2B controls INV1 based on the output voltage Vo signal and the reactor current iLf1 signal. A disturbance observer 2 estimates the load current from the current and voltage values ​​to control the feedback control circuit.

[0021] The disturbance observer 2 can estimate the load current regardless of the type of disturbance observer used, such as a zero-order disturbance observer, a first-order disturbance observer, a notch-type disturbance observer, an extended disturbance observer that estimates disturbances of periodic functions, or a high-order disturbance observer that takes vibration frequency into account.

[0022] For example, details of the zero-order disturbance observer are described in the reference document below. https: / / web.archive.org / web / 20200323132957id_ / https: / / www.jstage.jst.go.jp / article / sicejl1962 / 39 / 10 / 39_10_608 / _pdf

[0023] Details of the first-order disturbance observer are described in the references listed below. https: / / doi.org / 10.1541 / ieejias.120.382

[0024] Details of the notch-type disturbance observer are described in the references listed below. https: / / doi.org / 10.1541 / ieejjia.5.413

[0025] Details of the extended disturbance observer that estimates disturbances of periodic functions are described in the reference document listed below. https: / / doi.org / 10.1541 / ieejias.134.241

[0026] Details of the high-order disturbance observer that takes vibration frequency into account are described in the reference document listed below. https: / / doi.org / 10.1541 / ieejias.128.948

[0027] In INV1, the desired output voltage Vo * The inverter output filter reactor current command value iLf1 that can be * The actual output filter reactor current iLf1 is controlled by tracking it. In addition, by installing the disturbance observer 2 in INV1, the output current value io1_est that INV1 shares almost equally with INV2 is estimated. * Therefore, the current that should flow through Cf1 is icf1 * It can be calculated as:

[0028] In the minor loop control described above, as shown in Figure 2A, the calculated icf1 * and iLf1 from io1_est estimated by disturbance observer 2 * is calculated and compared with the actual iLf1, and the pulse width command value Vinv1 is calculated to obtain the desired output voltage Vo. However, this alone will cause an error in the output voltage Vo due to an error in the capacitance value of Cf1, an error in the sensor gain of the output current value, etc. Therefore, the output voltage Vo is detected and the output voltage command value Vo *Based on the deviation from iLf1, the second controller 4 is used to * By adjusting the value Vinv1, a pulse width command value Vinv1 for controlling the output voltage Vo to the desired value is obtained.

[0029] To explain the control method of INV1 in more detail, first, in order for the output voltage at no load to become the desired output voltage Vo, if the capacitance of Cf1 is known, then the ICF1 flowing through Cf1 * Next, assuming that the output current io1 can be detected, the output filter reactor current iLf1 * The calculated iLf1 can be calculated. * By using the first controller 3 to follow and control the actual output filter reactor current iLf1, the output voltage Vo is ideally controlled to match the desired output voltage command value Vo * However, an error occurs in the output voltage Vo due to an error in the capacitance value of Cf1, an error in the sensor gain of the output current value, etc. Therefore, the output voltage Vo is detected and the output voltage command value Vo * Based on the deviation from iLf1, the second controller 4 is used to * By adjusting this, the pulse width command value Vinv1 for controlling the output voltage Vo to the desired value is obtained. However, since the output current io1 cannot (is not) actually be detected, the io1_est estimated by the disturbance observer 2 is used as io1.

[0030] The control by the first controller 3 and the second controller 4 can be, for example, PI control, PID control, P control or IP control.

[0031] Because the output voltages Vo of multiple inverter circuits must operate in sync, each inverter circuit determines whether a specified sine wave is detected at its output during startup. If a specified sine wave is detected, it synchronizes with the waveform and outputs an in-phase output voltage. If no specified sine wave is detected, it outputs its own output voltage. Even if multiple inverter circuits have the same output voltage Vo, even a slight voltage difference can cause a circulating current containing a DC component to flow between the inverter circuits. If this DC component is included in the disturbance observer 2, it is amplified and can cause cross currents. Therefore, by inputting io1_est through a high-pass filter 5, the DC component that causes cross currents between the inverter circuits is attenuated by the high-pass filter 5, resulting in a highly stable output voltage Vo.

[0032] As an example of a method for calculating the estimated load current io1_est by the disturbance observer 2, a method using a zero-order disturbance observer will be described.

[0033] First, the load current io1 is calculated by the following equation (1).

[0034]

number

[0035] However, the second term on the right-hand side contains a differential element, which induces instability. Therefore, we transform it into the following equation (2) and apply inexact differentiation using a first-order lag element (first-order lag filter). Multiplying both sides of equation (1) by a first-order lag element (equivalent to a low-pass filter) expressed as transfer function G(s) = gdis / (s + gdis) gives us the following equation (2).

[0036]

number

[0037] Here, (gdis / (s+gdis))·io1 on the left-hand side is the load current value that has passed through a first-order lag element, and can be thought of as the estimated load current io1_est, which is the load current that has passed through a low-pass filter. However, if equation (2) is left as is, the second term on the right-hand side contains a differential term, which can lead to instability, so it must be transformed into the following equation (3).

[0038]

number

[0039] Equation (3) does not include a differential term, which can prevent instability. As a result, the estimated load current io1_est can be calculated as shown in the block diagram of the disturbance observer 2 in Figure 4.

[0040] In a parallel configuration of parallel inverter devices, if an error occurs in the same output voltage Vo detected by multiple inverter circuits, it can cause cross currents to flow between the inverter circuits. The output voltage Vo value of each inverter circuit varies depending on the inverter circuit due to variations in the detection circuits and elements, so measures must be taken to make the values ​​as uniform as possible. The following methods can be used to match the output voltage detection values ​​of the two inverter circuits, INV1 and INV2.

[0041] When INV1 detects a predetermined reference voltage Vos (V) determined as the output voltage, INV1 connects the resistive load 11 for adjusting the output voltage detection value (shown in Figure 5) to the parallel inverter device 1 for a short period of time ts (sec), causing a pulsed load current to flow after the LC filter of each inverter circuit. When INV2 detects the pulsed load current, the sampled value is redefined as Vos (V) and the output voltage detection value of INV2 is reset. This operating mode makes it possible to adjust for variations in the output voltage detection value of each inverter circuit.

[0042] More specifically, the AC terminals a and b connected to the rectifier element 16 in FIG. 5 are connected to the output terminals of INV1 (both ends of Cf1 in FIG. 1 ). The control terminal 13 of the load resistor connection switch element 12 is connected via a current-limiting resistor 14 to a gate driver (not shown) for adjusting the output voltage detection value of the INV1 control microcomputer. The load resistor 15 serves as a current-limiting resistor when a pulsed load current of approximately several hundred microseconds flows. If the load resistor 15 is always connected, losses will occur in the load resistor 15, reducing the efficiency of INV1. Therefore, the load resistor connection switch element 12 connects the load resistor 15 only when necessary, for approximately several hundred microseconds. The load resistor connection switch element 12 is normally turned off to disconnect the load resistor 15. To easily control the load resistor connection switch element 12, the circuit of the output voltage detection value adjustment resistor load 11 must be a DC circuit. Therefore, the rectifier element 16 converts the AC output of INV1 to DC.

[0043] Although FIG. 1 shows an example in which there are two inverter circuits, when three or more inverter circuits are provided, they can be connected as shown in FIG.

[0044] The following means are available as a circulating current compensation method for suppressing circulating current.

[0045] When the output voltage Vo is zero, the PWM output command values ​​Va and Vb of the inverter circuits INV1 and INV2 are saved, and the PWM command values ​​Va and Vb are averaged every half cycle to calculate the circulating current compensation value Vcom. The calculated circulating current compensation value Vcom is then subtracted from the PWM output command value. In the case of Figure 7(a), Va = 2, Vb = -2, and Vcom = 0, meaning no circulating current is occurring. As in Figure 7(b), when Va = 4, Vb = 0, and a command is issued to generate a circulating current in the positive direction, Vcom = 2 is subtracted from the command to compensate. Note that the circulating current compensation value Vcom is a DC component. [Example]

[0046] The results of an experiment using the parallel inverter device 1 of this embodiment will be described. The experiment was performed using DSP control with a sampling frequency of 10 kHz, and the DC voltage Vdc was 200 V and Vo * = 100Vrms, resistive load.

[0047] Figures 8 and 9 show the output waveforms when switching between parallel operation and single unit operation. Prior to the experiment, the output voltage sensor gain of each inverter circuit was adjusted. Parallel operation and single unit operation were switched simply by disconnecting and connecting the parallel connection terminals, with no other control signals being given for switching operation. It was confirmed that each inverter circuit automatically achieved approximately equal load sharing while maintaining a constant output voltage according to the operating conditions, and that the load current shared by each inverter circuit was calculated appropriately. It was also confirmed that there was almost no transient phenomenon related to the sharing ratio when changing the load sharing (switching between single unit operation and parallel operation), and that high-speed response was possible.

[0048] Fig. 10 shows the output waveform without circulating current compensation, and Fig. 11 shows the output waveform with circulating current compensation. An error of 5% was applied to the output voltage sensor gain. Without circulating current compensation, a DC component, which is a circulating current, immediately flows in the reactor current, causing instability, and the impact of this increases. On the other hand, with circulating current compensation, compensation ensures a stable output waveform, and it was confirmed that the load is shared almost equally between each inverter circuit.

[0049] As described above, the parallel inverter device 1 of this embodiment is a parallel inverter device 1 operated in parallel so that the load can be shared approximately equally among the inverter circuits, and includes a plurality of inverter circuits INV1, INV2 each consisting of a plurality of semiconductor switches Q1 to Q4, Q5 to Q8 and an LC filter, and connected in parallel. Each of the inverter circuits INV1, INV2 includes an output voltage detection circuit that detects the output voltage Vo of the parallel inverter device 1, a reactor current detection circuit that detects the reactor currents iLf1, iLf2 of the LC filter, a feedback control circuit that controls the inverter circuits INV1, INV2 based on a signal of the output voltage Vo and signals of the reactor currents iLf1, iLf2, and a disturbance observer 2 that outputs load current estimates io1_est, io2_est from current and voltage values ​​to estimate the load current for control of the feedback control circuit.

[0050] In this case, the problem of reduced reliability is solved by eliminating the need for a common signal line between the inverter circuits, and parallel operation with excellent load response can be achieved while automatically and approximately equalizing the load sharing between the inverter circuits without prior adjustment.

[0051] Furthermore, the parallel inverter device 1 of this embodiment receives the load current estimates Io1_est and Io2_est calculated by load current estimation via a high-pass filter 5 .

[0052] In this case, by attenuating the DC component that causes a cross current component between the inverter circuits with the high-pass filter 5, it is possible to obtain a highly stable output voltage Vo.

[0053] In addition, the parallel inverter device 1 of this embodiment stores the PWM output command values ​​Va and Vb of the inverter circuits INV1 and INV2 when the output voltage Vo is zero, and calculates the circulating current compensation value Vcom by averaging the PWM command values ​​Va and Vb every half cycle.

[0054] In this case, by performing circulating current compensation, a stable output waveform can be ensured, and the load can be shared among the inverter circuits almost equally.

[0055] Although the present invention has been described above based on the embodiments and examples, the present invention can be embodied in various modifications. [Explanation of symbols]

[0056] 1 Parallel inverter device 2. Disturbance observer 3 First Controller 4 Second Controller 5 High-pass filter 11 Resistive load for adjusting output voltage detection value 12 Switch element for connecting load resistor 13 Control terminal 14 Current limiting resistor 15 Load Resistance 16 Rectifying element INV1, INV2 inverter circuit Q1~Q8 Semiconductor switches Lf1, Lf2 filter reactor Cf1, Cf2 filter capacitors Vo output voltage Vo * Output voltage command value io1, io2 Output current (load current) io1_est, io2_est Estimated load current (estimated value of load current) iLf1, iLf2, iLf1 * , iLf1 ** , iLf2 * , iLf2 ** (Output filter) Reactor current icf1, icf2, icf1 * , icf2 * (Output filter) Capacitor current Vinv1, Vinv2 pulse width command value Va, Vb PWM output command value when output voltage Vo is zero Vcom circulating current compensation value

Claims

1. A parallel inverter device that is operated in parallel and can share the load approximately equally among the inverter circuits, a plurality of inverter circuits each consisting of a plurality of semiconductor switches and an LC filter, and connected in parallel; Each of the inverter circuits is an output voltage detection circuit for detecting an output voltage of the parallel inverter device; a reactor current detection circuit for detecting a reactor current of the LC filter; a feedback control circuit that controls the inverter circuit based on a signal of the output voltage and a signal of the reactor current; a disturbance observer for outputting an estimated value of a load current from current and voltage values, for estimating a load current for control of the feedback control circuit; A parallel inverter device comprising:

2. 2. The parallel inverter device according to claim 1, wherein the estimated value of the load current calculated by the load current estimation is input via a high-pass filter.

3. 2. The parallel inverter device according to claim 1, wherein a PWM output command value of the inverter circuit is stored when the output voltage is zero, and the PWM command value is averaged every half cycle to calculate a circulating current compensation value.

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