Memory device

Abstract

To provide a storage device having a long lifespan. [Solution] The memory cell includes a magnetoresistive element and a switching element connected to the magnetoresistive element. The operation of setting the magnetoresistive element to a first resistance state includes a first period, a second period after the first period, a third period after the second period, a fourth period after the third period, and a fifth period after the fourth period. In the first period, a first operation is performed to set the magnetoresistive element to a second resistance state exhibiting a lower resistance than the first resistance state. In the second period, first data is acquired based on the resistance state of the magnetoresistive element. In the third period, a second operation is performed to set the magnetoresistive element to the first resistance state. In the fourth period, second data is acquired based on the resistance state of the magnetoresistive element. In the fifth period, a third operation is performed to set the magnetoresistive element to the first resistance state.

Description

[Technical Field]

[0001] FIELD Embodiments generally relate to storage devices. [Background technology]

[0002] 2. Description of the Related Art Storage devices using magnetoresistive elements are known, and are required to have a long life. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0106886 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a storage device having a long lifespan. [Means for solving the problem]

[0005] A memory device according to one embodiment includes a memory cell, a first wiring connected to a first end of the memory cell, and a second wiring connected to a second end of the memory cell. The memory cell includes a magnetoresistive element and a switching element connected to the magnetoresistive element. The first wiring is connected to the first end of the memory cell. The second wiring is connected to the second end of the memory cell. The operation of setting the magnetoresistive element to a first resistance state includes a first period, a second period after the first period, a third period after the second period, a fourth period after the third period, and a fifth period after the fourth period. During the first period, a first operation is performed to set the magnetoresistive element to a second resistance state exhibiting a lower resistance than the first resistance state. During the second period, first data is acquired based on the resistance state of the magnetoresistive element. During the third period, a second operation is performed to set the magnetoresistive element to the first resistance state. During the fourth period, second data is acquired based on the resistance state of the magnetoresistive element. In the fifth period, a third operation is performed to set the magnetoresistive element in the first resistance state. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 shows functional blocks of a storage device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a memory cell array of the memory device of the first embodiment. [Figure 3] FIG. 3 is a perspective view of a part of the memory cell array of the memory device of the first embodiment. [Figure 4] FIG. 4 shows a cross section of an example of the structure of a memory cell in the memory device of the first embodiment. [Figure 5] FIG. 5 shows an example of the voltage and current characteristics of the memory cell of the memory device of the first embodiment. [Figure 6] FIG. 6 shows some functional blocks and components of the storage device of the first embodiment. [Figure 7] FIG. 7 shows an example of components and connections of the components in the read circuit of the storage device of the first embodiment. [Figure 8]FIG. 8 shows an example of components and connections of the components in the write circuit of the storage device of the first embodiment. [Figure 9] FIG. 9 shows the flow of data writing in the storage device of the first embodiment. [Figure 10] FIG. 10 shows an example of the magnitude of the current flowing through the memory cell over time during AP writing in the memory device of the first embodiment. [Figure 11] FIG. 11 shows a first example of components and connections of the components of the current adjustment circuit of the memory device of the second embodiment. [Figure 12] FIG. 12 shows a second example of components and connections of the components of the current adjustment circuit of the memory device of the second embodiment. [Figure 13] FIG. 13 shows a second example of components and connections of the components of the current adjustment circuit of the memory device of the second embodiment. [Figure 14] FIG. 14 shows the potentials of several nodes over time during data reading from the memory device of the second embodiment. [Figure 15] FIG. 15 shows the flow of data writing in the storage device of the second embodiment. [Figure 16] FIG. 16 shows an example of the magnitude of the current flowing through the memory cell over time during AP writing in the memory device of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In some embodiments or different embodiments, components having substantially the same functions and configurations may be distinguished from one another by adding an additional number or letter to the end of the reference numeral. In the embodiment following a certain described embodiment, differences from the described embodiment will be mainly described. All descriptions of one embodiment also apply to descriptions of other embodiments, unless explicitly or obviously excluded.

[0008] It is not essential that each functional block be distinguished as in the following example. Some functions may be performed by a functional block different from the illustrated functional block, or may be divided into smaller functional subblocks.

[0009] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is always or selectively conductive.

[0010] Hereinafter, embodiments will be described using a three-dimensional Cartesian coordinate system. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, with up pointing toward the Z direction. The direction opposite to the Z direction is referred to as the -Z direction.

[0011] 1. First embodiment 1.1.Configuration (Structure) FIG. 1 shows functional blocks of a magnetic memory device according to a first embodiment. The memory device 1 is a device for storing data. The memory device 1 is a magnetic memory device that stores data using a stack of magnetic materials exhibiting variable resistance. As shown in FIG. 1, the memory device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0012] The memory cell array 11 is a collection of a plurality of arranged memory cells MC. The memory cells MC can store data in a non-volatile manner. A plurality of word lines WL and a plurality of bit lines BL are located in the memory cell array 11. Each memory cell MC is connected to one word line WL and one bit line BL. The word lines WL are associated with rows. The bit lines BL are associated with columns. One memory cell MC is specified by selecting one row and one column.

[0013] The input / output circuit 12 is a circuit that inputs and outputs data and signals. The input / output circuit 12 receives a control signal CNT, a command CMD, address information ADD, and data DAT from outside the memory device 1, for example, from a memory controller. The input / output circuit 12 outputs the data DAT. When data is written to the memory device 1, the data DAT is write data. When data is read from the memory device 1, the data DAT is read data.

[0014] The voltage generation circuit 18 is a circuit that generates voltages of various magnitudes from voltages received from outside the memory device 1. The voltages received from outside include a power supply voltage VDD and a ground voltage VSS. The voltage generation circuit 18 outputs a voltage of a fixed magnitude that is used for reading data. The voltage generation circuit 18 outputs a voltage of a fixed magnitude that is used for writing data.

[0015] The write circuit 16 is a circuit that controls writing of data to the memory cells MC. It receives write data DAT from the input / output circuit 12 and a voltage for data writing from the voltage generation circuit 18. The write circuit 16 outputs a voltage and current used for data writing based on the control of the control circuit 13 and the write data DAT.

[0016] The read circuit 17 is a circuit that controls the reading of data from the memory cells MC. The read circuit 17 receives a voltage for data reading from the voltage generating circuit 18. Under the control of the control circuit 13, the read circuit 17 determines the data held in the memory cells MC using the voltage used for data reading. The determined data is supplied to the input / output circuit 12 as read data DAT. The read circuit 17 includes a sense amplifier.

[0017] The row selection circuit 14 is a circuit that selects a row of memory cells MC. The row selection circuit 14 receives address information ADD from the input / output circuit 12. The row selection circuit 14 receives a voltage for data writing from the write circuit 16. The row selection circuit 14 receives a voltage for data reading from the read circuit 17. During data writing, the row selection circuit 14 uses the voltage for data writing to select one or more word lines WL associated with the row specified by the received address information ADD. During data reading, the row selection circuit 14 uses the voltage for data reading to select one or more word lines WL associated with the row specified by the received address information ADD.

[0018] The column selection circuit 15 is a circuit that selects a column of memory cells MC. The column selection circuit 15 receives address information ADD from the input / output circuit 12. The column selection circuit 15 receives a voltage for data writing from the write circuit 16. The column selection circuit 15 receives a voltage for data reading from the read circuit 17. During data writing, the column selection circuit 15 uses the voltage for data writing to select one or more bit lines BL associated with the column identified by the received address information ADD. During data reading, the column selection circuit 15 uses the voltage for data reading to select one or more bit lines BL associated with the column identified by the received address information ADD.

[0019] The control circuit 13 is a circuit that controls the operation of the memory device 1. The control circuit 13 receives a control signal CNT and a command CMD from the input / output circuit 12. The control circuit 13 controls the write circuit 16 and the read circuit 17 based on the control indicated by the control signal CNT and the command CMD. Specifically, the control circuit 13 controls the write circuit 16 to supply the voltage received by the write circuit 16 from the voltage generation circuit 18 to the row selection circuit 14 and the column selection circuit 15 while writing data to the memory cell MC. The control circuit 13 controls the read circuit 17 to supply the voltage received by the read circuit 17 from the voltage generation circuit 18 to the row selection circuit 14 and the column selection circuit 15 while reading data from the memory cell MC.

[0020] 2 is a circuit diagram of a memory cell array of the memory device of Embodiment 1. As shown in Fig. 2, M+1 (M is a positive integer) word lines WL (WL_0, WL_1, ..., WL_M) and N+1 (N is a positive integer) bit lines BL (BL_0, BL_1, ..., BL_N) are located in the memory cell array 11.

[0021] Each memory cell MC is connected to one word line WL and one bit line BL. Each memory cell MC includes one MTJ element MTJ and one switching element SE. In each memory cell MC, the MTJ element MTJ and the switching element SE are connected in series. The switching element SE of each memory cell MC is connected to one word line WL. The MTJ element MTJ of each memory cell MC is connected to one bit line BL.

[0022] The MTJ element MTJ is an element that exhibits a tunnel magnetoresistance effect and includes, for example, a magnetic tunnel junction (MTJ). The MTJ element MTJ is also called a magnetoresistance effect element MTJ. The MTJ element MTJ is a variable resistance element that can be switched between a low resistance state and a high resistance state. The MTJ element MTJ can store one bit of data by utilizing the difference between two resistance states. In one example, the MTJ element MTJ stores data "0" in a low resistance state and data "1" in a high resistance state. The following description is based on this example.

[0023] The switching element SE is an element that electrically connects or disconnects both ends of itself. The switching element SE has two terminals. When the voltage applied between the two terminals is less than a first threshold, the switching element SE is in a high-resistance state, e.g., an electrically non-conductive state (off state). When the voltage applied between the two terminals increases and becomes equal to or greater than the first threshold, the switching element SE changes to a low-resistance state, e.g., an electrically conductive state (on state). When the voltage applied between the two terminals of the switching element SE in the low-resistance state decreases and becomes equal to or less than a second threshold, the switching element SE changes to a high-resistance state. The switching element SE has the same function of switching between the high-resistance state and the low-resistance state based on the magnitude of the voltage applied in the first direction, but also in a second direction opposite to the first direction. In other words, the switching element SE is a bidirectional switching element. Depending on the on or off state of the switching element SE, it is possible to control whether or not a current is supplied to the MTJ element MTJ connected to the switching element SE, i.e., to select or deselect the MTJ element MTJ.

[0024] 3 is a perspective view of a portion of the memory cell array of the memory device of Embodiment 1. As shown in FIG. 3, a plurality of conductors 21 and a plurality of conductors 22 are provided.

[0025] The conductors 21 have a linear shape, extend in the X direction, and are aligned in the Y direction. Each conductor 21 functions as one word line WL.

[0026] The conductor 22 is located in the Z direction from the conductor 21. The conductors 22 have a linear shape, extend in the Y direction, and are aligned in the X direction. Each conductor 22 functions as one bit line BL.

[0027] One memory cell MC is provided at each intersection of the conductor 21 and the conductor 22. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as the switching element SE and the structure that functions as the MTJ element MTJ each include one or more layers. In one example, the structure that functions as the MTJ element MTJ is located on the upper surface of the structure that functions as the switching element SE. The lower surface of the memory cell MC is in contact with the upper surface of one of the conductors 21. The upper surface of the memory cell MC is in contact with the lower surface of one of the conductors 22.

[0028] FIG. 4 shows a cross-section of an example of the structure of a memory cell of the memory device of the first embodiment. As shown in FIG. 4, the switching element SE includes a variable resistance material 25. The variable resistance material 25 is a material that exhibits dynamically variable resistance and has, for example, a layer shape. The variable resistance material 25 is a two-terminal switching element, with a first terminal being one of the upper and lower surfaces of the variable resistance material 25 and a second terminal being the other of the upper and lower surfaces of the variable resistance material 25. When the voltage applied between the two terminals is less than a first threshold (threshold voltage Vth), the variable resistance material is in a "high resistance" state, e.g., an electrically non-conductive state. When the voltage applied between the two terminals increases and becomes equal to or greater than the first threshold, the variable resistance material changes to a "low resistance" state, e.g., an electrically conductive state. When the voltage applied between the two terminals of the variable resistance material 25 in the low resistance state decreases and becomes equal to or less than a second threshold, the variable resistance material changes to a high resistance state. The variable resistance material 25 includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator includes, for example, an oxide, such as SiO2 or a material substantially consisting of SiO2. The dopant includes, for example, arsenic (As) or germanium (Ge). Note that in this embodiment, the variable resistance material 25 is described as having the above-mentioned composition, but is not limited to this composition. The phrase "substantially consists (or consists of)" and similar phrases mean that the constituent element "substantially consists of" is allowed to contain unintentional impurities.

[0029] The switching element SE may further include a lower electrode 24 and an upper electrode 26. Figure 4 shows such an example. A variable resistance material 25 is located on the upper surface of the lower electrode 24, and the upper electrode 26 is located on the upper surface of the variable resistance material 25.

[0030] The MTJ element MTJ includes a ferromagnetic layer 27, an insulating layer 28, and a ferromagnetic layer 29. For example, as shown in FIG. 4, the insulating layer 28 is located on the upper surface of the ferromagnetic layer 27, and the ferromagnetic layer 29 is located on the upper surface of the insulating layer 28.

[0031] The ferromagnetic layer 27 is a layer of a material exhibiting ferromagnetism. The ferromagnetic layer 27 has an easy axis of magnetization that runs through the interfaces between the ferromagnetic layer 27, the insulating layer 28, and the ferromagnetic layer 29. For example, the easy axis of magnetization is at an angle of 45° to 90° with respect to the interfaces, for example, the easy axis of magnetization runs in a direction perpendicular to the interfaces. The magnetization direction of the ferromagnetic layer 27 is intended to remain unchanged even when data is read or written to the memory cell MC. The ferromagnetic layer 27 can function as a so-called reference layer. The ferromagnetic layer 27 may include multiple layers. Hereinafter, the ferromagnetic layer 27 may also be referred to as the reference layer 27.

[0032] The insulating layer 28 is a layer of an insulator. The insulating layer 28 contains, for example, magnesium oxide (MgO) or is substantially made of MgO, and functions as a so-called tunnel barrier.

[0033] The ferromagnetic layer 29 is a layer of a material exhibiting ferromagnetism. The ferromagnetic layer 29 includes, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is essentially composed of CoFeB or FeB. The ferromagnetic layer 29 has an easy axis of magnetization that runs through the interfaces of the ferromagnetic layer 27, the insulating layer 28, and the ferromagnetic layer 29. For example, the easy axis of magnetization is at an angle of 45° to 90° with respect to the interface, and for example, the easy axis of magnetization runs in a direction perpendicular to the interface. The magnetization direction of the ferromagnetic layer 29 is changeable by writing data to the memory cell MC, and the ferromagnetic layer 29 can function as a so-called memory layer. Hereinafter, the ferromagnetic layer 29 may be referred to as a memory layer 29.

[0034] When the magnetization direction of the memory layer 29 is parallel to the magnetization direction of the reference layer 27, the MTJ element MTJ has a low resistance. When the magnetization direction of the memory layer 29 is antiparallel to the magnetization direction of the reference layer 27, the MTJ element MTJ has a resistance higher than the resistance when the magnetization directions of the memory layer 29 and the reference layer 27 are antiparallel. Hereinafter, a state in which the magnetization direction of the ferromagnetic layer 29 of a certain MTJ element MTJ is parallel to the magnetization direction of the reference layer 27 may be referred to as the MTJ element MTJ being in a "parallel state" or a "P state." A state in which the magnetization direction of the ferromagnetic layer 29 of a certain MTJ element MTJ is antiparallel to the magnetization direction of the reference layer 27 may be referred to as the MTJ element MTJ being in an "antiparallel state" or an "AP state."

[0035] When a current of a certain magnitude or more, Icp, flows from the memory layer 29 to the reference layer 27, the magnetization direction of the memory layer 29 becomes parallel to the magnetization direction of the reference layer 27. The operation of changing the MTJ element MTJ to a parallel state is sometimes referred to as a “P write.” Because the reversal of the magnetization direction is a phenomenon that occurs depending on probability, in one example, a P write current Iwp larger than the current Icp can be passed through the MTJ element MTJ to change the MTJ element MTJ to a parallel state with a margin. The P write current Iwp is larger than the read current Ir. Because the reversal of the magnetization direction is a phenomenon that occurs depending on probability, even if a current smaller than the P write current Iwp is passed from the memory layer 29 to the reference layer 27, there is a possibility that the MTJ element MTJ will change from an antiparallel state to a parallel state.

[0036] When a current of a certain magnitude or more, Icap, flows from the reference layer 27 to the memory layer 29, the magnetization direction of the memory layer 29 becomes antiparallel to the magnetization direction of the reference layer 27. The current Icap is larger than the current Icp. The operation for turning the MTJ element MTJ into the antiparallel state is sometimes called "AP write." As with P write, in one example, to allow for a margin and turn the MTJ element MTJ into the antiparallel state, an AP write current Iwap larger than the current Icap is passed through the MTJ element MTJ. The AP write current Iwap is larger than the P write current Iwp. Because magnetization reversal is a phenomenon that occurs depending on probability, even if a current smaller than the AP write current Iwap flows from the reference layer 27 to the memory layer 29, the MTJ element MTJ may change from the parallel state to the antiparallel state.

[0037] The MTJ element MTJ may include further layers.

[0038] FIG. 5 shows an example of the voltage and current characteristics of a memory cell in the memory device of the first embodiment. The horizontal axis of the graph indicates the magnitude of the terminal voltage of the memory cell MC (i.e., the difference in potential between both ends). The vertical axis of the graph indicates the magnitude of the current flowing through the memory cell MC on a logarithmic scale. FIG. 5 shows hypothetical characteristics that do not actually appear using dashed lines. FIG. 5 shows the cases when the memory cell MC is in a low resistance state and a high resistance state.

[0039] When the voltage is increased from 0, the current continues to increase until it reaches the threshold voltage Vth. Until the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is off, that is, non-conductive.

[0040] When the voltage is further increased and reaches the threshold voltage Vth, i.e., point A, the relationship between voltage and current shows a discontinuous change, exhibiting the characteristics shown at points B1 and B2. The magnitude of the current at points B1 and B2 is significantly larger than the magnitude of the current at point A. This sudden change in current is due to the switching element SE of the memory cell MC being turned on. The magnitude of the current at points B1 and B2 depends on the resistance state of the MTJ element MTJ of the memory cell MC.

[0041] When the voltage is reduced from a state in which the switching element SE is on, for example, a state in which the voltage and current show the relationship shown at point B1 or point B2 and points with higher voltages than these, the current continues to decrease.

[0042] When the voltage is further reduced and reaches a certain magnitude, the voltage-current relationship shows a discontinuous change. The voltage at which the voltage-current relationship begins to show a discontinuity depends on the terminal voltage of the MTJ element MTJ of the memory cell MC, i.e., on whether the MTJ element MTJ is in a high-resistance state or a low-resistance state. When the MTJ element MTJ is in a low-resistance state, the voltage-current relationship shows a discontinuity from point C1. When the MTJ element MTJ is in a high-resistance state, the voltage-current relationship shows a discontinuity from point C2. When the voltage-current relationship reaches points C1 and C2, it begins to show the characteristics shown by points D1 and D2, respectively. The magnitudes of the current at points D1 and D2 are significantly smaller than the magnitudes of the current at points C1 and C2, respectively. This sudden change in current is due to the switching element SE of the memory cell MC being turned off.

[0043] The terminal voltage at point D1 of the memory cell MC including the MTJ element MTJ in the low resistance state is referred to as a low hold voltage VhdL, and the terminal voltage at point D2 of the memory cell MC including the MTJ element MTJ in the high resistance state is referred to as a high hold voltage VhdH.

[0044] 6 shows some functional blocks and components of the memory device of the first embodiment. As shown in FIG. 6, the write circuit 16 is connected to the global word lines GWL and the global bit lines GBL. The read circuit 17 is connected to the global word lines GWL and the global bit lines GBL.

[0045] The global word line GWL is connected to a row selection circuit 14. The row selection circuit 14 connects the global word line GWL to one word line WL specified by address information ADD.

[0046] The global bit line GBL is connected to a column selection circuit 15. The column selection circuit 15 connects the global bit line GBL to one bit line BL specified by address information ADD.

[0047] 7 shows an example of components and connections of the components in the read circuit of the memory device of the first embodiment. As shown in FIG. 7, the read circuit 17 includes a read control circuit 31, a read current circuit 32, a current sink circuit 33, a connection circuit 36, charge storage circuits 37 and 38, and a sense amplifier circuit 39.

[0048] The read current circuit 32 is a circuit that supplies a current to a current path including the connected wiring. The read current circuit 32 is connected to the global bit line GBL and can supply a read current Ir of a fixed magnitude to the current path including the global bit line GBL. The read current circuit 32 operates under the control of the read control circuit 31 and is enabled or disabled under the control of the read control circuit 31. The read current circuit 32 supplies the read current Ir to the global bit line GBL for a dynamically variable period based on the control of the read control circuit 31. In one example, the read current circuit 32 includes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected between a high-potential node and the global bit line GBL. In this example, the transistor receives a voltage from the read control circuit 31 at its gate. The voltage controls the magnitude of the read current Ir. The high-potential node receives a power supply voltage VDD or an internal power supply voltage generated by the voltage generation circuit 18.

[0049] The current sink circuit 33 is a circuit that sinks current from a connected wiring. The current sink circuit 33 is connected to the global word line GWL and can sink current from the global word line GWL. The current sink circuit 33 operates under the control of the read control circuit 31 and is enabled or disabled under the control of the read control circuit 31. In one example, the current sink circuit 33 includes a MOSFET connected between the global word line GWL and a node that receives a ground voltage VSS. In this example, the transistor receives a control signal from the read control circuit 31 at its gate. The control signal turns the transistor on or off.

[0050] The connection circuit 36 ​​is a circuit that connects the global bit line GBL to one of the nodes N1 and N2 that is dynamically selected. The connection circuit 36 ​​operates under the control of the read control circuit 31. In one example, the connection circuit 36 ​​includes a switch circuit connected between the global bit line GBL and the node N1, and a switch circuit connected between the global bit line GBL and the node N2. In one example, each switch circuit includes a p-type MOSFET and an n-type MOSFET that are connected in parallel and receive signals of inverted logic at their gates.

[0051] The charge storage circuit 37 is a circuit that stores the charge accumulated at the node N1 at the start of the floating, and thus the potential at the node N1 at the start of the floating, while the node N1 is electrically floating. In one example, the charge storage circuit 37 includes a capacitor connected between the node N1 and the node of the ground voltage VSS.

[0052] The charge storage circuit 38 is a circuit that stores the charge stored at the node N2 at the start of the floating, and thus the potential at the node N2 at the start of the floating, while the node N2 is electrically floating. In one example, the charge storage circuit 38 includes a capacitor connected between the node N2 and the node of the ground voltage VSS.

[0053] The sense amplifier circuit 39 is a circuit that outputs a signal Dout based on a comparison between the potentials of the nodes N1 and N2. The signal Dout has a level indicating that the potentials of the nodes N1 and N2 are substantially the same, i.e., the difference between the potentials of the nodes N1 and N2 is within a certain range. The signal Dout has a level indicating that the potentials of the nodes N1 and N2 are different, i.e., the difference between the potentials of the nodes N1 and N2 exceeds a certain range.

[0054] The read control circuit 31 is a circuit that controls the entire data read operation. Data read includes a data write step, as will be described later. During the data write step included in the data read operation, the read control circuit 31 instructs the write control circuit 41 to execute the necessary data write. The write control circuit 41 is included in the write circuit 16, as will be described later.

[0055] 8 shows an example of components and connections of the components in the write circuit of the memory device of the first embodiment. As shown in FIG. 8, the write circuit 16 includes a write control circuit 41, a write current circuit 42, a current sink circuit 43, and connection circuits 44 and 45.

[0056] The write current circuit 42 is a circuit that supplies current to a current path including the connected wiring. The write current circuit 42 is connected to node N3 and can supply a write current of a fixed magnitude to a current path including node N3. The write current circuit 42 supplies one constant current that is dynamically selected from multiple constant currents of different magnitudes. The write current circuit 42 can supply a P write current Iwp and an AP write current Iwap. The write current circuit 42 can supply an AP write current Iwap_1 that is slightly higher than the AP write current Iwap. The write current circuit 42 can also supply an AP write current Iwap_A for each case of A, where A is an integer greater than or equal to 2. Each AP write current Iwap_A is slightly higher than the AP write current Iwap_A-1. The write current circuit 42 operates under the control of the read control circuit 31. The write current circuit 42 supplies the P write current Iwp and one of the AP write currents Iwap, Iwap_1, and Iwap_A-1 under the control of the read control circuit 31. The write current circuit 42 supplies the AP write current Iwap to the node N1 for a dynamically variable period under the control of the read control circuit 31.

[0057] In one example, the write current circuit 42 includes a MOSFET connected between a high potential node and node N3. In this example, the transistor receives a voltage at its gate from the write control circuit 41. The voltage controls the magnitude of the current provided by the write current circuit 42. The high potential node receives the power supply voltage VDD or an internal power supply voltage generated by the voltage generation circuit 18.

[0058] The current sink circuit 43 is a circuit that sinks current from the connected wiring. The current sink circuit 43 is connected to the node N4 and can sink current from the node N4. The current sink circuit 43 operates under the control of the write control circuit 41 and is enabled or disabled under the control of the write control circuit 41. In one example, the current sink circuit 43 includes a MOSFET connected between the node N4 and a node that receives the ground voltage VSS. In this example, the transistor receives a control signal from the write control circuit 41 at its gate. The control signal turns the transistor on or off.

[0059] The connection circuit 44 is a circuit that connects one of the nodes N3 and N4, which is dynamically selected, to the global bit line GBL. The connection circuit 44 operates under the control of the write control circuit 41. In one example, the connection circuit 44 includes a switch circuit connected between the node N3 and the global bit line GBL, and a switch circuit connected between the node N4 and the global bit line GBL.

[0060] The connection circuit 45 is a circuit that connects one of the nodes N3 and N4, which is dynamically selected, to the global word line GWL. The connection circuit 45 operates under the control of the write control circuit 41. In one example, the connection circuit 45 includes a switch circuit connected between the node N3 and the global word line GWL, and a switch circuit connected between the node N4 and the global word line GWL.

[0061] The current sink circuit 43 may be common to the current sink circuit 33. In this case, the connection circuits 44 and 45 are connected to the nodes N3 and N2, respectively.

[0062] The write control circuit 41 is a circuit that controls the entire data writing process. Data writing includes a data reading step, as will be described later. During the data reading step included in the data writing process, the write control circuit 41 instructs the read control circuit 31 to execute the necessary data reading.

[0063] 1.2.Operation 9 shows a data write flow of the memory device of the first embodiment. The flow of FIG. 9 is performed in a state where a memory cell MC to which data is to be written is connected to a global word line GWL and a global bit line GBL via a row selection circuit 14 and a column selection circuit 15. Hereinafter, the memory cell MC to which data is to be written may be referred to as a selected memory cell MC_s. The flow of FIG. 9 starts when the write circuit 16, based on receipt of a command or the like, decides to write data "1" to the selected memory cell MC_s, i.e., to put the MTJ element MTJ of the selected memory cell MC_s into a high-resistance state.

[0064] 9, the write control circuit 41 performs P write to the selected memory cell MC_s (step ST1). To execute step ST1, the write control circuit 41 controls the write current circuit 42, the current sink circuit 43, and the connection circuits 44 and 45 to pass a P write current Iwp to the selected memory cell MC_s. That is, the write current circuit 42 is connected to the global bit line GBL via the connection circuit 44, and the current sink circuit 43 is connected to the global word line GWL via the connection circuit 45. In this state, the write control circuit 41 enables the current sink circuit 43 and causes the write current circuit 42 to pass a P write current Iwp. Hereinafter, the P write of step ST1 may be referred to as reference data write.

[0065] The write control circuit 41 reads data from the selected memory cell MC_s (step ST2). To execute step ST2, the write control circuit 41 instructs the read control circuit 31 to execute data read. Upon receiving the instruction, the read control circuit 31 controls the read current circuit 32 and the current sink circuit 33 to read data. That is, the read control circuit 31 enables the current sink circuit 33 and causes the read current circuit 32 to flow a read current Ir. The flow of the read current Ir generates a potential on the global bit line GBL whose magnitude is based on the resistance state of the selected memory cell MC_s.

[0066] During the data read of step ST2, the read control circuit 31 controls the connection circuit 36 ​​to maintain the global bit line GBL disconnected from node N2 and connected to node N1. This transfers the potential of the global bit line GBL to node N1. When the transfer is complete, the read control circuit 31 controls the connection circuit 36 ​​to disconnect node N1 from the global bit line GBL, electrically floating node N1. This causes the charge storage circuit 37 to store a potential at node N1 whose magnitude is based on the resistance state of the selected memory cell MC_s. Hereinafter, step ST2 and similar data reads performed immediately after the reference data write may be referred to as reference data reads. Hereinafter, the data obtained by the reference data read, i.e., the charge stored in the charge storage circuit 37 by the reference data read, may be referred to as reference read data.

[0067] The write control circuit 41 performs AP write to the selected memory cell MC_s (step ST3). To execute step ST3, the write control circuit 41 controls the write current circuit 42, the current sink circuit 43, and the connection circuits 44 and 45 to pass an AP write current Iwap_0 through the selected memory cell MC_s. That is, the write current circuit 42 is connected to the global word line GWL via the connection circuit 45, and the current sink circuit 43 is connected to the global bit line GBL via the connection circuit 44. In this state, the write control circuit 41 enables the current sink circuit 43 and causes the write current circuit 42 to pass an AP write current Iwap_0. The AP write current Iwap_0 is smaller than the AP write current Iwap, more specifically, the AP write current Iwap_D when the first embodiment is not used. The AP write current Iwap_0 is passed over a period Tw_0.

[0068] The write control circuit 41 reads data from the selected memory cell MC_s (step ST4). Step ST4 is the same as step ST2. As a result of step ST2, a potential having a magnitude based on the resistance state of the selected memory cell MC_s is generated on the global bit line GBL.

[0069] Meanwhile, the potential of the global bit line GBL is stored in the charge storage circuit 38. That is, during the data read of step ST4, the read control circuit 31 controls the connection circuit 36 ​​to maintain the global bit line GBL disconnected from node N1 and connected to node N2. This transfers the potential of the global bit line GBL to node N2. When the transfer is complete, the read control circuit 31 controls the connection circuit 36 ​​to disconnect node N2 from the global bit line GBL, causing node N2 to electrically float. Hereinafter, data read immediately after AP write (step ST3), such as in step ST4, may be referred to as verify data read. Furthermore, hereinafter, the data obtained by verify data read, i.e., the charge stored in the charge storage circuit 38 by verify data read, may be referred to as verify read data.

[0070] The write control circuit 41 compares the reference read data with the verify read data (step ST5). To perform step ST5, the write control circuit 41 instructs the read control circuit 31 to start operating the sense amplifier circuit 39. Upon receiving the instruction, the sense amplifier circuit 39 outputs a signal Dout having a value based on the potentials of nodes N1 and N2. The signal Dout is received by the write control circuit 41. If the signal Dout indicates that the potentials of nodes N1 and N2 are substantially the same, this indicates that the MTJ element MTJ of the selected memory cell MC_s is not in the AP state, i.e., the AP write performed in step ST3 was not successful. On the other hand, if the signal Dout indicates that the potentials of nodes N1 and N2 are substantially different, this indicates that the MTJ element MTJ of the selected memory cell MC_s is in the AP state, i.e., the AP write performed in step ST3 was successful.

[0071] The write control circuit 41, referring to the signal Dout, if the MTJ element MTJ of the selected memory cell MC_s is in the AP state (step ST6_Yes), ends the flow of Fig. 9. The write control circuit 41, referring to the signal Dout, if the MTJ element MTJ of the selected memory cell MC_s is not in the AP state (step ST6_No), performs further AP writing to the selected memory cell MC_s (step ST7).

[0072] Step ST7 is almost the same as step ST3. The difference is that the AP write current Iwap used and / or the time for which the AP write current Iwap is flowed may be different. That is, in one example, step ST7 may use the AP write current Iwap_1. The AP write current Iwap_1 is larger than the AP write current Iwap_0. In another example, the AP write current Iwap_0 is flowed for a period Tw_1. The period Tw_1 is longer than the period Tw_0. The AP write current Iwap_0 may also be used.

[0073] Step ST7 continues from step ST4. In step ST7 when the MTJ element MTJ of the selected memory cell MC_s is not in the AP state in the subsequent step ST6, the AP write current Iwap_2 and / or the period Tw_2 may be used. The AP write current Iwap_2 is larger than the AP write current Iwap_1. The period Tw_2 is longer than the period Tw_1. Similarly, each time step ST7 is performed, if the AP write current Iwap_g was used in the previous step ST7, the AP write current Iwap_g+1 may be used. g is a positive integer. The AP write current Iwap_g+1 is larger than the AP write current Iwap_g. Similarly, each time step ST7 is performed, if the period Tw_g was used in the previous step ST7, the period Tw_g+1 may be used. The period Tw_g+1 is longer than the period Tw_g.

[0074] 10 shows an example of the magnitude of the current flowing through the memory cell over time during AP writing in the memory device of Embodiment 1. The current is the cell current flowing through the selected memory cell MC_s.

[0075] 10, the P write current Iwp flows from time t1 to time t2. The period from time t1 to time t2 corresponds to the period of the operation in step ST1 of the flow in FIG.

[0076] The read current Ir flows from time t3 to time t4. The period from time t3 to time t4 corresponds to the period of operation in step ST2 of the flow in FIG.

[0077] The AP write current Iwap_0 flows from time t4 to time t5. The period from time t4 to time t5 corresponds to the period of the operation in step ST3 of the flow in FIG.

[0078] The read current Ir flows from time t5 to time t6. The period from time t5 to time t6 corresponds to the period of the operation in step ST4 of the flow in FIG.

[0079] No current flows from time t6 to time t7. The period from time t6 to time t7 corresponds to the period of operation in step ST5 of the flow in FIG.

[0080] The period from time t7 onwards corresponds to the case where step ST7 is performed in the flow of Figure 9. Several cases of the operation performed as step ST7 are indicated by solid lines, dashed lines, and dashed dotted lines. The solid lines indicate cases where the same conditions as step ST3 are used in step ST7. As indicated by the solid lines, the AP write current Iwap_0 flows from time t7 to time t8.

[0081] The dashed line indicates a case where the same AP write current Iwap as that used in step ST3 is applied in step ST7 for a longer period than that used in step ST3. As indicated by the dashed line, the AP write current Iwap_0 is applied from time t7 to time t9. Time t9 comes after time t8.

[0082] The dashed-dotted line indicates the case where the AP write current Iwap_1 is used in step ST7. As indicated by the dashed-dotted line, the AP write current Iwap_1 is caused to flow from time t7 to time t8.

[0083] 1.3.Advantages (Effects) According to a first embodiment, a memory device including memory cells having a long lifespan can be provided, as described below.

[0084] The lifetime of a memory cell depends on the magnitude and duration of the voltage applied to the memory cell. In a memory device including an MTJ element, the highest voltage applied to the MTJ element occurs when an AP write current flows through the MTJ element in the AP state. This can occur when an AP write current is passed through an MTJ element already in the AP state based on write data, because a memory device including an MTJ element can overwrite data.

[0085] According to the first embodiment, for an AP write, a P write is performed, reference read data is acquired, an AP write is performed, verify read data is acquired, the reference read data and verify read data are compared, and if the comparison result indicates the P state of the MTJ element, a further AP write is performed. The first AP write uses an AP write current Iwap_0 that is smaller than the normal AP write current Iwap_D. Therefore, even if the selected memory cell MC_s is in the AP state, the voltage applied to the selected memory cell MC_s by the first AP write is lower than the voltage in the case where the AP write current Iwap_D is used. This prevents a high voltage from being applied to the MTJ element MTJ, thereby preventing deterioration in the lifespan of the MTJ element MTJ and, ultimately, the memory cell MC.

[0086] The AP write current Iwap_0 is smaller than the AP write current Iwap_D. Therefore, using the AP write current Iwap_0 makes it more difficult to put the MTJ element MTJ into the AP state than using the AP write current Iwap_D. However, after the AP write using the AP write current Iwap_0, the resistance state of the MTJ element MTJ of the selected memory cell MC_s is confirmed, and if it is in the P state, further AP write is performed. Therefore, even if the MTJ element MTJ is in the P state after the AP write using the AP write current Iwap_0, the MTJ element MTJ can be put into the AP state.

[0087] 2. Second embodiment Configuration 11 shows an example of the components and connections of the components in the readout circuit of the memory device of the second embodiment. As shown in FIG. 11, the readout circuit 17_B of the memory device 1_B of the second embodiment does not include the readout current circuit 32 and the current sink circuit 33 of the first embodiment, but includes voltage application circuits 51, 52, 53, and 54 and a current adjustment circuit 56.

[0088] The voltage application circuit 51 is a circuit that applies a voltage to a connected node. The voltage application circuit 51 is connected to the global word line GWL_1 and applies a precharge voltage VPRCH to the global word line GWL_1. The global word line GWL_1 is a part of the global word line GWL. In one example, the precharge voltage VPRCH has a fixed magnitude and is higher than the ground voltage VSS. The voltage application circuit 51 is disabled or enabled based on the control of the read control circuit 31. While the voltage application circuit 51 is enabled, it applies the precharge voltage VPRCH to the global word line GWL_1. The precharge voltage VPRCH is supplied from the voltage generation circuit 18. In one example, the voltage application circuit 51 includes a switch circuit connected between the node that receives the precharge voltage VPRCH and the global word line GWL.

[0089] The voltage application circuit 52 is a circuit that applies a voltage to a connected node. The voltage application circuit 52 is connected to the global word line GWL_1 and applies a non-selection voltage VUSEL to the global word line GWL. In one example, the non-selection voltage VUSEL has a fixed magnitude and is between the pre-charge voltage VPRCH and the ground voltage VSS. The non-selection voltage VUSEL is supplied from the voltage generation circuit 18. The voltage application circuit 52 is disabled or enabled based on control of the read control circuit 31. While the voltage application circuit 52 is enabled, it applies the non-selection voltage VUSEL to the global word line GWL_1. In one example, the voltage application circuit 52 includes a switch circuit connected between the node that receives the non-selection voltage VUSEL and the global word line GWL_1.

[0090] The voltage application circuit 53 is a circuit that applies a voltage to a connected node. The voltage application circuit 53 is connected to the global bit line GBL and applies a non-selection voltage VUSEL to the global bit line GBL. The voltage application circuit 53 is disabled or enabled based on the control of the read control circuit 31. While the voltage application circuit 53 is enabled, it applies the non-selection voltage VUSEL to the global bit line GBL. In one example, the voltage application circuit 53 includes a switch circuit connected between the node that receives the non-selection voltage VUSEL and the global bit line GBL.

[0091] The voltage application circuit 54 is a circuit that applies a voltage to a connected node. The voltage application circuit 54 is connected to the global bit line GBL and applies a ground voltage VSS to the global bit line GBL. The voltage application circuit 54 is disabled or enabled based on the control of the read control circuit 31. While the voltage application circuit 54 is enabled, it applies the ground voltage VSS to the global bit line GBL. In one example, the voltage application circuit 54 includes a switch circuit connected between the global bit line GBL and a node that receives the ground voltage VSS.

[0092] The current adjustment circuit 56 is a circuit that adjusts the magnitude of the current flowing through the global word line GWL. The current adjustment circuit 56 adjusts the magnitude of the current flowing into the global word line GWL_1 and supplies the adjusted current to the global word line GWL_2. The global word line GWL_2 is a part of the global word line GWL.

[0093] FIG. 12 shows a first example of the components and connections of the current adjustment circuit of the memory device of the second embodiment. As shown in FIG. 12, the current adjustment circuit 56 includes an n-type MOSFET TN1 and a p-type MOSFET TP1. The transistors TN1 and TP1 are connected in parallel between the global word lines GWL_1 and GWL_2. The transistor TN1 receives a control signal CN1 at its gate. The transistor TP1 receives a control signal CN1 at its gate. The symbol "" indicates the inverse logic of the signal without the symbol "". The control signals CN1 and CN1 are supplied from the read control circuit 31.

[0094] 13 shows a second example of components and connections of the current adjustment circuit of the memory device of the second embodiment. As shown in FIG. 13, the current adjustment circuit 56 includes connection circuits 61 and 62 and capacitance-equipped paths 63, 64, and 65.

[0095] The connection circuit 61 is a circuit that connects the global word line GWL_1 to a dynamically selected one of the capacitive paths 63, 64, and 65. The connection circuit 61 operates under the control of the read control circuit 31. In one example, the connection circuit 61 includes a switch between the global word line GWL_1 and the capacitive path 63, a switch between the global word line GWL_1 and the capacitive path 64, and a switch between the global word line GWL_1 and the capacitive path 65.

[0096] The connection circuit 62 is a circuit that connects a dynamically selected one of the capacitive paths 63, 64, and 65 to the global word line GWL_1. The connection circuit 62 operates under the control of the read control circuit 31. In one example, the connection circuit 62 includes a switch between the capacitive path 63 and the global word line GWL_2, a switch between the capacitive path 64 and the global word line GWL_2, and a switch between the capacitive path 65 and the global word line GWL_2.

[0097] The capacitive path 63 is a path that electrically connects the connection circuits 61 and 62 and has a capacitance. The capacitive path 63 adds a capacitance EC1 to the global word line GWL while being connected to the global word lines GWL_1 and GWL_2 by the connection circuits 61 and 62. In one example, the capacitive path 63 includes a conductor connected to the connection circuits 61 and 62, and a capacitor CP1 connected between the conductor and a node receiving the ground voltage VSS. The capacitive element CP1 has a capacitance EC1. Examples of the capacitive element CP1 include a capacitive element and a parasitic capacitance.

[0098] The capacitive path 64 is a path that electrically connects the connection circuits 61 and 62 and has a capacitance. The capacitive path 64 adds a capacitance EC2 to the global word line GWL while connected to the global word lines GWL_1 and GWL_2 by the connection circuits 61 and 62. The capacitance EC2 is larger than the capacitance EC1. In one example, the capacitive path 64 includes a conductor connected to the connection circuits 61 and 62, and a capacitive element CP2 connected between the conductor and a node receiving the ground voltage VSS. The capacitive element CP2 has a capacitance EC2. Examples of the capacitive element CP2 include a capacitive element and a parasitic capacitance.

[0099] The capacitive path 65 is a path that electrically connects the connection circuits 61 and 62 and has a capacitance. The capacitive path 65 adds a capacitance EC3 to the global word line GWL while connected to the global word lines GWL_1 and GWL_2 by the connection circuits 61 and 62. The capacitance EC3 is larger than the capacitance EC2. In one example, the capacitive path 65 includes a conductor connected to the connection circuits 61 and 62, and a capacitive element CP3 connected between the conductor and a node at ground potential. The capacitive element CP3 has a capacitance EC3. Examples of the capacitive element CP3 include a capacitive element and a parasitic capacitance.

[0100] 2.2.Operation FIG. 14 shows the potentials of several nodes over time during data reading from the memory device of the second embodiment.

[0101] The period shown in Figure 14 occurs when a selected memory cell MC_s is connected to the global word line GWL and the global bit line GBL via the row selection circuit 14 and the column selection circuit. Therefore, the bit line BL connected to the selected memory cell MC_s has a potential that follows the potential of the global bit line GBL. Also, the word line WL connected to the selected memory cell MC_s has a potential that follows the potential of the global word line GWL. Hereinafter, the potential of the global bit line GBL may be referred to as the global bit line potential VBL. Also, the potential of the global word line GWL may be referred to as the global word line potential VWL.

[0102] 14, the global bit line potential VBL and the global word line potential VWL have the unselected potential VUSEL. This can be achieved by disabling the voltage application circuits 51 and 54 and enabling the voltage application circuits 52 and 53. The unselected potential VUSEL is a potential having a magnitude that the wiring has as a result of the unselected voltage VUSEL being applied thereto, and in one example, has substantially the same magnitude as the unselected voltage VUSEL.

[0103] At time t11, the global word line potential VWL is set to the precharge potential VPRCH. This can be achieved by disabling the voltage application circuit 52 and enabling the voltage application circuit 51. The precharge potential VPRCH is a potential having a magnitude that is achieved by applying the precharge voltage VPRCH to the wiring, and in one example, has substantially the same magnitude as the precharge voltage VPRCH.

[0104] At time t12, the global word line potential VWL is electrically floated, which can be achieved by disabling both the voltage application circuits 51 and 52.

[0105] At time t13, the global bit line potential VBL is set to the ground potential VSS. This can be achieved by disabling the voltage application circuit 53 and enabling the voltage application circuit 54. The ground potential VSS is a potential having a magnitude that is achieved by applying the ground voltage VSS to the wiring, and in one example, has substantially the same magnitude as the ground voltage VSS.

[0106] As the global bit line potential VBL decreases from time t13, the difference between the global word line potential VWL and the global bit line potential VBL reaches the threshold voltage Vth at time t14. This turns on the switching element SE of the selected memory cell MC_s. Therefore, the global word line GWL is electrically connected to the global bit line GBL via the on-state switching element SE in the selected memory cell MC_s. This causes a cell current to flow from the global word line GWL to the global bit line GBL. The cell current has a peak value IPr.

[0107] Since the global word line GWL is electrically floating, the global word line potential VWL drops when a cell current flows. At this time, the global word line potential VWL drops at different speeds depending on the state of the MTJ element MTJ of the selected memory cell MC_s. When the MTJ element MTJ of the selected memory cell MC_s is in a high-resistance state, the global word line potential VWL drops more slowly than when the MTJ element MTJ of the selected memory cell MC_s is in a low-resistance state.

[0108] At time t15, the global word line potential VWL reaches a level based on the resistance state of the MTJ element MTJ of the selected memory cell MC_s. That is, as the global word line potential VWL drops, the difference between the global word line potential VWL and the global bit line potential VBL decreases. As a result, when the terminal voltage of the selected memory cell MC_s reaches a certain level based on the resistance state of the MTJ element MTJ of the selected memory cell MC_s, the switching element SE of the selected memory cell MC_s turns off. As a result, the global word line potential VWL stops dropping, and the global word line potential VWL maintains a certain level.

[0109] Fig. 15 shows a flow of data writing in the memory device of the second embodiment. The flow of Fig. 15 is performed when a selected memory cell MC_c is connected to a global word line GWL and a global bit line GBL via a row selection circuit 14 and a column selection circuit 15. The flow of Fig. 15 starts when the write circuit 16, based on receipt of a command or the like, decides to write "1" data to the selected memory cell MC_s, i.e., to put the MTJ element MTJ of the selected memory cell MC_s into a high-resistance state.

[0110] As shown in FIG. 15, step ST1 is performed.

[0111] The write control circuit 41 reads data from the selected memory cell MC_s (step ST11). Step ST11 corresponds to reading reference data. To execute step ST11, the write control circuit 41 instructs the read control circuit 31 to execute a data read. Upon receiving the instruction, the read control circuit 31 performs the operation described above with reference to FIG. 14 to read the data. When a cell current of a peak value IPr flows, a potential having a magnitude based on the resistance state of the MTJ element MTJ of the selected memory cell MC_s is generated on the global bit line GBL.

[0112] During data read, the write control circuit 41 instructs the read control circuit 31 to limit the upper limit of the current flowing from the global word line GWL_2 to an upper limit IUL_0 from time t13 in FIG. 14 by controlling the current adjustment circuit 56. In the example shown in FIG. 12, the read control circuit 31 adjusts the current flowing through the transistors TN1 and TP1 by controlling the magnitude of the control signals CN and CN based on the received instruction. In the example shown in FIG. 13, the read control circuit 31 controls the connection circuits 61 and 62 based on the received instruction to connect the global word lines GWL_1 and GWL_2 by the capacitive path 63.

[0113] Furthermore, during step ST11, the same control as in step ST2 is performed, so that the charge storage circuit 37 stores reference read data at node N1.

[0114] The write control circuit 41 performs AP write and data read in parallel for the selected memory cell MC_s (step ST12). The data read in step ST12 corresponds to verify data read. To execute step ST12, the write control circuit 41 instructs the read control circuit 31 to execute data read. Upon receiving the instruction, the read control circuit 31 performs the operation described above with reference to FIG. 14 to read data.

[0115] During data read, the write control circuit 41 instructs the read control circuit 31 to limit the upper limit of the current flowing from the global word line GWL_2 to an upper limit IUL_1 starting from time t13 in FIG. 14 by controlling the current adjustment circuit 56. The upper limit IUL_1 is greater than the upper limit IUL_0. In the example shown in FIG. 12, the read control circuit 31 controls the magnitude of the control signals CN and CN based on the received instruction to create a state in which the transistors TN1 and TP1 can pass a current greater than the current that can flow through the transistors TN1 and TP1 during the reference data read of step ST11. In the example shown in FIG. 13, the read control circuit 31 controls the connection circuits 61 and 62 based on the received instruction to connect the global word lines GWL_1 and GWL_2 by the capacitive path 64. As a result, during data read, the global word line GWL has a capacitance greater than the capacitance added to the global word line GWL during the (reference) data read (step ST11). Therefore, a large amount of charge is stored in the global word line GWL immediately before the global word line GWL is brought into an electrically floating state at time t12, and therefore, the cell current flowing through the selected memory cell MC_s from time t13 onwards is large.

[0116] The flow of the cell current generates a potential on the global bit line GBL, the magnitude of which depends on the resistance state of the MTJ element MTJ of the selected memory cell MC_s.

[0117] During step ST12, the same control as in step ST4 is performed, so that the charge storage circuit 38 stores the verify read data in the node N2.

[0118] During data read, under the control of the current adjustment circuit 56, the cell current flowing through the selected memory cell MC_s from time t13 is larger than the cell current flowing through the selected memory cell MC_s in step ST11. This cell current functions as the AP write current Iwap_B_0 and causes AP write to the selected memory cell MC_s. The AP write current Iwap_B_0 has a certain peak value IP_0. The peak value IP_0 is larger than the peak value IPr. The peak value IP_0 may be the same as the AP write current Iwap or may be smaller than the AP write current Iwap. In one example, the peak value IP_0 is smaller than the AP write current Iwap. The AP write current Iwap_B_0 flows for a period Tw_B_0.

[0119] 12, the control signals CN and CN have magnitudes that allow the cell current of peak value IPr to flow without the AP write current Iwap_B_0 flowing from time t13 during the operation of step ST2. Also, the control signals CN and CN have magnitudes that allow the AP write current Iwap_B_0 to flow from time t13 during the operation of step ST12.

[0120] In the case where the current adjustment circuit 56 has the configuration shown in FIG. 13, the capacitive element CP2 of the capacitive path 64 has a size that causes step ST12 to store an amount of charge in the global word line GWL that allows an AP write current Iwap_B_0 of peak value IP_0 to flow.

[0121] As described above with reference to FIG. 5, whether the switching element SE is turned off depends on the terminal voltage of the MTJ element MTJ. Therefore, regardless of the magnitude of the cell current, when the terminal voltage of the selected memory cell MC_s reaches a specific magnitude based on the resistance state of the MTJ element MTJ of the selected memory cell MC_s, the switching element SE of the selected memory cell MC_s is turned off. Therefore, the flow of the cell current for AP writing does not affect data reading. Step ST12 continues to step ST5.

[0122] If the MTJ element MTJ of the selected memory cell MC_s is in the AP state (step ST6_Yes), the write control circuit 41 ends the flow of Fig. 15. If the MTJ element MTJ of the selected memory cell MC_s is not in the AP state (step ST6_No), the write control circuit 41 performs further AP writing to the selected memory cell MC_s (step ST13).

[0123] Step ST13 is substantially the same as step ST12. The difference is that the AP write current Iwap_B used and / or the time for which the AP write current Iwap_B is flowed may be different. That is, in one example, step ST13 may use the AP write current Iwap_B_1. The AP write current Iwap_B_1 has a peak value IP_1. The peak value IP_1 is greater than the peak value IP_0 of the AP write current Iwap_B_0. In another example, the AP write current Iwap_B_0 is flowed for a period Tw_B_1. The period Tw_B_1 is longer than the period Tw_B_0.

[0124] The magnitude of the peak value IP of the AP write current Iwap_B and / or the time during which the AP write current Iwap_B flows can be adjusted by selecting one of the capacitive paths 63, 64, and 65. To pass a greater number of AP write currents Iwap_B having different peak values ​​IP, additional capacitive paths are provided. The additional capacitive paths have a capacitance greater than that of the capacitive element CP3.

[0125] Step ST13 continues from step ST5. In step ST13 when the MTJ element MTJ of the selected memory cell MC_s is not in the AP state in the subsequent step ST6, an AP write current Iwap_2 having a peak value IP_2 and / or a period Tw_B_2 may be used. The peak value IP_2 is greater than the peak value IP_1 of the AP write current Iwap_B_1. The period Tw_B_2 is longer than the period Tw_B_1. Similarly, each time step ST13 is performed, if an AP write current Iwap_B_g having a peak value IP_g was used in the previous step ST13, an AP write current Iwap_B_g+1 having a peak value IP_g+1 may be used. The peak value IP_g+1 is greater than the peak value IP_g. Similarly, each time step ST13 is performed, if the period Tw_B_g was used in the previous step ST13, a period Tw_B_g+1 is used. The period Tw_B_g+1 is longer than the period Tw_B_g.

[0126] 16 shows an example of the magnitude of the current flowing through the memory cell over time during AP writing in the memory device of Embodiment 2. The current is the cell current flowing through the selected memory cell MC_s.

[0127] 16, the P write current Iwp flows from time t21 to time t22. The period from time t21 to time t22 corresponds to the period of the operation in step ST1 of the flow in FIG.

[0128] A read current of peak value IPr flows from time t23 to time t24. The period from time t23 to time t24 corresponds to the period of operation in step ST11 of the flow in FIG.

[0129] From time t25 to time t26, an AP write current Iwap_B_0 with a peak value IP_0 flows. The period from time t25 to time t26 corresponds to the period of step ST12 in the flow of FIG.

[0130] No current flows from time t26 to time t27. The period from time t26 to time t27 corresponds to the period of operation in step ST5 of the flow in FIG.

[0131] The period from time t27 onwards corresponds to the case where step ST13 is performed in the flow of Figure 15. Several cases of the operation performed as step ST13 are indicated by solid lines and dashed dotted lines. The solid lines indicate cases where the same conditions as step ST12 are used in step ST13. As indicated by the solid lines, an AP write current Iwap_B_0 with a peak value IP_0 flows from time t27 to time t28.

[0132] The dashed-dotted line indicates the case where the AP write current Iwap_B_1 is used in step ST13. As indicated by the dashed-dotted line, the AP write current Iwap_B_1 flows with a peak value IP_1 from time t27 to time t29.

[0133] 2.3.Advantages According to the second embodiment, as in the first embodiment, for AP write, a P write is performed, reference read data is obtained, an AP write is performed, verify read data is obtained, the reference read data and the verify read data are compared, and if the result of the comparison indicates the P state of the MTJ element, a further AP write is performed, thereby obtaining the same advantages as in the first embodiment.

[0134] Furthermore, according to the second embodiment, data reading is performed using the low hold voltage VhdL and high hold voltage VhdH obtained during the process of the drop in the terminal voltage of the selected memory cell MC_s, and data reading and AP writing are performed in a single operation. Data reading using the low hold voltage VhdL and high hold voltage VhdH utilizes the phenomenon in which the switching element SE is turned off based on the resistance state of the MTJ element MTJ of the selected memory cell MC_s, so that control of the application of current to the selected memory cell MC_s is simple. Furthermore, because data reading and AP writing are performed in a single operation, the entire AP writing is completed in a short time.

[0135] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0136] 31...read control circuit, 32...Read current circuit, 33...Current sink circuit, 36...connection circuit, 37, 38...charge storage circuit, 38...charge storage circuit, 39...Sense amplifier circuit, 41...write control circuit, 42...Write current circuit, 43...Current sink circuit, 44, 45, 61, 62...connection circuit, 51, 52, 53, 54...Voltage application circuit, 56...Current adjustment circuit, 63, 64, 65...Capacity-equipped routes,

Claims

1. a memory cell including a magnetoresistive element and a switching element connected to the magnetoresistive element; a first wiring connected to a first end of the memory cell; a second wiring connected to a second end of the memory cell; Equipped with the operation of setting the magnetoresistive element in a first resistance state includes a first period, a second period after the first period, a third period after the second period, a fourth period after the third period, and a fifth period after the fourth period; During the first period, a first operation is performed to set the magnetoresistive element to a second resistance state exhibiting a lower resistance than the first resistance state, During the second period, first data based on a resistance state of the magnetoresistive element is acquired; a second operation is performed in the third period to set the magnetoresistive element in the first resistance state; In the fourth period, second data based on a resistance state of the magnetoresistive element is acquired; In the fifth period, a third operation is performed to set the magnetoresistive element in the first resistance state. storage device.

2. the third operation is performed when the magnetoresistive element is not in the first resistance state. The storage device according to claim 1 .

3. the third operation is performed when the magnetoresistive element is not in the first resistance state based on the first data and the second data. The storage device according to claim 1 .

4. the second operation includes passing a first current through the memory cell in a first direction; the third operation includes passing a second current, a first current greater than the first current, in the first direction through the memory cell; The storage device according to claim 1 .

5. the first operation includes passing a third current through the memory cell in a second direction opposite to the first direction; The storage device according to claim 4.

6. the second operation includes passing a first current through the memory cell in a first direction for a sixth period of time; the third operation includes passing the first current through the memory cell in the first direction for a seventh period longer than the sixth period; The storage device according to claim 1 .

7. the first operation includes passing a second current through the memory cell in a second direction opposite to the first direction; The storage device according to claim 6.

8. the first data is based on a potential generated in the second wiring by supplying a current to the memory cell, the second data is based on a potential generated in the second wiring when a current is supplied to the memory cell; The storage device according to any one of claims 1 to 7.

9. a memory cell including a magnetoresistive element and a switching element connected to the magnetoresistive element; a first wiring connected to a first end of the memory cell; a second wiring connected to a second end of the memory cell; Equipped with the operation of setting the magnetoresistive element in a first resistance state includes a first period, a second period after the first period, a third period after the second period, and a fourth period after the third period; During the first period, a first operation is performed to set the magnetoresistive element to a second resistance state exhibiting a lower resistance than the first resistance state, a second operation is performed in the second period to acquire first data based on a resistance state of the magnetoresistive element; a third operation is performed in the third period to set the magnetoresistive element to the first resistance state and to acquire second data based on the resistance state of the magnetoresistive element; In the fourth period, a fourth operation is performed to set the magnetoresistive element in the first resistance state. storage device.

10. the third operation is performed when the magnetoresistive element is not in the first resistance state. The storage device according to claim 9.

11. the third operation is performed when the magnetoresistive element is not in the first resistance state based on the first data and the second data. The storage device according to claim 9.

12. the third operation includes passing a first current through the memory cell in a first direction and having a first peak value; the fourth operation includes passing a second current through the memory cell in the first direction, the second current having a second peak value greater than the first peak value; The storage device according to claim 9.

13. the first operation includes passing a third current through the memory cell in a second direction opposite to the first direction; The storage device of claim 12.

14. the third operation includes passing a first current through the memory cell in a first direction for a fifth period of time; the fourth operation includes passing the first current through the memory cell in the first direction for a sixth period longer than the fifth period; The storage device according to claim 9.

15. the first operation includes passing a second current through the memory cell in a second direction opposite to the first direction; The storage device of claim 14.

16. The third operation is applying a first voltage to a first wiring; applying the first voltage to the first wiring and then electrically floating the first wiring; applying a second voltage lower than the first voltage to the second wiring while the first wiring is electrically floating; Including, the second data is based on a potential generated in the first wiring after the second voltage is applied to the second wiring; The storage device according to any one of claims 9 to 15.

17. The fourth operation is applying the first voltage to the first wiring; applying the first voltage to the first wiring and then electrically floating the first wiring; applying the second voltage to the second wiring while the first wiring is electrically floating; Including, The storage device of claim 16.

18. The second operation is applying the first voltage to the first wiring; applying the first voltage to the first wiring and then electrically floating the first wiring; applying the second voltage to the second wiring while the first wiring is electrically floating; Including, The storage device of claim 16.

19. During the second operation, the first wiring includes a path through which a current having an upper limit of a first value flows; During the third operation, the first wiring includes a path through which a current having an upper limit of a second value greater than the first value flows. The storage device according to claim 9.

20. During the second operation, the first wiring has a first capacitance; During the third operation, the first wiring has a second capacitance greater than the first capacitance. The storage device according to claim 9.

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