magnetic memory devices

Abstract

Reduce the write time. The magnetic memory device includes a conductive layer extending in a first direction, a magnetoresistive element stacked in a second direction intersecting the first direction and having a first end in contact with the conductive layer and a second end not in contact with the conductive layer, and a control circuit configured to write data to the magnetoresistive element. In a write operation, the control circuit is configured to pass a current through the conductive layer in a first period, stop the current in a second period following the first period, and apply a negative first potential difference to the second end with respect to the first end.

Description

[Technical Field]

[0001] FIELD Embodiments relate to magnetic memory devices. [Background technology]

[0002] 2. Description of the Related Art Magnetic memory devices using magnetoresistive elements as memory elements are known, and various methods have been proposed for writing data to magnetoresistive elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0051820 [Patent Document 2] US Patent Application Publication No. 2018 / 0090674 [Patent Document 3] U.S. Patent Application Publication No. 2020 / 0211612 [Non-patent literature]

[0004] [Non-Patent Document 1] K. Cai, et al., “Selective operations of multi-pillar SOT-MRAM for high density and low power,” 2022 Symposium on VLSI Technology & Circuits Digest of Technical Papers, pp. 375-376. Summary of the Invention [Problem to be solved by the invention]

[0005] Reduce the write time. [Means for solving the problem]

[0006] In one embodiment, the magnetic memory device includes a conductive layer extending in a first direction, a magnetoresistive element stacked in a second direction intersecting the first direction and having a first end in contact with the conductive layer and a second end not in contact with the conductive layer, and a control circuit configured to write data to the magnetoresistive element, wherein the control circuit is configured to, in a write operation, pass a current through the conductive layer in a first period, stop the current in a second period following the first period, and apply a first negative potential difference to the second end with respect to the first end. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a magnetic memory device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array according to the embodiment. [Figure 3] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive element and surrounding wiring according to the embodiment. [Figure 4] FIG. 10 is a waveform diagram showing an example of magnetization reversal of a storage layer in a write operation in a magnetic memory device according to the embodiment. [Figure 5] FIG. 2 is a circuit diagram showing an example of voltages applied in a write operation in the magnetic memory device according to the embodiment. [Figure 6] FIG. 2 is a circuit diagram showing an example of voltages applied in a write operation in the magnetic memory device according to the embodiment. [Figure 7] 1A and 1B are diagrams showing an example of the VCMA effect occurring in a memory layer during a write operation in a magnetic memory device according to an embodiment. [Figure 8] 1A and 1B are cross-sectional views showing an example of a write operation in a magnetic memory device according to an embodiment. [Figure 9] 1A and 1B are cross-sectional views showing an example of a write operation in a magnetic memory device according to an embodiment. [Figure 10] FIG. 4 is a waveform diagram showing a first example of a write operation in the magnetic memory device according to the embodiment. [Figure 11] FIG. 10 is a waveform diagram showing a second example of a write operation in the magnetic memory device according to the embodiment. [Figure 12] FIG. 10 is a waveform diagram showing a third example of a write operation in the magnetic memory device according to the embodiment. [Figure 13] FIG. 10 is a waveform diagram showing a fourth example of a write operation in a magnetic memory device according to a modified example. [Figure 14] FIG. 10 is a waveform diagram showing a fifth example of a write operation in a magnetic memory device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, several embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference symbol. Furthermore, when multiple components having the same reference symbol are to be distinguished from one another, a subscript will be added to the common reference symbol. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference symbol, without a subscript. Subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase alphabets added to the end of a reference symbol, symbols, and indexes indicating an array.

[0009] In this specification, the magnetic memory device is, for example, an MRAM (Magnetoresistive Random Access Memory). The magnetic memory device includes a magnetoresistive effect element as a storage element. The magnetoresistive effect element is a resistance change element that has a magnetoresistive effect due to a magnetic tunnel junction (MTJ). The magnetoresistive effect element is also called an MTJ element.

[0010] 1. Configuration First, the configuration of the magnetic memory device according to the embodiment will be described.

[0011] 1.1 Magnetic memory devices 1 is a block diagram showing an example of the configuration of a magnetic memory device according to an embodiment. The magnetic memory device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0012] The memory cell array 10 is a data storage section in the magnetic memory device 1. The memory cell array 10 includes a plurality of memory cells MC. Each of the plurality of memory cells MC corresponds to a pair of a row and a column. Memory cells MC in the same row are connected to the same word line WL, and memory cells MC in the same column are connected to the same pair of a first bit line BL1 and a second bit line BL2.

[0013] The row selection circuit 11 is a circuit that selects a row of the memory cell array 10. The row selection circuit 11 is connected to the memory cell array 10 via word lines WL. The row selection circuit 11 receives the decoded result (row address) of the address ADD from the decode circuit 13. The row selection circuit 11 selects a word line WL corresponding to a row based on the decoded result of the address ADD. Hereinafter, the selected word line WL will be referred to as a selected word line WL. Furthermore, word lines WL other than the selected word line WL will be referred to as unselected word lines WL.

[0014] The column selection circuit 12 is a circuit that selects a column of the memory cell array 10. The column selection circuit 12 is connected to the memory cell array 10 via a first bit line BL1 and a second bit line BL2. The column selection circuit 12 receives a decoded result (column address) of the address ADD from the decode circuit 13. The column selection circuit 12 selects a first bit line BL1 and a second bit line BL2 corresponding to a column based on the decoded result of the address ADD. Hereinafter, the selected first bit line BL1 and the selected second bit line BL2 will be referred to as a selected bit line BL1 and a selected bit line BL2, respectively. In addition, the first bit line BL1 other than the selected bit line BL1 and the second bit line BL2 other than the selected bit line BL2 will be referred to as an unselected bit line BL1 and an unselected bit line BL2, respectively.

[0015] The decode circuit 13 is a decoder that decodes the address ADD from the input / output circuit 17. The decode circuit 13 supplies the decoded result of the address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes a column address and a row address.

[0016] The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 writes data to the memory cells MC.

[0017] The read circuit 15 includes, for example, a sense amplifier (not shown). The read circuit 15 reads data from the memory cells MC.

[0018] The voltage generation circuit 16 generates voltages for various operations of the memory cell array 10 using a power supply voltage provided from outside (not shown) of the magnetic memory device 1. For example, the voltage generation circuit 16 generates various voltages required for a write operation and outputs them to the write circuit 14. Also, for example, the voltage generation circuit 16 generates various voltages required for a read operation and outputs them to the read circuit 15.

[0019] The input / output circuit 17 controls communication with the outside of the magnetic memory device 1. The input / output circuit 17 transfers an address ADD from the outside of the magnetic memory device 1 to the decode circuit 13. The input / output circuit 17 transfers a command CMD from the outside of the magnetic memory device 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signals CNT between the outside of the magnetic memory device 1 and the control circuit 18. The input / output circuit 17 transfers data DAT from the outside of the magnetic memory device 1 to the write circuit 14, and outputs data DAT transferred from the read circuit 15 to the outside of the magnetic memory device 1.

[0020] The control circuit 18 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The control circuit 18 controls the operations of the row selection circuit 11, the column selection circuit 12, the decode circuit 13, the write circuit 14, the read circuit 15, the voltage generation circuit 16, and the input / output circuit 17 in the magnetic memory device 1 based on a control signal CNT and a command CMD.

[0021] 1.2 Memory cell array Next, the configuration of the memory cell array of the magnetic memory device according to the embodiment will be described.

[0022] 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array according to an embodiment. In FIG. 2, each of the word lines WL, the first bit lines BL1, and the second bit lines BL2 is classified and indicated by a subscript including an index (“<>”).

[0023] The memory cell array 10 includes a plurality of memory cells MC, a plurality of word lines WL, a plurality of first bit lines BL1, and a plurality of second bit lines BL2. In the example of FIG. 2, the plurality of memory cells MC are (M+1)×(N+1) memory cells MC<0,0>, MC<0,1>, ..., MC<0,N>, MC<1,0>, ..., and MC<M,N> (M and N are integers of 2 or more). In the example of FIG. 2, M and N are integers of 2 or more, but this is not limiting. M and N may be 0 or 1. The plurality of word lines WL includes (M+1) word lines WL <0> , W.L. <1> , …, and WL <m>The plurality of first bit lines BL1 includes (N+1) first bit lines BL1 <0> , WBL <1> , …, and WBL <n>The plurality of second bit lines BL2 includes (N+1) second bit lines BL2 <0> , RBL <1> , …, and RBL <n>Includes:

[0024] A plurality of memory cells MC are arranged in a matrix in the memory cell array 10. Each memory cell MC is associated with one of a plurality of word lines WL and a pair of a first bit line BL1 and a second bit line BL2 among a plurality of first bit lines BL1 and a plurality of second bit lines BL2. That is, the memory cell MC<i,j> (0≦i≦M, 0≦j≦N) are the word lines WL , first bit line BL1 <j>, and the second bit line BL2 <j>is connected to.

[0025] Memory cell MC<i,j> is the word line WL a first end connected to the first bit line BL1; <j>and a second end connected to the second bit line BL2. <j>and a third terminal connected to the memory cell MC.<i,j> , switching element SEL1<i,j> and SEL2<i,j> , magnetoresistive element MTJ<i,j> , and wiring SOTL<i,j> Includes:

[0026] Wiring SOTL<i,j> The wiring SOTL includes a first portion, a second portion, and a third portion between the first portion and the second portion.<i,j> The first part of the word line WL Connected to Wiring SOTL<i,j> The second part of the first bit line BL1 <j>Connected to Wiring SOTL<i,j> The third part of the second bit line BL2 <j>Switching element SEL1<i,j> is wiring SOTL<i,j> and the second part of the first bit line BL1 <j>The magnetoresistive element MTJ is connected between the<i,j> is wiring SOTL<i,j> and the second bit line BL2 <j>The switching element SEL2 is connected between the<i,j> is a magnetoresistive element (MTJ)<i,j> and the second bit line BL2 <j>and are connected between.

[0027] The switching elements SEL1 and SEL2 are two-terminal switching elements. Two-terminal switching elements differ from three-terminal switching elements such as transistors in that they do not include a third terminal. When the voltage applied between the two terminals is less than the threshold voltages Vth1 and Vth2, respectively, the switching elements SEL1 and SEL2 are in a "high-resistance" state or "off" state, e.g., an electrically non-conductive state. When the voltage applied between the two terminals is equal to or greater than the threshold voltages Vth1 and Vth2, respectively, the switching elements SEL1 and SEL2 are in a "low-resistance" state or "on" state, e.g., an electrically conductive state. More specifically, for example, when the voltage applied to the corresponding memory cell MC is less than the threshold voltages Vth1 and Vth2, the switching elements SEL1 and SEL2 function as an insulator with a high resistance and block current (become an off state). When the voltage applied to the corresponding memory cell MC is greater than the threshold voltages Vth1 and Vth2, the switching elements SEL1 and SEL2 function as a conductor with a low resistance and pass current (become an on state). The switching elements SEL1 and SEL2 switch between passing and blocking current depending on the magnitude of the voltage applied to the corresponding memory cell MC, regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current).

[0028] The wiring SOTL is a current path in the memory cell MC. For example, when the switching element SEL1 is in an on state and the switching element SEL2 is in an off state, the wiring SOTL functions as a current path between the word line WL and the first bit line BL1. Also, for example, when the switching element SEL1 is in an off state and the switching element SEL2 is in an on state, a part of the wiring SOTL functions as a current path between the word line WL and the second bit line BL2.

[0029] The magnetoresistive element MTJ is a resistance change element. The magnetoresistive element MTJ can switch its resistance value between a low resistance state and a high resistance state based on a current whose path is controlled by the switching elements SEL1 and SEL2. The magnetoresistive element MTJ functions as a memory element that stores data nonvolatilely by changing its resistance state.

[0030] 1.3 Magnetoresistive element and surrounding wiring Next, the configuration of the magnetoresistive effect element and peripheral wiring of the magnetic memory device according to the embodiment will be described.

[0031] 3 is a cross-sectional view showing the cross-sectional structure of the magnetoresistive element and surrounding wiring according to the embodiment. As shown in FIG. 3, the wiring SOTL includes a conductive layer 20. The magnetoresistive element MTJ includes a stacked structure 30. The stacked structure 30 includes a ferromagnetic layer 31, a non-magnetic layer 32, a ferromagnetic layer 33, a non-magnetic layer 34, and a ferromagnetic layer 35.

[0032] Hereinafter, the stacking direction of the stacked structure 30 is referred to as the Z direction. A plane perpendicular to the Z direction is referred to as the XY plane. In the XY plane, the direction in which the conductive layer 20 extends is referred to as the X direction. In the XY plane, the direction intersecting the X direction is referred to as the Y direction.

[0033] First, the configuration of the conductive layer 20 will be described.

[0034] The conductor layer 20 is a conductive film containing a nonmagnetic heavy metal. The heavy metal in the conductor layer 20 includes at least one element selected from the group consisting of tantalum (Ta), tungsten (W), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and manganese (Mn). The element contained as a heavy metal in the conductor layer 20 may include an oxide. Furthermore, when tantalum (Ta) or tungsten (W) is contained, the structure of the element is preferably a β structure. The conductor layer 20 generates a spin orbit torque (SOT) due to the bulk spin Hall effect when a current flows therethrough. The conductor layer 20 may also generate a spin effect due to the spin splitter effect. The spin orbit torque acts on the ferromagnetic layer 31.

[0035] Next, the configuration of the laminated structure 30 will be described.

[0036] A ferromagnetic layer 31 is provided in the central portion on the upper surface of the conductive layer 20. The ferromagnetic layer 31 is a conductive film having ferromagnetic properties. The ferromagnetic layer 31 is used as a storage layer. The ferromagnetic layer 31 has an easy axis of magnetization in a direction perpendicular to the film surface (Z direction). The ferromagnetic layer 31 is subjected to a spin-orbit torque generated in the conductive layer 20. When a spin-orbit torque of a predetermined magnitude is applied, the magnetization direction of the ferromagnetic layer 31 is configured to be reversed.

[0037] The ferromagnetic layer 31 is generally a ferromagnetic layer using at least one element selected from cobalt (Co), iron (Fe), and nickel (Ni). Typical ferromagnetic layers with perpendicular magnetization include cobalt-iron (CoFe) alloy, iron (Fe), cobalt-iron-boron (CoFeB), iron-boron (FeB), cobalt-boron (CoB), and cobalt-iron-nickel-boron (CoFeNiB). These have a body-centered cubic (BCC) structure. Elements such as phosphorus (P) and carbon (C) can be used instead of boron (B). Magnetic materials such as CoFeB generate perpendicular magnetic anisotropy at the interface when in contact with an oxide having a NaCl (001) structure. A typical example is an MgO (001) / CoFeB stacked structure.

[0038] The ferromagnetic layer 31 further contains a noble metal. The noble metal in the ferromagnetic layer 31 includes at least one element selected from, for example, gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os). Among these, platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os) are preferred. Furthermore, from the viewpoint of improving the VCMA effect described below, iridium (Ir) is most preferred. The noble metal preferably accounts for 50 at % or less of the ferromagnetic layer 31. If the noble metal is contained in the ferromagnetic layer 31 at more than 50 at %, the magnetic properties of the ferromagnetic layer 31 may be deteriorated. That is, if the ferromagnetic layer 31 contains more than 50 at % of the noble metal, there is a possibility that the saturation magnetization Ms and magnetic anisotropy energy Ku of the ferromagnetic layer 31 will be extremely reduced. Furthermore, it is more preferable that the concentration of the noble metal in the ferromagnetic layer 31 has a concentration gradient that is higher on the side closer to the nonmagnetic layer 32. This concentration gradient can be detected by nano-EDX (Energy Dispersive X-ray spectroscopy) analysis, nano-EELS (Electron Energy Loss Spectroscopy), or the like.

[0039] The ferromagnetic layer 31 has the function of generating the VCMA (Voltage-Controlled Magnetic Anisotropy) effect at the interface with the nonmagnetic layer 32 as described above. The VCMA effect is a phenomenon in which the energy barrier Eb required for magnetization reversal of a magnetic material is changed by applying a voltage. While the VCMA effect physically changes the energy barrier Eb, when measuring the VCMA effect, the change in the coercive force Hc of the ferromagnetic layer 31 is measured as a measurement parameter. A decrease in the coercive force Hc means a decrease in the energy barrier Eb. The noble metal contained in the ferromagnetic layer 31 can enhance the VCMA effect.

[0040] A nonmagnetic layer 32 is provided on the upper surface of the ferromagnetic layer 31. The nonmagnetic layer 32 is a nonmagnetic insulating film. The nonmagnetic layer 32 is used as a tunnel barrier layer. The nonmagnetic layer 32 is provided between the ferromagnetic layer 31 and the ferromagnetic layer 33 and forms a magnetic tunnel junction with these two ferromagnetic layers. When an initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic layer 31, the nonmagnetic layer 32 functions as a seed material that serves as a nucleus for growing a crystalline film from the interface with the ferromagnetic layer 31 during the crystallization process of the ferromagnetic layer 31. Similarly, when cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic layer 33, the nonmagnetic layer 32 also functions as a seed material for the ferromagnetic layer 33. Here, the initial amorphous layer is a layer that is amorphous immediately after deposition and crystallizes after annealing. The non-magnetic layer 32 has a tetragonal or cubic structure with the film surface oriented in the (001) plane. Examples of oxides used for the non-magnetic layer 32 include magnesium oxide (MgO). Magnesium oxide (MgO) has a NaCl structure. When magnesium oxide (MgO) is used for the non-magnetic layer 32, the (001) interface of magnesium oxide (MgO) and the (001) interface of cobalt iron boron (CoFeB) are aligned and crystal growth occurs during annealing. Therefore, cobalt iron boron (CoFeB) has a (001)-oriented body-centered cubic structure. The non-magnetic layer 32 may be made of a material other than magnesium oxide (MgO). In this case, a non-magnetic layer with a large VCMA coefficient β, which will be described later, is desirable. A large VCMA coefficient β can enhance the VCMA effect.

[0041] A ferromagnetic layer 33 is provided on the upper surface of the nonmagnetic layer 32. The ferromagnetic layer 33 is a conductive film having ferromagnetic properties. The ferromagnetic layer 33 is used as a reference layer. The ferromagnetic layer 33 has an easy axis of magnetization in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 33 is fixed. In the example of FIG. 3, the magnetization direction of the ferromagnetic layer 33 is oriented in a direction from the conductive layer 20 toward the stacked structure 30. Note that "the magnetization direction is fixed" means that the magnetization direction does not change even when a torque large enough to reverse the magnetization direction of the ferromagnetic layer 31 is applied. Typically, an interface layer is used for the ferromagnetic layer 33. An initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer for the ferromagnetic layer 33. Furthermore, an auxiliary ferromagnetic layer is provided in contact with the surface of the cobalt iron boron (CoFeB) layer opposite the surface in contact with the magnesium oxide (MgO) layer. The auxiliary ferromagnetic layer includes, for example, at least one alloy film selected from cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). The auxiliary ferromagnetic layer has a stacked structure such as a Co / Pt stacked structure or a Co / Pd stacked structure. The cobalt iron boron (CoFeB) layer serving as the initial amorphous layer is stacked with the CoPt, CoPd, Co / Pt stacked structure, or Co / Pd stacked structure. In this case, the interface layer of the ferromagnetic layer 33, for example the CoFeB layer, has (001)-oriented MgO formed closer to the nonmagnetic layer 32 than the other layers.

[0042] A non-magnetic layer 34 is provided on the upper surface of the ferromagnetic layer 33. The non-magnetic layer 34 is a conductive film having non-magnetic properties. The non-magnetic layer 34 is used as a spacer layer. The non-magnetic layer 34 is made of, for example, an element selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr), or an alloy thereof. For example, the thickness of the non-magnetic layer 34 is 2 nm or less.

[0043] A ferromagnetic layer 35 is provided on the upper surface of the nonmagnetic layer 34. The ferromagnetic layer 35 is a conductive film having ferromagnetic properties. The ferromagnetic layer 35 is used as a shift canceling layer. The ferromagnetic layer 35 has an easy axis of magnetization in a direction perpendicular to the film surface (Z direction). The ferromagnetic layer 35 includes, for example, at least one alloy layer selected from cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). The ferromagnetic layer 35 may also have a stacked structure such as a Co / Pt stacked structure or a Co / Pd stacked structure.

[0044] The ferromagnetic layer 33 and the ferromagnetic layer 35 are antiferromagnetically coupled by the nonmagnetic layer 34. That is, the ferromagnetic layer 33 and the ferromagnetic layer 35 are coupled so that their magnetization directions are antiparallel to each other. Such a coupled structure of the ferromagnetic layer 33, the nonmagnetic layer 34, and the ferromagnetic layer 35 is called an SAF (Synthetic Anti-Ferromagnetic) structure. With the SAF structure, the ferromagnetic layer 35 offsets the effect of the stray magnetic field of the ferromagnetic layer 33 on the change in the magnetization direction of the ferromagnetic layer 31, thereby substantially reducing the stray magnetic field of the ferromagnetic layer 33.

[0045] The magnetoresistive element MTJ can be in either a low resistance state or a high resistance state depending on whether the magnetization directions of the storage layer and the reference layer are parallel or antiparallel. In the embodiment, the magnetization direction of the storage layer relative to the magnetization direction of the reference layer is controlled without passing a write current through the magnetoresistive element MTJ. Specifically, a write method is adopted that utilizes spin-orbit torque generated by passing a current through the wiring SOTL.

[0046] When a write current Ic0 of a certain magnitude is passed through the wiring SOTL in the X direction, the relative relationship between the magnetization directions of the storage layer and the reference layer becomes parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ becomes the lowest, and the magnetoresistive element MTJ is set to a low resistance state. This low resistance state is called the "P (Parallel) state" and is defined as, for example, the data "0" state.

[0047] Furthermore, when a write current Ic1 flows through the wiring SOTL in the opposite direction to the write current Ic0, the relative relationship between the magnetization directions of the storage layer and the reference layer becomes anti-parallel. In this anti-parallel state, the resistance value of the magnetoresistive element MTJ becomes the highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state" and is defined as, for example, the data "1" state.

[0048] The way in which data "1" and data "0" are defined is not limited to the above example. For example, the P state may be defined as data "1" and the AP state may be defined as data "0."

[0049] The shape of the magnetoresistive element MTJ as viewed from the Z direction is elliptical or circular. From the viewpoint of high-density integration of memory cells MC, the shape of the magnetoresistive element MTJ as viewed from the Z direction is preferably circular. From the viewpoint of reducing the area and power consumption, the short side length of the magnetoresistive element MTJ when it is elliptical and the radius of the magnetoresistive element MTJ when it is circular are preferably 100 nm or less.

[0050] 1.2 Write Operation Next, the write operation of the magnetic memory device according to the embodiment will be described.

[0051] 1.2.1 SOT period and relaxation period 4 is a waveform diagram showing an example of magnetization reversal of the memory layer during a write operation in the magnetic memory device according to the embodiment. In the example of Fig. 4, the time change of the Z-direction component mz when the magnetization of the memory layer is expressed as a unit vector is plotted on the vertical axis and time on the horizontal axis, and the example of Fig. 4 shows the time change of the Z-direction component mz.

[0052] In the following, for convenience of explanation, the state of the Z-direction component mz=1 indicates a state in which the magnetization direction of the memory layer is oriented toward the reference layer in the Z direction. The state of the Z-direction component mz=-1 indicates a state in which the magnetization direction of the memory layer is oriented toward the wiring SOTL in the Z direction. That is, when the magnetization direction of the reference layer is the same as that in FIG. 3, FIG. 4 shows how the magnetization direction of the memory layer is reversed by a write operation so that the state of the magnetoresistive element MTJ changes from the P state to the AP state.

[0053] 4, the write operation mainly includes an SOT period and a relaxation period following the SOT period. In the example of FIG. 4, the Z-direction component mz of the magnetization direction of the storage layer is assumed to be "1" until time T10. Then, the SOT period starts from time T10.

[0054] The SOT period is a period during which spin-orbit torque is applied to the storage layer. The spin-orbit torque acting on the storage layer can orient the magnetization direction of the storage layer in a substantially horizontal direction. When the spin-orbit torque is applied to the storage layer, a bias magnetic field Hx is also applied in the X direction to the wiring SOTL. This allows the Z-direction component mz of the magnetization direction of the storage layer to have a polarity opposite to the polarity of the Z-direction component before the SOT period (a negative Z-direction component in the example of Figure 4). That is, during the SOT period, the magnetization direction of the storage layer, which had a component parallel to the magnetization direction of the reference layer before the write operation, tilts to have a component antiparallel to the magnetization direction of the reference layer.

[0055] In this embodiment, a positive VCMA effect is generated in the memory layer during the SOT period. This reduces the time D1 required for the Z-direction component mz of the magnetization direction of the memory layer to change from "1" to a negative value close to "0." The positive VCMA effect will be described later.

[0056] Next, a relaxation period begins at time T20. The relaxation period is a period during which the action of the spin-orbit torque on the storage layer is stopped and the magnetization direction of the storage layer is stabilized in the Z direction (parallel or anti-parallel to the magnetization direction of the reference layer). As described above, the storage layer has an easy axis of magnetization in the Z direction. Therefore, the magnetization direction of the storage layer, which was forced to be approximately horizontal by the spin-orbit torque, is oriented in the Z direction by stopping the action of the spin-orbit torque on the storage layer.

[0057] As described above, the magnetization direction of the storage layer is tilted to have a component antiparallel to the magnetization direction of the reference layer after the SOT period. Therefore, during the relaxation period, the magnetization direction of the storage layer is likely to tilt in a direction antiparallel to the magnetization direction of the reference layer. Then, when the reversal of the magnetization direction of the storage layer is completed, the relaxation period ends.

[0058] In this embodiment, a negative VCMA effect is generated in the memory layer during the relaxation period. This reduces the time D2 required for the Z-direction component mz of the magnetization direction of the memory layer to tilt from a negative value close to "0" to "-1." The negative VCMA effect will be described later.

[0059] By the above-described write operation, data is written to the magnetoresistive element MTJ.

[0060] 1.2.2 Applied voltage (SOT period) 5 is a circuit diagram showing an example of voltages applied in a write operation in the magnetic memory device according to the embodiment. In the example of FIG. 5, among the multiple memory cells MC, memory cell MC<m,n> When data is written to the SOT period, an example of the voltages applied to various wirings is shown (0 <m<M、0<n<N)。

[0061] Memory cell MC<m,n> When data is written to the word line WL <m>and the first bit line BL1 <n>A voltage VDD or VSS is applied to each of the word lines WL. <m>When a voltage VDD is applied to the first bit line BL1 <n>A voltage VSS is applied to the word line WL. <m>When a voltage VSS is applied to the first bit line BL1 <n>A voltage VDD is applied to the second bit line BL2. <n>A voltage V1 (=VDD / 2+Vg1) is applied to the word line WL. Here, Vg1 is a positive real number. <m>All word lines WL other than the first bit line BL1 <n>All the first bit lines BL1 and second bit lines BL2 other than <n>A voltage VDD / 2 is applied to all the second bit lines BL2 other than the first bit line BL1.

[0062] As a result, the word line WL <m>and the first bit line BL1 <n>In this case, a potential difference VDD occurs between the wiring SOTL<m,n> Magnetoresistive effect element MTJ<m,n> The potential at the connection point of the second bit line BL2 is VDD / 2. <n>Includes wiring SOTL<m,n> A positive potential difference Vg1 (>0) occurs relative to

[0063] Also, the word line WL <m>and the first bit line BL1 <n>A potential difference VDD / 2 occurs between any first bit line BL1 and the word line WL. <m>Any word line WL and the first bit line BL1 <n>A potential difference of VDD / 2 occurs between the word line WL <m>Any word line WL and the first bit line BL1 <n>No potential difference occurs between any first bit line BL1 and the wiring SOTL.<m,n> and the second bit line BL2 <n>The potential difference occurring between any pair of the wiring SOTL and the second bit line BL2 other than this pair is less than |Vg1|.

[0064] Here, the voltage VSS is a reference potential. The voltage VSS is, for example, 0 V. A voltage VDD (potential difference VDD) relative to the voltage VSS turns on the switching elements SEL1 and SEL2. A potential difference VDD / 2 turns off the switching element SEL1. A voltage V1 (potential difference Vg1) relative to the voltage VDD / 2 turns on the switching element SEL2. Wiring SOTL<m,n> and the second bit line BL2 <n>A potential difference occurring between any pair of the wiring SOTL and the second bit line BL2 other than the pair turns off the switching element SEL2.

[0065] Therefore, the switching element SEL1<m,n> and SEL2<m,n> The switching element SEL1 is turned on.<m,n> All switching elements SEL1 except for switching element SEL2 are in the OFF state.<m,n> All the switching elements SEL2 except for SEL1 are in the OFF state.

[0066] Therefore, wiring SOTL<m,n> While applying a potential difference VDD to the magnetoresistive element MTJ<m,n> A potential difference Vg1 can be applied to the wiring SOTL. By applying a potential difference VDD to the wiring SOTL, a current can be passed to change the resistance state of the magnetoresistive element MTJ. By applying a positive potential difference Vg1 to the magnetoresistive element MTJ, a positive VCMA effect can be generated in the memory layer. Note that, by turning on the switching element SEL2, the magnetoresistive element MTJ<m,n> Although a current flows through the electrode, the amount of the current is so small that it can be ignored.

[0067] During the above-mentioned SOT period, the memory cell MC<m,n> This state is also called a selected state.<m-1,n> , M.C.<m+1,n> ~MC<M,n> , M.C.<m,0> ~MC<m,n-1> , and M.C.<m,n+1> ~MC<m,N> The state of all memory cells MC that are not in the selected state or the half-selected state is also called a non-selected state. (Relaxation period) 6 is a circuit diagram showing an example of voltages applied in a write operation in the magnetic memory device according to the embodiment. In the example of FIG. 6, among the multiple memory cells MC, memory cell MC<m,n> 1 shows an example of voltages applied to various wirings during the relaxation period when data is written to the memory cell.

[0068] Memory cell MC<m,n> When data is written to the word lines WL, the first bit lines BL1, and the second bit lines BL <n>A voltage VDD / 2 is applied to all second bit lines BL2 except for the second bit lines BL2. <n>A voltage V2 (=VDD / 2+Vg2) is applied to the output terminals VDD and VDD+Vg2, where Vg2 is a negative real number.

[0069] As a result, all the word lines WL and all the first bit lines BL1 <n>Therefore, no potential difference occurs between the second bit line BL2 <n>No potential difference occurs in any of the second bit lines BL2 except for the second bit line BL2. <n>The wiring SOTL<0,n>, ..., SOTL<m,n> , …, and SOTL<M,n> A negative potential difference Vg2 (<0) is generated for each of the electrodes.

[0070] Here, the voltage V2 (potential difference Vg2) relative to the voltage VDD / 2 turns on the switching element SEL2.

[0071] Therefore, all the switching elements SEL1 are in the OFF state.<m,n> , ..., and SEL2<M,n> The switching elements SEL2<0, n>, ..., SEL2<m,n> , ..., and SEL2<M,n> All the switching elements SEL2 except for SEL1 are in the OFF state.

[0072] Therefore, wiring SOTL<m,n> Without generating a potential difference between the magnetoresistive element MTJ<m,n> By applying a negative potential difference Vg2 to the magnetoresistive element MTJ, a negative VCMA effect can be generated in the memory layer.

[0073] During the relaxation period, the memory cells MC<0, n>, . . . , MC<m,n> , …, and MC<M,n> The state of all memory cells MC that are not in the relaxed state is also called the unselected state.

[0074] 1.2.3 VCMA effect 7 is a diagram showing an example of the VCMA effect occurring in the memory layer during a write operation in a magnetic memory device according to the embodiment. In FIG. 7, the horizontal axis represents the relative angle of the magnetization direction vector between the memory layer and the reference layer (the magnetization direction of the memory layer relative to the magnetization direction of the reference layer), and the vertical axis represents the free energy curve of the memory layer, showing the change in the free energy curve of the memory layer depending on whether or not the VCMA effect occurs. Specifically, the solid line L0 corresponds to the case where the VCMA effect does not occur. The dotted line L1 corresponds to the case where a positive VCMA effect occurs. The dashed-dotted line L2 corresponds to the case where a negative VCMA effect occurs.

[0075] As shown in FIG. 7, the free energy curve of the storage layer is low when the magnetization direction of the storage layer is parallel or antiparallel to the magnetization direction of the reference layer. This corresponds to the fact that the magnetoresistive element MTJ is stable when it is in the P state or AP state. On the other hand, the free energy curve of the storage layer is maximum when the magnetization direction of the storage layer is oriented horizontally. This corresponds to the existence of an energy barrier Eb when the state of the magnetoresistive element MTJ changes from the P state to the AP state or from the AP state to the P state. The energy barrier Eb is also called perpendicular magnetic anisotropy energy.

[0076] The energy barrier Eb is expressed as follows using the potential difference Vg applied to the magnetoresistive element MTJ:

[0077] Eb(Vg)=Eb(0)-βVg / t where β is a VCMA coefficient, which is a real coefficient, and t is the thickness of the tunnel barrier layer.

[0078] As shown by the solid line L0 and the dotted line L1, when a positive potential difference Vg1 is applied to the magnetoresistive element MTJ (i.e., to the second bit line BL2 relative to the connection portion of the wiring SOTL with the magnetoresistive element MTJ), the energy barrier Eb(Vg1) becomes lower than the energy barrier Eb(0). This reduces the energy required for magnetization reversal of the memory layer, thereby facilitating magnetization reversal of the memory layer. In this embodiment, modulation of the energy barrier Eb that promotes magnetization reversal of the memory layer is called a positive VCMA effect.

[0079] On the other hand, as shown by the solid line L0 and the dashed-dotted line L2, when a negative potential difference Vg2 is applied to the magnetoresistive element MTJ (i.e., to the second bit line BL2 with respect to the connection portion of the wiring SOTL with the magnetoresistive element MTJ), the energy barrier Eb(Vg2) becomes higher than the energy barrier Eb(0). This makes it possible to increase the energy required for magnetization reversal of the memory layer, thereby suppressing magnetization reversal of the memory layer. In this embodiment, modulation of the energy barrier Eb so as to suppress magnetization reversal of the memory layer is called the negative VCMA effect.

[0080] 1.2.4 Magnetization reversal 8 and 9 are cross-sectional views showing an example of a write operation in a magnetic memory device according to the embodiment. FIGS. 8(A) and 9(A) schematically show the current flowing through a memory cell MC in a selected state during the SOT period and the change in the magnetization direction of the magnetoresistive element MTJ. FIGS. 8(B) and 9(B) schematically show the change in the magnetization direction of the magnetoresistive element MTJ in a relaxed state during the relaxation period. FIG. 8 corresponds to a write operation when writing data "1". FIG. 9 corresponds to a write operation when writing data "0".

[0081] First, the write operation of data "1" will be described with reference to Fig. 8. In the example of Fig. 8, a write current Ic1 flows from the word line WL (right side of the paper) to the first bit line BL1 (left side of the paper).

[0082] As shown in FIG. 8A, during the SOT period, a potential difference VDD is generated across the wiring SOTL, which turns on the switching element SEL1. By controlling the potential difference VDD, a write current Ic1 flows in the wiring SOTL. When the write current Ic1 flows in the wiring SOTL, a spin-orbit torque is generated that tries to make the magnetization direction of the storage layer horizontal. The spin-orbit torque acts on the storage layer adjacent to the wiring SOTL. Although not shown in FIG. 8, a bias magnetic field Hx in the X direction is applied to the storage layer.

[0083] Therefore, the magnetization direction of the storage layer is tilted in a direction that is substantially horizontal and has a component antiparallel to the magnetization direction of the reference layer due to the spin-orbit torque and the application of the bias magnetic field Hx.

[0084] In addition, a potential difference Vg1 is generated across both ends of the magnetoresistive element MTJ so that the reference layer side has a higher potential than the memory layer side. This generates a positive VCMA effect, lowering the energy barrier Eb of the memory layer. As a result, the magnetization direction of the memory layer is quickly tilted with the assistance of the positive VCMA effect.

[0085] Next, as shown in Figure 8(b), during the relaxation period, no potential difference occurs between both ends of the wiring SOTL. This stops the write current Ic1 and the effect of the spin-orbit torque disappears. During the SOT period, the state of the storage layer transitions from the P state to the AP state by crossing the energy barrier Eb. Therefore, during the relaxation period, the magnetization direction of the storage layer tilts to a more stable state in the AP state (i.e., a state completely antiparallel to the magnetization direction of the reference layer).

[0086] In addition, a potential difference Vg2 is generated across both ends of the magnetoresistive element MTJ so that the reference layer side is at a lower potential than the memory layer side. This generates a negative VCMA effect, raising the energy barrier Eb of the memory layer. As a result, the magnetization direction of the memory layer tilts more quickly with the assistance of the negative VCMA effect.

[0087] By performing the above operation, the magnetization direction of the storage layer is reversed to a direction antiparallel to the magnetization direction of the reference layer, and the operation of writing data "1" is completed.

[0088] Next, a write operation of data "0" will be described with reference to Fig. 9. In the example of Fig. 9, a write current Ic0 flows from the first bit line BL1 (left side of the paper) to the word line WL (right side of the paper).

[0089] As shown in FIG. 9A, during the SOT period, a potential difference VDD is generated across the wiring SOTL, which turns on the switching element SEL1. By controlling the potential difference VDD, a write current Ic0 flows in the wiring SOTL. When the write current Ic0 flows in the wiring SOTL, a spin-orbit torque is generated that tries to make the magnetization direction of the storage layer horizontal. The spin-orbit torque acts on the storage layer adjacent to the wiring SOTL. Although not shown in FIG. 9, a bias magnetic field Hx in the X direction is applied to the storage layer.

[0090] Therefore, the magnetization direction of the storage layer is tilted in a direction that is substantially horizontal and has a component parallel to the magnetization direction of the reference layer due to the spin-orbit torque and the application of the bias magnetic field Hx.

[0091] In addition, a potential difference Vg1 is generated across both ends of the magnetoresistive element MTJ so that the reference layer side has a higher potential than the memory layer side. This generates a positive VCMA effect, lowering the energy barrier Eb of the memory layer. As a result, the magnetization direction of the memory layer is quickly tilted with the assistance of the positive VCMA effect.

[0092] Next, as shown in Figure 9(b), during the relaxation period, no potential difference occurs between both ends of the wiring SOTL. This stops the write current Ic0 and the effect of the spin-orbit torque disappears. During the SOT period, the state of the storage layer transitions from the AP state to the P state by crossing the energy barrier Eb. Therefore, during the relaxation period, the magnetization direction of the storage layer tilts to a more stable state in the P state (i.e., a state completely parallel to the magnetization direction of the reference layer).

[0093] In addition, a potential difference Vg2 is generated across both ends of the magnetoresistive element MTJ so that the reference layer side is at a lower potential than the memory layer side. This generates a negative VCMA effect, raising the energy barrier Eb of the memory layer. As a result, the magnetization direction of the memory layer tilts more quickly with the assistance of the negative VCMA effect.

[0094] By operating as described above, the magnetization direction of the memory layer is reversed in a direction parallel to the magnetization direction of the reference layer, and the write operation of data "0" is completed.

[0095] 1.2.5 Applied Pattern of Potential Difference Vg FIG. 10 is a waveform diagram showing a first example of the potential difference applied to the magnetoresistive effect element in the write operation of the magnetic memory device according to the embodiment. FIG. 11 is a waveform diagram showing a second example of the potential difference applied to the magnetoresistive effect element in the write operation of the magnetic memory device according to the embodiment. FIG. 12 is a waveform diagram showing a third example of the potential difference applied to the magnetoresistive effect element in the write operation of the magnetic memory device according to the embodiment.

[0096] As shown in FIG. 10, the potential difference Vg1 may start to be applied at the start of the SOT period and end at the end of the SOT period. The potential difference Vg2 may start to be applied at the start of the relaxation period and end at the end of the relaxation period. Also, the absolute values of each of the potential differences Vg1 and Vg2 may be equal or different.

[0097] As shown in FIG. 11, the potential difference Vg1 may start to be applied at the start of the SOT period and end at time T15 (T10 < T15 < T20) during the SOT period. The potential difference Vg2 may start to be applied (at time T15) at the end of the application of the potential difference Vg1 and end at the end of the relaxation period.

[0098] As shown in FIG. 12, the potential difference Vg1 may start to be applied at the start of the SOT period. The potential difference Vg2 may end to be applied at the end of the relaxation period. And the potential difference may be continuously changed from the start of the application of the potential difference Vg1 to the end of the application of the potential difference Vg2.

[0099] 1.3 Effects According to the Embodiment The magnetic memory device 1 according to the embodiment employs a write method that utilizes spin-orbit torque. In this case, the magnetization direction of the storage layer tilts horizontally during the SOT period and then completely reverses during the relaxation period. In particular, because the magnetization direction changes during the relaxation period without relying on spin-orbit torque, it may take a long time for the magnetization direction to reverse.

[0100] According to the embodiment, in a write operation, the write circuit 14 passes a write current through the wiring SOTL during the SOT period. Furthermore, the write circuit 14 stops the write current during the relaxation period and applies a negative potential difference Vg2 between the first terminal of the magnetoresistive element MTJ, which is connected to the wiring SOTL, and the second terminal. This significantly increases the energy barrier Eb of the storage layer during the relaxation period. Therefore, the magnetization direction of the storage layer, which was tilted horizontally during the SOT period, can be quickly reversed. This reduces the write time.

[0101] Furthermore, the magnetization direction fluctuates due to the influence of thermal disturbance. As a result, the magnetization direction of the storage layer, which was tilted horizontally during the SOT period, may return to its original direction. According to the embodiment, the energy barrier Eb of the storage layer can be significantly increased during the relaxation period. This makes it difficult for the magnetization direction of the storage layer, which was tilted horizontally, to return to its original direction. Therefore, write errors can be reduced.

[0102] 2. Modifications, etc. The above-described embodiment is not limited to the above-described example, and various modifications are possible.

[0103] In the above embodiment, the case where the potential difference Vg1 is applied to the magnetoresistive element MTJ during the SOT period has been described, but the present invention is not limited to this.

[0104] Fig. 13 is a waveform diagram showing a fourth example of the potential difference applied to the magnetoresistive effect element in a write operation in the magnetic memory device according to the modification. Fig. 14 is a waveform diagram showing a fifth example of the potential difference applied to the magnetoresistive effect element in a write operation in the magnetic memory device according to the embodiment. Figs. 13 and 14 correspond to Figs. 10 and 11 in the embodiment, respectively.

[0105] 13 and 14, the potential difference Vg1 may be 0. Even in this case, it is possible to shorten the relaxation period and suppress the occurrence of write errors during the relaxation period.

[0106] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0107] 1...Magnetic memory device 10...Memory cell array 11...Row selection circuit 12...Column selection circuit 13...Decoding circuit 14...Write circuit 15...Readout circuit 16...Voltage generation circuit 17...Input / output circuit 18...Control circuit 20...Conductive layer 30…Laminated structure 31,33,35...Ferromagnetic layer 32,34...Nonmagnetic layer< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / m>

Claims

1. a conductive layer extending in a first direction; a magnetoresistive element stacked in a second direction intersecting the first direction, the magnetoresistive element having a first end in contact with the conductive layer and a second end not in contact with the conductive layer; a control circuit for writing data to the magnetoresistive element; Equipped with In a write operation, the control circuit A current is passed through the conductive layer during a first period; During a second period following the first period, the current is stopped and a negative first potential difference is applied to the second terminal relative to the first terminal. It was configured as follows: Magnetic memory device.

2. In the write operation, the control circuit further applying a second potential difference that is positive to the second terminal relative to the first terminal during the first period; It was configured as follows:

10. The magnetic memory device of claim 1.

3. the first period has a first sub-period and a second sub-period following the first sub-period; In the write operation, the control circuit The current is passed through the conductive layer during the first period; During the second period, the current is stopped; applying a negative potential difference to the second terminal relative to the first terminal during the second sub-period and the second period; It was configured as follows:

3. The magnetic memory device of claim 2.

4. In the write operation, the control circuit The potential difference applied to the second terminal relative to the first terminal is continuously changed from the second potential difference to the first potential difference over the first period to the second period. It was configured as follows: The memory device of claim 2 .

5. In the write operation, the control circuit During the first period, the potential difference between the first terminal and the second terminal is set to approximately 0. It was configured as follows:

10. The magnetic memory device of claim 1.

6. the first period has a first sub-period and a second sub-period following the first sub-period; In the write operation, the control circuit The current is passed through the conductive layer during the first period; During the second period, the current is stopped; In the first sub-period, a potential difference between the second terminal and the first terminal is set to approximately 0. It was configured as follows:

6. The magnetic memory device according to claim 5.

7. In the write operation, the control circuit When writing first data, the current is caused to flow in a direction parallel to the second direction; When writing second data different from the first data, the current is passed in a direction antiparallel to the second direction. It was configured as follows:

10. The magnetic memory device of claim 1.

8. the conductive layer contains at least one element selected from tantalum (Ta), tungsten (W), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and manganese (Mn); 10. The magnetic memory device of claim 1.

9. The magnetoresistive effect element is a first ferromagnetic layer in contact with the conductive layer; a second ferromagnetic layer provided on the opposite side of the first ferromagnetic layer from the conductive layer; a first nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer; Including, The first nonmagnetic layer contains magnesium oxide (MgO).

10. The magnetic memory device of claim 1.

10. the first ferromagnetic layer contains at least one element selected from cobalt (Co), iron (Fe), and nickel (Ni); 10. The magnetic memory device of claim 9.

11. the first ferromagnetic layer further contains at least one element selected from gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os); 11. The magnetic memory device of claim 10.

12. The magnetoresistive effect element is a third ferromagnetic layer provided on the opposite side of the second ferromagnetic layer from the first ferromagnetic layer; a second nonmagnetic layer provided between the second ferromagnetic layer and the third ferromagnetic layer; Further comprising: the second nonmagnetic layer contains at least one element selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr); 10. The magnetic memory device of claim 9.

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