Indication device

Abstract

To provide a display device with a narrow frame and excellent design, which can be manufactured at low cost. [Solution] The display device includes a substrate, at least one pixel on the substrate, at least one pad on the substrate, and routing wiring. The at least one pad is configured to be electrically connected to a semiconductor element provided on the semiconductor substrate. The routing wiring electrically connects the at least one pixel to the at least one pad. The at least one pixel has a transistor, a planarization film on the transistor, and a display element located on the planarization film and electrically connected to the transistor. The semiconductor element has a circuit configured to drive the at least one pixel, a bump electrically connected to the circuit, and a dummy bump electrically independent from the circuit. The routing wiring is arranged to overlap the dummy bump via the planarization film when connecting the bump to the at least one pad.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] As display devices become larger and have higher definition, the driver circuits for driving the display devices are also required to operate at high speeds. For this reason, some display devices are equipped with a semiconductor element having an integrated circuit formed on a semiconductor substrate as part of the driver circuit (for example, the whole or part of a signal line driver circuit) (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-184061 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a display device having a novel structure, or to provide a display device with a narrow frame and excellent design that can be manufactured at low cost. [Means for solving the problem]

[0005] One embodiment of the present invention is a display device. The display device includes a substrate, at least one pixel on the substrate, at least one pad on the substrate, and routing wiring. The at least one pad is configured to be electrically connected to a semiconductor element provided on the semiconductor substrate. The routing wiring electrically connects the at least one pixel to the at least one pad. The at least one pixel includes a transistor, a planarization film on the transistor, and a display element located on the planarization film and electrically connected to the transistor. The semiconductor element includes a circuit configured to drive the at least one pixel, a bump electrically connected to the circuit, and a dummy bump electrically independent from the circuit. The routing wiring is arranged to overlap the dummy bump via the planarization film when connecting the bump to the at least one pad.

[0006] One embodiment of the present invention is a display device. The display device includes a substrate, at least one pixel on the substrate, at least one pad on the substrate, lead wiring, and a semiconductor element. The lead wiring electrically connects the at least one pixel to the at least one pad. The semiconductor element is electrically connected to the at least one pad and is provided on the semiconductor substrate. The at least one pixel includes a transistor, a planarization film on the transistor, and a display element located on the planarization film and electrically connected to the transistor. The semiconductor element includes a circuit configured to drive the at least one pixel, a bump electrically connected to the circuit, and a dummy bump electrically independent from the circuit. The lead wiring overlaps the dummy bump via the planarization film. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 2] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 3] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 4]1 is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present invention. [Figure 5] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 6] FIG. 2 is a schematic bottom view of a semiconductor element mounted on a display device according to an embodiment of the present invention. [Figure 7] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 8] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 9] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 10] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 11] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 12] 1 is a schematic end view of a display device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0009] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in the previous drawings may be given the same reference numerals, and duplicated explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures, and when these are individually represented, a hyphen and a natural number are added after the reference numeral.

[0010] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0011] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0012] In this specification and claims, the expression "a structure exposed from another structure" means a state in which a part of a structure does not overlap with another structure, and this part that does not overlap with another structure also includes a state in which the part overlaps with yet another structure. The state expressed by this expression also includes a state in which the structure is not in contact with the other structure.

[0013] 1. Overall configuration of the display device FIG. 1 shows a schematic top view of a display device 100 according to one embodiment of the present invention. The display device 100 shown in FIG. 1 is a liquid crystal display device and includes a substrate 102 and an opposing substrate (not shown in FIG. 1) facing the substrate 102. Various conductive films, semiconductor films, insulating films, and the like are patterned using a photolithography process and disposed between the substrate 102 and the opposing substrate. These conductive films, semiconductor films, insulating films, and the like are appropriately combined to form a plurality of pixels 120, each including a display element, and a gate line driving circuit 104 for driving the pixels. The plurality of pixels 120 and the area between adjacent pixels 120 are collectively referred to as the display area, and the area surrounding the display area is referred to as the frame area. The gate line driving circuit 104 is provided in the frame area. A semiconductor element 210 having a circuit (integrated circuit) formed on a semiconductor substrate is also mounted in the frame area as a signal line driving circuit. A flexible printed circuit board (hereinafter, FPC) 106 is electrically connected to the display device 100, and power and various control signals for displaying an image are input to the semiconductor element 210 and the gate line driving circuit 104 from an external circuit (not shown) via the FPC. The semiconductor element 210 and the gate line driving circuit 104 generate various signals for controlling the pixels based on these control signals and supply them to the pixels 120. This controls the pixels 120, allowing an image to be reproduced on the display area. Although not shown in FIG. 1 , various patterned conductive films are used to form signal lines for supplying video signals, initialization signals, etc. to the pixels 120, gate lines for supplying gate signals to the pixels 120, pads for mounting the semiconductor element 210, terminals for electrical connection of the FPC 106, and the like on the substrate 102.

[0014] In an optional configuration, the display device 100 can function as a touch panel. In this case, as shown in FIG. 2 , a plurality of detection electrodes 200 are arranged in a matrix having a plurality of rows and a plurality of columns on the display area. The plurality of detection electrodes 200 are electrically connected to each other in the row and column directions, and each detection electrode 200 is arranged so as to overlap a plurality of pixels 120. Each detection electrode 200 is electrically connected to a detection wiring (not shown in FIG. 2 ), thereby electrically connecting each detection electrode 200 to a semiconductor element 210 via the detection wiring. A pulsed AC potential is supplied from the semiconductor element 210 to the detection electrode 200 via the detection wiring, and potential fluctuations of the detection electrode 200 due to capacitive coupling caused by contact or proximity of an input means such as a finger or a touch pen are detected by the semiconductor element 210. This allows the coordinates of the input means on the display device 100 to be identified. As will be described later, the detection electrode 200 also functions as a common electrode for the display elements provided on the display device 100.

[0015] 1 and 3, the substrate 102 and the counter substrate 110 are fixed to each other by a sealant 108. The sealant 108 is formed so as to surround the display area, and a liquid crystal layer 166 is injected into the space formed by the substrate 102, the counter substrate 110, and the sealant 108. The FPC 106 and the semiconductor element 210 are fixed on the substrate 102 and exposed from the counter substrate 110.

[0016] 2. Pixel configuration FIG. 4 shows an equivalent circuit diagram of the pixel 120. Here, the equivalent circuit shows pixels 120 arranged in a matrix of 4 rows and 4 columns. In the example shown in FIG. 4, each pixel 120 includes a transistor (hereinafter, referred to as a switching transistor) 130, a capacitance element 128, and a display element 160. The gate of the switching transistor 130 is connected to a gate line 122 extending from the gate line driving circuit 104. One terminal of the switching transistor 130 is electrically connected to a signal line 124 extending from the semiconductor element 210, and the other terminal is connected to one electrode of the capacitance element 128 and a pixel electrode of the display element 160. A constant potential is supplied to the other electrode of the capacitance element 128. As described above, the detection electrode 200 functions as a common electrode for the display element 160. Therefore, the pixel electrode of the display element 160 (i.e., the detection electrode 200) is electrically connected to the detection wiring 202. During the display period of each pixel 120, a constant potential is applied to the detection electrode 200 via the detection wiring 202, and the gradation of the display element 160 is controlled by the potential difference between the pixel electrode 162 and the detection electrode 200. Meanwhile, a pulsed AC potential is supplied to the detection electrode 200 between the detectors, and is used to identify the coordinates of the input means. Note that the circuit configuration of each pixel 120 is not limited to the configuration shown in Fig. 4, and each pixel 120 can be configured by appropriately combining one or more transistors and one or more capacitive elements in addition to the display element 160.

[0017] FIG. 5 shows a schematic end view of a display device 100 including one pixel. As shown in FIG. 5, a switching transistor 130 is provided directly on the substrate 102 or on an undercoat 112 of any configuration. There are no restrictions on the configuration of the switching transistor 130, and it may be a bottom-gate transistor, a top-gate transistor, or a transistor having a pair of gate electrodes sandwiching a channel from above and below. In the example shown in FIG. 5, the switching transistor 130 is a top-gate transistor and includes a semiconductor film 132, a gate insulating film 134 on the semiconductor film 132, a gate electrode 136 overlapping the semiconductor film 132 via the gate insulating film 134, one or more interlayer insulating films (here, a first interlayer insulating film 138 and a second interlayer insulating film 140) covering the gate electrode 136, and a source electrode 142 and a drain electrode 144 electrically connected to the semiconductor film 132 through openings provided in the interlayer insulating films.

[0018] Two planarization films (a first planarization film 146 and a second planarization film 148) are provided on the switching transistor 130. The first planarization film 146 absorbs irregularities caused by the switching transistor 130, the capacitive element 128, and the like, forming a flat upper surface. A detection wiring 202 that supplies a potential to the detection electrode 200 extends over the first planarization film 146 from the semiconductor element 210 side, and the second planarization film 148 is formed to cover the detection wiring 202. The detection electrode 200 is formed on the second planarization film 148. The detection electrode 200 and the detection wiring 202 are electrically connected via an opening provided in the second planarization film 148.

[0019] The display element 160 shown in FIG. 5 is an IPS (In-Plain Switching) liquid crystal element, and the pixel electrode 162 is arranged in a comb-like shape or with one or more openings or slits. Therefore, although the pixel electrode 162 is depicted as being divided into multiple parts in FIG. 5 , these are physically and electrically connected to form a single pixel electrode 162 within each pixel 120. The pixel electrode 162 is electrically connected to the drain electrode 144 of the switching transistor 130 via openings provided in the first planarization film 146 and the second planarization film 148. An inter-electrode insulating film 150 is formed on the detection electrode 200, which also functions as a common electrode, to prevent electrical conduction between the detection electrode 200 and the pixel electrode 162. A first light distribution film 164, a liquid crystal layer 166, and a second alignment film 168 are sequentially provided on the pixel electrode 162 and the detection electrode 200, and the pixel electrode 162, the detection electrode 200, the first light distribution film 164, the liquid crystal layer 166, and the second alignment film 168 form the display element 160.

[0020] A light-shielding film 174 that covers the switching transistors 130 and the detection wiring 202 is provided on the counter substrate 110 (below the counter substrate 110 in FIG. 5). Although not shown in FIG. 5, the light-shielding film 174 is provided so as to overlap the gate lines 122, the signal lines 124, and the like. Meanwhile, a color filter 172 for providing color information is arranged in the region where the pixel electrode 162 and the detection electrode 200 overlap, and each pixel 120 thereby functions as a minimum unit for providing color information. An overcoat 176 is formed so as to cover the color filter 172 and the light-shielding film 174. Although not shown, spacers for maintaining the thickness of the liquid crystal layer 166 may be provided within the liquid crystal layer 166.

[0021] The various components described above can be formed using, for example, the materials described below. The substrate 102 and the counter substrate 110 are configured to contain glass, quartz, or polymers such as polyimide and polycarbonate that are transparent to visible light. The substrate 102 and / or the counter substrate 110 may be flexible. The size and shape of the substrate 102 and the counter substrate 110 may be selected appropriately depending on the intended use of the display device 100. The semiconductor film 132 is composed of a Group 14 element such as silicon or an oxide semiconductor such as an indium-gallium oxide semiconductor or an indium-gallium-zinc oxide. There are no restrictions on the crystallinity of the semiconductor film 132, and it may be amorphous or polycrystalline. The undercoat 112, the gate insulating film 134, the interlayer insulating films (the first interlayer insulating film 138 and the second interlayer insulating film 140), the interelectrode insulating film 150, and the overcoat 176 are each an inorganic film containing an inorganic compound, and may be composed of one or more films containing a silicon-containing inorganic compound such as silicon oxide or silicon nitride. The first planarization film 146 and the second planarization film 148 may contain polymers such as epoxy resin, acrylic resin, silicone resin, and polyimide resin. The gate electrode 136 may be formed of one or more layers containing a metal with a relatively high melting point, such as molybdenum, tantalum, tungsten, or chromium, or an alloy containing at least one metal selected from these. The source electrode 142, the drain electrode 144, and the detection wiring 202 may be formed of one or more layers containing, in addition to the above metals, a highly conductive metal such as aluminum or copper, or an alloy containing at least one metal selected from these. The detection electrode 200 and the pixel electrode 162 may be formed of a conductive oxide, such as indium-tin oxide or indium-zinc oxide, that transmits at least a portion of visible light. The first alignment film 164 and the second alignment film 168 may be formed of a polymer, such as polyimide.

[0022] 3. Semiconductor elements A schematic bottom view of the semiconductor element 210 is shown in Fig. 6. As shown in Fig. 6, the semiconductor element 210 has a plurality of bumps formed on the bottom surface of a main body 212 that includes a semiconductor substrate and a circuit. Specifically, the semiconductor element 210 has a plurality of input bumps 214 for inputting signals input via the FPC 106 to the circuit, as well as a plurality of output bumps 216 for outputting various signals generated within the semiconductor element 210 and inputting them to the pixels 120 and the gate line driving circuit 104. The plurality of input bumps 214 and the plurality of output bumps 216 are electrically connected to the circuit within the main body 212.

[0023] As can be seen from FIG. 6 , the input bumps 214 are arranged in a single row in the longitudinal direction of the semiconductor element 210. In contrast, the output bumps 216 are arranged in multiple rows in a staggered arrangement. The output bumps 216 can be divided into three bump groups, each including two or more output bumps 216. In one bump group (first bump group) 216-1, the output bumps 216 are arranged in multiple rows (four rows in this case) parallel to the arrangement direction of the input bumps 214 (i.e., the longitudinal direction of the semiconductor element 210), forming a staggered arrangement. Meanwhile, the output bumps 216 included in the second bump group 216-2, which is one of the other bump groups, are also arranged in multiple rows in a staggered arrangement, but the direction of each row is inclined from the arrangement direction of the input bumps 214. Similarly, the remaining bump group, the third bump group 216-3, includes multiple output bumps 216 arranged in a staggered pattern across multiple rows, but the direction of each row is tilted from the direction of the input bumps 214. The first bump group 216-1 is located between the second bump group 216-2 and the third bump group 216-3. The output bumps 216 included in the second bump group 216-2 and the third bump group 216-3 are arranged symmetrically with respect to the first bump group 216-1, such that the distance to the input bumps 214 decreases as the distance from the first bump group 216-1 increases. As will be described later, this arrangement allows for effective use of the frame area. In other words, it allows for efficient arrangement of wiring lines connected to the output bumps 216 to supply various signals to the pixels 120, preventing short circuits or current leaks between the wiring lines. As a result, it is possible to provide display devices with narrow frames and excellent design with a high yield. The number of rows in which the output bumps 216 are arranged is not limited to four, but may be two, three, five or more.

[0024] However, if the input bumps 214 and the output bumps 216 are formed in this manner, as will be described later, the semiconductor element 210 may tilt if pressure is applied to the semiconductor element 210 when the semiconductor element 210 is mounted on the substrate 102. This is because each row formed by the multiple output bumps 216 is curved and the multiple output bumps 216 are arranged asymmetrically around an axis parallel to the longitudinal direction of the semiconductor element 210. For this reason, multiple dummy bumps 218 are provided to prevent poor contact of the semiconductor element 210 caused by the semiconductor element 210 tilting. The dummy bumps 218 are arranged in areas created by the tilt of the multiple rows formed by the output bumps 216 included in the second bump group 216-2 and the third bump group 216-3. Specifically, a plurality of dummy bumps 218 are provided on the opposite side of the input bumps 214 relative to the second bump group 216-2, and similarly, a plurality of dummy bumps 218 are provided on the opposite side of the input bumps 214 relative to the third bump group 216-3. The plurality of dummy bumps 218 are provided, for example, parallel to the direction in which the input bumps 214 are arranged. Although not shown, the plurality of dummy bumps 218 may also be arranged across multiple rows or in a staggered arrangement. The plurality of dummy bumps 218 may also be arranged on a bent or curved line. Unlike the input bumps 214 and the output bumps 216, the dummy bumps 218 are electrically isolated and independent from the circuitry of the semiconductor element 210, are not electrically connected to the circuitry or the pixels 120, and do not exert any electrical effect on the display device 100.

[0025] 4. Frame area 7 is a schematic top view of a portion of the frame region, showing the frame region where the semiconductor element 210 and FPC 106 are disposed. As shown in FIG. 7, a plurality of terminals 180 including a patterned conductive film are provided on the substrate 102, and a plurality of input pads 182 and a plurality of output pads 184 are provided at positions corresponding to the input bumps 214 and output bumps 216 of the semiconductor element 210, respectively.

[0026] The multiple terminals 180 are electrically connected to multiple input pads 182 by wiring (not shown), and supply signals input from an external circuit via the FPC 106 to the semiconductor element 210. The multiple input pads 182 are electrically connected to multiple input bumps 214 of the semiconductor element 210, and the multiple output pads 184 are electrically connected to multiple output bumps 216 of the semiconductor element 210. Therefore, the input pads 182 are arranged in the same manner as the input bumps 214, and the output pads 184 are arranged in the same manner as the output bumps 216.

[0027] That is, the multiple input pads 182 are arranged parallel to one side of the substrate 102 (the side closest to the multiple terminals 180 and parallel to the arrangement direction of the terminals 180; in the example shown in FIG. 1, this is the short side). In other words, the multiple input pads 182 are arranged parallel to the longitudinal direction of the region (region R3 in FIG. 7) on which the semiconductor element 210 is mounted. In contrast, the output pads 184 are arranged in a staggered pattern across multiple rows. The multiple output pads 184 can be divided into three pad groups, each including two or more output pads 184. In one pad group (first pad group) 184-1, the multiple output pads 184 are arranged in a staggered pattern across multiple rows (four rows in this case) that are arranged parallel to the longitudinal direction of region R3. Meanwhile, the output pads 184 included in the second pad group 184-2, one of the other pad groups, are also arranged in a staggered pattern across multiple rows, but the direction of each row is tilted from the side and the direction of the arrangement of the input pads 182. Similarly, the output pads 184 included in the third pad group 184-3, the remaining pad group, are also arranged in a staggered pattern across multiple rows, but the direction of each row is tilted from the side and the direction of the arrangement of the input pads 182. The first pad group 184-1 is sandwiched between the second pad group 184-2 and the third pad group 184-3. The output pads 184 included in the second pad group 184-2 and the third pad group 184-3 are arranged symmetrically with respect to the first pad group 184-1, and are arranged such that the distance to the side of the substrate 102 or the input pads 182 decreases as the distance from the first pad group 184-1 increases.

[0028] 8 and 9 are schematic enlarged views of regions R1 and R2 shown in FIG. 7, respectively. Region R2 includes region R4 that overlaps with dummy bumps 218 of the semiconductor element 210. As shown in FIG. 8, each output pad 184 is connected to a lead-out wiring 188. The lead-out wiring 188 is electrically connected to the signal line 124 or the detection wiring 202 that extends through the display region. In region R1, the output pads 184 included in the first pad group 184-1 are arranged in a staggered pattern across multiple rows, with each row extending parallel to the longitudinal direction of region R3 in which the semiconductor element 210 is mounted. The lead-out wiring 188 extends perpendicular to this longitudinal direction toward the display region.

[0029] As can be seen from FIG. 1, the width of the display area (the length in the longitudinal direction of the semiconductor element 210) is greater than the length of the semiconductor element 210 in the longitudinal direction. Therefore, as shown in FIG. 7, the direction of the rows formed by the plurality of output pads 184 included in the second pad group 184-2 or the third pad group 184-3 is tilted from the arrangement direction of the plurality of input pads 182. Furthermore, as shown in FIG. 9, at least a portion of the lead-out wiring 188 extending from the output pads 184 included in the second pad group 184-2 (or the third pad group 184-3) is bent, and at least a portion of the bent lead-out wiring 188 extends in a direction tilted from the direction perpendicular to the arrangement direction of the plurality of input pads 182. By adopting such an arrangement, it is possible to efficiently utilize the frame area, and as a result, it is possible to increase the width / wiring spacing (L / S) of the lead-out wiring 188. This makes it possible to prevent problems such as an increase in wiring resistance due to an inability to ensure the width of the lead wiring 188 caused by variations during manufacturing, or a leak occurring due to an inability to ensure the spacing between the lead wiring 188.

[0030] 7 and 9, the lead-out wiring 188 is also arranged in the region R4 where the dummy bumps 218 of the semiconductor element 210 are arranged. Therefore, in the display device 100, the dummy bumps 218 overlap with one or more lead-out wirings 188 in the frame region.

[0031] FIG. 10 shows a schematic diagram of the end surface along the dashed lines AA′ and BB′ in FIG. 9 . As shown in the schematic diagram of the BB′ end surface, the output pad 184 is configured to include, in addition to a portion of a first wiring 188-1 that constitutes a part of the lead wiring 188, a first conductive film 190 on the first wiring 188-1, a second conductive film 192 on the first conductive film 190, a third conductive film 194 on the second conductive film 192, and a fourth conductive film 196 on the third conductive film 194. The first wiring 188-1 is present in the same layer as the gate electrode 136 of the switching transistor 130. Therefore, the first wiring 188-1 has the same thickness and composition as the gate electrode 136. The first wiring 188-1 is the lowest conductive film in the output pad 184 and extends on the gate insulating film 134 toward the display area. The first conductive film 190 is in physical and electrical contact with the first wiring 188-1 and exists in the same layer as the source electrode 142 and the drain electrode 144 of the switching transistor 130. Therefore, the first conductive film 190 has the same thickness and composition as the source electrode 142 and the drain electrode 144. The second conductive film 192 is in physical and electrical contact with the first conductive film 190 and exists in the same layer as the detection wiring 202. Therefore, the second conductive film 192 has the same thickness and composition as the detection wiring 202. The third conductive film 194 is in physical and electrical contact with the second conductive film 192 and exists in the same layer as the detection electrode 200. Therefore, the third conductive film 194 has the same thickness and composition as the detection electrode 200. The fourth conductive film 196 is in physical and electrical contact with the third conductive film 194 and exists in the same layer as the pixel electrode 162. Therefore, the fourth conductive film 196 has the same thickness and composition as the pixel electrode 162. As described above, the detection electrode 200 and the pixel electrode 162 are configured to contain a conductive oxide. Therefore, in the process after forming the third conductive film 194 that exists in the same layer as the detection electrode 200, corrosion of the first wiring 188-1, the first conductive film 190, and the second conductive film 192, which contain metal, can be prevented.

[0032] In the frame region, the first wiring 188-1 may be connected to a second wiring 188-2 (see AA' end face in FIG. 10 ) existing in the same layer as the source electrode 142 or the drain electrode 144 of the switching transistor 130 via an opening (not shown) provided in the interlayer insulating film (first interlayer insulating film 138, second interlayer insulating film 140). In this case, the first wiring 188-1 does not extend to the display region, and a signal supplied from the output pad 184 to the first wiring 188-1 is supplied to the display region via the second wiring 188-2. Similarly, the second wiring 188-2 may be connected to a third wiring 188-3 (see AA' end face in FIG. 10 ) existing in the same layer as the detection wiring 202 via an opening (not shown) provided in the first planarization film 146. In this case, the second wiring 188-2 does not extend to the display area, and a signal supplied from the first wiring 188-1 to the second wiring 188-2 is supplied to the display area via the third wiring 188-3. In this way, the multiple lead-out wirings 188 are configured by the first wiring 188-1, the second wiring 188-2, and the third wiring 188-3 located in different layers. Although not shown, the first wiring 188-1 and the second wiring 188-2 may intersect with each other via an interlayer insulating film (first interlayer insulating film 138, second interlayer insulating film 140). Furthermore, the second wiring 188-2 and the third wiring 188-3 may intersect with each other via the first planarization film 146. Similarly, the third wiring 188-3 may intersect with the interlayer insulating films (first interlayer insulating film 138, second interlayer insulating film 140) and the first planarizing film 146 interposed therebetween.

[0033] The first planarization film 146 extends from the display region to the frame region and covers multiple lead-out wirings 188 (i.e., first wiring 188-1 and second wiring 188-2) that exist in different layers. Similarly, the second planarization film 148 also extends from the display region to the frame region and covers all of the lead-out wirings 188 that exist in different layers (i.e., the first wiring 188-1, second wiring 188-2, and third wiring 188-3). The inter-electrode insulating film 150 also extends from the display region to the frame region and is disposed in the frame region so as to contact the top and side surfaces of the second planarization film 148 and the side surfaces of the first planarization film 146. In the frame region, a portion of the first planarization film 146 may be exposed from the second planarization film 148. In this case, the inter-electrode insulating film 150 may be in contact with the upper surface of the first planarization film 146 exposed from the second planarization film 148. The second planarization film 148 may or may not be provided on the input pad 182 side from the output pad 184 (see the BB' end face in FIG. 10).

[0034] As shown in FIG. 11 , the semiconductor element 210 is mounted on the substrate 102 by electrically connecting the output bumps 216 and the output pads 184 via the anisotropic conductive film 198. Although not shown, the input bumps 214 and the input pads 182 are also electrically connected to each other via the anisotropic conductive film 198. Specifically, the anisotropic conductive film 198 is disposed on the input pads 182 and the output pads 184, and the semiconductor element 210 is disposed thereon. At this time, the dummy bumps 218 may be in direct contact with the inter-electrode insulating film 150 covering the first planarization film 146 and the second planarization film 148. In this state, the anisotropic conductive film 198 is heated while applying pressure to the semiconductor element 210 from above. Thereafter, by cooling, the resin contained in the anisotropic conductive film 198 solidifies, and the conductive particles contained in the anisotropic conductive film 198 form conductive paths. This electrically connects the input bump 214 and the output bump 216 to the input pad 182 and the output pad 184, respectively.

[0035] As described above, although the output bumps 216 are arranged asymmetrically on the bottom surface of the semiconductor element 210 with respect to an axis parallel to the longitudinal direction of the semiconductor element 210, the dummy bumps 218 are also provided, allowing the semiconductor element 210 to be mounted on the substrate 102 without tilting. Furthermore, although the interelectrode insulating film 150 is subjected to pressure from the dummy bumps 218 when pressure is applied, the routing wiring 188 located below the interelectrode insulating film 150 is protected by the first planarization film 146 and the second planarization film 148, which are made of polymer. Therefore, even if the dummy bumps 218 overlap the routing wiring 188 during mounting of the semiconductor element 210, damage or disconnection of the routing wiring 188 can be prevented. Because of these characteristics, the display device 100 can make more effective use of the frame area than conventional display devices in which dummy pads are formed in region R4 and the routing wiring is arranged to avoid the dummy pads. This allows the frame area to be made smaller, resulting in a display device with superior design. Furthermore, the L / S of the lead-out wiring 188 can be increased, which can prevent problems caused by an increase in the density of the lead-out wiring 188. This also contributes to improving the manufacturing yield of high-definition display devices and reducing manufacturing costs.

[0036] Depending on the heights of the output bumps 216 and the dummy bumps 218, excessive pressure may be applied to the inter-electrode insulating film 150 when the semiconductor element 210 is fixed. In this case, as shown in FIG. 12, a portion of the second planarization film 148 may be formed to be thinner. That is, the thickness of the second planarization film 148 in the region R4 that overlaps with the dummy bumps 218 of the semiconductor element 210 may be made thinner than that in the region that does not overlap with the dummy bumps 218. This makes it possible to prevent damage or disconnection of the routing wiring 188 due to excessive pressure.

[0037] The second planarization film 148, which has regions of different thicknesses, may be formed by exposure using a gray-tone mask or a half-tone mask. For example, a positive resist for providing the second planarization film 148 is applied to the substrate 102 on which the detection wiring 202 has been formed, and then the resist is exposed through the gray-tone mask or the half-tone mask. The gray-tone mask or the half-tone mask is positioned so that a slit in the gray-tone mask that is smaller than the resolution of the exposure machine or a semi-transparent portion of the half-tone mask overlaps with the region R4 that overlaps with the dummy bumps 218. Meanwhile, the gray-tone mask or the half-tone mask is positioned so that light is not irradiated onto the region not overlapping with the dummy bumps 218, and the region where the second planarization film 148 is not to be formed does not block light from the exposure machine. As a result, the region R4 that overlaps with the dummy bumps 218 becomes an intermediately exposed region, the region not overlapping with the dummy bumps 218 becomes an unexposed region, and the region where the second planarization film 148 is not to be formed becomes an exposed region. Thereafter, development is performed to make the thickness of the region R4 that overlaps with the dummy bump 218 smaller than the thickness of the region that does not overlap with the dummy bump 218. When using a negative resist, the unexposed portion and the exposed portion can be swapped.

[0038] Although the above-described embodiments have been described using a liquid crystal display device as the display device, the above-described embodiments can also be applied to an electroluminescent display device that uses organic electroluminescence.

[0039] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0040] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0041] 100: display device, 102: substrate, 104: gate line driving circuit, 106: flexible printed circuit board, 108: sealing material, 110: opposing substrate, 112: undercoat, 120: pixel, 122: gate line, 124: signal line, 128: capacitance element, 130: switching transistor, 132: semiconductor film, 134: gate insulating film, 136: gate electrode, 138: first interlayer insulating film, 140: second interlayer insulating film, 142: source electrode, 144: drain electrode, 146: first planarization film, 148: second planarization film, 150: interelectrode insulating film, 160: display element, 162: pixel electrode, 164: first light alignment film, 166: liquid crystal layer, 168: second alignment film, 172: color filter, 174: light-shielding film, 1 76: overcoat, 180: terminal, 182: input pad, 184: output pad, 184-1: first pad group, 184-2: second pad group, 184-3: third pad group, 188: routing wiring, 188-1: first wiring, 188-2: second wiring, 188-3: third wiring, 190: first conductive film, 192: second conductive film, 194: third conductive film, 196: fourth conductive film, 198: anisotropic conductive film, 200: detection electrode, 202: detection wiring, 210: semiconductor element, 212: main body, 214: input bump, 216: output bump, 216-1: first bump group, 216-2: second bump group, 216-3: third bump group, 218: dummy bump

Claims

1. substrate, at least one pixel on the substrate; At least one pad located on the substrate and configured to be electrically connected to a semiconductor element provided on the semiconductor substrate; and a wiring line electrically connecting the at least one pixel to the at least one pad; The at least one pixel transistors, a planarization film on the transistor; and a display element located on the planarization film and electrically connected to the transistor; The semiconductor element is a circuit configured to drive the at least one pixel; a bump electrically connected to the circuit; and a dummy bump electrically independent from the circuit; The display device, wherein the lead-out wiring is arranged so as to overlap the dummy bump via the planarization film when the bump is connected to the at least one pad.

2. The display device according to claim 1 , wherein the planarization film comprises a first planarization film and a second planarization film on the first planarization film.

3. further comprising an inorganic film covering the planarization film, The display device according to claim 1 , wherein the inorganic film is configured to contact the dummy bump when connecting the bump to the at least one pad.

4. The transistor is Semiconductor film, a gate electrode overlapping the semiconductor film; a gate insulating film sandwiched between the semiconductor film and the gate electrode; and a source electrode and a drain electrode electrically connected to the semiconductor film; 2. The display device according to claim 1, wherein at least a part of the lead-out wiring is present in the same layer as the gate electrode, the source electrode, or the drain electrode.

5. further comprising a detection electrode between the transistor and the display element; The display device according to claim 1 , wherein at least a part of the lead-out wiring is present in the same layer as the detection electrodes.

6. 3. The display device according to claim 2, wherein the thickness of the second planarization film in a region overlapping the dummy bump when the bump is connected to the at least one pad is smaller than the thickness of the second planarization film in a region not overlapping the dummy bump.

7. the at least one pixel includes a plurality of pixels; the at least one pad includes a plurality of pads each electrically connected to a corresponding one of the plurality of pixels; The display device according to claim 1 , wherein the plurality of pads are arranged across a plurality of rows.

8. The display device according to claim 7 , wherein the plurality of pads are arranged in a staggered pattern.

9. The plurality of pads are divided into a first pad group and a second pad group, each of which includes two or more of the pads; In the first pad group, the rows are parallel to one side of the substrate; The display device according to claim 7 , wherein in the second pad group, the rows are inclined from the side.

10. 10. The display device of claim 9, wherein in the second pad group, the distance from the pad to the side decreases as the distance from the first pad group increases.

11. substrate, at least one pixel on the substrate; at least one pad on the substrate; a wiring line electrically connecting the at least one pixel to the at least one pad; and a semiconductor element electrically connected to the at least one pad and provided on a semiconductor substrate; The at least one pixel transistors, a planarization film on the transistor; and a display element located on the planarization film and electrically connected to the transistor; The semiconductor element is a circuit configured to drive the at least one pixel; a bump electrically connected to the circuit; and a dummy bump electrically independent from the circuit; The display device, wherein the lead wiring overlaps the dummy bump via the planarization film.

12. The display device according to claim 11 , wherein the planarization film comprises a first planarization film and a second planarization film on the first planarization film.

13. further comprising an inorganic film covering the planarization film, The display device according to claim 11 , wherein the inorganic film is in contact with the dummy bump.

14. The transistor is Semiconductor film, a gate electrode overlapping the semiconductor film; a gate insulating film sandwiched between the semiconductor film and the gate electrode; and a source electrode and a drain electrode electrically connected to the semiconductor film; The display device according to claim 11 , wherein the lead-out wiring is present in the same layer as the gate electrode, the source electrode, or the drain electrode.

15. further comprising a detection electrode between the transistor and the display element; The display device according to claim 11 , wherein the lead-out wiring is present in the same layer as the detection electrodes.

16. The display device according to claim 12 , wherein the thickness of the second planarization film in the region overlapping with the dummy bump is smaller than the thickness in the region not overlapping with the dummy bump.

17. the at least one pixel includes a plurality of pixels; the at least one pad includes a plurality of pads each electrically connected to a corresponding one of the plurality of pixels; The display device according to claim 11 , wherein the pads are arranged across a plurality of rows.

18. The display device according to claim 17 , wherein the pads are arranged in a staggered pattern.

19. The plurality of pads are divided into a first pad group and a second pad group, each of which includes two or more of the pads; In the first pad group, the rows are parallel to one side of the substrate; 18. The display device of claim 17, wherein in the second pad group, the rows are inclined from the side.

20. 20. The display device of claim 19, wherein in the second group of pads, the distance from the pads to the side decreases as the distance from the first group of pads increases.

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