Method and apparatus for reducing feature charging in a plasma processing chamber

Abstract

A method and apparatus for reducing feature charging in a plasma processing chamber is provided. [Solution] A plasma processing method for plasma processing of a substrate (103) in a processing chamber (100) that enables a process used to eliminate or reduce the impact of trapped charge disposed within features formed on the substrate on etch rate and defect formation includes synchronizing the supply of pulse voltage (PV) waveforms (460, 461) and alternatively the supply of a radio frequency (RF) waveform to enable independent control of the generation of electrons provided during one or more stages of multiple PV waveform cycles to neutralize trapped charge generated within features formed on the substrate.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing. In particular, embodiments of the present disclosure relate to plasma processing systems used to process substrates. [Background technology]

[0002]

[0002] Reliably producing high aspect ratio features is one of the key technological challenges for next generation semiconductor devices. One method for forming high aspect ratio features uses a plasma-assisted etching process to bombard material formed on the surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003] As semiconductor device technology nodes advance toward 2 nanometers (nm) and below, the fabrication of smaller, high-aspect-ratio features requires atomic-level precision during various plasma fabrication processes. In etching processes, where plasma-generated ions play a key role in the success of the etching process, ion energy and directionality control are key factors for the desired formation of etched high-aspect-ratio features. Feature distortion-type defects in high-aspect-ratio features, such as kinks, tapers, and micro-trench formation, are all believed to be related to charge trapped within the formed feature. FIG. 1 is a schematic diagram of a formed feature, including charge trapped within the wall of the feature, formed within a portion of the surface of a substrate. In typical ion-assisted etching applications, it is believed that positive charge tends to accumulate deep within the wall of the feature due to the different angular distributions of ions and electrons. As shown in FIG. 1, the accumulation of positive charge within the feature generates a local electric field that slows incoming ions during plasma processing, thereby reducing the etch rate when the high-aspect-ratio feature is formed and increasing the likelihood of feature distortion within the formed high-aspect-ratio feature.

[0004]

[0004] Therefore, there is a need for a system, device(s), and method that addresses the above-mentioned problems. Summary of the Invention

[0005]

[0005] Embodiments provided herein broadly include apparatus, e.g., plasma processing systems, and methods for plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defects on the surface of the substrate and improving etch rates.

[0006]

[0006] Several embodiments of the present disclosure may provide a plasma processing system. The plasma processing system includes a substrate support assembly, a first waveform generator, a first electrode, a second waveform generator, and a controller. The substrate support assembly includes a substrate support surface, a bias electrode, and a first dielectric layer disposed between the bias electrode and the substrate support surface. The first waveform generator is coupled to the bias electrode. In this case, the first waveform generator is configured to generate a first plurality of pulsed voltage waveforms established at the bias electrode. Each pulsed voltage waveform of the first plurality of pulsed voltage waveforms includes a first stage and a second stage having a voltage level lower than a voltage level in the first stage. The first electrode is disposed above the substrate support surface. The second waveform generator is coupled to the first electrode. In this case, the second waveform generator is configured to generate a second plurality of pulsed voltages established at the first electrode. Each pulse voltage waveform of the second plurality of pulse voltage waveforms includes a first stage and a second stage having a voltage level higher than the voltage level in the first stage. The controller includes a memory containing computer-implemented instructions that, when executed by the processor, are configured to synchronize generation of the first and second plurality of pulse voltage waveforms such that a first stage of a pulse voltage waveform in the first plurality of pulse voltage waveforms and a first stage of a pulse voltage waveform in the second plurality of pulse voltage waveforms at least partially overlap in time, and a second stage of a pulse voltage waveform in the first plurality of pulse voltage waveforms and a second stage of a pulse voltage waveform in the second plurality of pulse voltage waveforms at least partially overlap in time.

[0007]

[0007] Several embodiments of the present disclosure may further provide a plasma processing system. The plasma processing system includes a substrate support assembly, a first waveform generator, a first electrode, a second waveform generator, and a controller. The substrate support assembly includes a substrate support surface, a bias electrode, and a first dielectric layer disposed between the bias electrode and the substrate support surface. The first waveform generator is coupled to the bias electrode, where the first waveform generator is configured to generate a first plurality of pulsed voltage waveforms established at the bias electrode. Each pulsed voltage waveform of the first plurality of pulsed voltage waveforms includes a first stage and a second stage. The first electrode is disposed above the substrate support surface. The second waveform generator is coupled to the first electrode, where the second waveform generator is configured to generate a second plurality of pulsed voltage waveforms established at the first electrode. Each pulsed voltage waveform of the second plurality of pulsed voltage waveforms includes a first stage and a second stage. The controller includes a memory including computer-implemented instructions. The instructions, when executed by a processor, are configured to synchronize generation of a first plurality of pulsed voltage waveforms and a second plurality of pulsed voltage waveforms, whereby each pulsed voltage waveform in the first plurality of pulsed voltage waveforms and each pulsed voltage waveform in the second plurality of pulsed voltage waveforms are inversely configured.

[0008]

[0008] Embodiments of the present disclosure may further provide a processing method. The processing method includes establishing a first pulsed voltage waveform at a bias electrode disposed within a substrate support assembly using a first waveform generator, and establishing a second pulsed voltage waveform at a surface of the first electrode disposed on the substrate support assembly using a second waveform generator. The first pulsed voltage waveform includes a first stage and a second stage having a voltage level lower than that of the first stage. The second pulsed voltage waveform includes the first stage and a second stage having a voltage level higher than that of the first stage. During the processing method, the first pulsed voltage waveform and the second pulsed voltage waveform are synchronized, such that the first stage of the first pulsed voltage waveform and the first stage of the second pulsed voltage waveform at least partially overlap in time, and the second stage of the first pulsed voltage waveform and the second stage of the second pulsed voltage waveform at least partially overlap in time.

[0009]

[0009] Embodiments of the present disclosure may further provide a processing method. The processing method includes establishing a first pulsed voltage waveform at a bias electrode disposed in a substrate support assembly by using a first waveform generator, and establishing an RF waveform at a first electrode disposed on the substrate support assembly by using an RF waveform generator. The first pulsed voltage waveform may include a first stage and a second stage having a voltage level lower than the voltage level in the first stage. The substrate support assembly includes a substrate support surface, a bias electrode, and a first dielectric layer disposed between the bias electrode and the substrate support surface. The RF waveform may include a sinusoidal waveform. The first pulsed voltage waveform and the RF waveform are synchronized, such that a trough of the RF waveform is formed during a period when the first stage of the first pulsed voltage waveform is established at the bias electrode, and a peak of the RF waveform is formed during a period when the second stage of the first pulsed voltage waveform is established at the bias electrode.

[0010]

[0010] So that the above features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered to limit the scope of the present disclosure, as other equally effective embodiments may also be acceptable. [Brief explanation of the drawings]

[0011] [Figure 1]

[0011] FIG. 1 is a schematic cross-sectional view of a portion of a substrate during a conventional plasma process. [Figure 2A]

[0012] 2A-2B are schematic cross-sectional views of a process chamber that may be adapted to perform one or more of the methods described herein, according to one or more embodiments. [Figure 2B] 2A-2B are schematic cross-sectional views of a process chamber that may be adapted to perform one or more of the methods described herein, according to one or more embodiments. [Figure 3]

[0013] 1 illustrates an example of a pulse voltage (PV) waveform that may be established at the surface of a substrate using one or more of the embodiments described herein. [Figure 4A]

[0014] 4A-4C show examples of pulse voltage (PV) waveforms that may be established at an electrode using one or more of the embodiments described herein. [Figure 4B] 4A-4C show examples of pulse voltage (PV) waveforms that may be established at an electrode using one or more of the embodiments described herein. [Figure 4C] 4A-4C show examples of pulse voltage (PV) waveforms that may be established at an electrode using one or more of the embodiments described herein. [Figure 5A]

[0015] 1 illustrates a synchronized pulse voltage (PV) waveform that may be established at electrodes in a process chamber using one or more of the embodiments described herein. [Figure 5B]

[0016] FIG. 1 is a simplified schematic diagram of a processing chamber including an overlaid representation of a PV waveform applied to electrodes within the process chamber according to one or more embodiments provided herein. [Figure 6A]

[0017] 1 illustrates synchronized RF and pulsed voltage (PV) waveforms that may be established at electrodes in a process chamber using one or more of the embodiments described herein. [Figure 6B]

[0018] FIG. 1 is a simplified schematic diagram of a processing chamber including an overlaid representation of RF and PV waveforms applied to electrodes within the process chamber according to one or more embodiments provided herein. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0019] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is believed that elements and features of one embodiment may be beneficially incorporated in multiple other embodiments without further recitation.

[0013]

[0020] Embodiments provided herein include apparatus and methods for plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defects and improving plasma etch rates in features formed on a surface of a substrate. In some embodiments, the apparatus and methods disclosed herein are configured to improve etch selectivity for different materials on a substrate. In some embodiments, the apparatus and methods enable processes that can be used to eliminate or reduce the impact of trapped charge disposed within features formed on a substrate on etch rates and defect formation. In some embodiments, a plasma processing method includes providing multiple pulsed voltage (PV) waveforms, and alternatively, synchronizing the provision of PV waveforms and radio frequency (RF) waveforms, to enable the generation of electrons provided during one or more stages of the PV waveform cycle to neutralize trapped charge generated in features formed on a substrate.

[0014]

[0021] As described in further detail below, one or more of the processes disclosed herein include the generation of secondary electrons. The secondary electrons are emitted from an electrode disposed on or adjacent to the surface of a substrate while a PV waveform is established at a bias electrode disposed adjacent to the substrate during plasma processing. Embodiments of the present disclosure may also include apparatus and methods for providing a pulsed voltage (PV) waveform to one or more electrodes in a processing chamber while biasing and clamping a substrate during a plasma process. In some embodiments, the PV waveform(s) are established by one or more PV waveform generators electrically coupled to one or more electrodes disposed in a substrate support assembly. In some embodiments, at least one of the one or more electrodes includes a chuck electrode coupled to one of the one or more PV waveform generators.

[0015]

[0022] In some embodiments, a radio frequency (RF) generating RF waveform is provided from an RF generator to one or more electrodes in the process chamber to establish and maintain a plasma within the process chamber, while a PV waveform(s) is / are used to at least: 1) generate secondary electrons to neutralize trapped charge created within features formed on the substrate, and 2) control a sheath voltage across the surface of the substrate during processing. The ability to control the sheath voltage so that it is substantially constant throughout the plasma process also enables the creation of a desired ion energy distribution function (IEDF) at the surface of the substrate during one or more plasma processing operations, thereby improving plasma processing results by providing an IEDF that includes a single (narrow) peak corresponding to ions accelerated toward the surface of the substrate. In some embodiments, different pulse voltage levels (i.e., peak-to-peak voltage levels (V)) are used to generate an IEDF with two or more discrete IED peaks, as described further below. pp It may be desirable to continuously or burst-deliver a PV waveform having a .times. ...

[0016]

[0023] Beneficially, the apparatus and methods disclosed herein can be used alone or in combination to provide individual tuning knobs for controlling ion energy, electron energy, ion and electron angular distribution functions, and the flux of ions and electrons interacting with the surface of a substrate. Thus, the ability to individually control ion energy, electron energy, ion and electron angular distribution functions, and electron and ion flux at a processed substrate provides desired tuning parameters that can be used to optimize the etch profiles required for tight tolerances, higher etch selectivity, and processing throughput necessary for cost-effective manufacturing for next generation electronic devices.

[0017] Multiple Embodiments of a Plasma Processing System

[0024] 2A and 2B are schematic cross-sectional views of processing systems 10A and 10B, respectively, configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing systems 10A and 10B shown in FIGS. 2A and 2B are configured for plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing. However, it should be noted that the embodiments described herein may also be used with processing systems configured for use in other plasma-assisted processes, such as plasma deposition processes, e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0018]

[0025] As shown in Figures 2A-2B, the processing systems 10A-10B are configured to generate a capacitively coupled plasma (CCP). In that case, the processing systems 10A-10B include an upper electrode (e.g., chamber lid 123) disposed within the processing space 129. The upper electrode faces a lower electrode (e.g., substrate support assembly 136) also disposed within the processing space 129. In a typical CCP processing system, a plasma generator assembly 163 is electrically coupled to one of the upper or lower electrodes to provide an RF signal used to ignite and sustain a plasma 101 within a processing region 129A disposed above the substrate 103. The plasma generator assembly 163 will generally include an RF generator 118 and an RF matching network 160. In some embodiments, the RF generator 118 is configured to provide an RF signal having a frequency greater than 400 kHz, e.g., about 1 MHz or greater, or about 2 MHz or greater, e.g., about 13.56 MHz or greater, about 27 MHz or greater, about 40 MHz or greater, hi some configurations, the RF frequency is between about 30 MHz and about 200 MHz, e.g., between about 30 MHz and about 160 MHz, between about 30 MHz and about 120 MHz, or between about 30 MHz and about 60 MHz.

[0019]

[0026] Each of the processing systems 10A and 10B includes a processing chamber 100, a plasma generator assembly 163, one or more pulsed voltage (PV) source assemblies 196-199, a substrate support assembly 136, and a system controller 126. The processing chamber 100 typically includes a chamber body 113. The chamber body 113 includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define a processing space 129. A substrate 103 is loaded into and removed from the processing space 129 through an opening (not shown) in one of the one or more sidewalls 122. The opening is sealed by a slit valve (not shown) during plasma processing of the substrate 103. The one or more sidewalls 122 and the chamber base 124 generally include materials sized and shaped to provide structural support for the elements of the processing chamber 100 and configured to withstand pressure and additional energy applied thereto. Meanwhile, plasma 101 is generated within a reduced pressure environment maintained within process space 129 of process chamber 100 during processing. In one example, one or more sidewalls 122 and chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy. In some embodiments, a dielectric coating is present on sidewall 122. The dielectric coating can be anodized aluminum oxide, aluminum oxide, yttrium oxide, or a mixture thereof. The thickness of the dielectric coating can vary from 100 nm to 10 cm.

[0020]

[0027] In some embodiments, a gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the process space 129 from a process gas source 119 in fluid communication with the process space 129. In other embodiments, the gas inlet 128 comprises a showerhead (FIG. 2B). The showerhead is used to supply one or more process gases provided by the process gas source 119 to the process space 129. In still other embodiments, gases are supplied through several nozzles in the sidewall. The process space 129 is fluidly coupled to one or more dedicated vacuum pumps via a vacuum outlet 120. The one or more dedicated vacuum pumps maintain the process space 129 at subatmospheric pressure and evacuate the process gases and / or other gases from the process space 129.

[0021]

[0028] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103 (including the substrate bias method described herein). The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the processing chamber and its associated sub-processors. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). The support circuits 135 are conventionally coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct and command the processor within the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the system controller 126 specifies which operations are performable by components in the processing systems 10A and / or 10B. Typically, the program is readable by the CPU 133 in the system controller 126 and includes code that, when executed by the processor (CPU 133), performs operations associated with the plasma processing schemes described herein. The program may include instructions that are used to control various hardware and electrical components in the processing systems 10A and / or 10B to thereby perform various process operations and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions that are used to perform one or more of the actions described below.

[0022]

[0029] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an electrostatic chuck (ESC) substrate support) and a support base 107 disposed on a grounded support shaft 138 that extends through the chamber base 124. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a grounded plate 112. The support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111, and the grounded plate 112 is interposed between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein. The one or more cooling channels are fluidly coupled to and in fluid communication with a coolant source (not shown) (such as a refrigerant source or a water source having a relatively high electrical resistance). In some embodiments, the substrate support 105 includes a heater (not shown) (such as a resistive heating element embedded within the dielectric material of the substrate support 105). Here, the support base 107 is formed of a corrosion-resistant, heat-conducting material, such as a corrosion-resistant metal (e.g., aluminum, an aluminum alloy, or stainless steel), and is coupled to the substrate support by adhesive or mechanical means.

[0023]

[0030] In some embodiments, the processing chamber 100 further includes a quartz tube 110 or collar that at least partially circumscribes portions of the substrate support assembly 136 to prevent the substrate support 105 and / or support base 107 from contacting corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz tube 110, insulator plate 111, and grounded plate 112 are circumscribed by a cathode liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma generation in the space below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0024]

[0031] Typically, the substrate support 105 is formed of a dielectric material (e.g., a bulk-sintered ceramic material such as a corrosion-resistant metal oxide or metal nitride material), such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (YO3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded within the dielectric material. In one configuration, the bias electrode 104 is a chucking pole used to secure (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 relative to the plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0025]

[0032] The processing systems 10A and 10B also generally include a first PV source assembly 196 for establishing a first PV waveform at the bias electrode 104, and a second PV source assembly 198 ( FIG. 2A ) or 199 ( FIG. 2B ) for establishing a second PV waveform and / or RF waveform at an upper electrode, such as the chamber lid 123. Each of the one or more PV source assemblies 196-199 may include a PV waveform generator 150 and an RF filter assembly 151. In one embodiment, as shown in FIG. 2A , the second PV source assembly 198 further includes at least one plasma generator assembly 163. In some embodiments, the PV waveform generator 150 and the RF filter assembly 151 in the second PV source assembly 198 ( FIG. 2A ) or 199 ( FIG. 2B ) are replaced by a second plasma generator assembly 163 configured to operate at the same frequency as the first PV source assembly 196. In some embodiments, the PV source assemblies 196 and 197 further include a clamping network 116 used to "clamp" or "chuck" the substrate 103 to the substrate support surface 105A of the substrate support 105. The RF filter assembly 151 is configured to block the RF signal (and any associated harmonics) generated by the plasma generator assembly 163 and, in some embodiments, the second RF generator assembly, from passing toward the PV waveform generator 150 disposed within each of the one or more PV source assemblies 196-199. In some embodiments, the chamber lid 123 and the substrate support assembly 136 are configured in a parallel plate-like configuration, such that the surface 123A of the chamber lid 123 is substantially parallel to the substrate support surface 105A of the substrate support assembly 136. In some alternative embodiments, the chamber lid 123 has a low-angle concave conical or slightly concave shape relative to the planar substrate support assembly 136 centered at the center of the chamber lid 123.

[0026]

[0033] Overall control of the delivery of PV waveforms from each of the PV waveform generators 150 in one or more PV source assemblies 196-199 is controlled using signals provided by the system controller 126. In one embodiment, the PV waveform generator 150 is configured to output a periodic voltage function at a time interval of a predetermined length through the use of signals from a transistor-transistor logic (TTL) located within the system controller 126. In one embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant negative voltage across its output (i.e., output to ground) during regularly repeating time intervals of a predetermined length by repeatedly opening and closing one or more switches at a predetermined rate. In one example, a first switch is used to connect the high-voltage supply to the bias electrode 104 during a first stage of the pulse interval, and a second switch is used to connect the bias electrode 104 to ground during a second stage of the pulse interval. In another embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant voltage across its output (i.e., output to ground) during regularly repeating time intervals of predetermined length by repeatedly opening and closing one or more internal switches (not shown) at a predetermined rate.

[0027]

[0034] In an effort to efficiently deliver the RF signal from the RF generator 118 to one or more electrodes in the process chamber 100 and to protect the RF generator 118, the plasma generator assembly 163 includes an RF matching circuit 162 and a first filter assembly 161. The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV waveform generator 150, thereby blocking current flow to the RF matching circuit 162 and the RF generator 118.

[0028]

[0035] 2A and 2B, the substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is disposed below the edge ring 114, surrounds the bias electrode 104, and / or is spaced apart from the center of the bias electrode 104 and the center of the substrate support surface 105A. In some embodiments, the processing system 10A or 10B may therefore include a first PV source assembly 196 for establishing a first PV waveform at the bias electrode 104, a second PV source assembly 198 or 199 for establishing a PV waveform and / or an RF waveform at the upper electrode (e.g., the chamber lid 123), and a third PV source assembly 197 for establishing a second PV waveform at the edge control electrode 115. Generally, in a processing chamber 100 configured to process a circuit substrate, the edge control electrode 115 is ring-shaped, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in FIG. 2A , the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 2A , the edge control electrode 115 comprises a conductive mesh, foil, and / or plate disposed a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 as the bias electrode 104. In some other embodiments, such as shown in FIG. 2B , the edge control electrode 115 comprises a conductive mesh, foil, and / or plate disposed on or within the region of the quartz tube 110. The quartz tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or coupled to an edge ring 114 disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (such as AlN).

[0029]

[0036] As described above, in some embodiments, the bias electrode 104 and the edge control electrode 115 are each electrically coupled to the clamping network 116. The clamping network 116 provides a chucking voltage, such as a static DC voltage between approximately −5000 V and approximately 10,000 V, to the bias electrode 104 and the edge control electrode 115 using an electrical conductor, such as a coaxial power supply line 106 (e.g., a coaxial cable). Applying similarly configured PV waveforms to the bias electrode 104 and the edge control electrode 115 can help improve plasma uniformity across the surface of the substrate during processing, thereby helping to improve the results of the plasma treatment process. Adjusting the edge PV voltage can reduce feature tilt at the extreme wafer edge and improve the MTBC of the process kit. Application of sufficient clamping voltage to the bias electrode 104 and the edge control electrode 115 can facilitate temperature control of the substrate and edge ring. Clamping network 116 includes bias compensation circuit element 116A, DC power supply 155, and bias compensation module blocking capacitor 116. The bias compensation module blocking capacitor 116A is also referred to herein as blocking capacitor C5. Blocking capacitor C5 is disposed between the output of PV waveform generator 150 and bias electrode 104 or edge control electrode 115.

[0030]

[0037] The edge control electrode 115 may be biased through the use of a second PV waveform generator 150 that is different from the PV waveform generator 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 may be biased using the PV waveform generator 150 that is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of a third PV source assembly 197 is configured to bias the edge control electrode 115.

[0031]

[0038] In some embodiments, as shown in FIG. 2B , the edge control electrode 115, when used in conjunction with an edge tuning circuit 170, is generally positioned to affect or modify a portion of the generated plasma 101 that is above or outside the peripheral edge of the substrate 103. In some embodiments, the edge tuning circuit 170 electrically coupled to the edge control electrode 115 can be used to manipulate one or more characteristics of the RF power used to ignite and / or maintain a plasma in the processing region 129A above the edge control electrode 115. For example, in some embodiments, the edge tuning circuit 170 can be used to adjust and / or manipulate one or more of the voltage, current, and / or stage of the RF power used to ignite and / or maintain a plasma 101 in a processing region disposed between the edge control electrode 115 and the chamber lid 123. In some embodiments, the edge tuning circuit 170 is electrically coupled between the edge control electrode 115 and the plasma generator assembly 163, as shown in FIG. 2B . In some embodiments, the edge-tuned circuit 170 is configured as a resonant circuit. The resonant circuit includes an inductor and a capacitor (e.g., an LC circuit). The capacitor is used to adjust the characteristics of the RF power used to maintain the plasma in the processing region 129A. In one embodiment, the edge-tuned circuit 170 includes an inductor and a variable capacitor arranged in parallel (i.e., a parallel LC resonant circuit). In another embodiment, the inductor and the variable capacitor are arranged in series (i.e., a series LC resonant circuit). The type of LC resonant circuit (e.g., parallel or series) selected for the edge-tuned circuit 170 may depend on the desired distribution of plasma density over the substrate support assembly 136, such as the desired distribution of plasma density from the center to the edge of the substrate support assembly 136 and / or over the periphery of the substrate 103.

[0032]

[0039] 2A , in some embodiments, the upper electrode assembly 131 includes an upper electrode (e.g., chamber lid 123), an electrode insulator 143, and an upper grounded plate 145. The upper electrode is disposed on and electrically isolated from the grounded sidewall 122 by a lid insulator 137. In FIG. 2A , the upper electrode, such as the chamber lid 123, is electrically coupled to at least one plasma generator assembly 163. The at least one plasma generator assembly 163 is configured to ignite and maintain a plasma 101 in a processing region therebetween. In some embodiments, the plasma generator assembly 163 is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially constant sinusoidal frequency to the chamber lid 123 based on control signals provided from the system controller 126. In this configuration, as shown in FIG. 2A, the process gas source 119 can be configured to supply one or more process gases to the process region 129A through one or more ports formed in the grounded wall 122.

[0033]

[0040] In some alternative embodiments, the upper electrode assembly 131 includes an upper electrode (e.g., chamber lid 123) and a lid plate 139 configured to form a showerhead configured to evenly distribute one or more gases provided from the process gas source 119 to the process region 129A through a plurality of holes 123B formed in the upper electrode. The upper electrode assembly 131 is also disposed on and electrically isolated from the grounded wall 122 by a lid insulator 137. While a second PV source assembly 199 having a showerhead-type upper electrode assembly 131 is shown in FIG. 2B, this configuration is not intended to be a limitation on the scope of the disclosure provided herein, as either the second PV source assembly 198 or 199 can be used with any of the various upper electrode assembly 131 configurations disclosed herein.

[0034]

[0041] As shown in FIG. 2B , one or more components of the substrate support assembly 136, such as the support base 107, are electrically coupled to a plasma generator assembly 163. In some embodiments, the plasma generator assembly 163 is configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially constant sinusoidal frequency to the support base 107 of the substrate support assembly 136, generally based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107, which is disposed proximate to the substrate support 105 and within the substrate support assembly 136. Also shown in FIG. 2B , the upper electrode may also be electrically coupled to the at least one plasma generator assembly 163. The at least one plasma generator assembly 163 is configured to ignite and maintain a plasma 101 in a processing region therebetween, or to provide a low-frequency RF signal, as described further below.

[0035] Multiple examples of waveforms

[0042] It has been discovered that the application of PV waveforms (one or more) to the bias electrode 104 and edge control electrode 115 during plasma processing can be used to desirably control the sheath voltage across the surface and edge of a substrate during plasma processing. The ability to control and maintain a substantially constant sheath voltage throughout a significant portion of a PV waveform cycle (e.g., the “ion current stage” of FIG. 3 ) enables the production of a desired ion energy distribution function (IEDF) at the surface of the substrate during a significant portion of one or more plasma processing operations. The application of PV waveforms to the bias electrode 104 and edge control electrode 115 can be used to improve plasma processing results by enabling the population of ions accelerated toward the surface of the substrate to be contained within one or more (narrow) IEDF peaks, depending on the type and number of PV waveforms provided to the electrodes. Controlling the IEDF can also have the advantage of helping to reduce the amount of trapped charge (or trapped charge effects) found in high aspect ratio features by tightly controlling the magnitude and range of ion energies during plasma processing.

[0036]

[0043] 3 shows an example of a multi-stage sequence 402 of PV waveforms 425 established at the substrate 103, with the PV waveform 401 (FIG. 4A) established at the bias electrode 104 based on the PV waveform generated by the PV waveform generator 150. The PV waveforms 401 established at the bias electrode 104 and the edge control electrode 115 are shown in FIG. 4A as a multi-stage sequence 490. The PV waveforms 401 may be established at the bias electrode 104 and the edge control electrode 115 through the use of the PV waveform generators 150 in the respective PV source assemblies 196 and 197 and the DC power supplies 155 of the corresponding clamping networks 116. Generally, the output of the PV waveform generator 150 may be controlled by settings in a plasma processing recipe stored in the memory of the system controller 126 to generate the PV waveform 401. The PV waveform 401 is herein referred to as a pulsed voltage level V ppThe peak-to-peak voltage level V established at the various electrodes based on the power supply line inductance and series capacitance (one or more) and stray capacitance. pp is the output of the PV waveform generated by the PV waveform generator 150 (e.g., the output voltage V OUT ), but in reality it is different.

[0037]

[0044] Waveform period T P The PV waveform 425, having a sheath collapse and recharge stage 450, a sheath generation stage 451, and an ion current stage 452, is characterized as including a sheath collapse and recharge stage 450 extending between points 420 and 421. The sheath generation stage 451 extends between points 421 and 422. The ion current stage 452 extends between points 422 and 420, returning to the start of the next sequentially established pulse voltage waveform. For ease of explanation herein, the sheath collapse and recharge stage 450 and the sheath generation stage 451 occur primarily within the first region 405 of the PV waveform 425, while the ion current stage 452 occurs primarily within the second region 406 of the PV waveform 425. The sheath collapse stage portion of the sheath collapse and recharge stage 450 generally includes a period during which the sheath capacitance is discharged and the bulk plasma comes into contact with the substrate surface. Electrons in the bulk plasma neutralize excess positive charge on the substrate surface and internal features. Internal features are deposited by ion flux and / or secondary electron flux during the ion current stage. In some embodiments, negative charge can also be injected or accumulated on the substrate surface during the sheath collapse and recharge stage 450. The plasma current during the recharge stage portion is also carried by electrons; that is, in the absence of a cathode sheath, electrons reach the substrate and accumulate surface charge. The sheath generation stage 451 generally charges the floating capacitors of the processing chamber, regenerates the sheath, and generates a sheath voltage (V SHThe ion current stage 452 is generally a long stage (e.g., >50%, such as approximately 80%-90% of the PV waveform cycle) of the PV waveform. It is associated with the generation of high-energy ions by the generated sheath. The high-energy ions are used to perform the plasma etching process on the substrate 103. However, the generated ion current results in a buildup of positive charge on the substrate surface, gradually discharging the sheath and chuck capacitor, slowly reducing the sheath voltage drop and causing the substrate potential to approach zero. This results in a voltage drop in the substrate PV waveform 425 (FIG. 3). Due to the generated sheath voltage drop, the pulse waveform (or waveforms) must move to the next PV waveform cycle.

[0038]

[0045] Depending on the desired plasma processing conditions, the PV waveform frequency (1 / T P ), pulse voltage level V pp It may be desirable to control and set at least the PV waveform characteristics, such as the pulse voltage on-time, and / or other parameters of the PV waveform 401. In one embodiment, the pulse voltage (PV) on-time is determined by the ion current period (e.g., the time between point 422 and the next point 420 in FIG. 3 ) and the waveform period T P and is greater than 50%, or greater than 70%, for example between 80% and 95%.

[0039]

[0046] 4B illustrates an alternating PV waveform in which the PV waveform generator 150 is configured to control the generation of a multi-step-shaped PV waveform 441 of a multi-step series 491 established at the bias electrode 104 and the edge control electrode 115. In some embodiments, the multi-step-shaped PV waveform 441 is generated by the PV waveform generator 150. The PV waveform generator 150 is configured to provide a positive voltage during one or more stages (e.g., first region 405) of a voltage pulse and a time-varying negative voltage during one or more stages (e.g., second region 406) of the voltage pulse through the use of one or more internal switches and a DC power supply.

[0040]

[0047] In some embodiments, as shown in FIG. 4C , the PV waveform generator 150 is configured to provide an alternating sequence 492 of a multi-stage positive PV waveform 431 to the bias electrode 104 and the edge control electrode 115. Each positive pulse in the positive PV waveform 431 can include multiple stages, such as a sheath collapse stage, a recharge stage, a sheath creation stage, and an ion current stage. In some embodiments, the multi-stage positive PV waveform 431 includes a sequence of repeating cycles, such that the waveform in each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval. The multi-stage positive PV waveform 431 also includes a positive voltage that is present only during at least a portion of the first time interval. The multi-stage positive PV waveform 431 is substantially constant during at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a positive voltage supply during at least a portion of the first time interval.

[0041]

[0048] 4A, 4B, and 4C each represent a pulsed voltage waveform that may be established at node N connected to the input of clamping network 116, and therefore may differ from the pulsed voltage waveforms established at bias electrode 104 and edge control electrode 115. The DC offset ΔV seen in each PV waveform depends on the bias applied by DC power supply 155 in clamping network 116 and various characteristics of the configuration of PV waveform generator 150 used to establish the PV waveform. Generally, the pulsed voltage waveforms established at electrodes 104 and 115 (e.g., negative PV waveform 401, shaped PV waveform 441, or positive PV waveform 431) have a waveform period T P The waveform period T Pcan be between about 1 μs and about 5 μs, e.g., about 2.5 μs. In some embodiments, the pulse voltage waveform has a frequency between about 1 kHz and about 1 MHz, or about 400 kHz, e.g., about 1 MHz or less, or about 500 kHz or less. In some embodiments, the pulse waveform frequency can range between about 10 kHz and about 500 kHz, or between about 50 kHz and 400 kHz, or between about 50 kHz and 200 kHz.

[0042] Methods for reducing trapped charge

[0049] As briefly mentioned above, the apparatus and methods disclosed herein are used to eliminate or reduce the effects of trapped charge disposed within features formed on a substrate. In some embodiments, the method includes synchronizing the delivery of multiple pulsed voltage (PV) waveforms to result in the generation of electrons during one or more stages of a PV waveform cycle to neutralize trapped charge found within features formed on the substrate. In an alternative embodiment, the method includes synchronizing the delivery of a PV waveform and a radio frequency (RF) waveform to result in the generation of electrons during one or more stages of a PV waveform cycle to neutralize trapped charge within features formed on the substrate.

[0043]

[0050] 5A shows three synchronized PV waveforms 460, 461, and 462, which are provided to the chamber lid 123, bias electrode 104, and edge control electrode 115, respectively, by use of second PV source assemblies 198, 199, first PV source assembly 196, and third PV source assembly 197. In one embodiment, the PV waveforms 461 and 462 provided to the bias electrode 104 and edge control electrode 115 have PV on-time, pulse voltage level V pp , and the waveform period T P In another embodiment, PV waveforms 461 and 462 include PV waveforms having the same waveform characteristics, such as a pulse voltage level V applied to the PV waveform in a sequence of PV waveform pulses provided to each of the electrodes. ppPV waveforms 461 and 462 include PV waveforms having the same waveform characteristics except for different waveforms. PV waveforms 461 and 462 may include PV waveform shapes similar to PV waveforms 401, 431, or 441 described above in connection with FIGS. 4A-4C.

[0044]

[0051] 5A , PV waveform 460 applied to the upper electrode is synchronized with the delivery of PV waveforms 461 and 462. However, the PV waveform characteristics of PV waveform 460 desirably differ from the PV waveform characteristics of PV waveforms 461 and 462. In some embodiments, as shown in FIG. 5A , PV waveform 460 is the inverse of, or "inversely configured" with, PV waveforms 461 and 462. In other words, the low voltage state of PV waveform 460 seen in first stage 455 of PV waveform 460 coincides with the high voltage state produced during first stage 405 of PV waveforms 461 and 462, and the high voltage state of PV waveform 460 provided in second stage 456 of PV waveform 460 coincides with the low voltage state produced during second stage 406 of PV waveforms 461 and 462. In some embodiments, there may be a controlled time lag between the start of stage 455 and the start of 405, and / or between the end of stage 455 and the end of stage 405. For example, stage 455 may be embedded within stage 405, or stage 405 may be embedded within stage 455.

[0045]

[0052] Applying an inversely configured PV waveform 460 increases the sheath voltage generated at the surface of the upper electrode (e.g., chamber lid 123) during the first stage 455 of the PV waveform 460. A higher sheath voltage causes ions to be accelerated to higher energies during the process of impacting the surface of the upper electrode during the first stage 455, thereby generating secondary electrons. Secondary electrons are generated when ions impact the surface of the upper electrode, and the yield of secondary electrons resulting from ion impacts depends on the incident ion energy. In the incident ion energy range of several hundred to several thousand electron volts (eV), the yield of secondary electrons increases with incident ion energy. Therefore, a higher sheath voltage at the upper electrode during stage 455 increases the generation of secondary electrons from the upper electrode during stage 455. The secondary electrons are accelerated toward the substrate by the sheath voltage generated at the upper electrode. As the sheath voltage increases, the generated secondary electrons have an increased velocity perpendicular to the substrate. The angular distribution of these secondary electrons is thereby centered near zero degrees (0°) from an axis oriented perpendicular to the surface of the upper electrode, allowing more electrons to travel deep into the features formed on the substrate to neutralize the positive charge inside the features. P The total amount of secondary electrons emitted from the upper electrode during will generally depend on the duration of the first stage 455, the pulse voltage of the PV waveform 460, the material properties of the material exposed to the ion flux, and the gas composition used to generate the plasma 101 in the process chamber.

[0046]

[0053] In some embodiments, the voltage gradient or pulse rise / fall time at the beginning of stages 455 and 405 can be set differently. A steep voltage ramp during stage 405 can cause fast substrate sheath collapse. Under some plasma processing conditions, such as low pressure (<10 mT), high substrate sheath thickness, and / or the use of electronegative gas chemistries, the bulk plasma resistance is relatively high during fast substrate sheath collapse. This is because the electron density is low and electron inertia tends to inhibit a rapid response to a fast substrate voltage ramp. A fast substrate voltage ramp induces a strong transient electric field above the substrate surface, which results in the acceleration of bulk electrons toward the substrate. As the bulk electrons accelerate across the strong transient electric field region, they gain energies of up to hundreds to thousands of electron volts (eV) and become highly directional toward the substrate. This provides another source of highly directional electrons that can travel deep into features formed on the substrate and neutralize the residual positive charge created there. Thus, in some embodiments, the generated secondary electrons can have energies up to 3 keV and are highly directional toward the substrate surface. Separately, during the low voltage states of PV waveforms 461 and 462, a sheath (e.g., ion current stage 452) is generated above the surface of the substrate, causing accelerating ions to impact and etch the surface of substrate 103.

[0047]

[0054] In some embodiments, the high-energy, directional electrons can also be utilized to promote cross-linking of a top mask material formed on the surface of the substrate. This top mask material may be composed of cross-linked carbon and some dopants, such as silicon, nitrogen, and oxygen. The high-energy, directional electrons provide sufficient energy to create active atomic sites, which then form new chemical bonds within the mask material. This improves the etch resistance of the mask to the plasma and the selectivity of the etch material to the mask.

[0048]

[0055] In some embodiments, high-energy electrons can also be used to improve the selectivity of etched materials relative to etch-stop layers. Because highly directional electrons can penetrate deep into the bottom of a feature, they can modify the chemical state of the upper etch-stop layer when the etch-stop layer is exposed to the plasma. The modified etch-stop layer is more resistant to being etched by the plasma, thereby improving etch selectivity. Such selectivity is particularly useful for etching complex 3D structures, such as staircases, where several etch-stop layers exist at different depths in different trenches.

[0049]

[0056] FIG. 5B shows a simplified schematic diagram of the processing chamber 100. This diagram also includes an overlaid representation of a PV waveform cycle of a PV waveform 460 applied to an upper electrode (e.g., the chamber lid 123) and a PV waveform 461 applied to the bias electrode 104. For ease of illustration, a PV waveform 462 is omitted from FIG. 5B, but may also be simultaneously applied to the edge control electrode 115. As shown in FIG. 5B, during the second region 406 of the PV waveform 461 and the second region 456 of the PV waveform 460, a sheath 503 is generated above the surface of the substrate 103. This allows ions 504 provided in the ion flux 505 to impact the surface 103A of the substrate 103. The process of impacting the surface of the substrate during the ion current stage 452 will continue for a period extending between time T0 and time T1. During this stage, positive charge will be deposited in features on the substrate 103. The bias applied to the bias electrode 104 is a peak-to-peak voltage V generated by the PV waveform generators 150 in the first and second PV source assemblies 196 and 198. PP and pulse voltage on time, which controls the sheath thickness and sets the ion energy used to bombard the surface 103A of the substrate 103. In some embodiments, the PV waveform generator 150 controls pulse voltage levels (e.g., V ) between 0.01 kV and 10 kV. pp) to the bias electrode 104 and the edge control electrode 115.

[0050]

[0057] During first region 405 of PV waveform 461 and first region 455 of PV waveform 460, a sheath 508 is generated above the surface of the upper electrode (i.e., chamber lid 123). This allows ions provided in the generated ion flux to impact the surface of the upper electrode, thereby generating secondary electrons 506 contained within electron flux 507. As shown in FIG. 5B, the process of impacting the surface of the upper electrode continues for a period extending between time T1 and time T2. First regions 405 and 455 are generated over a pulse period T P In one example, the first regions 405 and 455 may have a duration between 50 nanoseconds (ns) and 1000 ns. In some embodiments, the PV waveform generator 150 in the second PV source assembly generates pulsed voltage levels (e.g., V pp) to the upper electrode (e.g., chamber lid 123). The energy provided to the generated electrons by the generation of the sheath 508 then causes the electrons to migrate to, interact with, and neutralize trapped positive charges deposited in features formed on the surface of the substrate 103 during stages 456 and 406 of the PV waveforms 460 and 461 of the waveform cycle. Also, in some embodiments, the configuration of the upper electrode as a parallel plate relative to the substrate support surface 105A and the generation of the sheath 508 above the upper electrode (i.e., surface 123A of the chamber lid 123) causes the generated secondary electrons to be accelerated by the voltage on the sheath 508 in a direction perpendicular to the substrate surface 103A, such as the vertical direction shown in FIG. 5 . The generation of a desirably directed electron flux promotes the delivery of electrons to lower portions (i.e., deeper portions) of etched features formed in the surface of the substrate. The directionality of the generated secondary electrons further enables the generated electrons to travel to, interact with, and neutralize trapped positive charges deposited within features formed on the surface of the substrate 103 during stage 406 of the PV waveform cycle.

[0051]

[0058] In some embodiments, the duration of first region 405 of PV waveform 461 is substantially equal to the duration of first region 455 of PV waveform 460. Thus, in some embodiments, first region 405 of PV waveform 461 is synchronized with first region 455 of PV waveform 460, such that the start of first region 455 of PV waveform 460 and the start of first region 455 of PV waveform 460 begin substantially simultaneously, and first regions 455 and 405 have substantially the same duration. However, in some embodiments, first region 405 of PV waveform 461 is offset in time from first region 455 of PV waveform 460, such that first region 455 of PV waveform 460 and first region 455 of PV waveform 460 overlap in time. In some cases, such as when there is an offset in time between the generation of first regions 455 and 405, it may be desirable for the duration of first region 405 of PV waveform 461 to be shorter or longer than the duration of first region 455 of PV waveform 460.

[0052]

[0059] In some embodiments, it is desirable to select the material of the upper electrode exposed to the ion flux so as to maximize the production of secondary electrons generated at the upper electrode surface. In some embodiments, the exposed surface of the upper electrode is formed from a conductive or semiconducting material, or a dielectric material selected from the group consisting of metals, semiconductor materials, and doped semiconductor materials, or combinations thereof. In one example, the material exposed at the upper electrode surface of the upper electrode is amorphous or crystalline silicon (Si), silicon carbide (SiC), silicon nitride (SiN xIn another embodiment, the material exposed at the upper electrode surface of the upper electrode is a silicon-containing material, such as silicon dioxide, silicon nitride, silicon dioxide (SiO2), or a moderately or heavily doped silicon material. In another embodiment, the material exposed at the upper electrode surface of the upper electrode is a material including graphite, germanium (Ge), gallium (Ga), or a combination or doped version thereof. In another embodiment, the material exposed at the upper electrode surface of the upper electrode is a material including a metal, such as aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), or nickel (Ni), or a combination thereof. In another embodiment, the material exposed at the upper electrode surface of the upper electrode is a material including a dielectric, such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, yttrium oxide, zirconia oxide, or a combination thereof.

[0053]

[0060] Generally, it is desirable to control the amount of energy provided to ions impinging on the surface of the upper electrode and also to select a material that does not contaminate the substrate by producing ion-assisted chemical etching or physical sputtering by-products. These by-products may be deposited on the substrate surface during the time period defined by first region 405 of PV waveform 461 and first region 455 of PV waveform 460. In some embodiments, it is desirable to select an upper electrode material that is similar to the material being etched on the substrate. In some embodiments, it is desirable to select an upper electrode material that produces only sufficiently volatile by-products within normal process conditions (pressure and substrate temperature), thereby minimizing the amount of by-products deposited on the substrate surface. In some embodiments, it is desirable to select a process chemistry that is sufficiently polymerizable to form a coating on the upper electrode surface. This ensures that the ion-assisted chemical etching reaction occurs mostly within the polymer coating layer, protecting the bulk upper electrode material from erosion.

[0054]

[0061] In some embodiments, it may be desirable to select and / or adjust the process gas composition to control the secondary electron generation process. In one example, a process gas containing nitrogen (N), oxygen (O), sulfur (NF or SF), or a fluorine-containing gas (e.g., NF, F, CF, CF) can be used to react with the upper electrode surface (e.g., Si or SiC) to form a top layer of a new material on the upper electrode that has a higher secondary electron emission coefficient. The process gas may also contain inert gases such as argon (Ar), krypton (Kr), and neon (Ne). In another example, a plasma etching process containing a polymerizing process gas such as CF, CF, CF, CF, CHF, and CHF can be used to form a polymer coating on the upper electrode surface that has a higher secondary electron emission coefficient than the bulk upper electrode material. In one embodiment, the plasma etching process includes supplying a process gas having a composition formed by generating a C4F6 gas flow rate to C3F6 gas flow rate ratio of about 4, a C4F6 gas flow rate to O2 gas flow rate ratio of about 0.8, and a C4F6 gas flow rate to N2 gas flow rate ratio of about 1.1 at a chamber pressure between about 1 mTorr and 40 mTorr.

[0055]

[0062] As shown in FIG. 5B by the partial view of second region 406 of repeated PV waveform 461 and second region 456 of PV waveform 460, after one PV waveform cycle is completed, multiple additional PV waveform cycles are repeated consecutively. In some embodiments, the PV waveform has a waveform period T of about 2.5 μs. P and is continuously repeated in PV waveform bursts having burst periods between about 100 microseconds (μs) and about 10 milliseconds (ms). The PV waveform bursts may have a burst duty cycle that is between about 5% and 100%, for example, between about 30% and about 95%. The duty cycle is the ratio of the burst period divided by the burst period plus the non-burst periods (i.e., when no PV waveform is generated) that separate the burst periods.

[0056]

[0063] 6A , two PV waveforms 461 and 462 are applied to bias electrode 104 and edge control electrode 115, respectively, using first PV source assembly 196 and third PV source assembly 197, and are synchronized with RF waveform 470 provided to chamber lid 123 by RF generator assembly 163. As also described above, PV waveforms 461 and 462 may include PV waveforms having identical or substantially identical waveform characteristics and having a similar PV waveform shape as PV waveforms 401, 431, or 441.

[0057]

[0064] 6A, RF waveform 470 is synchronized with the delivery of PV waveforms 461 and 462. RF waveform 470 may include a sinusoidal waveform having a frequency that matches the frequency of PV waveforms 461 and 462. In one example, RF waveform 470 and PV waveforms 461 and 462 are synchronized with a frequency (1 / T) of less than about 1 MHz, for example, between about 50 kHz and 500 kHz. P ) . As shown in FIG. 6A , RF waveform 470 is inversely shaped or “inversely configured” to PV waveforms 461 and 462. As shown in FIG. 6A , the low points in the sinusoidal waveform (i.e., the troughs of the RF waveform) coincide with the high voltage states produced during first regions 405 of PV waveforms 461 and 462, and the high voltage points of RF waveform 470 (i.e., the peaks of the RF waveform) coincide with the low voltage states produced during second regions 406 of PV waveforms 461 and 462. In some embodiments, the duration of first region 405 of PV waveform 461 is substantially equal to the duration of first region 475 of RF waveform 470. In one example, the duration of first region 405 of PV waveform 461 is equal to the duration of one-half the period of RF waveform 470. In some embodiments, first region 405 of PV waveform 461 is offset in time from first region 475 of RF waveform 470. As a result, the first region 455 of the PV waveform 460 and the first region 475 of the RF waveform 470 overlap in time.

[0058]

[0065] Supplying an inversely configured RF waveform 470 contributes to the generation of a larger sheath voltage sheath 608 at the surface of the upper electrode (e.g., chamber lid 123) during the low points of the RF waveform 470. The higher sheath voltage accelerates ions to higher energies during the period when they collide with the surface of the upper electrode. Secondary electrons are generated by ions colliding with the upper electrode surface, and the yield of secondary electrons depends on the incident ion energy. In the incident ion energy range of several hundred to several thousand electron volts (eV), the yield of secondary electrons increases with incident ion energy. Therefore, a higher sheath voltage at the upper electrode during stage 475 increases the generation of secondary electrons from the upper electrode during stage 475. The secondary electrons are accelerated toward the substrate by the sheath voltage near the upper electrode. A higher sheath voltage results in a desirable increase in the velocity of the secondary electrons in a direction perpendicular to the substrate. The angular distribution of these secondary electrons is thereby centered closer to zero degrees, allowing more electrons to travel deeper into features on the substrate to neutralize the positive charge inside the features. The steep voltage ramp of step 405 can cause fast substrate sheath collapse. Under some plasma processing conditions, such as low pressure (<10 mT), high substrate sheath thickness, and / or the use of electronegative gas chemistries, the bulk plasma resistance becomes relatively high during fast substrate sheath collapse because the electron density is low and electron inertia tends to inhibit a rapid response to fast substrate voltage ramps. A fast substrate voltage ramp induces a strong transient electric field on the substrate surface, which results in the acceleration of bulk electrons toward the substrate. When the bulk electrons are accelerated across the strong transient electric field region, they gain energies of up to hundreds to thousands of electron volts (eV) and become highly directional toward the substrate. This provides another source of highly directional electrons that travel deep into features formed on the substrate and neutralize the residual positive charge there. Thus, in some embodiments, the secondary electrons generated can have energies up to 3 keV and are highly directional towards the substrate surface.

[0059]

[0066] 6B shows a simplified schematic diagram of the processing chamber 100. This diagram also includes an overlaid representation of a PV waveform cycle of an RF waveform 470 applied to an upper electrode (e.g., chamber lid 123) and a PV waveform 461 applied to the bias electrode 104. As shown in FIG. 6B, during the second region 406 of the PV waveform 461 and the second region 476 of the RF waveform 470, a sheath 503 is generated above the surface of the substrate 103. This accelerates ions 504 from the bulk plasma to impact the surface 103A of the substrate 103. As described above, the bias applied to the bias electrode 104 is determined by the peak-to-peak voltage V applied by the PV waveform generator 150 and the RF generator assembly 163. PP This controls the sheath thickness and sets the ion energy used to bombard the surface 103A of the substrate 103.

[0060]

[0067] During the first region 405 of the PV waveform 461 and the first region 475 of the RF waveform 470, a sheath 608 is generated above the surface of the upper electrode (i.e., the chamber lid 123). This allows ions accelerated from the bulk plasma through the sheath 608 to impact the surface of the upper electrode. This generates secondary electrons 606 contained within an electron flux 607. As shown in FIG. 6B , the process of impacting the surface of the upper electrode continues for a period extending between time T1 and time T2. Due to the parallel geometry of the upper electrode and the substrate, the secondary electrons are accelerated by the sheath 608 in a direction perpendicular to the substrate surface. The secondary electrons are thereby highly directional toward the substrate and can travel deep into features formed on the surface of the substrate 103, interacting with and neutralizing the trapped positive charges therein during stage 405 of the PV waveform cycle. In some embodiments, the highly energetic electrons generated during stage 405 of the PV waveform cycle may also be utilized to improve the selectivity of the etch material relative to the mask material and / or the etch material relative to the etch stop layer.

[0061]

[0068] Some embodiments of the present disclosure may provide a processing method. The processing method includes establishing a first pulsed voltage waveform at a bias electrode disposed within a substrate support assembly using a first waveform generator and establishing a second pulsed voltage waveform at a surface of the first electrode disposed above the substrate support assembly using a second waveform generator. The first pulsed voltage waveform includes a first stage and a second stage having a voltage level lower than that of the first stage. The second pulsed voltage waveform includes the first stage and a second stage having a voltage level higher than that of the first stage. During the processing method, the first pulsed voltage waveform and the second pulsed voltage waveform are synchronized such that the first stage of the first pulsed voltage waveform and the first stage of the second pulsed voltage waveform at least partially overlap in time, and the second stage of the first pulsed voltage waveform and the second stage of the second pulsed voltage waveform at least partially overlap in time. The voltage level during the first stage of the second pulsed voltage waveform can be configured to generate secondary electrons from the surface of the first electrode, where the first electrode includes silicon. During the processing method, the duration of the first stage of the first pulsed voltage waveform and the duration of the first stage of the second pulsed voltage waveform can be substantially equal. In some embodiments, the voltage level during the first stage of the second pulsed voltage waveform is configured to cause ions to collide with the surface of the first electrode, gaining energy up to 3 keV and generating secondary electrons that can have a high directionality toward the substrate surface. The frequencies of the first pulsed voltage waveform and the second pulsed voltage waveform can also be less than about 1 MHz.

[0062]

[0069] The processing methods disclosed herein may further include establishing a third pulsed voltage waveform at a second electrode disposed within the substrate support assembly by use of a third waveform generator, wherein the third pulsed voltage waveform includes a first stage and a second stage having a voltage level lower than that of the first stage. In some embodiments, the first stage of the first pulsed voltage waveform and the first stage of the third pulsed voltage waveform are established simultaneously, and the second stage of the first pulsed voltage waveform and the second stage of the third pulsed voltage waveform are established simultaneously.

[0063]

[0070] Some embodiments of the present disclosure may provide a processing method. The processing method includes establishing a first pulsed voltage waveform at a bias electrode disposed within a substrate support assembly using a first waveform generator and establishing an RF waveform at a first electrode disposed above the substrate support assembly using an RF waveform generator. The first pulsed voltage waveform includes a first stage and a second stage having a voltage level lower than the voltage level in the first stage. The substrate support assembly includes a substrate support surface, a bias electrode, and a first dielectric layer disposed between the bias electrode and the substrate support surface. In some embodiments, the RF waveform includes a sinusoidal waveform. The first pulsed voltage waveform and the RF waveform are synchronized such that a valley of the RF waveform is formed during a period when the first stage of the first pulsed voltage waveform is established at the bias electrode, and a peak of the RF waveform is formed during a period when the second stage of the first pulsed voltage waveform is established at the bias electrode. The processing method may further include establishing a third pulsed voltage waveform at a second electrode disposed within the substrate support assembly using a third waveform generator. In this case, the third pulsed voltage waveform includes a first stage and a second stage having a voltage level lower than that of the first stage. The first stage of the first pulsed voltage waveform and the first stage of the third pulsed voltage waveform may be established simultaneously, and the second stage of the first pulsed voltage waveform and the second stage of the third pulsed voltage waveform may also be established simultaneously. The first pulsed voltage waveform and the RF waveform may have a frequency of less than about 1 MHz.

[0064]

[0071] Thus, the above-described embodiments can be used alone or in combination to provide fine control over the generation of highly directional electrons toward a substrate surface in a portion of a waveform applied to an upper electrode disposed within a processing region of a capacitively coupled plasma (CCP) chamber. Advantageously, the embodiments can be implemented using a system without adjusting or modifying individual chamber components, thereby providing process recipe parameters that can be easily adjusted during the processing of one or more substrates.

[0065]

[0001] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is defined by the following claims.

Claims

1. 1. A plasma processing system comprising: Assume that the substrate support assembly comprises: a substrate support surface; a bias electrode, and a first dielectric layer disposed between the bias electrode and the substrate support surface; a first waveform generator coupled to the bias electrode, the first waveform generator configured to generate a first plurality of pulsed voltage waveforms established at the bias electrode, each pulsed voltage waveform of the first plurality of pulsed voltage waveforms including a first stage and a second stage having a voltage level lower than a voltage level in the first stage; a first electrode disposed on the substrate support surface; a second waveform generator coupled to the first electrode, the second waveform generator configured to generate a second plurality of pulsed voltage waveforms established at the first electrode, each pulsed voltage waveform of the second plurality of pulsed voltage waveforms including a first stage and a second stage having a voltage level higher than a voltage level in the first stage; a controller comprising a memory containing computer-implemented instructions that, when executed by a processor, are configured to synchronize generation of the first plurality of pulsed voltage waveforms and the second plurality of pulsed voltage waveforms, thereby: the first stage of the pulsed voltage waveform within the first plurality of pulsed voltage waveforms and the first stage of the pulsed voltage waveform within the second plurality of pulsed voltage waveforms at least partially overlap in time; The second stage of the pulsed voltage waveform within the first plurality of pulsed voltage waveforms and the second stage of the pulsed voltage waveform within the second plurality of pulsed voltage waveforms at least partially overlap in time.

2. 2. The plasma processing system of claim 1, wherein a duration of the first stage of the pulsed voltage waveforms in the first plurality of pulsed voltage waveforms and a duration of the first stage of the pulsed voltage waveforms in the second plurality of pulsed voltage waveforms are substantially equal.

3. 10. The plasma processing system of claim 1, wherein the substrate support assembly further comprises a second electrode positioned at a distance from a center of the substrate support surface and a center of the first electrode.

4. 4. The plasma processing system of claim 3, further comprising: a second waveform generator coupled to the second electrode, the second waveform generator configured to generate a third plurality of pulsed voltage waveforms established at the second electrode, each pulsed voltage waveform of the third plurality of pulsed voltage waveforms including a first stage and a second stage having a voltage level lower than a voltage level in the first stage.

5. 5. The plasma processing system of claim 4, wherein the computer-implemented instructions are further configured to synchronize the generation of the first plurality of pulsed voltage waveforms with the generation of the third plurality of pulsed voltage waveforms.

6. 10. The plasma processing system of claim 1, further comprising a radio frequency (RF) generator electrically coupled to the bias electrode, the first electrode, or the second electrode.

7. 2. The plasma processing system of claim 1, wherein the first electrode has a surface facing the substrate support surface, the surface being substantially parallel to the substrate support surface.

8. 8. The plasma processing system of claim 7, further comprising a radio frequency (RF) generator electrically coupled to the first electrode.

9. 2. The plasma processing system of claim 1, wherein each of the pulsed voltage waveforms in the first plurality of pulsed voltage waveforms and each of the pulsed voltage waveforms in the second plurality of pulsed voltage waveforms are configured inversely.

10. establishing a first pulsed voltage waveform at a bias electrode disposed within the substrate support assembly by using a first waveform generator; The first pulse voltage waveform is The first stage, a second stage having a voltage level lower than the voltage level in the first stage; and establishing a second pulsed voltage waveform at a surface of a first electrode disposed above the substrate support assembly by using a second waveform generator; The second pulse voltage waveform is The first stage, a second stage having a voltage level higher than the voltage level in the first stage; The first pulse voltage waveform and the second pulse voltage waveform are synchronized, thereby the first stage of the first pulsed voltage waveform and the first stage of the second pulsed voltage waveform at least partially overlap in time; establishing a second pulsed voltage waveform, wherein the second stage of the first pulsed voltage waveform and the second stage of the second pulsed voltage waveform at least partially overlap in time.

11. 11. The method of claim 10, wherein the duration of the first stage of the first pulsed voltage waveform and the duration of the first stage of the second pulsed voltage waveform are substantially equal.

12. establishing a third pulsed voltage waveform at a second electrode disposed within the substrate support assembly by using a third waveform generator; The third pulse voltage waveform is The first stage, a second stage having a voltage level lower than the voltage level in the first stage.

13. the first stage of the first pulse voltage waveform and the first stage of the third pulse voltage waveform are established simultaneously; The method of claim 10 , wherein the second stage of the first pulsed voltage waveform and the second stage of the third pulsed voltage waveform are established simultaneously.

14. 11. The method of claim 10, wherein the first pulsed voltage waveform and the second pulsed voltage waveform have a frequency less than about 1 MHz.

15. The substrate support assembly includes: a substrate support surface; and The method of claim 10 including a first dielectric layer disposed between the bias electrode and the substrate support surface.

16. 11. The method of claim 10, wherein the voltage levels in the first stage of the second pulsed voltage waveform are configured to generate secondary electrons from the surface of the first electrode.

17. 17. The method of claim 16, wherein the first electrode comprises silicon.

18. 20. The method of claim 17, wherein the voltage levels within the first stage of the second pulsed voltage waveform are configured to cause ions to bombard the surface of the first electrode and generate secondary electrons that can have energies up to 3 keV and can be highly directional toward a substrate surface.

19. establishing a first pulsed voltage waveform at a bias electrode disposed within the substrate support assembly by using a first waveform generator; The first pulse voltage waveform is The first stage, a second stage having a voltage level lower than the voltage level in the first stage; The substrate support assembly includes: a substrate support surface; a bias electrode; establishing a first pulsed voltage waveform comprising a first dielectric layer disposed between the bias electrode and the substrate support surface; and establishing an RF waveform at a first electrode disposed above the substrate support assembly by using an RF waveform generator; the RF waveform comprises a sinusoidal waveform; The first pulse voltage waveform and the RF waveform are synchronized, thereby a trough of the RF waveform is generated during the period when the first stage of the first pulse voltage waveform is established at the bias electrode; Establishing an RF waveform, wherein a peak of the RF waveform is generated during a period when the second stage of the first pulse voltage waveform is established at the bias electrode.

20. 20. The method of claim 19, wherein the first pulsed voltage waveform and the RF waveform have a frequency of less than about 1 MHz.

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