calculus circuit

Abstract

An AI system that creates a netlist from a document showing a circuit diagram or a circuit configuration, and an operating method of the AI ​​system are provided. [Solution] An SIH includes an AI system including an electronic device ED having an input / output interface, a control unit, and a conversion unit, where the input / output interface INTFC is electrically connected to a control unit CTL, and the conversion unit PTN is electrically connected to the control unit. The input / output interface has a function of sending input data generated by a user's operation to the control unit, and the control unit has a function of sending the input data to the conversion unit. The input data is a circuit diagram depicting a circuit configuration or a document file showing the circuit configuration. The conversion unit has a circuit configured with a neural network, and converts the input data into a netlist using the neural network of the conversion unit.

Description

[Technical Field]

[0001] One aspect of the present invention relates to an AI system and a method of operating an AI system.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, signal processing device, processor, electronic device, system, driving method thereof, Examples of the manufacturing method and the inspection method thereof are as follows. [Background technology]

[0003] An artificial neural network (hereafter referred to as a neural network) is a It is an information processing system modeled on a neural network. It is expected that this will lead to the realization of computers with higher performance than conventional von Neumann computers. In recent years, various research projects have been conducted to build neural networks on electronic circuits. There are.

[0004] For example, Patent Document 1 describes a method for converting the charging characteristics of a secondary battery into image data and performing convolutional neural network analysis. Using a neural network (CNN), the normal characteristics of the secondary battery are determined from the image data. A control system is disclosed that distinguishes between abnormal characteristics and abnormal characteristics. Reference 2 discloses a system that analyzes literature data using neural networks. It has been done. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 021095 [Patent Document 2] Japanese Patent Application Laid-Open No. 2018-49430 Summary of the Invention [Problem to be solved by the invention]

[0006] When manufacturing electronic devices, semiconductor devices, semiconductor wafers, etc., The specifications are determined in advance and the circuit diagram is created based on those specifications. Even if the circuit diagram is created, the direction and placement of wiring, circuit elements, etc. may differ depending on the creator. Therefore, even if the specifications and circuit configuration are the same, the circuit diagram may differ. Sometimes the eyes are different.

[0007] In other words, even if the specifications and circuit configuration are the same, there are many variations depending on how the circuit is represented. There can be a circuit diagram of the pattern. For example, by using image recognition processing such as Igence, When an image search is performed using a circuit diagram as an input image, specifications and circuit configurations are stored in the database. Even if a circuit with the same structure as the circuit diagram exists, the appearance may differ from the input image. Therefore, circuits in the database may not be output in the image search results.

[0008] One aspect of the present invention is an AI system that converts an image or document showing a circuit configuration into a netlist. Another object of the present invention is to provide a system that allows searching for a circuit configuration. An object of the present invention is to provide an AI system. Another object of the present invention is to provide a novel AI system. One of the objectives is to provide a method for operating the above-mentioned method.

[0009] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One aspect of the present invention includes a first electronic device, the first electronic device having an input / output interface and The AI ​​system has a control unit and a first conversion unit. The input / output interface is The first conversion unit is electrically connected to the control unit, and the first conversion unit is electrically connected to the control unit. The output interface transmits input data generated by user operations to the control unit. The control unit has a function of transmitting the input data to the first conversion unit. The first conversion unit has a circuit in which a neural network is configured, and the second conversion unit It has a function of converting input data into the first netlist by the network. The input data is a circuit diagram depicting the circuit configuration or a document file showing the circuit configuration. .

[0011] (2) Alternatively, in one aspect of the present invention, in the configuration (1), the first electronic device is The first database may be electrically connected to the control unit. The first database is electrically connected to the control unit, and the second database is electrically connected to the control unit. The second netlist is stored in the second database, and the second netlist is linked to the second netlist. The control unit stores the document data of the first database. The function to search for the circuit configuration of the first netlist and the function to search for the circuit configuration of the second netlist If the second netlist is found, the literature data is read from the second database. , and a function of outputting the signal to an input / output interface.

[0012] (3) Alternatively, one aspect of the present invention is the above-mentioned configuration (1), further comprising a second electronic device and a first electronic device. The device has an external interface, and the second electronic device has a third database and a fourth database. The third database may be electrically connected to the external interface. The fourth database is electrically connected to an external interface, and the third database is electrically connected to an external interface. The second netlist is stored in the fourth database. The control unit stores the literature data linked to the document through an external interface. and communicates with the second electronic device to search the third database for the circuit of the first netlist. The function to search for the configuration and the third database in the search for the circuit configuration of the first netlist If the second netlist is found in the database, the literature data is read from the fourth database. and outputs the result to the input / output interface.

[0013] (4) Alternatively, one aspect of the present invention includes a first electronic device and a second electronic device, an input / output interface, a control unit, and an external interface; The device is an AI system with a second conversion unit. The input / output interface provides power to the control unit. The external interface is electrically connected to the control unit and the second conversion unit of the second electronic device. The input / output interface is also connected to the The control unit has a function of transmitting the generated input data to the control unit, and the control unit transmits the input data to an external interface. The second conversion unit of the second electronic device has a function of transmitting the second conversion signal to the second conversion unit of the second electronic device via the interface. The first conversion unit has a circuit in which a neural network is configured, and the second conversion unit The control unit has a function of converting input data into a first netlist through an external network. The device has a function of acquiring the first netlist from the second electronic device via the interface. The input data is a circuit diagram showing the circuit configuration or a document file showing the circuit configuration. It is.

[0014] (5) Alternatively, in one aspect of the present invention, in the configuration (4), the second electronic device is The third database may include an external interface and a fourth database. The fourth database is electrically connected to the external interface. The third database stores the second netlist, and the fourth database stores the second netlist. The database stores literature data linked to the second netlist. and communicating with the second electronic device via the external interface to access the third database. In addition, it has a function to search for the circuit configuration of the first netlist and a function to search for the circuit configuration of the first netlist. If the search finds a second netlist from a third database, the literature data from the fourth database and output to the input / output interface. do.

[0015] (6) Alternatively, one aspect of the present invention is a device having an input / output interface, a control unit, and a first conversion unit. The first conversion unit is a neural network that is configured to convert the The input / output interface is electrically connected to the control unit, and The unit is electrically connected to the control unit. The operation method of the AI ​​system includes first to third steps. The first step is to input the input data created by the user to the control unit. The second step is performed by the neural network of the first conversion unit. a step of converting input data into a first netlist; and a third step of converting the input data into a first netlist. and outputting the signal to the input / output interface via the input / output interface.

[0016] (7) Alternatively, the operating method (6) according to one aspect of the present invention includes the fourth to sixth steps. The AI ​​system may include a first database and a second database. The first database is electrically connected to the control unit, and the second database is electrically connected to the control unit. The first database stores the second netlist, and the second database The database stores literature data linked to the second netlist. The step of searching the first database for the circuit configuration of the first netlist. The fifth step is to find the second netlist from the first database in the fourth step. If the document data is found, it is read from the second database and used as an input / output interface. and a sixth step of outputting the data from the first database to the second database in the fourth step. If the netlist is not found, the control unit determines whether the first netlist is in the first database. and outputting information that the information was not found from the database to the input / output interface. do.

[0017] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device and may contain a semiconductor device.

[0018] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0019] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0020] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0021] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0022] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0024] In addition, in this specification, the term "resistance element" refers to a circuit element, wiring, etc. that has a resistance value. Therefore, in this specification, the term "resistance element" refers to a wiring having a resistance value, a source- This includes transistors, diodes, coils, etc., through which current flows between the drains. Therefore, the term "resistive element" is used in place of "resistance," "load," and "area with a resistive value." Conversely, the terms "resistance," "load," and "area with resistance" can be used interchangeably. The resistance value may be, for example, Preferably, the resistance is 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more. Ω or more and 1Ω or less. For example, it can be 1Ω or more and 1×109 Even below Ω good.

[0025] In this specification, the term "capacitive element" refers to a circuit element having a capacitance value, The capacitance may be a wiring area, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification and the like, a "capacitance element" refers to a pair of electrodes and a capacitor included between the electrodes. Not only the circuit elements including dielectrics, but also the parasitic capacitance that appears between wirings, This includes the gate capacitance that appears between the gate and either the source or drain of the capacitor. In addition, terms such as "capacitance element," "parasitic capacitance," and "gate capacitance" are used in place of "capacitance." Conversely, the term "capacitance" can be translated as "capacitance element," "parasitic capacitance," or " The term "gate capacitance" can be used interchangeably with "pair of electrodes" in "capacitance." The term "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value should be, for example, between 0.05 fF and 10 pF. Alternatively, the capacitance may be set to, for example, 1 pF or more and 10 μF or less.

[0026] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source and drain" (or first electrode, or first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate is provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, the terms "gate" and "backgate" are interchangeable for the same transistor. In addition, if a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes called.

[0027] In this specification, a node may be a terminal, a wiring, or the like depending on the circuit configuration, device structure, etc. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0028] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the ground potential as the earth potential, we can change the word "voltage" to "potential." The potential does not necessarily mean 0V. Note that the potential is relative and the reference Depending on the potential, the potential applied to the wiring etc. may be changed.

[0029] Generally, "electric current" is the phenomenon of charge transfer (electrical conduction) that accompanies the movement of positively charged bodies. However, the statement "electrical conduction of positively charged bodies is occurring" does not necessarily mean "the opposite direction" In other words, "electrical conduction of negatively charged bodies occurs in the In this document, unless otherwise specified, "current" refers to the phenomenon of charge movement accompanying the movement of carriers (electric current). The carriers referred to here are electrons, holes, anions, and cations. , complex ions, etc., and in systems where current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.) ) The carriers differ depending on the direction of the current. Also, the direction of the current in wiring etc. is The direction of movement of negative carriers is expressed as a positive current amount. In other words, the direction of movement of negative carriers is , the direction is opposite to the direction of the current and is expressed as a negative current amount. Therefore, unless otherwise specified regarding the positive or negative sign (or direction of the current), it is assumed that "current flows from element A to element B." A statement such as "current flows from element B to element A" can be rephrased as "current flows from element B to element A" Furthermore, statements such as "current is input to element A" should be interpreted as "current is output from element A." This can be rephrased as "can be" or "can be used for other purposes."

[0030] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0031] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0032] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0033] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0034] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, the terms "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where the "electrodes" and "wiring" are integrally formed. "Terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" refers to a combination of multiple "electrodes," "wiring," "terminals," etc. For example, "electrode" is a "wiring" or "terminal." For example, a "terminal" can be a part of a "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be used interchangeably with "area." " may be replaced with terms such as "

[0035] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In addition, the opposite is also true, and terms such as "signal line" can be used to refer to "power line". In some cases, it may be possible to change the term to "potential" or "voltage" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0036] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This can result in the formation of DOS (Density of States) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, especially hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. If the semiconductor is a silicon layer, Impurities that change the properties of the body include, for example, oxygen, group 1 elements excluding hydrogen, and group 2 elements. These include the elements of Group 13, Group 15, etc.

[0037] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0038] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0039] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0040] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0041] According to one aspect of the present invention, an AI that converts an image or document showing a circuit configuration into a netlist is Alternatively, according to one aspect of the present invention, a system for searching for a circuit configuration can be provided. Alternatively, one aspect of the present invention can provide a novel AI system. Alternatively, according to one aspect of the present invention, a novel AI system can be provided. A method of operation of the present invention can be provided.

[0042] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, it may not have [Brief explanation of the drawings]

[0043] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of the system. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of the system. [Figure 3] FIG. 3 is a flowchart showing an example of the operation of the system. [Figure 4] FIG. 4 is a flowchart showing an example of the operation of the system. [Figure 5] FIG. 5 is a diagram for explaining the procedure for creating a netlist from a circuit diagram. [Figure 6] FIG. 6 is a diagram for explaining the procedure for creating a netlist from a document file. [Figure 7] FIG. 7 is a block diagram illustrating an example of the operation of the system. [Figure 8] 8A and 8B are diagrams illustrating a hierarchical neural network. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a circuit included in the arithmetic circuit. [Figure 11] FIG. 11 is a timing chart showing an example of the operation of the arithmetic circuit. [Figure 12] FIG. 12 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of the arithmetic circuit. [Figure 14] FIG. 14 is a circuit diagram showing an example of the configuration of the arithmetic circuit. [Figure 15] FIG. 15 is a circuit diagram showing an example of the configuration of the arithmetic circuit. [Figure 16] FIG. 16 is a circuit diagram showing an example of an equivalent circuit of the arithmetic circuit of FIG. [Figure 17] FIG. 17 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 18] FIG. 18 is a timing chart showing an example of the operation of the arithmetic circuit. [Figure 19] FIG. 19 is a cross-sectional view illustrating the configuration of the semiconductor device. [Figure 20] FIG. 20 is a cross-sectional view illustrating the configuration of the semiconductor device. [Figure 21] 21A to 21C are cross-sectional views illustrating the configuration of a semiconductor device. [Figure 22]22A and 22B are cross-sectional views illustrating examples of the structure of a transistor. [Figure 23] FIG. 23 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 24] 24A and 24B are schematic cross-sectional views illustrating examples of the structure of a transistor. [Figure 25] FIG. 25 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 26] FIG. 26A is a top view showing an example of the configuration of a capacitor, and FIGS. 26B and 26C are cross-sectional perspective views showing the example of the configuration of a capacitor. [Figure 27] 27A is a top view showing an example of the configuration of a capacitor, FIG. 27B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 27C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 28] Figure 28A is a diagram explaining the classification of IGZO crystal structures, Figure 28B is a diagram explaining the XRD spectrum of quartz glass, Figure 28C is a diagram explaining the XRD spectrum of crystalline IGZO, and Figure 28D is a diagram explaining the micro-electron beam diffraction pattern of crystalline IGZO. [Figure 29] FIG. 29A is a circuit diagram showing the configuration of a multiplication circuit included in the prototype semiconductor device, and FIG. 29B is an optical microscope photograph of the prototype semiconductor device. [Figure 30] Figure 30A is a graph showing the source-drain current IDS(VW, VX) of transistor M2 of a multiplication circuit included in a prototype semiconductor device when data equivalent to VW is written to the multiplication circuit and a voltage VX is applied to wiring VX, and Figure 30B is a graph showing the multiplication characteristics of the multiplication circuit included in the prototype semiconductor device calculated from Figure 30A. [Figure 31] FIG. 31 is a graph showing the temperature dependence of the multiplication characteristics of a multiplication circuit included in a prototype semiconductor device. [Figure 32] 32A and 32B are graphs showing the time change in the multiplication characteristics of a multiplication circuit included in a prototype semiconductor device. [Figure 33]FIG. 33A is a graph showing the multiplication characteristics of a multiplication circuit included in a prototype semiconductor device, and FIG. 33B is a graph showing the degree of variation in the multiplication characteristics when each potential is written to the multiplication circuit included in the prototype semiconductor device. [Figure 34] FIG. 34 is a graph showing the degree of element-to-element variation in the read current of each of a plurality of multiplication circuits included in the prototype semiconductor device. [Figure 35] 35A, 35B, 35C, and 35D are graphs showing the degree of element variation in read current in a configuration of a plurality of multiplication circuits, obtained by Monte Carlo analysis. [Figure 36] FIG. 36 is a diagram showing an example of a hierarchical artificial neural network model used to calculate the inference accuracy. [Figure 37] FIG. 37 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 38] FIG. 38A is a graph showing the result of multiplying the first data by the second data, and FIG. 38B is a graph showing the calculated value according to the number of rows in the memory cell array. [Figure 39] 39A and 39B are histograms showing the variation in the value of the product of the first data and the second data when variation in transistor characteristics is taken into consideration. [Figure 40] Figure 40A is a graph showing the degree of agreement output from the output layers of a neural network constructed using a circuit simulator and a neural network constructed using a programming language, and Figure 40B is a graph showing the correlation between the values ​​output from the output layers of a neural network constructed using a circuit simulator and a neural network constructed using a programming language. [Figure 41] FIG. 41 shows an example of an output waveform from the output layer in a neural network constructed using a circuit simulator. DETAILED DESCRIPTION OF THE INVENTION

[0044] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can feed the neural network with existing information and generate results. The process of determining the combined strength is sometimes called "learning."

[0045] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information through neural networks is sometimes called "inference" or "cognition."

[0046] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0047] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. It can also be called OS FET or OS When referring to a transistor, it refers to a transistor having a metal oxide or oxide semiconductor. This can be rephrased as sta.

[0048] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0049] In addition, in this specification and the like, the configurations shown in each embodiment (or example) may be used in other embodiments. The present invention can be realized by appropriately combining the above-described configuration with the configuration shown in the embodiment (or other embodiments). In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be applied to each other. Any suitable combination is possible.

[0050] In addition, the contents (or part of the contents) described in one embodiment (or example) The above-mentioned embodiment and the example thereof may be different from each other (or may be a part of the contents). The contents ( (or a part of the content) You can make changes etc.

[0051] The contents described in the embodiments (or examples) are the same as those of the respective embodiments (or examples). In the example, the contents are described using various figures or the text in the specification. This refers to the content.

[0052] It should be noted that the drawings (or even a part thereof) described in one embodiment (or example) Another part of the figure, another figure (or part thereof) described in the embodiment (or example) ) and in one or more other embodiments (or one or more other examples) By combining at least one of the figures (or even a part of the figure) This allows for even more diagrams to be constructed.

[0053] The embodiments (or examples) described in this specification are explained with reference to the drawings. However, the embodiment (or example) can be implemented in many different ways, and It is understood that various changes in form and details may be made by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the present invention can be easily understood by those skilled in the art. It should be noted that the present invention is not limited to the above. ) In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, in perspective views and the like, the drawings are used as a single unit and repeated explanations may be omitted. In order to ensure clarity, some components may be omitted.

[0054] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0055] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. This is a schematic illustration of an ideal example and is not limited to the shapes or values shown in the drawings. For example it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing shifts.

[0056] Also, for this specification, etc., when In:Ga:Zn = 4:2:3 or in the vicinity thereof, with respect to the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when In:Ga:Zn = 5:1:6 or in the vicinity thereof, with respect to the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also when In:Ga:Zn = 1:1:1 or in the vicinity thereof, with respect to the total number of atoms, when In is 1 Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, when In:Ga:Zn = 5:1:3 or in the vicinity thereof, with respect to the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less ( 0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when In:Ga:Zn = 10:1:3 or in the vicinity thereof, with respect to the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when In:Zn = 2:1 or in the vicinity thereof with respect to the total number of atoms, when In is 1, Zn is greater than 0.25 and less than 0.75 (0.25 < Zn ≤ 0.75). Also, when In:Zn = 5:1 or in the vicinity thereof , with respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and less than or equal to 0.25 (0 .12 < Zn ≤ 0.25). Also, In:Zn = 10:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.07 and less than or equal to 0.12 (0.0 7 < Zn ≤ 0.12).

[0057] (Embodiment 1) In this embodiment, a system according to an aspect of the present invention will be described.

[0058] FIG. 1 shows a system (sometimes referred to as an electronic device) having a function of converting "circuit drawings", "circuit configurations described in the scope of claims", etc. in AI using a neural network into a netlist. Also, the system has a function of searching within an existing database using the converted netlist. The netlist is data having connection information of circuit elements, logic circuits, signal conversion circuits, potential level conversion circuits, voltage sources, current sources, switching circuits, amplifier circuits, etc. included in an electronic circuit. Specifically, the netlist is data in which the connection destinations of the terminals of the circuit elements, circuits, etc. included in the electronic circuit are described, and is used in circuit simulators, circuit design software, etc. The system SIH shown in FIG. 1 has an electronic device ED. The electronic device ED has an input / output interface INTFC, a control unit CTL, a conversion unit PTN, a database DTB1,

[0059] a database DTB2, and a storage unit MP.

[0060]

[0061] ​​​​​​​​​The input / output interface INTFC is electrically connected to the control unit CTL. The input interface INTFC is used when the user uses the system SIH. It has the function of inputting and outputting information between the user and the electronic device ED. INTFCs include, for example, organic EL (Electro Luminescence) Displays, LCD displays, keyboards, pointing devices (For example, a mouse.) The device may have an input device such as a touch panel.

[0062] The memory unit MP is electrically connected to the control unit CTL. The memory unit MP is a volatile memory. The device includes a non-volatile memory device.

[0063] As a volatile storage device, for example, a DRAM (Dynamic Random Access Memory) Volatile storage devices are, for example, It has functions such as temporarily storing data required during startup of software, etc. do.

[0064] Non-volatile storage devices include, for example, HDDs (hard disk drives), SSDs ( Solid-state drives, optical disks, magnetic tapes, etc. When optical disks, magnetic tapes, etc. are used in documents, reading and writing Non-volatile storage devices, including optical disks and magnetic tapes, are collectively called non-volatile storage devices. The non-volatile storage device may store, for example, software execution programs, circuit configurations, etc. It has the function to save the drawings, netlists of circuit configurations, etc.

[0065] The converter PTN is electrically connected to the control unit CTL. Document files that describe circuits in text (for example, patent claims) The conversion unit PTN has the function of converting the neural network into a netlist. The conversion unit PTN may be configured as a neural network. If the neural network has been trained, The weighting coefficients between the neurons included in the neural network are assumed to be fixed.

[0066] The database DTB1 is electrically connected to the control unit CTL. B1 has a function to store document data such as patent specifications, papers, and documents.

[0067] The database DTB2 is electrically connected to the control unit CTL. B2 is, for example, the number of times described in the bibliographic data stored in the database DTB1. The netlist also has the function of saving the netlist of the network. The control number and control code are used to link the list with the circuit configuration of the relevant literature data. It may be included.

[0068] Note that database DTB1 and database DTB2 are treated as a single database. You can also summarize it as follows.

[0069] In addition, databases DTB1 and DTB2 contain literature data and Since the netlist etc. are saved, there are databases DTB1 and DTB2. may be included in the memory unit MP. In particular, the database DTB1, the database DT B2 is preferably a non-volatile memory device of the memory unit MP.

[0070] As shown in FIG. 2, the electronic device ED may also have an external interface INF. The external interface INF communicates with the electronic device WSV outside the electronic device ED. Therefore, the external interface INF has a function to connect the control unit CTL and the electronic The detector WSV is electrically connected to the detector WSV.

[0071] The electronic device WSV can be, for example, an external server. The interface INF is connected to the electronic device WSV via an internet line, etc. It is preferable that

[0072] The electronic device WSV includes, for example, a database WDTB1, a database WDTB2, and The database WDTB1 has the same data as the database DTB1. In addition, the database WDTB2 contains the database Like DTB2, the network of the circuit described in the literature data of the database WDTB1 The conversion unit WPTN, like the conversion unit PTN, stores circuit diagrams, circuit It has the function of converting document files that express the above in text into netlists.

[0073] At least one of the database WDTB1, the database WDTB2, and the conversion unit WPTN , may function as an external server. Database WDTB1, Database WDTB2 By providing at least one of the conversion units WPTN as an external server, the provided server In some cases, it may be possible to increase the scale, storage capacity, and computing power of the database. By having database WDTB1 act as a foreign server, database WDTB1 It may be possible to store more bibliographic data than the database DTB1. Database WDTB2 acts as an external server, 2 can store more information, such as netlists, than the database DTB2. In addition, for example, the conversion unit WPTN may perform a larger calculation than the conversion unit PTN. In some cases, it may be possible to have a circuit.

[0074] <<Example 1>> Here, an example of the operation of the system SIH in Fig. 1 will be described. This is a flowchart showing an example of the operation of the IH system. The steps include steps TI01 to STI03. Also, in FIG. 3, the start of the operation example is indicated by "START " and the end of the operation example is described as "END". Note that in this operation example, Or, explain how to convert a document file that describes a circuit into a netlist. .

[0075] Step STI01 is a step in which a user inputs an input / output signal from an electronic device using an input / output interface INTFC. A step in which a circuit diagram or a document file that describes the circuit in text is input to the control unit CTL of the device ED. The circuit diagram can be input by a user using, for example, circuit design software. software, circuit simulator, paint software, CAD software, etc. A means for creating a road map, etc. Also, a means for the user to input the document file. For example, create a document file using word processing software, a text editor, etc. In addition, circuit diagrams and document files in the process of being created, completed circuit diagrams, etc. The document file may be temporarily stored in the memory unit MP. The circuit diagram or document file created in step STI01 is called input data.

[0076] In step STI01, other than the created data, Circuit diagrams, document files, etc. read from the database DTB1 may also be applied.

[0077] Step STI02 converts the input data created in step STI01 into a network in the conversion unit PTN. Specifically, for example, the user may input the Using the interface INTFC, the control unit CTL receives input data and the The control unit CTL transmits a signal including an instruction to convert the input data into a netlist. Upon receiving this signal, the input data is sent to the conversion unit PTN. receives the input data and converts the input data into a netlist.

[0078] When the input data is a circuit diagram, the method of converting the input data to a netlist is as follows: For example, a method using a convolutional neural network (CNN) is preferable. When the input data is a document file, the input data can be converted to a netlist using the For example, a method using a recurrent neural network is preferable. A specific example of a method for converting the above into a netlist will be described later.

[0079] The converted netlist may be temporarily stored in the memory unit MP.

[0080] Step STI03 converts the netlist converted in step STI02 into an input / output interface. The method further includes a step of outputting the data to a display device included in the interface INTFC. Specifically, for example, the netlist converted in step STI02 is and transmitted to a display device included in the input / output interface INTFC. Then, by displaying the netlist on the display device, the user can change the input data. The contents of the converted netlist can be checked.

[0081] After step STI03 is performed, this operation ends.

[0082] <<Example 2>> Next, we will look at an example of operation in the system SIH in Figure 1, which is different from the flowchart in Figure 3. FIG. 4 is a flowchart showing an example of the operation of the system SIH. This flowchart further includes steps STI04 to STI08 in addition to the operation example of FIG. This example shows how the converted netlist is used to create the circuit. Explain how to perform a search.

[0083] Steps STI01 to STI03 shown in the flowchart of FIG. Please refer to the description of steps STI01 to STI03 in the flowchart of FIG. To pour drinks.

[0084] Step STI04 uses the netlist converted in step STI02 to Specifically, for example, the control The control CTL is stored in the database DTB2 for the database DTB2. Send a signal containing an instruction to read the netlist linked to the literature data. Then, the database DTB2 receives the signal and then calculates the netlist and transmits it to the control unit CTL, which then reads out the converted data in step STI02. The netlist is compared with the netlist contained in the database DTB2.

[0085] In addition, reading of netlists linked to literature data from database DTB2 may be for all netlists stored in the database DTB2, or You can also specify conditions to narrow down the netlist to a portion of the netlists stored in the database DTB2. stomach.

[0086] The search performed in step STI04 is performed on the network converted in step STI02. You can extract exact matches to the list, or partial matches (similar ) may be extracted.

[0087] The converted netlist used for the search may be temporarily stored in the memory unit MP. .

[0088] The circuit search performed in step STI04 may also use AI. Specifically, for example, using AI, the netlist converted in step STI02 and the data The netlists linked to the literature data stored in the database DTB2 and The descriptions are compared, and the types, numbers, and connection configurations of the circuit elements in each netlist are checked. The similarity, which indicates how closely they match, is calculated, and search results are sorted by the most similar. may be output.

[0089] Step STI05 is the search for step STI04, and the determining whether the translated netlist is found in the database DTB2; Here, the netlist found in the database DTB2 has the step There are cases where the netlist searched by STI04 matches perfectly, and cases where it matches only partially. In this determination, if the netlist searched in step STI04 is If it is found in database DTB2, the operation proceeds to step STI06. In this determination, the netlist searched in step STI04 is included in the database DTB If not found in step STI02, the operation proceeds to step STI07.

[0090] Step STI06 performs the search in step STI04 to find the data in database DTB2. The literature data corresponding to the used netlist is read from the database DTB1. Specifically, for example, the control unit CTL performs the following operations on the database DTB1: The net retrieved from database DTB2 that was found in the search in step STI04 and transmitting a signal including an instruction to retrieve the document data corresponding to the list. Upon receiving the signal, the DTB1 reads out the document data and controls the control unit C The control unit CTL transmits the document data to the input / output interface INTFC. The document data is then transmitted to a display device or the like included in the device. By displaying the data, the user can check the contents of the document data.

[0091] The converted netlist used for the search and the data read from the database DTB1 are The obtained document data may be temporarily stored in the memory unit MP.

[0092] After step STI06 is performed, this operation ends.

[0093] Step STI07 is the search for step STI04, and the The converted netlist is output as a result of not being found in the database DTB2. Specifically, for example, the control unit CTL has an input / output interface INTF For C, the netlist converted in step STI02 is stored in database DTB2. This sends information that the information was not found on the display device. By displaying the netlist, the user can see that the netlist converted in step STI02 is a database. You can check search results that were not found in DTB2.

[0094] Step STI08 stores the input data in database DTB1, and step STI The method further includes a step of storing the converted netlist in database DTB2. Specifically, the user uses the input / output interface INTFC to communicate with the control unit CTL. and commands to save the input data and the netlist converted in step STI02. By receiving the signal, the control unit CTL receives the input data and the input a signal including an instruction to write data to the database DTB1; The netlist converted in step STI02 and the netlist are stored as data. A signal including an instruction to write to database DTB2 is sent to database DTB2. When this happens, the input data sent to database DTB1 and the data sent to database DTB2 are The converted netlists are transferred from the memory MP where they are temporarily stored to the control It may be transmitted via the control unit CTL.

[0095] After step STI08 is performed, this operation ends.

[0096] Note that the operation method of one aspect of the present invention is the above-described steps STI01 to STI0 8. In this specification, the processes shown in the flowcharts are classified by function. However, in actual processing, It is difficult to separate the processes shown in the flow chart into functions, and multiple steps are included in one step. There may be cases where multiple steps are involved, or where a single step is involved across multiple steps. Therefore, the process shown in the flowchart is not limited to each step described in the specification. Specifically, depending on the situation, Or, if necessary, rearrange the order of steps, add or delete steps, etc. For example, step STI08 can be used to stop the operation if the user does not wish to do so. This can be removed from the example and does not need to be done.

[0097] Note that the operation method of one embodiment of the present invention is not limited to the operation example described in this embodiment. For example, in the above example, the conversion unit PTN of the electronic device ED is used to convert input data into a netlist. Although the conversion operation example has been described, the conversion unit PTN is instead a conversion unit of the electronic device WSV. In the above description, the database DTB1 of the electronic device ED and An example of searching for a circuit in a netlist using database DTB2 has been explained. Database DTB1 and database DTB2 are instead databases of electronic equipment WSV. Alternatively, the database WDTB1 and the database WDTB2 may be used.

[0098] According to one aspect of the present invention, an input device ED and an external electronic device WSV are used. Services for converting input data to netlists and / or for generating netlists A business model may be provided in which road search services and the like are charged for.

[0099] <<Example 1 of how to convert to a netlist>> Next, in step STI02 of the above operation example, when the input data is a circuit diagram, A method for converting the circuit diagram into a netlist will now be described.

[0100] FIG. 5 is a schematic diagram showing the flow of converting a circuit diagram into a netlist.

[0101] Stage PH1 in FIG. 5 is the input data to be input to the conversion unit PTN in step STI02. The image PIC shows an example of a circuit diagram. It shows the circuit symbols, wiring, and their connection configuration. In some cases, the image of Figure 5 As shown in the PIC, the image PIC contains the circuit symbol name, the letters indicating the wiring name, the symbols, etc. The circuit diagram shown in the image PIC of FIG. 5 may also include the names of the circuit symbols, Letters, symbols, etc. indicating the names of the wiring may not be included.

[0102] In step PH2 of FIG. 5, the image PIC of step PH1 is input to the converter PTN, and the image PI An example of object region recognition is shown in Fig. 5 at the left side of stage PH2. In the image PIC, the circuit symbols and electrical connection parts (such as the black circles in the circuit diagram shown in the image PIC) ) and are shown surrounded by dotted lines. Depending on the situation, the object area may be recognized including the wiring.

[0103] The object region recognition methods mentioned above include, for example, Objectness and CPM. C(Constrained Parametric Min-Cuts), Object t Proposals, etc.

[0104] Next, after the object area recognition is completed, image recognition is performed for each object area. This allows the conversion part PT to determine what kind of circuit element the circuit symbol surrounded by the dotted line is. For example, in the image PIC on the left side of step PH2 in FIG. By performing image recognition, the conversion unit PTN converts, for example, a circuit symbol surrounded by a thick dashed line into a capacitive element. For example, a circuit symbol surrounded by a thick dashed line is recognized as a transistor. The conversion unit PTN recognizes which circuit element a circuit symbol represents, and Names (e.g., letters, abbreviations, symbols, words, etc.) to be written in the netlist for the circuit symbols ) can be added.

[0105] Similarly, by performing image recognition, the converter PTN recognizes the electrical connections enclosed by the dotted lines. This allows the converter PTN to recognize electrical connections. For each part (such as a black circle), the name to be written in the netlist (for example, a letter, abbreviation, Symbols, words, etc.) can be added.

[0106] As a method of image recognition, for example, AI is used to roughly recognize the conversion part PTN. First, the circuit symbols are trained as training data, and the image is input to the conversion part PTN. Given a PIC, the circuit symbols contained in the image PIC are generated based on the learned circuit symbols. A method for extracting circuit symbols is given.

[0107] In addition, as a method for image recognition, for example, convolutional neural networks (CN N) can be used. Also, when using a convolutional neural network, In advance, we use the circuit symbol An image of the electrical connection (such as a black circle) or a part of such an image can be used. This allows the convolutional neural network to calculate the image PIC. Calculate the similarity between the filter and the circuit symbols and electrical connections (black dots, etc.) From the similarity, the circuit symbols and electrical connections included in the image PIC can be identified. It is possible to identify minutes (black circles, etc.).

[0108] In addition, the conversion part PTN recognizes the connection between the electrical connection part (black circle, etc.) and the circuit symbol. In this case, it is preferable to repeatedly perform object region recognition and image recognition. By performing area recognition and image recognition once, electrical connection parts (black dots, etc.) are recognized in the conversion part PTN. Symbols to identify electrical connections (black dots, etc.) and to describe them in the netlist. Next, the first image recognition is performed to identify the parts connected to the electrical connections (black dots, etc.). The second object area recognition is then performed by determining the direction in which the wiring is extending. The area is expanded in the direction of the wire extension, and the wiring and the electrical connection parts (black circles, etc.) are grouped together to form an object area. Then, the second image recognition is performed to determine the direction in which the wiring is extended. From the third time onwards, the recognition of the object area and the image recognition are repeated in the same way. Therefore, the converter PTN converts the wiring connected to the electrical connection part (black circle, etc.) Depending on the number of times object area recognition and image recognition are repeated, recognition can be achieved. The converter PTN recognizes the electrical connection between the circuit symbol and the electrical connection part (such as a black circle). In the image PIC on the left side of the stage PH2 in FIG. 5, for example, the object area is recognized. The wiring area obtained by repeatedly performing image recognition and image recognition is shown by the thick dashed double-dashed line. The enclosed area is shown.

[0109] In addition, the image PIC of stage PH1 contains the names of circuit symbols, letters and symbols indicating the names of wiring. If it is included, as shown in the image PIC on the right of step PH2 in Figure 5, the name, character, Symbols, etc. are recognized along with circuit symbols and electrical connections at the object area recognition stage. This allows the names, characters, symbols, etc. acquired by object region recognition to be displayed simultaneously. In this way, it is possible to link the circuit symbols and electrical connection parts that have been recognized as object regions. In addition, circuit symbols, names, letters, and symbols associated with electrical connections can be linked to the It can be treated as a symbol, character, etc. to be written in a list.

[0110] In step PH3 of FIG. 5, the circuit symbol recognized by the conversion unit PTN in step PH2 of FIG. This shows an example of how to describe the connection configuration between the circuit and the electrical connection parts (black dots, etc.) in the netlist. do.

[0111] On the left side of the netlist NTL, the circuit symbol recognized by the image PIC is displayed. SW (e.g., letters, abbreviations, symbols, words, etc.). For example, Tr[1 ], Tr[2] indicates the transistor in the circuit diagram depicted in the image PIC, and C[1] , EL[1] indicates the capacitance element of the circuit diagram depicted in the image PIC, 1 shows a light emitting element of a circuit diagram.

[0112] In addition, the netlist NTL contains the names of circuit elements as information indicating the connection configuration of the circuit symbols. To the right of the designation CSW, through the space SPC, the designation CN of the electrical connection part (black circle, etc.) P (for example, a letter, abbreviation, code, word, etc.) is written. If there are multiple CNPs, it is preferable to have a space between each CNP name. The order in which the names CNP of electrical connection parts (black dots, etc.) are written is determined by the order in which they are written in that column. The name is determined by the terminal of the CSW circuit symbol. For example, the netlist NTL Regarding the electrical connection of each terminal of a transistor, The order is to write the gate, then the other of the source or drain. In the netlist NTL, the electrical connections of each terminal of the light-emitting element are as follows: input terminal, output terminal The order of the input terminals is specified.

[0113] As described above, by performing object region recognition and image recognition, the input data is The circuit diagram can be converted into a netlist.

[0114] <<Example 2 of how to convert to a netlist>> Next, in step STI02 of the above example of operation, the input data is converted into a document file or the like. When this is done, a method for converting the circuit diagram into a netlist will be described.

[0115] FIG. 6 is a schematic diagram showing the flow of converting a document file into a netlist.

[0116] In step PH4 of FIG. 6, the input data is input to the conversion unit PTN in step STI02. 6 shows an example of a document file DOC shown in step PH4 of FIG. The circuit configuration is used as information for converting the netlist using the conversion unit PTN. It is written as an article.

[0117] An example of a document file DOC that describes a circuit configuration is a patent specification. the circuit description in the patent specification, the claims accompanying the patent specification, etc. As an example of the conversion method, the following table is used for the document file DOC. The text is assumed to be as shown in 1.

[0118] [Table 1]

[0119] When the above document file DOC is input as input data, the conversion unit PTN ,As an example, text analysis is performed on a document file DOC.

[0120] In addition, as a method of performing text analysis, for example, AI is used to analyze the PTN conversion part. In advance, document files (e.g., papers, patent publications, etc.) are used as training data. The netlist corresponding to the document file must be learned in advance. This makes it possible to convert a document file into a format that is suitable for the conversion unit PTN. When the document file is converted into a netlist based on the learned content, can be done.

[0121] In addition, as a method for creating the above-mentioned training data, for example, From a netlist to multiple document files (e.g., multiple files with the same content but different descriptions) Examples include methods for generating numerical "claims" and the like.

[0122] In addition, as a method for text analysis, for example, recurrent neural networks (R NN) can be used.

[0123] By performing text analysis on the document file DOC, the conversion part PTN converts the document file Recognize circuit elements, wiring, or electrical connection points from the circuit configuration shown in the file DOC For example, the first paragraph of a document file DOC can be analyzed using text analysis. By performing the above, the conversion unit PTN converts the circuit configuration shown in the document file DOC into the first It is recognized that the first transistor, the second transistor, the capacitance element, and the light-emitting element are included. Then, for example, the second, third, fifth, and seventh paragraphs By performing text analysis on the sentence, the conversion part PTN converts the text into the document file DOC. The circuit configuration includes a signal line, a scanning line, a first power supply line, and a second power supply line electrically connected to each other. Here, the conversion unit PTN can recognize that the names of the circuit elements are The term CSW (e.g., letter, abbreviation, code, word, etc.) may be used to refer to, for example, the first transistor. is Tr[1], the second transistor is Tr[2], the capacitance element is C[1], and the light-emitting element is EL [1] and the name of the electrical connection point CNP (e.g., letter, abbreviation, code, single The signal lines, scanning lines, first power supply lines, and second power supply lines are, for example, By naming the stages N1, N2, N5, and N6, the stages P It is possible to write the H5 netlist NTL.

[0124] The netlist NTL shown in step PH5 of FIG. 6 is the netlist NTL shown in step P of FIG. It is assumed that the rules are the same as those for writing the netlist NTL shown in H3. A space SPC is provided between the circuit element name CSW and the electrical connection point name CNP. It is being done.

[0125] Continuing from step PH5, by performing text analysis on the document file DOC The translation unit PTN can describe the netlist NTL in more detail. For example, By performing text analysis on the sentences in the fourth and eighth paragraphs of the document file DOC, The switching unit PTN is connected to the source of the first transistor, the gate of the second transistor, and the capacitance element It is possible to recognize that one of the pair of electrodes of the device is connected to the same electrical connection point. Here, the converter PTN names the electrical connection point N3. .

[0126] Furthermore, perform text analysis on the 6th and 9th paragraphs of the document file DOC. Thus, the conversion unit PTN includes the source of the second transistor, the input terminal of the light emitting element, and the capacitor It is possible to recognize that the other of the pair of electrodes of the element is connected to the same electrical connection point. Here, the conversion unit PTN names the electrical connection point N4. do.

[0127] As mentioned above, text analysis is performed on the document file DOC, and the document file DOC Determine the circuit elements included in the circuit configuration described in and their electrical connections By extracting the netlist N shown in step PH6 of FIG. You can write TL.

[0128] By using the system described in this embodiment, it is possible to It can be converted to a netlist and the converted netlist can be retrieved from the database. In addition, the database contains information on magazines, science and engineering books, papers, academic conferences and lectures. When technical documents such as documents from conferences, patent publications, patent bulletins, etc. are stored ( Infringement of intellectual property rights such as copyrights, or violation of intellectual property laws. (This assumes that the user is not a user of the system.) By using the system, the user It can be determined whether the created circuit diagram or document file is new. Furthermore, by using the system, the user can It can be determined whether the document file is publicly known. By using the system, the user can easily access the circuit diagrams or document files created by the user. This allows for more efficient investigation of techniques.

[0129] Here, we will explain a specific example of netlist search using the system SIH shown in Figure 1. Reveal.

[0130] For example, as shown in Figure 7, in the system SIH in Figure 1, the database DTB1 contains In the example, information PKEDD, information PKPD, information HSCD, and information HSPD are stored. The database DTB2 contains the netlist PKEDN, the netlist PKPN, and the netlist Consider the case where a netlist HSCN and a netlist HSPN are stored (where ,In ,Fig. 7, ,the ,input / output ,interface ,INTFC, ,control ,unit ,CTL, ,conversion ,unit ,PTN, ,storage ,unit , MP omitted).

[0131] The information PKEDD includes, for example, a circuit diagram, a specification sheet, etc. of a known electronic device, and the information PKP D is, for example, the technical content (patent specifications, especially patent drawings, patent claims) that was involved by people other than the user. The information HSCD contains, for example, patent applications in which the user has been involved. The scope of the patent claims for the circuit in the specification (whether or not an application has been filed) is included, and the information HSPD is For example, if the user has circuit diagrams of patent specifications (regardless of whether they have been filed or not) in which the user was involved, do.

[0132] The netlist PKEDN is a netlist corresponding to the circuit diagram included in the information PKEDD. The netlist PKPN includes the patent drawings and patent claims contained in the information PKPD. The netlist HSCN corresponds to the range of the request, and the information HSCD The netlist HSPN corresponds to the scope of the included patent claims, etc. The information HSPD contains a netlist corresponding to patent drawings, etc. ,As an expression of the link between the netlist and the information, the netlist PKEDN and the information PKED D, between the netlist PKPN and information PKPD, between the netlist HSCN and information H SCD, and between the netlist HSPN and the information HSPD. do.

[0133] Here, as the first search SRC1, one network corresponding to a circuit diagram of a known electronic device is searched. List PKEDN is a list of multiple netlists such as the scope of patent claims of patent applications that the user has been involved in. Consider the case where the search range is the netlist HSCN. If a netlist corresponding to the netlist PKEDN is found from HSCN and the The application date of the patent corresponding to the found netlist is earlier than the date when the child device was made publicly known. If so, it can be found that the electronic device infringes on the user's patent. By performing the first search SRC1, infringement of the user's patent is detected for known electronic devices. A contact investigation can be carried out.

[0134] In addition, as the second search SRC2, the scope of claims before the patent application in which the user is involved is searched. A single netlist HSCN is converted into a plurality of netlists corresponding to the circuit diagram of a known electronic device. List PKEDN and multiple netlists corresponding to technical content other than the user's involvement Consider the case where PKPN and are searched within the search range. In this case, multiple netlists are used. From PKEDN and multiple netlists PKPN, select the netlist corresponding to the netlist HSCN. If the netlist is found, the netlist HSCN can be determined to be publicly known. In other words, by conducting the second search SRC2, the novelty of the invention in which the user was involved can be investigated. This allows users to review patent applications before they are filed. It may be possible to increase effectiveness.

[0135] In addition, as a third search SRC3, one network corresponding to a circuit diagram of a known electronic device is searched. PKEDN is a netlist of multiple drawings of patent applications that users have been involved in. In this case, we consider the case where we search from multiple netlists HSPN. , a netlist corresponding to the netlist PKEDN is found, and the publicly known If the application date of the patent corresponding to the found netlist is earlier than the date of The electronic device may have utilized the content of a patent application in which the user was involved. In other words, by performing the third search SRC3, it is possible to find the known electronic device. To check the degree of similarity between the circuit diagram and the circuit diagram of the patent application in which the user is involved can be done.

[0136] In the above, the third search SRC3 is a search result corresponding to a circuit diagram of a known electronic device. The netlist PKEDN is then combined with multiple netlists such as drawings for patent applications that the user has worked on. The case where the search range is HSPN has been explained, but the third search SRC3 is A netlist HSPN, such as a drawing for a patent application in which I was involved, is used to compare the circuit of a known electronic device. It is also possible to search multiple netlists PKEDN corresponding to the diagram as the search range. In the case of the patent application, the circuit diagram of a known electronic device and the circuit diagram of the contents of the patent application in which the user was involved are The degree of similarity can be examined.

[0137] Furthermore, the first search SRC1 and the third search SRC3 may be performed simultaneously.

[0138] In addition, each of the first search SRC1, the second search SRC2, and the third search SRC3 is AI can be used. For example, by using AI, the netlist to be searched can be The netlists included in the search range are compared with the descriptions of the netlists included in the search range. Indicates how closely the types, numbers, and connection configurations of circuit elements match in the list. The similarity can be calculated and the search results can be output in descending order of similarity.

[0139] As mentioned above, in the system SIH in Figure 1, the information stored in the database DTB1 The information PKEDD, the information PKPD, the information HSCD, and the information HSPD are data The netlist is linked to the netlist stored in the database DTB2. The first search SRC1, the second search SRC2, and the third search SRC3 each search the netlist separately. You can search without converting files (e.g., circuit diagrams, document files, etc.). This makes searching easier and faster.

[0140] In addition, while the above example shows a search using the system SIH in Figure 1, the system S in Figure 2 The same search example as above can be performed using IH.

[0141] By the way, for the neural network that the conversion unit PTN or the conversion unit WPTN has, To perform learning, a large amount of data (sometimes called big data) is required. As a method for preparing a large amount of data, for example, a netlist is automatically randomly generated. Then, create a program to generate the circuit, and then use circuit design software, circuit simulator, etc. Image data is created from the netlist using the It is preferable to program the process so that the image data creation and the image data creation can be performed in a series. By this, a set of the netlist and the image data of the circuit is prepared as learning data. In addition, as a method for preparing a large amount of data, for example, a netlist can be automatically generated. Then, we created a program to randomly generate the netlist. Create a program to create a document file. At this time, generate a netlist and It is preferable to program the file so that it can be created in a series. A set of a netlist and a document file can be prepared as learning data.

[0142] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0143] (Embodiment 2) In this embodiment, a neural network used in the system of one embodiment of the present invention will be described. An example of an arithmetic circuit that performs the above arithmetic operation will be described.

[0144] <Hierarchical neural network> First, we will explain about hierarchical neural networks. For example, the network has one input layer, one or more intermediate layers (hidden layers), and one output layer. The hierarchical neural network shown in FIG. 8A has a layer and a layer, and is composed of a total of three or more layers. Neural network 100 is an example of such a network. The layer has R layers (where R can be an integer of 4 or greater). The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In addition, in FIG. 8A, the (k-1)th layer and the kth layer (where k is 3 or more and R-1) are used as intermediate layers. The following integers are used.) are shown in the figure, and other intermediate layers are omitted from the illustration. .

[0145] Each layer of the neural network 100 has one or more neurons. In this case, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is 1 or more ) and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 ( k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Neuron N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.) It has.

[0146] In addition, in Figure 8A, neuron N1 (1) , neuron N p (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , Neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) are also shown. The illustration of the .

[0147] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) We are focusing on the following.

[0148] Figure 8B shows the k-th layer neuron N j (k) and neuron N j (k) The signal input to and neuron N j (k) 10 shows the signal output from the

[0149] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron N j ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0150] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the neuron in the next layer. The (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer Newron N j (k) The signal input to can be expressed by equation (D1).

[0151]

number

[0152] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1 ) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) · z m (k-1) is input. At this time, the k-th layer neuron N j (k) The signal input to The sum of the numbers j (k) is expressed as equation (D2).

[0153]

number

[0154] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and neurons signal z1 (k-1) ~z m (k-1) The result of the sum of products of and is biased. When the bias is b, equation (D2) can be rewritten as follows:

[0155]

number

[0156] Neuron N j (k) u j (k) Depending on j (k) Generates And neuron N j (k) Output signal z from j (k) is defined as follows:

[0157]

number

[0158] The function f(uj (k) ) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0159] By the way, the signal output by the neuron in each layer, the weight coefficient w, or the bias b is The value may be an analog value or a digital value. For example, the digital value may be a binary value. It may be a ternary value, or a value with an even larger number of bits. For analog values, the activation function can be, for example, a linear ramp function or a sigmoid function. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function with a value of 1 or less can be used. The signal output by the neurons in each layer is It may be three or more values, in which case the activation function has three or more values, for example, outputs -1, 0, or A step function with a value of 0, 1, or 2 can be used. For example, an activation function that outputs five values ​​can be set to -2, -1, 0, 1, or A step function with a weighting factor of 2 may be used. Use a digital value for at least one of the number w or bias b. This allows for a reduction in circuit size, power consumption, or speed of operation. Also, the signals output by the neurons in each layer, the weight coefficients w, and Alternatively, the accuracy of the calculation can be improved by using an analog value for at least one of the biases b. The degree can be improved.

[0160] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, equations (D1), (D2) (or (D3)), and (D4) are used to calculate It generates an output signal and outputs it to the next layer. The signal output from the neural network 100 corresponds to the result calculated by the neural network 100. .

[0161] <Configuration example 1 of an arithmetic circuit> Next, in the above-mentioned neural network 100, the product-sum operation and the activation function operation are performed. An example of a circuit that performs this will be described.

[0162] FIG. 9 shows an example of the configuration of the arithmetic circuit MAC1. The arithmetic circuit MAC1 shown in FIG. A multiplication and accumulation operation is performed on the first data stored in the memory cell described below and the input second data. The first data is a circuit that calculates an activation function using the result of the product-sum operation. The first data and the second data are, for example, analog data or multi-value data (discrete data). data).

[0163] The arithmetic circuit MAC1 includes a current source circuit CS, a current mirror circuit CM, a circuit WDD, and A circuit WLD, a circuit CLD, a circuit OFST, an activation function circuit ACTV, and a memory cell It has array CA.

[0164] The memory cell array CA includes a memory cell AM[1], a memory cell AM[2], and a memory The memory cell AMref[1] has a memory cell AMref[2]. 1] and memory cell AM[2] have the role of storing the first data, and memory cell AM ref[1] and memory cell AMref[2] are reference registers required for multiply-and-accumulate operations. The reference data also has the function of storing the first data and the second data. Similarly, it can be analog data or multi-valued data (discrete data).

[0165] The memory cell array CA in FIG. 9 has two memory cells in the row direction, two memory cells in the column direction, and The memory cell array CA has three or more memory cells arranged in the row direction. Alternatively, three or more of them may be arranged in a matrix in the column direction. When multiplication is performed instead of arithmetic, the memory cell array CA has one memory cell in the row direction and two memory cells in the column direction. Two or more of them may be arranged in a matrix.

[0166] Memory cell AM[1], memory cell AM[2], memory cell AMref[1], The memory cells AMref[2] and AMref[3] are transistors Tr11 and T r12 and a capacitance C1.

[0167] The transistor Tr11 is preferably an OS transistor. The channel forming region of the transistor Tr11 is made of indium, element M (for example, For example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium Tungsten, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One selected from neodymium, hafnium, tantalum, tungsten, magnesium, etc. The oxide preferably contains at least one of zinc and tantalum. The transistor Tr11 has the structure of the transistor described in the third embodiment in particular. It is more preferable that:

[0168] By using an OS transistor as the transistor Tr11, the transistor T Since the leakage current of r11 can be suppressed, a multiply-and-accumulate circuit with high calculation accuracy can be realized. In addition, by using an OS transistor as the transistor Tr11, When the transistor Tr11 is in a non-conductive state, the voltage from the storage node to the write word line is The leakage current can be made very small. That is, the potential of the retention node can be refreshed. Since the number of operations can be reduced, the power consumption of the product-sum operation circuit can be reduced.

[0169] In addition, by using an OS transistor for transistor Tr12, Since it can be fabricated at the same time as the master transistor 11, the fabrication process of the sum-of-products operation circuit can be shortened. In addition, the channel formation region of the transistor Tr12 may be covered with oxide. Silicon may be contained in the amorphous silicon (hydrogenated silicon). silicon dioxide), microcrystalline silicon, polycrystalline silicon, single crystal Crystalline silicon may also be used.

[0170] Memory cell AM[1], memory cell AM[2], memory cell AMref[1], In each of the memory cells AMref[2] and AMref[3], the first terminal of the transistor Tr11 is electrically connected to the gate of the transistor Tr12. The first terminal of the capacitor C1 is electrically connected to the wiring VR. It is electrically connected to the gate of Tr12.

[0171] In the memory cell AM[1], the second terminal of the transistor Tr11 is electrically connected to the wiring WD. The gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the line BL, and the third terminal of the capacitor C1 is The second terminal is electrically connected to the wiring CL[1]. In [1], the first terminal of the transistor Tr11 and the gate of the transistor Tr12 The connection point between the first terminal of the capacitor C1 and the first terminal of the capacitor C2 is the node NM[1]. The current flowing from the second terminal of the transistor Tr12 is I AM[1] Let's say.

[0172] In the memory cell AM[2], the second terminal of the transistor Tr11 is electrically connected to the wiring WD. The gate of the transistor Tr11 is electrically connected to the wiring WL[2]. The second terminal of the transistor Tr12 is electrically connected to the line BL, and the third terminal of the capacitor C1 is The second terminal is electrically connected to the wiring CL[2]. In [2], the first terminal of the transistor Tr11 and the gate of the transistor Tr12 The connection point between the first terminal of the capacitor C1 and the first terminal of the capacitor C2 is the node NM[2]. The current flowing from the second terminal of the transistor Tr12 is I AM[2] Let's say.

[0173] In the memory cell AMref[1], the second terminal of the transistor Tr11 is connected to the line WD The gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BLref. The second terminal of the capacitor C1 is electrically connected to the wiring CL[1]. In the memory cell AMref[1], the first terminal of the transistor Tr11 and the The connection point between the gate of the transistor Tr12 and the first terminal of the capacitor C1 is called the node NMref[1 In addition, the current flowing from the wiring BLref to the second terminal of the transistor Tr12 is Flow I AMref[1] Let's say.

[0174] In the memory cell AMref[2], the second terminal of the transistor Tr11 is connected to the line WD The gate of transistor Tr11 is electrically connected to the wiring WL[2]. The second terminal of the transistor Tr12 is electrically connected to the wiring BLref. The second terminal of the capacitor C1 is electrically connected to the wiring CL[2]. In the memory cell AMref[2], the first terminal of the transistor Tr11 and the The connection point between the gate of the transistor Tr12 and the first terminal of the capacitor C1 is called the node NMref[2 In addition, the current flowing from the wiring BLref to the second terminal of the transistor Tr12 is Flow I AMref[2] Let's say.

[0175] The above-mentioned nodes NM[1], NM[2], NMref[1], and NMref[2] serves as the retention node for each memory cell.

[0176] The wiring VR is connected to the memory cell AM[1], the memory cell AM[2], and the memory cell AMref[ 1], and the first terminal of the transistor Tr12 of each memory cell AMref[2]. This is the wiring for passing current between the second terminals. Therefore, the wiring VR gives a predetermined potential. In this embodiment, the potential applied by the wiring VR is the reference potential. The potential may be equal to or lower than the reference potential.

[0177] The current source circuit CS is electrically connected to the wiring BL and the wiring BLref. The power supply circuit CS has a function of supplying current to the wiring BL and the wiring BLref. The current amounts supplied to the wiring BL and wiring BLref are different from each other. In this configuration example, the current flowing from the current source circuit CS to the wiring BL is I C and the current source circuit The current flowing from the circuit CS to the wiring BLref is I Cref Let's say.

[0178] The current mirror circuit CM has a line IL and a line ILref. In FIG. 9, the connection point between the wiring IL and the wiring BL is referred to as a node NP. The wiring ILref is electrically connected to the wiring BLref, and in FIG. The connection point between the wire ILref and the wire BLref is the node NPref. The current corresponding to the potential of the node NPref is supplied to the node NP of the wiring BLref. ref to the wiring ILref, and a current of the same amount as the current is discharged to the node N of the wiring BL. In FIG. 9, the node NP is connected to the wiring IL. The current flowing out from the node NPref to the wiring ILref is I CM and write In addition, the wiring BL is connected from the current mirror circuit CM to the memory cell array CA. The current flowing is I B In the wiring BLref, the current mirror circuit CM is connected to the memory The current flowing through the cell array CA is I Bref It is written as follows.

[0179] The circuit WDD is electrically connected to the wiring WD and the wiring WDref. D transmits data to be stored in each memory cell of the memory cell array CA. It has the function of trusting.

[0180] The circuit WLD is electrically connected to the wiring WL[1] and the wiring WL[2]. When writing data to a memory cell in the memory cell array CA, the data The memory cell selector has the function of selecting the memory cell to be written to.

[0181] The circuit CLD is electrically connected to the wiring CL[1] and the wiring CL[2]. The circuit CLD is connected to the second terminal of the capacitor C1 of each memory cell in the memory cell array CA. It has the function of applying a potential to the

[0182] The circuit OFST is electrically connected to the wiring BL and the wiring OL. is the amount of current flowing from the wiring BL to the circuit OFST and / or the amount of current flowing from the wiring BL to the circuit OFST. The circuit OFST has the function of measuring the amount of change in the current flowing. The circuit OFST outputs the measurement result directly to the wiring OL. Alternatively, the measurement result may be converted into a voltage and output to the wiring OL. 9, the signal flowing from the wiring BL to the circuit OFST may be configured to be output to the wiring OL. The current flowing through the α He wrote:

[0183] For example, the circuit OFST can have the configuration shown in FIG. The circuit OFST includes a transistor Tr21, a transistor Tr22, and a transistor Tr2 3, a capacitance C2, and a resistance R1.

[0184] The first terminal of the capacitor C2 is electrically connected to the line BL, and the first terminal of the resistor R1 is electrically connected to the line B. The second terminal of the capacitor C2 is electrically connected to the first terminal of the transistor Tr21. The first terminal of the transistor Tr21 is electrically connected to the gate of the transistor Tr22. The first terminal of the transistor Tr22 is electrically connected to the transistor Tr2. The first terminal of the transistor Tr23 is electrically connected to the wiring OL. The first terminal of the capacitor C2 and the first terminal of the resistor R1 are electrically connected to each other. The connection point is a node Na, and the second terminal of the capacitor C2, the first terminal of the transistor Tr21, and The electrical connection point with the gate of the transistor Tr22 is defined as a node Nb.

[0185] The second terminal of the resistor R1 is electrically connected to the wiring VrefL. The second terminal of the transistor Tr21 is electrically connected to the wiring VaL, and the gate of the transistor Tr21 is The second terminal of the transistor Tr22 is electrically connected to the wiring VDD. The second terminal of the transistor Tr23 is electrically connected to the wiring VSSL. The gate of the transistor Tr23 is electrically connected to the wiring VbL. .

[0186] The wiring VrefL is a wiring that applies a potential Vref, and the wiring VaL is a wiring that applies a potential Va. The wiring VbL is a wiring that applies a potential Vb. The wiring VDDL is a wiring that applies a potential VD The wiring VSSL is a wiring that applies a potential VSS. In the configuration example of the circuit OFST, the potential VDD is a high level potential, and the potential VSS is a low level potential. The wiring RST switches the transistor Tr21 between a conductive state and a non-conductive state. This is wiring that provides the potential to generate the signal.

[0187] In the circuit OFST shown in FIG. 10, a transistor Tr22, a transistor Tr23, The wiring VDDL, wiring VSSL, and wiring VbL form a source follower circuit. It has been done.

[0188] In the circuit OFST shown in FIG. 10, the resistor R1 and the wiring VrefL connect the node N A potential is applied to a according to the current flowing from the wiring BL and the resistance of the resistor R1.

[0189] An example of the operation of the circuit OFST shown in FIG. 10 will be described. When a current (hereinafter referred to as the first current) flows, the resistor R1 and the wiring VrefL A potential corresponding to the first current and the resistance of the resistor R1 is applied to the node Na. The transistor Tr21 is turned on, and a potential Va is applied to the node Nb. Transistor Tr21 is set to a non-conducting state.

[0190] Next, when a second current (hereinafter referred to as a second current) flows from the wiring BL, As when a current flows, a second voltage is applied to the node Na by the resistor R1 and the wiring VrefL. A potential corresponding to the current and the resistance of resistor R1 is applied. At this time, node Nb is in a floating state. Since the node Na is in a switching state, the potential of the node Na changes, and the node The potential of node Nb also changes. The change in the potential of node Na is called ΔV Na and the capacitive coupling coefficient is 1 Then, the potential of node Nb is Va+ΔV Na The threshold voltage of transistor Tr22 is Value voltage V th When this is the case, the potential from the wiring OL is Va+ΔV Na -V th will be output. Here, the potential Va is the threshold voltage V th By doing so, the potential ΔV Na Output It is possible.

[0191] Potential ΔV Na is the change in current from the first current to the second current, the resistance value of resistor R1, and the potential Vr The resistance value of the resistor R1 and the potential Vref can be known. Therefore, by using the circuit OFST shown in FIG. Na From, wiring BL The change in the current flowing through the

[0192] The activation function circuit ACTV is electrically connected to the wiring OL and the wiring NIL. The activation function circuit ACTV receives the change in current measured by the circuit OFST via the wiring OL. The activation function circuit ACTV receives the result of the The circuit performs calculations according to a set of functions. For example, the set of functions is a sigmoid function. Use functions such as tanh function, softmax function, ReLU function, and threshold function. These functions are then applied as activation functions in neural networks. .

[0193] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0194] FIG. 11 shows a timing chart of an example of the operation of the arithmetic circuit MAC1. The chart shows the wiring WL[1], wiring WL[2], wiring WL[3], wiring WL[4], wiring WL[5], wiring WL[6], wiring WL[7], wiring WL[8], wiring WL[9], wiring WL

[10] , wiring WL

[11] , wiring WL

[12] , wiring WL

[13] , wiring WL

[14] , wiring WL

[15] , wiring WL

[16] , wiring WL[ Line WD, wire WDref, node NM[1], node NM[2], node NMref[1 ], node NMref[2], wiring CL[1], and wiring CL[2]. , current I B -I α , and current I Bref In particular, the magnitude of the current I B - I α is connected from the wiring BL to the memory cell AM[1] of the memory cell array CA, the memory cell AM [2] shows the total current flowing.

[0195] <<From time T01 to time T02>> Between time T01 and time T02, a high-level potential (see FIG. 11) is applied to the wiring WL[1]. ) is applied to the wiring WL[2], and a low-level potential (shown as High in Figure 11) is applied to the wiring WL[3]. In addition, the wiring WD is applied with a ground potential (Fig. 11 GND is written as V PR -V W[1] A large potential is applied to the wiring W Dref is V above ground potential. PR A large potential is applied. Furthermore, the wiring CL[1] , and the wiring CL[2] are connected to a reference potential (represented as REFP in FIG. 11). is applied.

[0196] In addition, the potential V W[1] is a potential corresponding to the first data position. PR teeth , is the potential corresponding to the reference data.

[0197] At this time, the respective transistors of the memory cell AM[1] and the memory cell AMref[1] A high-level potential is applied to the gate of transistor Tr11, so memory cell AM[1] and The transistors Tr11 of the memory cell AMref[1] and the memory cell AMref[2] are turned on. Therefore, in the memory cell AM[1], the wiring WD and the node NM[1] are in a conductive state. Since the node NM[1] is in the V PR -V W[1] Similarly, memory In cell AMref[1], there is conduction between wire WDref and node NMref[1]. state, the potential of node NMref[1] becomes V PR This becomes:

[0198] Here, the transactions of the memory cell AM[1] and the memory cell AMref[1] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of the transistor Tr12 in AM[1] is I AM[ 1],0 When I AM[1],0 can be expressed by the following formula:

[0199]

number

[0200] k is the channel length, channel width, mobility, and gate insulating film thickness of the transistor Tr12. It is a constant determined by the capacitance etc. th is the threshold voltage of transistor Tr12. be.

[0201] The second terminal of the transistor Tr12 of the memory cell AMref[1] is connected to the wiring BLref. The current flowing through the first terminal is I AMref[1],0 Similarly, when AMre f[1],0can be expressed by the following formula:

[0202]

number

[0203] The transistors of the memory cell AM[2] and the memory cell AMref[2] A low-level potential is applied to the gate of memory cell Tr11, so memory cell AM[2] and The transistor Tr11 of each memory cell AMref[2] is turned off. Therefore, the potential is not written to the node NM[2] and the node NMref[2]. .

[0204] <<From time T02 to time T03>> Between time T02 and time T03, a low-level potential is applied to the wiring WL[1]. At this time, the memory cells AM[1] and AMref[1] are A low-level potential is applied to the gate of transistor Tr11, so memory cell AM[1] , and the transistor Tr11 of the memory cell AMref[1] is turned off. .

[0205] In addition, a low-level potential has been applied to the wiring WL[2] since before time T02. Therefore, each of the memory cells AM[2] and AMref[2] The transistor Tr11 continues to be in the off state from before time T02.

[0206] As described above, memory cell AM[1], memory cell AM[2], memory cell AMref [1] and the transistor Tr11 of the memory cell AMref[2] are in the off state. Therefore, between time T02 and time T03, node NM[1], node The potentials of nodes NM[2], NMref[1], and NMref[2] are Retained.

[0207] In particular, as described in the explanation of the circuit configuration of the arithmetic circuit MAC1, the memory cell AM[1], memory cell AM[2], memory cell AMref[1], and memory cell AMref[2] By applying OS transistors to each transistor Tr11, the transistor This reduces the leakage current flowing between the first and second terminals of the starter transistor 11. , node NM[1], node NM[2], node NMref[1], and node NMre Each potential of f[2] can be maintained for a long time.

[0208] Between time T02 and time T03, the wiring WD and the wiring WDref are grounded. A potential is applied to memory cell AM[1], memory cell AM[2], and memory cell AM The transistor Tr11 of each of the memory cells AMref[1] and AMref[2] is Since it is in the off state, when a potential is applied from the wiring WD and the wiring WDref, Node NM[1], node NM[2], node NMref[1], and node NMref The potential held in each of [2] is not rewritten.

[0209] <<From time T03 to time T04>> Between time T03 and time T04, a low-level potential is applied to the wiring WL[1]. A high level potential is applied to the wiring WL[2]. In addition, a potential higher than the ground potential is applied to the wiring WD. Rimo V PR -V W[2]A large potential is applied to the wiring WDref, and V P R A large potential is applied. Furthermore, as before time T02, the wiring CL[1], and the wiring CL[2] are applied with a reference potential.

[0210] In addition, the potential V W[2] is a potential corresponding to one of the first data.

[0211] At this time, the respective transistors of the memory cell AM[2] and the memory cell AMref[2] A high-level potential is applied to the gate of transistor Tr11, so memory cell AM[2] and The transistors Tr11 of the memory cell AMref[1] and the memory cell AMref[2] are turned on. Therefore, in the memory cell AM[2], the wiring WD and the node NM[2] are in a conductive state. Since the node NM[2] is in the V PR -V W[2] Similarly, memory In cell AMref[2], there is conduction between wire WDref and node NMref[2]. state, the potential of node NMref[2] becomes V PR This becomes:

[0212] Here, the transactions of the memory cell AM[2] and the memory cell AMref[2] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of the transistor Tr12 in AM[2] is I AM[ 2],0 When I AM[2],0 can be expressed by the following formula:

[0213]

number

[0214] The second terminal of the transistor Tr12 of the memory cell AMref[2] is connected to the wiring BLref. The current flowing through the first terminal is I AMref[2],0 Similarly, when AMre f[2],0 can be expressed by the following formula:

[0215]

number

[0216] <<From time T04 to time T05>> Here, between time T04 and time T05, the wiring BL and the wiring BLref The flowing current will now be explained.

[0217] A current is supplied to the wiring BLref from the current source circuit CS. f includes the current mirror circuit CM, the memory cell AMref[1], and the memory cell AMr The current is discharged by ef[2]. The current supplied from the current source circuit CS is discharged through the wiring BLref. The supplied current is I Cref The current drawn by the current mirror circuit CM is I C M,0 Then, the following equation holds according to Kirchhoff's law:

[0218]

number

[0219] The wiring BL is supplied with a current from the current source circuit CS. Current is drained by the input mirror circuit CM, memory cell AM[1], and memory cell AM[2]. Furthermore, a current flows from the wiring BL to the circuit OFST. The current supplied from the power supply circuit CS is I C The current flowing from the wiring BL to the circuit OFST is I α,0 Then, the following equation holds according to Kirchhoff's law:

[0220]

number

[0221] <<From time T05 to time T06>> Between time T05 and time T06, the line CL[1] is at a potential higher than the reference potential V X[ 1] At this time, the memory cell AM[1] and the memory cell AMre The second terminal of each capacitor C1 of f[1] is connected to the potential V X[1] is applied, The potential at the gate of transistor Tr12 rises.

[0222] In addition, the potential V x[1] is a potential corresponding to one of the second data.

[0223] The increase in the potential of the gate of transistor Tr12 corresponds to the change in the potential of line CL[1]. , the potential is multiplied by a capacitive coupling coefficient determined by the configuration of the memory cell. , the capacitance of capacitor C1, the gate capacitance of transistor Tr12, the parasitic capacitance, etc. In this operation example, to avoid the complexity of the explanation, the increase in the potential of the wiring CL[1] is also included in the The increase in the potential of the gate of transistor Tr12 is also assumed to be the same value. M[1] and the capacitance coupling coefficient of memory cell AMref[1] are set to 1. This is equivalent to being

[0224] Since the capacitance coupling coefficient is set to 1, the memory cell AM[1] and the memory cell AMref The second terminal of each capacitor C1 in [1] is connected to a potential V X[1] By applying The potentials of the node NM[1] and the node NMref[1] are V X[1] Rise .

[0225] Here, the transactions of the memory cell AM[1] and the memory cell AMref[1] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of the transistor Tr12 in AM[1] is I AM[ 1],1 When I AM[1],1 can be expressed by the following formula:

[0226]

number

[0227] In other words, the potential V X[1] By applying The current flowing to the first terminal via the second terminal of transistor Tr12 of resonator AM[1] is I AM[1],1 -I AM[1],0 (In Figure 11, ΔI AM[1] ) increase do.

[0228] Similarly, the first line of the transistor Tr12 in the memory cell AMref[1] is connected to the wiring BLref. The current flowing through the second terminal to the first terminal is I AMref[1],1 When I AMre f[1],1 can be expressed by the following formula:

[0229]

number

[0230] In other words, the potential V X[1] By applying from the first terminal through the second terminal of the transistor Tr12 of the memory cell AMref[1]. The current that flows is I AMref[1],1 -I AMref[1],0 (In Figure 11, ΔI AM ref[1] ) increases.

[0231] Here, the current flowing through the wiring BL and the wiring BLref will be described.

[0232] The wiring BLref receives a current from the current source circuit CS, just as it did from time T04 to time T05. The current I Cref At the same time, a current mirror circuit C M, memory cell AMref[1], and memory cell AMref[2] drain current. The current drawn by the current mirror circuit CM in the wiring BLref is I CM,1 Then, the following equation holds according to Kirchhoff's law:

[0233]

number

[0234] The wiring BL receives the current from the current source circuit CS in the same manner as from time T04 to time T05. Flow I C At the same time, the wiring BL is connected to the current mirror circuit CM and the memory cell AM. [1], current is drained by memory cell AM[2]. Furthermore, current flows from wiring BL to circuit O In the wiring BL, the current flowing from the wiring BL to the circuit OFST is I α,1 Then, the following equation holds according to Kirchhoff's law:

[0235]

number

[0236] Current flowing from the wiring BL to the circuit OFST between time T04 and time T05 I α,0 Between time T05 and time T06, the wiring BL is connected to the circuit OFST. Flowing current I α,1 The difference between and is ΔI α Hereafter, ΔI α In the calculation circuit MAC1, This is called the differential current. α Using equations (E1) to (E10), It can be expressed as follows:

[0237]

number

[0238] <<From time T06 to time T07>> Between time T06 and time T07, the reference potential is applied to the line CL[1]. At this time, the memory cells AM[1] and AMref[1] are Since the reference potential is applied to the second terminal of the capacitor C1, the node NM[1] and the node N The potential of Mref[1] returns to the potential between time T04 and time T05.

[0239] <<From time T07 to time T08>> Between time T07 and time T08, the line CL[1] is at a potential higher than the reference potential V X[ 1] A higher potential is applied, and the line CL[2] is V higher than the reference potential.X[2] A high potential is applied At this time, the memory cells AM[1] and AMref[1] are The second terminal of the capacitor C1 is connected to a potential V X[1] is applied to the memory cell AM[2] and the memory cell The second terminal of each capacitor C1 in the AMref[2] is connected to the potential V X[2] is applied. Therefore, memory cell AM[1], memory cell AM[2], memory cell AMref[1], The potential of the gate of each transistor Tr12 of the memory cell AMref[2] is Rise.

[0240] The potentials of the nodes of the memory cell AM[1] and the memory cell AMref[1] The change refers to the operation between time T05 and time T06. Similarly, for memory cell AMref[2], the capacitive coupling coefficients of each memory cell are The explanation will be given assuming the number 1.

[0241] Since the capacitance coupling coefficient is set to 1, the memory cell AM[2] and the memory cell AMref [2] The second terminal of each capacitor C1 is connected to the potential V X[2] By applying The potentials of the node NM[2] and the node NMref[2] are V X[2] Rise .

[0242] Here, the transactions of the memory cell AM[2] and the memory cell AMref[2] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of the transistor Tr12 in AM[1] is I AM[ 2],1 When I AM[2],1 can be expressed by the following formula:

[0243]

number

[0244] In other words, the potential V X[2] By applying The current flowing to the first terminal via the second terminal of transistor Tr12 of resonator AM[2] is I AM[2],1 -I AM[2],0 (In Figure 11, ΔI AM[2] ) increase do.

[0245] Similarly, the first line of the transistor Tr12 in the memory cell AMref[2] is connected to the wiring BLref. The current flowing through the second terminal to the first terminal is I AMref[2],1 When I AMre f[2],1 can be expressed by the following formula:

[0246]

number

[0247] In other words, the potential V X[2] By applying The current flows from the first terminal to the second terminal of the transistor Tr12 of the memory cell AMref[2]. The current that flows is I AMref[2],1 -I AMref[2],0 (In Figure 11, ΔI AM ref[2] ) increases.

[0248] Here, the current flowing through the wiring BL and the wiring BLref will be described.

[0249] The wiring BLref receives a current from the current source circuit CS, just as it did from time T04 to time T05. The current I Cref At the same time, a current mirror circuit C M, memory cell AMref[1], and memory cell AMref[2] drain current. The current drawn by the current mirror circuit CM in the wiring BLref is I CM,2 Then, the following equation holds according to Kirchhoff's law:

[0250]

number

[0251] The wiring BL receives the current from the current source circuit CS in the same manner as from time T04 to time T05. Flow I C At the same time, the wiring BL is connected to the current mirror circuit CM and the memory cell AM. [1], current is drained by memory cell AM[2]. Furthermore, current flows from wiring BL to circuit O In the wiring BL, the current flowing from the wiring BL to the circuit OFST is I α,3 Then, the following equation holds according to Kirchhoff's law:

[0252]

number

[0253] Current flowing from the wiring BL to the circuit OFST between time T04 and time T05 I α,0 Between time T07 and time T08, the wiring BL is connected to the circuit OFST. Flowing current I α,3 and the difference current ΔI α is expressed by the formulas (E1) to (E8), Using equations (E12) to (E15), the following equation can be expressed:

[0254]

number

[0255] As shown in equations (E11) and (E16), the differential current ΔI input to the circuit OFST α is a plurality of first data potentials V W and a plurality of second data potentials V X and the sum of the products In other words, the differential current ΔI α By measuring the circuit OFST, The sum of products of the first data and the second data can be calculated.

[0256] <<From time T08 to time T09>> Between time T08 and time T09, the wiring CL[1] and the wiring CL[2] At this time, the reference potential is applied to memory cell AM[1] and memory cell AM[2]. , the capacitance C1 of the memory cell AMref[1] and the memory cell AMref[2] Since the reference potential is applied to the second terminal of The potentials of the nodes NMref[1] and NMref[2] are respectively changed from time T06 to time T07. The potential returns to the potential up to time T07.

[0257] Between time T05 and time T06, V X[1] Applying Between time T07 and time T08, the wiring CL[1] and the wiring CL[2] Each V X[1] , V X[2] was applied to the wiring CL[1] and wiring CL[2]. The potential of the line CL[1] and / or the line CL When a potential lower than the reference potential REFP is applied to the wiring CL[1] and / or The potential of the storage node of the memory cell connected to the wiring CL[2] is changed by capacitive coupling. This allows the first data and the second data, which are negative values, to be used in the multiplication and accumulation operation. For example, from time T07 to time T08, In this case, V X[2] Not -V X[2] When the differential current Δ I α can be expressed as the following formula:

[0258]

number

[0259] In this example of operation, the memory cell array has memory cells arranged in a matrix of 2 rows and 2 columns. Although the memory cell array CA has been discussed, a memory cell array with one row and two or more columns, or Similarly, the sum-of-products operation can be performed on a memory cell array with more than two rows and three columns. In this case, the product-sum operation circuit selects one of the multiple columns as the reference data (potential V PR ) By using memory cells that are the same size, the multiply-and-accumulate operation can be performed simultaneously for the remaining columns of multiple columns. In other words, by increasing the number of columns in the memory cell array, high-speed multiplication and accumulation operations can be performed. In addition, by increasing the number of rows, In the sum-of-products operation, the number of terms to be added can be increased. Minute current ΔI α can be expressed by the following formula:

[0260]

number

[0261] When the product-sum calculation circuit described in this embodiment is applied to the hidden layer, the weight coefficient w s[k]s[k-1] (k) is stored as the first data in each memory cell AM of the same column. , the output signal z from the s[k-1]th neuron in the (k-1)th layer s[k-1] (k-1) is the potential (second data) applied from the wiring CL of each row, the differential current ΔI α From In addition, the sum of products of the first data and the second data can be calculated. By calculating the value of the activation function, the value of the activation function is used as a signal to Neuron output signal z s[k] (k) It can be said that:

[0262] Furthermore, when the product-sum operation circuit described in this embodiment is applied to the output layer, coefficient w s[L]s[L-1] (L) is set as the first data to each memory cell AM in the same column. The output signal z from the s[L-1]th neuron in the (L-1)th layer is stored. s[L-1] (L -1) is the potential (second data) applied from the wiring CL of each row, the differential current ΔI α In addition, the sum of the products of the first data and the second data can be calculated by The activation function value is then used as a signal to calculate the value of the activation function. [L] Neuron output signal z s[L] (L) It can be said that:

[0263] The input layer described in this embodiment is a buffer circuit that outputs the input signal to the second layer. It may also function as

[0264] In the arithmetic circuit described in this embodiment, the number of rows of memory cells AM is equal to the number of rows of the previous layer of memory cells AM. In other words, the number of rows of memory cells AM is the number of inputs to one neuron in the next layer. The number of columns of memory cells AM corresponds to the number of output signals of the previous layer neurons. In other words, the number of columns of memory cells AM is the number of neurons in the next layer. That is, the number of output signals from each neuron in the previous and next layers corresponds to the number of output signals from each neuron in the previous and next layers. The number of rows and columns of the memory cell array of the arithmetic circuit is determined by the number of The number of rows and columns of the memory cell array is determined according to the neural network. That's fine.

[0265] The configuration of the arithmetic circuit described in this embodiment may be changed depending on the situation. For example, the arithmetic circuit MAC1 shown in FIG. 9 may be changed to the arithmetic circuit MAC1 shown in FIG. The arithmetic circuit MAC1 of FIG. 12 differs from the arithmetic circuit MAC1 of FIG. 9 in that the memory cell array C A memory cell AM[1] and a memory cell AMB in the column including the memory cell AM[1] It is an added configuration.

[0266] The memory cell AMB is electrically connected to the wiring WD, the wiring BL, the wiring WLB, and the wiring CLB. The wiring WLB is electrically connected to the circuit WLD, and the wiring CLB is electrically connected to the circuit CLD.

[0267] In the memory cell AMB, the first terminal of the transistor Tr11 and the second terminal of the transistor Tr1 The connection point between the gate of the transistor 2 and the first terminal of the capacitor C1 is a node NMB.

[0268] When writing data to the memory cell AMB, the wiring WLB is connected to the circuit WLD. The line CLB functions as a line that supplies a selection signal to the memory AMB. It functions as a wiring that applies a constant potential to the second terminal of the capacitor C1 of the cell AMB. The constant potential is preferably a ground potential or a low level potential.

[0269] As an example of the operation of the arithmetic circuit MAC1 in FIG. 12, for example, In this case, between time T01 and time T05, the transistor Tr of the memory cell AMB 12 is turned off, the node NMB is set to the ground potential, the low level potential, or the wiring VR is set to the Then, in the timing chart of FIG. 11, from time T05 Until time T09, the source-drain Any current I BIAS The node NMB is connected to a potential V BIAS Hold. At this time, I BIAS is expressed by the following formula:

[0270]

number

[0271] In this case, equations (E16) and (E18) can be rewritten as the following equations.

[0272]

number

[0273]

number

[0274] Equations (E20) and (E21) further apply an arbitrary bias to the result of the multiply-and-accumulate operation. That is, by using the arithmetic circuit MAC1 of FIG. ) can be calculated. BIAS is not the potential of node NMB, but the potential of wiring C Since it is also determined by the potential given by LB, for example, in the timing chart of FIG. Between time T01 and time T05, the transistor Tr12 of the memory cell AMB To turn the device off, a ground potential is applied to the wiring CLB. During this time, the potential of the wiring CLB is changed from the ground potential to an arbitrary potential, and the transistor of the memory cell AMB is turned on. An arbitrary current I flows between the source and drain of transistor Tr12. BIAS Even if you let it flow good.

[0275] For example, the arithmetic circuit MAC1 shown in FIG. 9 may be replaced with the arithmetic circuit MAC1A shown in FIG. The arithmetic circuit MAC1A in FIG. 13 is the same as the current in the arithmetic circuit MAC1 in FIG. The circuit CMS, which combines the power supply circuit CS and the current mirror circuit CM, and the circuit OFST and activation The memory cell array CA includes a circuit OFAC that combines the function circuit ACTV and the memory cell array CA.

[0276] The circuit CMS includes, for example, a current mirror circuit CM, a current source circuit CS1, and a current source It has a circuit CS2 and a switch SW3.

[0277] The current mirror circuit CM includes, for example, a transistor Tr31 and a transistor Tr 32. The current source circuit CS1 includes, for example, a transistor Tr33 and The current source circuit CS2 includes a capacitor C6 and a switch SW1. It includes a transistor Tr34, a capacitor C7, and a switch SW2.

[0278] The circuit OFAC includes, for example, a switch SW4 and a resistor RE.

[0279] The transistors Tr31 to Tr33 are each shown in FIG. Therefore, it is preferable that the transistor Tr34 is a p-channel transistor. As shown in FIG. 13, it is preferable to use an n-channel transistor. Each of the transistors Tr31 to Tr34 may be, for example, a Si transistor. This can be done.

[0280] Unless otherwise specified, the transistors Tr31 to Tr34 are ON. The on-state includes the case where the device operates in the saturation region. The gate, source, and drain voltages of each transistor are set to operate in the saturation region. This includes when properly biased to a voltage in the range.

[0281] Each of the switches SW1 to SW4 is, for example, an electrical switch. Mechanical switches can be used. In particular, switches SW1 to SW4 When an electrical switch is used for each of the above, the electrical switch is an OS transistor. A silicon transistor, a silicon transistor, or the like can be used.

[0282] Regarding the memory cell array CA, the memory cell array CA of the arithmetic circuit MAC1 in FIG. Please refer to the description. In FIG. 13, the circuit CLD, the circuit WDD, and the circuit WLD are , and are omitted.

[0283] In the current mirror circuit CM, the first terminal of the transistor Tr31 is connected to the wiring VHE. The second terminal of the transistor Tr31 is electrically connected to the gate of the transistor Tr31. The first terminal of the transistor Tr32 is electrically connected to the wiring BLref. The second terminal of the transistor Tr32 is electrically connected to the line VHE. 1 terminal and a first terminal of a switch SW4 of the circuit OFAC.

[0284] In the current source circuit CS1, the first terminal of the transistor Tr33 is electrically connected to the wiring VHE. The second terminal of the transistor Tr33 is connected to the first terminal of the switch SW1. The second terminal of the transistor SW3 is electrically connected to the wiring BL, and the gate of the transistor Tr33 is electrically connected to the wiring BL. The terminal is electrically connected to the second terminal of the switch SW1 and the first terminal of the capacitor C6. The second terminal of the capacitor C6 is electrically connected to the line VHE.

[0285] In the current source circuit CS2, the first terminal of the transistor Tr34 is electrically connected to the line VLE. The second terminal of the transistor Tr34 is connected to the first terminal of the switch SW2. a first terminal of a switch SW3 in the circuit OFAC; and a first terminal of a switch SW4 in the circuit OFAC. The gate of the transistor Tr34 is connected to the second terminal of the switch SW2 and the first terminal of the capacitor C7. The second terminal of the capacitor C7 is electrically connected to the wiring VLE. It is being done.

[0286] In the circuit OFAC, the second terminal of the switch SW4 is electrically connected to the first terminal of the resistor RE. The second terminal of the resistor RE is electrically connected to the line VcL.

[0287] The wiring VHE functions as a wiring for supplying a constant voltage. The constant voltage may be, for example, The wiring VLE can be a wiring for supplying a constant voltage. The constant voltage can be, for example, a low level potential, a ground potential, etc. The wiring VcL functions as a wiring for supplying a constant voltage. , for example, a high-level potential, a low-level potential, a ground potential, etc.

[0288] The current mirror circuit CM generates a current according to the potential at the second terminal of the transistor Tr31. The voltage is supplied from the wiring VHE to the second terminal of the transistor Tr31, and the voltage is also supplied from the wiring VHE to the second terminal of the transistor Tr32. At this time, the voltage is supplied to the second terminal of the transistor Tr3. between the source and drain of transistor Tr31 and between the source and drain of transistor Tr32, respectively. The amounts of current flowing through the electrodes are preferably equal to each other.

[0289] The resistor RE included in the circuit OFAC is connected to the first terminal of the resistor RE via the switch SW4. The circuit OFAC has a function of converting an input current into a voltage. It functions as a voltage conversion circuit.

[0290] Next, a specific example of the operation of the arithmetic circuit MAC1A will be described.

[0291] First, the memory cell AM[1] and the memory cell AM[ 2], each holding node has V PR -V W[1] , V PR -V W[2] is retained Also, the memory cells AMref[ included in the memory cell array CA The storage nodes of memory cell AMref[1] and memory cell AMref[2] are both V PR Held by In addition, the wiring CL[1] and the wiring CL[2] are connected to a potential R Assume that EFP has been entered.

[0292] At this time, memory cell AM[1], memory cell AM[2], memory cell AMref[1 ], the current flowing through each transistor Tr12 of the memory cell AMref[2] is expressed by the formula (E1), equation (E3), equation (E2), and equation (E4).

[0293] Next, as shown in FIG. 14, the switches SW1 and SW2 are turned on. state, and the switches SW3 and SW4 are turned off.

[0294] Here, when the current flowing through the wiring BL is I3, the current I3 flows through the memory cell AM[1] , the current flows between the source and drain of each transistor Tr12 of the memory cell AM[2]. Therefore, from equations (E1) and (E3), I3 = I AM[1],0 +I AM[2],0 It can be said that:

[0295] In addition, in the current source circuit CS1, the switch SW1 is in the on state, so the transistor Transistor Tr33 is configured as a diode. The gate of transistor Tr33 has a potential corresponding to the current I3, and the source-drain A current I3 flows between the two terminals.

[0296] At this time, in the current source circuit CS1, the switch SW1 is turned off. The potential corresponding to the gate current I3 of the transistor Tr33 is maintained by the capacitor C6. As a result, the current source circuit CS1 outputs a current amount I3 to the wiring BL. It can be fixed.

[0297] On the other hand, when the current flowing through the wiring BLref is I4, the current I4 flows through the memory cell AMr ef[1], the source of the transistor Tr12 of the memory cell AMref[2] Since this is the total amount of current flowing between the drains, from equations (E2) and (E4), I4 = I A Mref[1],0 +I AMref[2],0 It can be said that:

[0298] As a result, in the current mirror circuit CM, the source-drain of the transistor Tr31 Therefore, a current I4 flows between the source and drain of the transistor Tr32. Current I4 also flows.

[0299] The current I4 flowing between the source and drain of transistor Tr32 is supplied to current source circuit CS2. Since the switch SW2 is on, the transistor Tr34 acts as a diode. Therefore, the gate of the transistor Tr34 is connected to the The potential is set to the same value, and a current I4 flows between the source and drain of the transistor Tr34.

[0300] Here, in the current source circuit CS2, the switch SW2 is turned off, and the transistor The potential of the gate of the transistor Tr34 according to the current I4 is maintained by the capacitor C7. As a result, the current source circuit CS2 can fix the amount of current it outputs to the wiring VLE to I4. This can be done.

[0301] Next, when the operation of the arithmetic circuit MAC1A changes from that of FIG. 14 to that of FIG. 15, the wiring CL[1] The potential of V X[1] +REFP, and the potential of the wiring CL[2] is V X[2] +RE It is assumed that it has changed to FP.

[0302] At this time, memory cell AM[1], memory cell AM[2], memory cell AMref[1 ], the current flowing through each transistor Tr12 of the memory cell AMref[2] is expressed by the formula (E7), (E12), (E8), and (E13).

[0303] As shown in FIG. 15, the switches SW3 and SW4 are turned on. To be in a certain state.

[0304] Here, when the current flowing through the wiring BL is I1, the current I1 flows through the memory cell AM[1] , the current flows between the source and drain of each transistor Tr12 of the memory cell AM[2]. Therefore, from equation (E7) and equation (E12), I1 = I AM[1],1 + I AM[2],1 It can be said that:

[0305] In addition, when the current flowing through the wiring BLref is I2, the current I2 flows through the memory cell AMr ef[1], the source of the transistor Tr12 of the memory cell AMref[2] Since this is the total amount of current flowing between the drains, from equations (E8) and (E13), I2 = I AMref[1],1 +I AMref[2],1 It can be said that:

[0306] As a result, in the current mirror circuit CM, the source-drain of the transistor Tr31 Therefore, a current I2 flows between the source and drain of transistor Tr32. Current I2 also flows.

[0307] Here, the switch SW4 of the circuit OFAC is in the ON state, so the circuit OFAC and Current flows between the first and second terminals of the switch SW4. When I5 is taken as I5, I5=I1-I2-I3+I4=2k(V W[1] V X[1] +V W [2] V X[2] ) and the sum of products can be calculated in the same way as equation (E16).

[0308] The equivalent circuit of the arithmetic circuit MAC1A in FIG. 15 is the circuit shown in FIG. 16. The current source CI1 shown in FIG. 16 is connected to the memory cell AM[1] and the memory cell A M[2], and the current source CI2 shown in FIG. 16 corresponds to the current source circuit CS1, and The current source CI3 shown in FIG. 16 corresponds to the current source circuit CS2, and the current source CI4 shown in FIG. This corresponds to the mirror circuit CM2.

[0309] The memory cell array CA of the arithmetic circuit MAC1A in FIG. 13 is a matrix of 2 rows and 2 columns. The above discussion deals with a memory cell array having memory cells arranged in one row and For memory cell arrays with two or more columns, or three or more rows and three or more columns Similarly, the sum-of-products operation can be performed on one of the multiple columns. , the reference data (potential V PR ) to hold the remaining data in multiple columns. It is possible to simultaneously perform multiplication and accumulation operations for as many columns as there are columns. Therefore, the number of terms to be added in the sum-of-products operation can be increased. In this case, the current I 5 is I5=2kΣV as in equation (E18). W[i] V X[i]It can be expressed as:

[0310] Here, in the circuit OFAC, the current I5 is converted into a voltage by the resistor RE. Although not shown in FIG. 3, the circuit OFAC performs a predefined operation depending on the voltage. By using a circuit that performs calculations according to a characteristic function, the same as the calculation circuit MAC1 in FIG. , and it is possible to perform hierarchical neural network operations.

[0311] <Configuration example 2 of arithmetic circuit> Next, in the above-mentioned neural network 100, the arithmetic circuit MAC1 has the circuit configuration An example of a circuit that performs a product-sum operation and an activation function operation with different values ​​will be described.

[0312] FIG. 17 shows an example of the configuration of the arithmetic circuit MAC2. The arithmetic circuit MAC2 shown in FIG. The first data corresponding to the voltage held in each cell and the input second data are multiplied and added together. The first circuit performs the multiplication and addition operations and calculates the activation function using the results of the multiplication and addition operations. The data and the second data may be, for example, analog data or multi-value data (discrete data).

[0313] The arithmetic circuit MAC2 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, The circuit SWS2, the cell array CA2, and the conversion circuits ITRZ[1] to ITRZ[ m] and

[0314] The cell array CA2 includes cells IM[1,1] to IM[m,n] (where m is 1). ) and cells IMref[1] to IM ref[m]. Cells IM[1,1] to IM[m,n] are the first data The cell IMref[1] to the cell I Mref[m] is the second data required to perform the product-sum operation on the stored potential. It has the function of supplying voltage to the signal lines XCL[1] to XCL[m].

[0315] The cell array CA2 in FIG. 17 has n+1 cells in the row direction, m cells in the column direction, and a matrix. The cell array CA2 has two or more cells in the row direction and one cell in the column direction. It may be configured such that more than one are arranged in a matrix.

[0316] Cells IM[1,1] to IM[m,n] include transistors F1 and F 2 and a capacitance C5, and the cells IMref[1] to IMref[m] are It includes a transistor F1m, a transistor F2m, and a capacitor C5m.

[0317] Unless otherwise specified, the transistors F1 and F1m are in the on state. The above cases include the case where the circuit finally operates in the linear region. The gate, source, and drain voltages of each transistor operate in the linear region. However, this includes cases where the voltage is appropriately biased in the range For example, the transistors F1 and F1m are in an on state. In the case of the linear mode, it may operate in the saturation region. It is also possible to mix the two cases.

[0318] In addition, unless otherwise specified, the transistors F2 and F2m are sub-threads. When operating in the threshold region (i.e., when transistor F2 or transistor F2m This includes the case where the gate-source voltage is lower than the threshold voltage. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are as follows: This includes when properly biased to voltages that operate in the subthreshold region. Therefore, the transistors F2 and F2m are configured as source-drain This includes cases where an off-state current flows between the transistors.

[0319] In addition, the transistor F1 and / or the transistor F1m are connected to the transistor Tr11. Similarly, it is preferably an OS transistor. In addition, the transistor F1 and / or The channel forming region of the transistor F1m is made of indium, element M (for example, For example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. The oxide may be an oxide containing at least one of: It is more preferable that the transistor Tr1 and / or the transistor F1m are It is more preferable that the transistor has the structure described in 3.

[0320] An OS transistor is used as the transistor F1 and / or the transistor F1m. This reduces the leakage current of the transistor F1 and / or the transistor F1m. This allows for the realization of a multiply-and-accumulate circuit with high calculation accuracy. By using OS transistors as transistors F1 and / or F1m, , the holding node when the transistor F1 and / or the transistor F1m are in a non-conducting state. This makes it possible to make the leakage current from the retention node to the write word line very small. This reduces the power consumption of the multiply-accumulate circuit. can be reduced.

[0321] Also, the transistor F2 and / or the transistor F2m are also OS transistors. By using a capacitor, it is possible to operate in a wide current range in the subthreshold region. Therefore, the current consumption can be reduced. By using an OS transistor for transistor F2m, the same Since it can be manufactured in one step, the manufacturing process of the sum-of-products operation circuit can be shortened in some cases. In addition, the transistor F2 and / or the transistor F2m have a channel forming region. The transistor may contain silicon, such as amorphous silicon. (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, Single crystal silicon or the like can be used.

[0322] In each of the cells IM[1,1] to IM[m,n], the transistor F1 The first terminal is electrically connected to the gate of the transistor F2. The first terminal of the capacitor C5 is electrically connected to the wiring VE. It is electrically connected to the gate of F2.

[0323] One embodiment of the present invention does not depend on the connection structure of the back gate of a transistor. In FIG. 17, the transistors F1 and F2 are shown with back gates. FIG. 17 shows a configuration having the back gate. Although the structure is not shown in the figure, the electrical connection destination of the back gate is determined at the design stage. For example, in a transistor with a back gate, the To increase the on-current of the transistor, the gate and back gate may be electrically connected. That is, for example, the gate and back gate of the transistor M2 may be electrically connected. In addition, for example, in a transistor having a back gate, the threshold of the transistor In order to change the voltage to a low value or to reduce the off-state current of the transistor, By providing wiring electrically connected to an external circuit, etc., the transformer is connected to the external circuit, etc. A potential may be applied to the back gate of the transistor F1. m, transistor F2m, and transistors F3[1] to F3[n], which will be described later. , transistor F4[1] to transistor F4[n], and further, not only FIG. 17 but also the specification or transistors shown in other drawings. The same is true for .

[0324] In addition, a semiconductor device according to one embodiment of the present invention may include a transistor having a structure For example, the transistors F1 and F2 shown in FIG. As shown in Figure 17, the structure does not have a back gate, that is, a single gate structure. The transistor may be a back gate. Another part of the transistors may have no back gate. , in this regard, transistor F1m, transistor F2m, transistor F 3[1] to transistor F3[n], transistor F4[1] to transistor F4[ n], and further, the circuit diagram shown in FIG. 17 as well as the transistors described elsewhere in the specification. The same is true for the transistors shown in the drawings or other figures.

[0325] The wiring VE is composed of cells IM[1,1], IM[m,1], IM[1,n], and In order to pass current between the first and second terminals of each transistor F2 of the filter IM[m,n], The wiring for the cell IMref[1] and the cell IMref[m] This functions as a wiring for passing a current between the first terminal and the second terminal of the transistor F2. For example, the wiring VE functions as a wiring that supplies a constant voltage. The constant voltage is For example, it can be a low level potential, a ground potential, or the like.

[0326] In the cell IM[1,1], the second terminal of the transistor F1 is connected to the wiring WCL[1]. The gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1], and the capacitor C5 The second terminal of the cell I is electrically connected to the wiring XCL[1]. In M[1,1], the first terminal of transistor F1, the gate of transistor F2, The connection point between the first terminal of the capacitor C5 and the node NN[1,1].

[0327] In the cell IM[m,1], the second terminal of the transistor F1 is connected to the wiring WCL[1]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1], and the capacitor C5 The second terminal of the cell I is electrically connected to the wiring XCL[m]. In M[m,1], the first terminal of transistor F1, the gate of transistor F2, The connection point between the first terminal of the capacitor C5 and the node NN[m,1].

[0328] In the cell IM[1,n], the second terminal of the transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n] and the capacitor C5 The second terminal of the cell I is electrically connected to the wiring XCL[1]. In M[1,n], the first terminal of transistor F1, the gate of transistor F2, The connection point between the first terminal of the capacitor C5 and the node NN[1,n].

[0329] In the cell IM[m,n], the second terminal of the transistor F1 is connected to the wiring WCL[n]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n] and the capacitor C5 The second terminal of the cell I is electrically connected to the wiring XCL[m]. In M[m,n], the first terminal of transistor F1, the gate of transistor F2, The connection point between the first terminal of the capacitor C5 and the node NN[m, n].

[0330] In the cell IMref[1], the second terminal of the transistor F1m is connected to the line XCL[1] The gate of the transistor F1m is electrically connected to the wiring WSL[1]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[1]. The second terminal of the capacitor C5 is electrically connected to the line XCL[1]. In cell IMref[1], the first terminal of transistor F1m and the first terminal of transistor F2 The connection point between the gate of m and the first terminal of the capacitor C5 is the node NNref[1]. .

[0331] In the cell IMref[m], the second terminal of the transistor F1m is connected to the wiring XCL[m] The gate of the transistor F1m is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[m]. The second terminal of the capacitor C5 is electrically connected to the line XCL[m]. In the cell IMref[m], the first terminal of the transistor F1m and the first terminal of the transistor F2 The connection point between the gate of m and the first terminal of the capacitor C5 is the node NNref[m]. .

[0332] The above-mentioned nodes NN[1,1], NN[m,1], NN[1,n], node NN[m,n], node NNref[1], and node NMref[m] are respectively It serves as a holding node for the cell.

[0333] The circuit SWS1 includes transistors F3[1] to F3[n]. The first terminal of the transistor F3[1] is electrically connected to the wiring WCL[1]. The second terminal of F3[1] is electrically connected to the circuit WCS and is the gate of the transistor F3[1]. The first terminal of the transistor F3[m] is electrically connected to the wiring SWL1. , and the second terminal of the transistor F3[m] is electrically connected to the wiring WCL[m]. The gate of transistor F3[m] is electrically connected to wiring SWL1. is connected.

[0334] Transistors F3[1] to F3[n] are the same as transistor Tr11. In addition, the transistor F1 and / or the transistor F2 are preferably OS transistors. The channel forming region of the transistor F1m is made of indium, element M (for example, , aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One selected from odymium, hafnium, tantalum, tungsten, magnesium, etc. It is more preferable that the oxide contains at least one of zinc and zinc. It is preferable that the transistors F3[1] to F3[n] are the same as those in the third embodiment. More preferably, the transistor structure is as described.

[0335] The circuit SWS1 is connected to the circuit WCS and each of the wirings WCL[1] to WCL[n]. , functioning as a circuit for switching between a conductive state and a non-conductive state.

[0336] The circuit SWS2 includes transistors F4[1] to F4[n]. The first terminal of the transistor F4[1] is electrically connected to the wiring WCL[1]. The second terminal of F4[1] is electrically connected to the conversion circuit ITRZ[1], and the second terminal of the transistor F The gate of transistor F4[1] is electrically connected to wiring SWL2. The first terminal of the transistor F4[m] is electrically connected to the wiring WCL[m], and the second terminal of the transistor F4[m] is electrically connected to the wiring WCL[m]. The transistor F4[m] is electrically connected to the conversion circuit ITRZ[1], and the gate of the transistor F4[m] is , and is electrically connected to the wiring SWL2.

[0337] Transistors F4[1] to F4[n] are the same as transistor Tr11. In addition, the transistor F1 and / or the transistor F2 are preferably OS transistors. The channel forming region of the transistor F1m is made of indium, element M (for example, , aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One selected from odymium, hafnium, tantalum, tungsten, magnesium, etc. It is more preferable that the oxide contains at least one of zinc and zinc. It is preferable that the transistors F4[1] to F4[n] are the same as those in the third embodiment. More preferably, the transistor structure is as described.

[0338] The circuit SWS2 is connected between the wiring WCL[1] and the circuit ITRZ[1] and between the wiring WCL[n ] and the circuit ITRZ[n], and functions as a circuit that switches between the conductive state and the non-conductive state. It works.

[0339] The circuit WCS transmits data to be stored in each cell of the cell array CA2. It has the function of trusting.

[0340] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The path XCS includes cells IMref[1] to IMref[m] of the cell array CA2. A function of supplying a current according to the reference data or a current according to the second data to each of the above. It has.

[0341] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing the first data to the cell of the cell array CA2, the line WSD By sending a predetermined signal to the wiring WSL[1] to the wiring WSL[m], the data is written to the The memory cell has a function of selecting a memory cell.

[0342] The circuit WSD is electrically connected to the wirings SWL1 and SWL2. The circuit WSD transmits a predetermined signal to the wiring SWL1 to connect the circuit WCS to the cell array. The function of making the connection between the wire CA2 and the wire SWL2 conductive or non-conductive, and the function of sending a predetermined signal to the wire SWL2 By transmitting, the conversion circuits ITRZ[1] to ITRZ[m] and the cell array a) It has the function of establishing a conductive state or a non-conductive state between the CA1 and the CA2.

[0343] Each of the conversion circuits ITRZ[1] to ITRZ[m] has an input terminal and an output terminal. Each of the conversion circuits ITRZ[1] to ITRZ[m] has a terminal. It has the function of converting the current input to the input terminal into a voltage corresponding to the current and outputting it from the output terminal. Each of the conversion circuits ITRZ[1] to ITRZ[m] is, for example, a circuit OFST can be applied. Each of [m] may have an activation function circuit ACTV, which uses the converted voltage , the activation function may be calculated and the result of the calculation may be output to the output terminal.

[0344] <Operation example 2 of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC2 will be described.

[0345] FIG. 18 shows a timing chart of an example of the operation of the arithmetic circuit MAC2. The chart shows the wiring SW L1, wiring SWL2, wiring WSL[i] (i is an integer between 1 and m-1), wiring WSL[i+1], wiring XCL[i], wiring XCL[i+1], node NN[i,j], The power of node NNref[i], node NN[i+1,j], and node NNref[i+1] Furthermore, the timing chart in Figure 18 shows the fluctuation of the cell IM[i,j]. The amount of current I flowing between the first and second terminals of the included transistor F2 F2 [i,j] and between the first terminal and the second terminal of the transistor F2m included in the cell IMref[i] Amount of current flowing I F2m [i] and transistor F included in cell IM[i+1,j] The amount of current I flowing between the first and second terminals of 2 F2 [i+1,j] and cell IMref[i +1], the amount of current I flowing between the first and second terminals of the transistor F2m F2 m The respective variations of [i+1] and are also shown.

[0346] In this operation example, the potential of the wiring VE is set to the ground potential GND. Before that, the cells IM[i,j] and IM[i+1,j] are included in Transistor F1, cell IMref[i], and cell IMref[i+1] are included in By turning on the transistor F1m, the node NN[i,j] and the node NNref[i] , the potentials of the nodes NN[i+1,j] and NNref[i+1] are set to the ground potential. It is assumed that the terminal is connected to GND.

[0347] Also, as an initial setting, the cells IM[1,1] to IM[m,n] are Each of the transistors F1, IMref[1], IMref[m], and IMref[m] includes The transistor F1m connected to the node NN[1,1] to the node NN[m, n], and the potentials of the nodes NNref[1] to NNref[m] are set to the ground potential GND. do.

[0348] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential ( is written as High.) is applied to the wiring SWL2, and a low-level potential (L in FIG. 18) is applied to the wiring SWL3. ow). This causes transistors F3[1] to F3[2] to A high-level potential is applied to the gate of each of the transistors F3[n]. Each of the transistors F3[1] to F3[n] is turned on, and the transistor F4[ A low-level potential is applied to the gates of transistors F1[n] to F4[n]. Each of the transistors F4[1] to F4[n] is turned off.

[0349] In addition, between time T11 and time T12, the wiring WSL[i], wiring WSL[i+ 1] is applied with a low level potential. The gate of the transistor F1 included in the cells IM[i,1] to IM[i,n] and the A low-level potential is applied to the gate of the transistor F1m included in the IMref[i]. When the voltage Vcc is applied, the transistors F1 and F1m are turned off. , cell IM[i+1,1] to cell IM[i+1,n] in the i+1th row of cell array CA2 and the gate of transistor F1 contained in cell IMref[i+1]. A low level potential is applied to the gate of the transistor F1m, and F1 and transistor F1m are turned off.

[0350] In addition, between time T11 and time T12, the wiring XCL[i], wiring XCL[i+ 1] has a ground potential GND applied to it.

[0351] Also, between time T11 and time T12, the wiring WCL[j] and the wiring XCL[i] , no current flows through the wire XCL[i+1]. F2 [i,j], I F2m [ i]I F2 [i+1,j], I F2m [i+1] becomes 0.

[0352] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is applied to the wiring WSL[i]. As a result, cells IM[i,1] to IM[i , n] and the gate of transistor F1 contained in cell IMref[i]. A high level potential is applied to the gate of the transistor F1m, which is connected to the The transistors F1 and F1m are turned on. Between them, the wirings WSL[1] to WSL[m] except for the wiring WSL[i] have low levels. A bell potential is applied to the cells IM[1,1] to IM[1,1] other than the i-th row of the cell array CA2. The transistor F1 included in the cell IM[m,n] and the cell IMref[1 ] to the transistor F1m included in the cell IMref[m] is in the off state. This shall be the case.

[0353] Furthermore, a low-level potential is applied to the wirings XCL[1] to XCL[m].

[0354] <<From time T13 to time T14>> Between time T13 and time T14, the transistor F3[j ], a current of I0[i,j] flows to the cell array CA2. The first transistor F1 included in the cell IM[i,j] in the i-th row of the cell array CA2 The terminal and the wiring WCL[j] are in a conductive state, and the i-th row of the cell array CA2 The first transistor F1 included in the cells IM[1,j] to IM[m,j] other than the cell IM[1,j] Since there is no conduction between terminal 1 and wiring WCL[j], A current of I0[i,j] flows through cell IM[i,j].

[0355] By the way, when the transistor F1 included in the cell IM[i,j] is turned on, Therefore, the transistor F2 included in the cell IM[i,j] is configured as a diode. Therefore, when current flows from the wiring WCL[j] to the cell IM[i,j], The potentials of the gate of transistor F2 and the second terminal of transistor F2 are approximately equal. The potential is determined by the amount of current flowing from the wiring WCL[j] to the cell IM[i,j] and the In this example, the potential of the first terminal of the resistor F2 is determined by the potential of the first terminal of the resistor F3 (GND in this example). , a current of I0[i,j] flows from the wiring WCL[j] to the cell IM[i,j]. Therefore, the potential of the gate of transistor F2 (node ​​NN[i,j]) is V g [i,j ]. In other words, in transistor F2, the gate-source voltage is V g [i,j]-GND, and the current I0 A current of [i,j] flows.

[0356] Here, the threshold voltage of transistor F2 is V th When the transistor F2 is The current I0[i,j] when operating in the threshold region can be expressed as follows: do.

[0357]

number

[0358] In addition, I a is V g V th [i,j] is the drain current, K is the temperature, This is a correction coefficient determined by the device structure, etc.

[0359] In addition, between time T13 and time T14, the wiring XCL[i ] as the current amount I ref0 At this time, the current contained in the cell IMref[i] The first terminal of the transistor F1m is in a conductive state with the wiring XCL[i]. Therefore, the current I ref0 A current of flows.

[0360] Similarly to cell IM[i,j], transistor F1 contained in cell IMref[i] When m is turned on, the transistor included in cell IMref[i,j] The cell F2m is configured as a diode connection. When current flows through f[i], the gate of transistor F2m and the first The potentials of the two terminals are almost equal. The amount of current flowing through IMref[i] and the potential of the first terminal of transistor F2m (here, GN In this example, the line XCL[i] is connected to the cell IMref[i ] to the current amount I ref0 The current flows through the gate of transistor F2 (node NNref[i]) is V gm [i], and the wiring XCL[i] The potential of V gm [i]. That is, in the transistor F2m, the gate-source The voltage is V gm [i]-GND, and between the first and second terminals of transistor F2m, Current amount I ref0 A current of flows.

[0361] Here, the threshold voltage of transistor F2m is V thm When [i] is set, the transistor The amount of current I when the transistor F2m operates in the subthreshold region ref0 is expressed as follows: The correction coefficient K is the sum of the values ​​of the transistor F2 included in the cell IM[i,j]. For example, the device structure and size (channel length, channel width) of a transistor ) are the same. Also, due to manufacturing variations, the correction coefficient K of each transistor varies. However, it is assumed that the variation is suppressed to the extent that the discussion below can be carried out with sufficient accuracy for practical purposes. do.

[0362]

number

[0363] Here, the weighting coefficient w[i,j], which is the first data, is defined as follows:

[0364]

number

[0365] Therefore, equation (F1) can be rewritten as follows:

[0366]

number

[0367] <<From time T14 to time T15>> Between time T14 and time T15, a low-level potential is applied to the wiring WSL[i]. As a result, cells IM[i,1] to IM[i , n] and the gate of transistor F1 contained in cell IMref[i]. A low level potential is applied to the gate of the transistor F1m, which is connected to the The transistors F1 and F1m are turned off.

[0368] When the transistor F1 included in the cell IM[i,j] is turned off, The capacitor C5 is connected to the potential of the gate of the transistor F2 (node ​​NN[i,j]) and the potential of the wiring XC The difference between the potential of L[i] and V g [i,j]-V gm [i] is held. Also, cell When the transistor F1 included in IMref[i] is turned off, the capacitance C5m is connected to the potential of the gate (node ​​NNref[i]) of transistor F2m and the potential of the wiring X The potential difference between CL[i] and 0 is maintained. The potential maintained by the capacitance C5m is In the operation from time T13 to time T14, the transistors F1m and F2m Depending on the characteristics of each transistor, the potential may be non-zero (here, Δ). However, the potential of the node NNref[i] is increased by adding Δ to the potential of the wiring XCL[i]. By considering that the potential becomes higher than the

[0369] <<From time T15 to time T16>> Between time T15 and time T16, GND is applied to the line XCL[i]. Therefore, the cells IM[i,1] to IM[i,n] in the i-th row contain The capacitance C5 in the node NN[i,1] to the node NN[i,n] is coupled by the capacitance C5. The potential changes, and the noise is generated by the capacitive coupling of the capacitor C5 included in the cell IMref[i]. The potential of node NNref[i] changes.

[0370] The amount of change in the potential of the nodes NN[i,1] to NN[i,n] is The amount of change in the potential of each cell IM[i,1] to This potential is multiplied by the capacitive coupling coefficient determined by the configuration of the cell IM[i,n]. The coefficient is calculated based on the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, etc. In each of the cells IM[i,1] to IM[i,n], When the capacitance coupling coefficient is p, the potential of the node NN[i,j] of the cell IM[i,j] is From the potential at the time between time T14 and time T15, p(V gm [i]-GND) Decreases.

[0371] Similarly, when the potential of the wire XCL[i] changes, the voltage contained in the cell IMref[i] The potential of node NNref[i] also changes due to the capacitive coupling caused by the capacitor C5m included in the When the capacitance coupling coefficient of the capacitance C5m is p, the same as the capacitance C5, the cell IMref The potential of the node NNref[i] of [i] is From the potential at p(V gm [i]-GND) decreases.

[0372] This reduces the potential of node NN[i,j] of cell IM[i,j], The transistor F2 is turned off, and similarly, the node NNref[i] of the cell IMref[i] i] drops, the transistor F2m also turns off. Between time T5 and time T16, I F2 [i,j], I F2m Each of [i] is 0 This becomes:

[0373] <<From time T16 to time T17>> Between time T16 and time T17, a high-level potential is applied to the wiring WSL[i+1]. As a result, the cells IM[i+1,1] to IM[i+1,1] in the i+1th row of the cell array CA2 are The gate of transistor F1 included in cell IM[i+1,n] and the gate of cell IMref[ i+1], and a high-level potential is applied to the gate of the transistor F1m included in The transistors F1 and F1m are turned on. Between time T6 and time T17, the wirings WSL[1] to WSL[i+1] are A low-level potential is applied to the wiring WSL[m], and the i+1th row and subsequent rows of the cell array CA2 are connected. The transistor F1 included in the outer cells IM[1,1] to IM[m,n], and i +Transistors included in cells IMref[1] to IMref[m] other than the first row Assume that the start F1m is in the off state.

[0374] Furthermore, a low-level potential is applied to the wirings XCL[1] to XCL[m].

[0375] <<From time T17 to time T18>> Between time T17 and time T18, the transistor F3[j ], a current of I0[i+1,j] flows to the cell array CA2. Then, the transistor included in the cell IM[i+1,j] in the i+1th row of the cell array CA2 is The first terminal of the capacitor F1 is in a conductive state with the wiring WCL[j], and the cell array C The transactions included in cells IM[1,j] to IM[m,j] other than the i+1th row of A2 Since there is no conduction between the first terminal of the transistor F1 and the wiring WCL[j], A current of I0[i+1,j] flows from WCL[j] to cell IM[i+1,j].

[0376] By the way, the transistor F1 included in the cell IM[i+1,j] is turned on. As a result, the transistor F2 included in the cell IM[i+1,j] is in diode connection. Therefore, current flows from the wiring WCL[j] to the cell IM[i+1,j]. When the transistor F2 is turned on, the voltages at the gate of the transistor F2 and the second terminal of the transistor F2 are The potential flows from the wiring WCL[j] to the cell IM[i+1,j]. The amount of current flowing through the transistor F2 and the potential of the first terminal of the transistor F2 (GND in this case) are also determined. In this operation example, the amount of current I0[i+1 , j], the gate of transistor F2 (node ​​NN[i+1, j]) is V g [i+1,j]. That is, in transistor F2, When the gate-source voltage is V g [i+1,j]-GND, and transistor F2 A current of magnitude I0[i+1,j] flows between the first terminal and the second terminal.

[0377] Here, the threshold voltage of transistor F2 is V th When [i+1,j] is used, When the transistor F2 operates in the subthreshold region, the current I0[i+1,j] is as follows: The correction coefficient is calculated by the following formula: The transistor F2 is set to K, which is the same as that of the transistor F2m included in the cell IMref[i]. do.

[0378]

number

[0379] In addition, between time T17 and time T18, the wiring XCL[i +1] as the current amount I ref0 At this time, the current of cell IMref[i+1] The first terminal of the transistor F1m included in the Therefore, the current I ref0 of Current flows.

[0380] The transistor contained in cell IMref[i+1] is the same as that contained in cell IM[i+1,j]. When the F1m signal is turned on, the signal contained in the cell IMref[i+1,j] The transistor F2m connected to the wiring XCL[i+1] is a diode-connected transistor. When current flows from the cell IMref[i+1] to the gate of the transistor F2m, The potentials of the second terminal of the transistor F2m and the second terminal of the transistor F2m are approximately equal. The amount of current flowing from XCL[i+1] to cell IMref[i+1] and the amount of current flowing from transistor F2m In this operation example, the potential of the wiring XCL [i+1] to cell IMref[i+1] with current I ref0 The current flowing The gate of transistor F2 (node ​​NNref[i+1]) is V gm [i+1] At this time, the potential of the wiring XCL[i+1] is also V gm Let [i+1]. That is, in transistor F2m, the gate-source voltage is V gm [i+1]-GN D, and the current I flows between the first and second terminals of the transistor F2m. ref0 The current of Flowing.

[0381] Here, the threshold voltage of transistor F2m is V thm When [i+1,j] is used, The current I when transistor F2m operates in the subthreshold region ref0 is expressed as The correction coefficient K is the sum of the total number of traces included in the cell IM[i+1,j]. It is the same as transistor F2.

[0382]

number

[0383] Here, the weighting coefficient w[i+1,j], which is the first data, is defined as follows:

[0384]

number

[0385] Therefore, equation (F5) can be rewritten as follows:

[0386]

number

[0387] <<From time T18 to time T19>> Between time T18 and time T19, a low-level potential is applied to the wiring WSL[i+1]. As a result, the cells IM[i+1,1] to IM[i+1,1] in the i-th row of the cell array CA2 are The gate of transistor F1 included in IM[i+1,n] and the gate of cell IMref[i+ 1], the gate of the transistor F1m included in The transistors F1 and F1m are both turned off.

[0388] When the transistor F1 included in the cell IM[i+1,j] is turned off, The capacitor C5 receives the potential of the gate of the transistor F2 (node ​​NN[i+1,j]) and The difference between the potential of the wiring XCL[i+1] and V g [i+1,j]-V gm [i+1] is saved Also, the transistor F1 included in the cell IMref[i+1] is in the off state. As a result, the capacitance C5m is connected to the gate of the transistor F2m (node ​​NNref The difference between the potential of the line XCL[i+1] and the potential of the line XCL[i+1] is kept at 0. The potential held by C5m is the same as that held by transistor F during the operation from time T18 to time T19. Depending on the transistor characteristics of 1m and transistor F2m, the potential is not 0 (here, However, the potential of the node NNref[i] may be different from that of the wiring XCL The following argument holds if we consider the potential to be the potential of [i] plus Δ.

[0389] <<From time T19 to time T20>> Between time T19 and time T20, GND is applied to the line XCL[i+1]. Therefore, the cells IM[i+1,1] to IM[i+1,n] in the i+1th row are The nodes NN[i,1] to NN[i,2] are connected by capacitive coupling with the capacitor C5 included in each node. The potential of NN[i+1,n] changes, and the capacitance C5 contained in cell IMref[i+1] The potential of the node NNref[i+1] changes due to the capacitive coupling caused by the

[0390] The amount of change in the potential of the nodes NN[i+1,1] to NN[i+1,n] is The change in the potential of L[i+1] is calculated by dividing the potential of each cell IM[ The capacitance coefficient is determined by the configuration of cells IM[i+1,1] to IM[i+1,n]. The capacitance coupling coefficient is determined by the capacitance of the capacitor C5, the gate capacitance of the transistor F2, and the parasitic capacitance The amount of data is calculated based on the amount of data in cells IM[i+1,1] to IM[i+1,n]. In each case, the capacitive coupling coefficient due to the capacitance C5 is calculated as follows: Similarly, when p is set, the capacitance coupling coefficient due to the capacitance C5 in each of the cells IM The potential of the node NN[i+1,j] of [i+1,j] is From the potential at the time between, p(V gm[i+1]-GND) decreases.

[0391] Similarly, when the potential of the wiring XCL[i+1] changes, the cell IMref[i+ 1], the capacitance C5m of node NNref[i+1] When the capacitance coupling coefficient of the capacitance C5m is p, the same as the capacitance C5, The potential of the node NNref[i+1] of the filter IMref[i+1] is From the potential at the time point between 19 and 20, p(V gm [i+1]-GND) decreases.

[0392] This causes the potential of node NN[i+1,j] of cell IM[i+1,j] to drop. Therefore, transistor F2 is turned off, and similarly, the node of cell IMref[i+1] Since the potential of NNref[i] drops, the transistor F2m also turns off. Therefore, between time T19 and time T20, I F2 [i+1,j], I F2m [i +1] will be 0.

[0393] <<From time T20 to time T21>> Between time T20 and time T21, a low-level potential is applied to the line SWL1. As a result, each of the transistors F3[1] to F3[n] A low level potential is applied to the gates of the transistors F3[1] to F3[n ] are each turned off.

[0394] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential is applied to the wiring SWL2. As a result, each of the transistors F4[1] to F4[n] A high-level potential is applied to the gates of the transistors F4[1] to F4[n ] are each turned off.

[0395] <<From time T22 to time T23>> Between time T22 and time T23, the circuit XCS supplies power to the wiring XCL[i]. Flow rate as I ref0 x[i] times x[i]I ref0 A current of In the example, x corresponds to the value of the neuron signal, which is the second data. The potential of XCL[i] ranges from 0 to V gm [i]+ΔV[i].

[0396] The potential of the wiring XCL[i] changes, and the cell I in the i-th row of the cell array CA2 Capacitive coupling by a capacitor C5 included in each of cells M[i,1] to IM[i,n] Therefore, the potentials of the nodes NN[i,1] to NN[i,n] also change. , the potential of node NN[i,j] of cell IM[i,j] is V g [i,j]+pΔV[i] This becomes:

[0397] Similarly, when the potential of the wire XCL[i] changes, the voltage contained in the cell IMref[i] The potential of node NNref[i] also changes due to the capacitive coupling caused by the capacitor C5m included in the Therefore, the potential of the node NNref[i] of the cell IMref[i] is V gm [i] +pΔV[i].

[0398] As a result, between time T22 and time T23, the first Current I1[i,j] flowing between terminals I and II of transistor F2m Current I flowing between the electrodes ref1 [i,j] can be written as follows:

[0399]

number

[0400]

number

[0401] From equations (F9) and (F10), x[i] can be expressed by the following equation.

[0402]

number

[0403] Therefore, equation (F9) can be rewritten as follows:

[0404]

number

[0405] That is, between the first terminal and the second terminal of the transistor F2 included in the cell IM[i,j] The current flowing through the It is proportional to the product of the signal value x[i] of the input signal and

[0406] In addition, between time T22 and time T23, the wiring XCL[i +1] as the current amount I ref0 x[i+1] is x[i+1] times I ref0 Current In this example, x corresponds to the value of the neuron signal, which is the second data. At this time, the potential of the wiring XCL[i+1] changes from 0 to V gm [i+1]+ΔV[i+1 ] shall be changed to

[0407] The potential of the wiring XCL[i+1] changes, and the i+1th row of the cell array CA2 The capacitance C included in each of the cells IM[i+1,1] to IM[i+1,n] By the capacitive coupling by 5, the nodes NN[i+1,1] to NN[i+1,n] The potential also changes. Therefore, the potential of node NN[i+1,j] of cell IM[i+1,j] is V g [i+1,j]+pΔV[i+1].

[0408] Similarly, when the potential of the wiring XCL[i+1] changes, the cell IMref[i+ 1], the capacitance C5m of node NNref[i+1] Therefore, the potential of node NNref[i+1] of cell IMref[i+1] also changes. The potential is V gm [i+1]+pΔV[i+1].

[0409] As a result, between time T22 and time T23, the first The current I1[i+1,j] flowing between the terminal and the second terminal of the transistor F2m is Current I flowing between the two terminals ref1 [i+1,j] can be written as follows:

[0410]

number

[0411]

number

[0412] From equations (F13) and (F14), x[i+1] can be expressed by the following equation.

[0413]

number

[0414] Therefore, equation (F13) can be rewritten as follows:

[0415]

number

[0416] That is, the first terminal and the second terminal of the transistor F2 included in the cell IM[i+1,j] The current flowing between the elements is the weight coefficient w[i+1,j], which is the first data, and the weight coefficient w[i+1,j], which is the second data. It is proportional to the product of the neuron's signal value x[i+1] and

[0417] Here, from the conversion circuit ITRZ[j], the transistor F4[j] and the wiring WCL[j] Consider the sum of the currents flowing through cells IM[i,j] and IM[i+1,j]. The sum of the currents is I S If [j], then I S [j] is given by equation (F12) and equation (F16). and can be expressed by the following formula:

[0418]

number

[0419] Therefore, the current output from the conversion circuit ITRZ[j] is the first data, which is the weighting coefficient The numbers w[i,j] and w[i+1,j] and the second data, the neuron signal value x[i ] and x[i+1], the current is proportional to the sum of the products of

[0420] In the above example of operation, the signal flowing to the cell IM[i,j] and the cell IM[i+1,j] The sum of the currents has been treated as multiple cells, cell IM[1,j] to cell IM[m , j] can also be treated as the sum of the currents flowing through each of the can be rewritten as the following equation:

[0421]

number

[0422] Therefore, in the case of the arithmetic circuit MAC2 having the cell array CA2 of three or more rows and two or more columns, However, as mentioned above, it is possible to perform a sum-of-products operation. One of the columns is designated as I ref0 , and xI ref0 By using it as a cell to hold The multiply-and-accumulate operations can be performed simultaneously for the remaining columns. By increasing the number of columns in the memory cell array, we have proposed a semiconductor device that achieves high-speed multiplication and accumulation processing. It can be provided.

[0423] When the product-sum calculation circuit described in this embodiment is applied to the hidden layer, the weight coefficient w s[k]s[k-1] (k) is used as the first data, and the current amount according to the first data is calculated in the same column. The output from the s[k-1]th neuron in the (k-1)th layer is signal z s[k-1] (k-1) is used as the second data, and a current according to the second data is supplied to the circuit XC By passing the current I from S to the wiring XCL of each row, the current I output from the circuit ITRZ S from The sum of products of the first data and the second data can be calculated. By calculating the value of the activation function, the value of the activation function is used as a signal to Neuron output signal z s[k] (k) It can be said that:

[0424] Furthermore, when the product-sum operation circuit described in this embodiment is applied to the output layer, coefficient w s[L]s[L-1] (L) is used as the first data, and the current amount according to the first data is Each cell IM in the same column is memorized sequentially, and the s[L-1]th neuron in the (L-1)th layer is The output signal z s[L-1] (L-1) is used as the second data, and a current according to the second data is generated. By passing the current I from the circuit XCS to the wiring XCL of each row, the current I output from the circuit ITRZ S The sum of products of the first data and the second data can be calculated from the above. The activation function value is calculated using s[L] neuron output signal z s[L] (L) It can be said that:

[0425] The input layer described in this embodiment is a buffer circuit that outputs the input signal to the second layer. It may also function as

[0426] In this embodiment, the transistors included in the arithmetic circuits MAC1 and MAC2 are The case where the transistor is an OS transistor or a Si transistor has been explained. One aspect of the invention is not limited to this. The transistors used are, for example, transistors with semiconductors such as Ge as the active layer, and ZnS A transistor with compound semiconductors such as CdS, GaAs, InP, GaN, and SiGe as the active layer. transistors with carbon nanotubes as the active layer, and transistors with organic semiconductors as the active layer A transistor or the like can be used.

[0427] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0428] (Embodiment 3) In this embodiment, a configuration example of the arithmetic circuit described in the above embodiment and a An example of the structure of an applicable transistor will be described.

[0429] <Configuration example of semiconductor device> The semiconductor device shown in FIG. 19 includes a transistor 300, a transistor 500, and a capacitor element 21A is a cross-sectional view of the transistor 500 in the channel length direction. 21B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 21C is a cross-sectional view of the transistor 500 in the channel width direction. 1 is a cross-sectional view of a transistor 300 in the channel width direction.

[0430] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the off-state current of the transistor 500 is small, it is For example, the transistor Tr1 of the memory cell array CA included in the arithmetic circuit MAC1 1, it is possible to retain written data for a long period of time. In other words, the frequency of refresh operations is low or no refresh operations are required. Therefore, the power consumption of the semiconductor device can be reduced.

[0431] The semiconductor device described in this embodiment includes a transistor 300, a transistor 310, and a transistor 320 as shown in FIG. The transistor 500 has a capacitance element 600. The capacitor 600 is provided above the transistor 300 and the transistor 500. The capacitor element 600 is provided in the arithmetic circuit MAC described in the above embodiment. 1, the capacitance of the memory cell array CA is C1, the capacitance of the circuit OFST is C2, etc. It is possible.

[0432] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the memory cell array CA included in the arithmetic circuit MAC1 described in the above embodiment This can be applied to the transistor Tr12 etc.

[0433] The substrate 311 is a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). It is preferable to do so.

[0434] The transistor 300 is formed by forming a semiconductor region 313 on the upper surface thereof and a channel region thereof as shown in FIG. 21C. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, and This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0435] The transistor 300 may be either a p-channel type or an n-channel type. .

[0436] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Alternatively, the insulating layer 12 may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (gallium aluminum arsenide), or the like. It uses silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 30 may be formed by using GaAs and GaAlAs. 0 stands for HEMT (High Electron Mobility Transistor) ) can also be used.

[0437] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0438] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0439] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0440] The transistor 300 shown in FIG. 19 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the structure and driving method. In the case of a unipolar circuit using only transistors, the structure of transistor 300 is as shown in FIG. The structure of the transistor 500 may be similar to that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail below.

[0441] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0442] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0443] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0444] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0445] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property that prevents hydrogen and impurities from diffusing is used in the area where the capacitor 500 is provided. It is preferable that

[0446] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0447] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0448] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0449] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductors 328 and 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0450] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring board from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0451] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0452] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0453] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0454] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0455] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0456] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0457] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0458] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0459] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0460] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described above. The semiconductor device is not limited to this. Alternatively, the number of wiring layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356 may be provided. Good too.

[0461] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 is made of a material that has a barrier property against oxygen and hydrogen. .

[0462] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. Hydrogen and impurities diffuse from the region where the capacitor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0463] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0464] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0465] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0466] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the film 516 .

[0467] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0468] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0469] Above the insulator 516 is the transistor 500 .

[0470] As shown in FIGS. 21A and 21B, the transistor 500 includes an insulator 514 and an insulator 550. 16, and the conductor 503 disposed so as to be embedded in the insulator 516 and the conductor 503. an insulator 520 disposed on the insulator 520; an insulator 522 disposed on the insulator 520; An insulator 524 is disposed on the insulating layer 522, and an oxide 530a is disposed on the insulating layer 524. and oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are arranged in a parallel relationship. an insulator disposed on the conductive material 542 and having an opening formed therein overlapping the conductive material 542a and the conductive material 542b; 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the formation surface of the oxide 530c. and a conductor 560 disposed on the surface of the insulator 550. do.

[0471] As shown in FIGS. 21A and 21B, the oxide 530a, the oxide 530b, the conductor 5 42a, and an insulator 544 may be disposed between the conductor 542b and the insulator 580. 21A and 21B, the conductor 560 is preferably formed in the insulator 550. The conductor 560a is provided on the side of the conductor 560a, and the conductor 560b is provided so as to be embedded inside the conductor 560a. 21A and 21B, it is preferable to have a conductor 560b. , the insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550. is preferred.

[0472] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0473] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, one embodiment of the present invention is not limited thereto. a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c The transistor 500 may have a layer structure or a stacked structure of four or more layers. Although the conductor 560 has a two-layer structure in the example, one embodiment of the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminate of three or more layers. The transistor 500 shown in FIGS. 19 and 21A is an example. However, the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method. stomach.

[0474] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0475] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the gap formed between the conductor 560 and the conductors 542a and 542b is Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0476] Conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. The threshold voltage of the transistor 500 is controlled by changing them independently without linking them together. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 It is possible to increase the threshold voltage of 00 to be higher than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the conductor 560 This can reduce the drain current when the potential applied to is 0V.

[0477] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0478] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. Although a layered structure is shown, one embodiment of the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.

[0479] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the above-mentioned function (i.e., that is difficult for oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0480] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0481] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. In this case, the conductor 503a is not necessarily provided. However, it may have a laminated structure, for example, titanium or titanium nitride and the above conductive material. It may also be laminated with other materials.

[0482] The insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0483] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. Reliability can be improved.

[0484] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0485] In addition, the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other and subjected to heat treatment. One or more of microwave treatment and RF treatment may be performed. By performing this, water or hydrogen in the oxide 530 can be removed. At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O + The reaction "H" occurs, and some of the hydrogen generated at this time is It combines with oxygen to form H2O, which is then removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may diffuse into the conductor 542a and the conductor 542b. The electrons may be trapped or captured (also called gettered).

[0486] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The microwave treatment may be performed at a pressure of 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0487] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably carried out at a temperature of, for example, 100° C. or higher and 450° C. or lower. The heat treatment is preferably performed at a temperature of 350° C. or higher and 400° C. or lower. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, and oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or nitrogen gas. After heat treatment in an active gas atmosphere, oxidizing gas was added at 10p to compensate for the oxygen that was released. The treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of an oxidizing gas. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0488] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. In other words, "V O +O→null reaction Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in the substance 530 recombines with the oxygen vacancy to form V. O inhibits the formation of H It is possible.

[0489] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0490] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductor 503 is preferably not diffused to the insulator 520 side. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0491] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as (Sr, Sr)TiO3 (BST) are used as single layers or laminated layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film By using a high-k material as the insulator, the transistor behavior can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0492] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Use an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum or hafnium as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use a material such as aluminum aluminate. When formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor 500 from being damaged. The layer functions as a layer that suppresses the intrusion of impurities such as hydrogen from the surrounding area into the oxide 530.

[0493] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0494] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining an insulator with silicon oxide or silicon oxynitride, it is possible to obtain a thermally stable Furthermore, it is possible to obtain the insulator 520 having a laminated structure with a high relative dielectric constant.

[0495] In the transistor 500 shown in FIGS. 21A and 21B, the second layer has a three-layer laminate structure. As the gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, the laminate structure is not limited to the same material, but may be a laminate structure made of different materials. stomach.

[0496] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor It is preferable to use a functional metal oxide. For example, the oxide 530 is In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryl Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, la tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. The In-M-Zn oxide that can be applied as a C-Axis Alignment Oxide (CAAC-OS) is ned Crystalline Oxide Semiconductor), CAC -OS(Cloud-Aligned Composite Oxide Semico The oxide 530 is preferably an In-Ga oxide. , In-Zn oxide, In oxide, etc. may also be used.

[0497] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. When the carrier concentration of the metal oxide is reduced, the impurity concentration in the metal oxide is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, Examples include silicon and silicon dioxide.

[0498] In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. In this case, oxygen vacancies may be formed in the metal oxide. When an oxygen atom is introduced, the oxygen vacancy and hydrogen bond to form V O May form H. V O H is for Donna It functions as a carrier and electrons are generated. It may combine with oxygen to produce electrons, which are carriers. Transistors using metal oxides containing a large amount of silicon tend to be normally on. In addition, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one aspect of the invention, V in oxide 530 O Reduce H as much as possible and use high purity intrinsic or It is preferable that V is substantially intrinsic with high purity. O Metal with sufficiently reduced H To obtain the oxide, impurities such as water and hydrogen must be removed from the metal oxide (dehydration, This is sometimes referred to as oxidation treatment.) and oxygen deficiency is compensated for by supplying oxygen to the metal oxide. It is important to note that this is sometimes referred to as oxygenation treatment. O Impurities such as H are not enough By using a metal oxide that has been reduced to a low level in the channel formation region of a transistor, stable current can be obtained. It can be given a special characteristic.

[0499] The defect where hydrogen has entered the oxygen vacancy can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, metal As a parameter of the oxide, instead of donor concentration, we use the capacitance assuming a state where no electric field is applied. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "energy concentration."

[0500] Therefore, when a metal oxide is used for the oxide 530, the hydrogen in the metal oxide should be as low as possible. Specifically, in the case of metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than 100%. Impurities such as hydrogen are sufficiently reduced. By using this metal oxide in the channel formation region of a transistor, stable electrical characteristics can be achieved. can be granted.

[0501] In addition, when a metal oxide is used for the oxide 530, the metal oxide has a band gap of It is a semiconductor that is intrinsic (also called type I) or substantially intrinsic, and has a channel The carrier concentration of the metal oxide in the formation region is 1×10 18 cm -3 It is preferable that it is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 Less than More preferably, 1×10 13 cm -3 More preferably, it is less than 1 x10 12 cm -3 It is more preferable that the metal oxide in the channel forming region is less than 1000 nm. The lower limit of the carrier concentration of the oxide is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0502] When a metal oxide is used for the oxide 530, the conductors 542a and 542b When the oxide 530 comes into contact with the conductor 542a, the oxygen in the oxide 530 is transferred to the conductor 542a and the conductor 542b. 2b, and the conductors 542a and 542b may be oxidized. The oxidization of the conductors 542a and 542b reduces the conductivity of the conductors 542a and 542b. It is highly likely that the oxygen in the oxide 530 will decrease. The conductors 542a and 542b absorb oxygen in the oxide 530 and diffuse into the oxide 530. This can be rephrased as "to do."

[0503] Furthermore, oxygen in the oxide 530 diffuses into the conductors 542a and 542b, Between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b A different layer may be formed between the conductor 542a and the conductor 542b. Since the conductor 54 also contains a large amount of oxygen, it is presumed that the different layer has insulating properties. The three-layer structure of the conductor 542b, the hetero layer, and the oxide 530b is a metal-insulator structure. -It can be considered as a three-layer structure consisting of semiconductors, and is MIS (Metal-Insulator diodes that are mainly of MIS structure or MIS structure This is sometimes called a joint structure.

[0504] The different layer is formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. For example, the different layers may be a conductor 542a and a conductor 542b and an oxide 542b. 30c, or between the conductor 542a and the conductor 542b and the oxide 530b. and between the conductor 542a and the oxide 530c. be.

[0505] The metal oxide that functions as the channel forming region in the oxide 530 has a band gap It is preferable to use one having a value of 2 eV or more, preferably 2.5 eV or more. The use of metal oxides with wide band gaps reduces the off-state current of transistors. It is possible.

[0506] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from structures formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0507] The oxide 530 has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, it is preferable to use The atomic ratio of element M in the metal oxide used for oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of element M to In is In the oxide 530b, the atomic ratio of the element M to In is preferably larger than that of the element M. In the metal oxide used for the oxide 530a, the atomic ratio of In to the element M is In the metal oxide, the atomic ratio of In to the element M is preferably larger than that of In. , oxide 530c can be oxide 530a or oxide 530b. Things can be used.

[0508] Specifically, the oxide 530a has an atomic ratio of In, Ga, and Zn of In:Ga:Z. Metal oxides with n=1:3:4 or 1:1:0.5 may be used. 0b, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=4:2:3, or 1 In addition, a metal oxide of In, Ga, and Zn may be used as the oxide 530c. The atomic ratio of In:Ga:Zn is 1:3:4, and the atomic ratio of Ga and Zn is Ga:Zn Metal oxides with a ratio of Ga:Zn=2:1 or Ga:Zn=2:5 may be used. As a specific example of the case where c is a laminated structure, the atomic ratio of In, Ga, and Zn is In:Ga Zn=4:2:3 and In:Ga:Zn=1:3:4, and Ga and Zn The atomic ratio of Ga:Zn is 2:1, and the atomic ratio of In, Ga, and Zn is In:Ga:Zn= The atomic ratio of Ga and Zn is 4:2:3, and the atomic ratio of In and Ga is 2:5. The atomic ratio of In to Zn is 4:2:3. and a layered structure with an atomic ratio of Ga to Zn of In:Ga:Zn=4:2:3. do.

[0509] In addition, for example, the ratio of In atoms to the element M in the metal oxide used for the oxide 530a The atomic ratio of In to element M in the metal oxide used for oxide 530b is When the atomic ratio of In, Ga, and Zn in the oxide 530b is In:Ga:Zn = 5:1:6 or nearby, In:Ga:Zn = 5:1:3 or nearby, In:G In-Ga-Zn oxide with a composition of a:Zn=10:1:3 or similar is used. It is possible.

[0510] In addition to the above, the oxide 530b may have a composition of, for example, In:Zn=2: 1 composition, In:Zn=5:1 composition, In:Zn=10:1 composition, any of these Metal oxides having compositions close to one another can be used.

[0511] These oxides 530a, 530b, and 530c are formed by the above atomic ratio. For example, oxide 530a and oxide 530c are preferably mixed together. The metal oxides and oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to the composition The compound 530b has a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition in the vicinity thereof. It is preferable that the metal oxide has the following composition. The atomic ratio in the oxide 530 By increasing the ratio of In in the composition of b, the on-current or field effect of the transistor can be improved. This is preferable because it can increase the mobility and the like.

[0512] The energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of oxide b. The electron affinity of oxide 530a and oxide 530c is smaller than that of oxide 530b. It is preferable that:

[0513] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower conduction band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 The interface between oxide 530a and oxide 530b, and the interface between oxide 530b and oxide 530c are It is preferable to lower the defect level density of the resulting mixed layer.

[0514] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0515] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0516] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use an alloy of tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride have low resistance to hydrogen or oxygen. It is preferable because it has barrier properties.

[0517] 21A and 21B, the conductor 542a and the conductor 542b have a single-layer structure. However, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be used. Alternatively, a titanium film and an aluminum film may be stacked. Two-layer structure with aluminum film laminated on stainless steel film, copper-magnesium-aluminum alloy Two-layer structure with copper film laminated on top of titanium film, two-layer structure with copper film laminated on top of titanium film, tungsten film A two-layer structure may be formed by laminating a copper film on top.

[0518] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A three-layer structure in which a titanium film or a copper film is laminated and a titanium film or a titanium nitride film is further formed on top of that. Molybdenum film or molybdenum nitride film and a An aluminum film or a copper film is laminated on top of it, and a molybdenum film or a molybdenum nitride film is further laminated on top of it. There are three-layer structures that form a transparent film. Transparent conductive materials may also be used.

[0519] As shown in FIG. 21A, the oxide 530 is formed of the conductor 542a (conductor 542b). At the interface and its vicinity, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a functions as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between 3a and region 543b.

[0520] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are In such a case, a metal compound layer containing the component may be formed in the region 543a (region The carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. become.

[0521] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the oxide 542a and the conductor 542b. 30 and may be provided so as to be in contact with the insulator 524.

[0522] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Smoke, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc. may be used. Alternatively, silicon nitride oxide or silicon nitride may be used as the insulator 544. You can be there.

[0523] In particular, the insulator 544 may be an oxide of aluminum or hafnium, or both. Insulators including aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use an oxide containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. This is preferable because it is difficult to crystallize during the treatment. If b is a material that is resistant to oxidation or does not significantly decrease in conductivity even when it absorbs oxygen, it is an insulating material. The insulator 544 is not an essential component and may be appropriately designed depending on the desired transistor characteristics. stomach.

[0524] By including the insulator 544, impurities such as water and hydrogen contained in the insulator 580 are converted into acids. The oxide 530c is prevented from diffusing into the oxide 530b through the insulator 550. In addition, the excess oxygen contained in the insulator 580 can prevent the conductor 560 from being oxidized. It is possible.

[0525] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is disposed in contact with the inside (top and side surfaces) of the insulating member 550. Similar to the insulator 524, an insulator containing excess oxygen and releasing oxygen when heated is used. It is preferable to form it using a

[0526] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0527] An insulator that releases oxygen when heated is used as the insulator 550, and is placed on the top surface of the oxide 530c. By providing the oxide 530b in contact with the insulator 550, the oxide 530c passes through the oxide 530b. In addition, oxygen can be effectively supplied to the channel forming region of the insulator 524. In addition, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0528] In addition, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, A metal oxide may be provided between the insulating material 550 and the conductor 560. It is preferable to suppress the diffusion of oxygen from the body 550 to the conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, it is possible to suppress the decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. Any material that can be used for the insulator 544 may be used.

[0529] Note that the insulator 550 may have a stacked structure similar to the second gate insulating film. As transistors become smaller and more highly integrated, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film is made of high-k material. By using a laminated structure of a thermally stable material and a thin film of a thin film, It is possible to reduce the gate potential during transistor operation. It may have a laminated structure.

[0530] The conductor 560 functioning as the first gate electrode has a two-layer structure in FIGS. 21A and 21B. However, it may have a single layer structure or a laminated structure of three or more layers.

[0531] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the conductor 56. Oa has the function of suppressing oxygen diffusion, so the oxygen contained in the insulator 550 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium, ruthenium oxide, or the like as the conductor 560a. An oxide semiconductor that can be used for the oxide 530 can be used. In that case, the conductor 560 By forming the conductive layer 560b by sputtering, the electrical resistance of the conductive layer 560a is reduced, and the conductive layer 560b is This is called an OC (Oxide Conductor) electrode. can be done.

[0532] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. A conductive material containing rubber as a main component can be used. For example, it may be a laminated structure of titanium or titanium nitride and the above conductive material. stomach.

[0533] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. Preferably, the insulator 580 has an excess oxygen region. For example, the insulator 58 0, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material contains silicon, silicon oxide having pores, or resin. Silicon nitride and silicon oxynitride are preferred because they are thermally stable. However, silicon oxide with vacancies can easily form excess oxygen regions in later processes. This is preferable because it can

[0534] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. The oxide 530 can be efficiently supplied through the insulator 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0535] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is inserted through the opening in the insulator 580 and the conductor 542a and the conductor 542b. It is formed so as to be embedded in the region sandwiched between 542b.

[0536] In miniaturizing semiconductor devices, it is required to shorten the gate length. It is necessary to prevent the conductivity of the conductor 60 from decreasing. In this embodiment, the conductor 560 may have a shape with a high aspect ratio. The conductor 560 is provided so as to be embedded in the opening of the insulator 580. Even a shape with a high ratio can be formed without causing the conductor 560 to collapse during the process. Cut.

[0537] The insulator 574 is connected to the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. The insulator 574 is preferably provided in contact with the , insulator 550, and insulator 580 can be provided with excess oxygen regions. Oxygen can be supplied into the oxide 530 from the excess oxygen region.

[0538] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from the group consisting of ammonium, cadmium, and ammonium can be used. .

[0539] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier to impurities such as hydrogen. It can also function as a membrane.

[0540] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen. It is preferably reduced.

[0541] In addition, the openings formed in the insulators 581, 574, 580, and 544 Conductor 540a and conductor 540b are placed in the opening. The conductors 540a and 540b are provided facing each other with the conductor 560 in between. It has the same structure as the conductor 546 and the conductor 548 described later.

[0542] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material. The insulator 582 may be made of the same material as the insulator 514. For example, aluminum oxide may be used. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0543] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0544] An insulator 586 is provided on the insulator 582. The insulator 586 is The same materials as those of 320 can be used. In addition, these insulators have a relatively low dielectric constant. By using insulating materials, it is possible to reduce the parasitic capacitance that occurs between wiring. The edge 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0545] Also, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator The edge 574, the insulator 581, the insulator 582, and the insulator 586 are provided with the conductor 546 and Conductors 548 and the like are embedded.

[0546] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or the transistor The conductor 546 functions as a plug or wiring that connects to the transistor 300. The conductor 548 can be formed using the same material as the conductor 328 and the conductor 330. Cut.

[0547] After the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By encasing the transistor 500 in the insulator with high barrier properties, moisture, In addition, it is possible to prevent hydrogen from penetrating the transistors 500. The whole may be wrapped in an insulator that has high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, the insulator 514 or the insulator An opening is formed that reaches the insulator 522, and the above-mentioned barrier is formed so as to contact the insulator 514 or the insulator 522. If a highly flexible insulator is formed, the manufacturing process of the transistor 500 can be performed simultaneously. In addition, examples of insulators with high barrier properties against hydrogen or water include The same material as the insulator 522 may be used.

[0548] Next, a capacitor 600 is provided above the transistor 500. 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0549] Moreover, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 12 functions as a plug or wiring that connects to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The body 610 can be formed simultaneously.

[0550] The conductor 612 and the conductor 610 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film) Indium tin oxide, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It is also possible.

[0551] In FIG. 19, the conductor 612 and the conductor 610 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties and high adhesion to highly conductive conductors A thin conductor may be formed.

[0552] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0553] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0554] By using this structure, a semiconductor device using a transistor having an oxide semiconductor This can suppress the fluctuation of electrical characteristics and improve reliability. In semiconductor devices using transistors having compound semiconductors, miniaturization or high integration is being attempted. It is possible.

[0555] Next, another example of the structure of an OS transistor will be described, which is shown in FIGS. 19 and 20. 22A and 22B are modifications of the transistor 500 shown in FIGS. 21A and 21B. 22A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 22B is a cross-sectional view of the transistor 500 in the channel length direction. 22A and 22B are cross-sectional views in the channel width direction of the transistor 500. The structure of the transistor 300 is different from that of other transistors included in the semiconductor device of one embodiment of the present invention. can also be applied.

[0556] The transistor 500 having the configuration shown in FIGS. 22A and 22B has an insulator 402 and an insulator 40 21A and 21B. An insulator 552 is provided in contact with the side surface of the conductor 540a, and an insulator 552 is provided in contact with the side surface of the conductor 540b. The provision of the insulator 552 is different from the transistor 500 having the configuration shown in FIGS. 21A and 21B. Furthermore, the absence of the insulator 520 is different from the transistors shown in FIGS. 21A and 21B. It is different from the Jista 500.

[0557] The transistor 500 having the configuration shown in FIGS. 22A and 22B has an insulator 40 on an insulator 512. 2 is provided. Insulator 404 is provided on insulator 574 and on insulator 402. It is being done.

[0558] In the transistor 500 having the configuration shown in FIGS. 22A and 22B, the insulators 514 and 51 6, insulator 522, insulator 524, insulator 544, insulator 580, and insulator 574 are provided. The insulator 404 covers these. , the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, and the side surface of the insulator 544 , the side of the insulator 524, the side of the insulator 522, the side of the insulator 516, the side of the insulator 514 , and the top surface of the insulator 402. As a result, the oxide 530 and the like are in contact with the top surface of the insulator 404. and is isolated from the outside by an insulator 402.

[0559] The insulators 402 and 404 are made of at least hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, the insulator 402 and the insulator 403 have a high function of suppressing the diffusion of water molecules. The insulator 404 is made of silicon nitride or silicon nitride oxide, which has a high hydrogen barrier property. It is preferable to use a material such as a silicon dioxide film, which prevents hydrogen and other impurities from diffusing into the oxide 530. Therefore, the deterioration of the characteristics of the transistor 500 can be suppressed. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0560] The insulator 552 includes the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 574. The insulator 552 is provided in contact with the insulator 544. The insulator 552 has a function of suppressing the diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of a material with a high hydrogen barrier property. Insulators such as silicon nitride, aluminum oxide, or silicon nitride oxide can be used. In particular, silicon nitride is a material with high hydrogen barrier properties, and is therefore suitable as the insulator 552. By using a material with a high hydrogen barrier property as the insulator 552, Impurities such as water or hydrogen pass through the insulator 580 and the like and the conductors 540a and 540b. In addition, the diffusion of the silicon dioxide into the oxide 530 can be suppressed. This can prevent oxygen from being absorbed by the conductors 540a and 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0561] FIG. 23 shows a transistor 500 and a transistor 300 in the configuration shown in FIGS. 22A and 22B. 5 is a cross-sectional view showing a configuration example of a semiconductor device in which a conductive material 546 is formed on a side surface thereof. , an insulator 552 is provided.

[0562] Also, the transistor 500 shown in FIGS. 22A and 22B may be used as a transistor For example, the transistor 500 in FIGS. 22A and 22B may be modified as follows: As a result, the transistor shown in FIG. 24 can be obtained. FIG. 24A shows the channel of the transistor. 24A is a cross-sectional view in the channel length direction of the transistor, and FIG. 24B is a cross-sectional view in the channel width direction of the transistor. In the transistor shown in FIGS. 24A and 24B, the oxide 530c is formed by the oxide 530c1 and the oxide 530c2. 22A and 22B in that it has a two-layer structure of the substrate 530c2.

[0563] The oxide 530c1 is formed on the top surface of the insulator 524, the side surface of the oxide 530a, and the side surface of the oxide 530b. The top surface and side surfaces, the side surfaces of the conductors 542a and 542b, the side surfaces of the insulator 544, and the insulating The oxide 530c2 contacts the side of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0564] The oxide 530c1 may be, for example, an In-Zn oxide. When the oxide 530c has a single layer structure, the oxide 530c can be used as the material 530c2. For example, the oxide 530c2 may be made of a material similar to the material that can be used for the oxide 530c2. n:Ga:Zn=1:3:4 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or G A metal oxide having an atomic ratio of a:Zn=2:5 can be used.

[0565] By forming the oxide 530c into a two-layer structure of the oxide 530c1 and the oxide 530c2, In this case, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be used as a power MOS transistor, for example. Note that the oxide 530c of the transistor having the structure shown in FIGS. The oxide 530c1 and oxide 530c2 may also have a two-layer structure.

[0566] The transistors having the configurations shown in FIGS. 24A and 24B may be the same as the transistors shown in FIGS. 19 and 20. The transistor 300 can be applied to the above-mentioned As described above, the memory cell array C included in the arithmetic circuit MAC1 etc. described in the above embodiment A transistor Tr12. The transistors are the transistors 300 and 500 included in the semiconductor device of one embodiment of the present invention. The present invention can also be applied to transistors other than those mentioned above.

[0567] FIG. 25 shows a transistor 500 having the configuration shown in FIG. 21A. 24A is a configuration example of a semiconductor device in which the transistor 300 has the configuration shown in FIG. 23, an insulator 552 is provided on the side of the conductor 546. As shown in FIG. 25, the semiconductor device of one embodiment of the present invention has a transistor Both transistor 300 and transistor 500 are OS transistors, while transistor 300 and transistor 500 can be configured differently.

[0568] Next, a capacitive element that can be applied to the semiconductor device of FIGS. 19 and 20 will be described.

[0569] 26A to 26C show one example of a capacitance element 600 that can be applied to the semiconductor device shown in FIG. As an example, a capacitor element 600A is shown. FIG. 26A is a top view of the capacitor element 600A. FIG. 26B is a perspective view showing a cross section of the capacitance element 600A taken along the dashed line L3-L4. FIG. 26C is a perspective view showing a cross section of the capacitance element 600A taken along the dashed line W3-L4. be.

[0570] The conductor 610 serves as one of a pair of electrodes of the capacitor 600A, and the conductor 620 serves as The insulator 630 functions as the other of the pair of electrodes of the capacitor 600A. It functions as a dielectric sandwiched between the electrodes.

[0571] The insulator 630 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, nitride Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The insulating layer may be formed of a single layer or a multilayer structure.

[0572] For example, the insulator 630 may be made of a material with high dielectric strength, such as silicon oxynitride. A laminated structure with a high dielectric constant (high-k) material may also be used. 600A has a high dielectric constant (high-k) insulator, ensuring sufficient capacity. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the capacitance element 600A is Destruction can be suppressed.

[0573] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, or oxide nitrides having silicon and hafnium Nitrides containing fluorine are also included.

[0574] Alternatively, the insulator 630 may be, for example, aluminum oxide, hafnium oxide, or tantalum oxide. , zirconium oxide, lead zirconate titanate (PZT), strontium titanate (Sr Insulators containing high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST) For example, when the insulator 630 is a laminate, the insulating material may be a silicon dioxide. a three-layer laminate in which zirconium, aluminum oxide, and zirconium oxide are formed in this order; Zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide, In addition, the insulator 630 may be a four-layer laminate in which the following layers are formed in order. Compounds containing tungsten and zirconium may also be used. As integration density increases, the gate insulator and the dielectric used in the capacitor element become thinner, resulting in a This can cause problems such as leakage current in transistors and capacitors. By using high-k materials as insulators that function as dielectrics for the capacitor elements, While maintaining the thickness of the film, the gate potential during transistor operation is reduced and the capacitance of the capacitor element is reduced. It becomes possible to secure it.

[0575] The capacitance element 600 is connected to the conductor 546 and the conductor 548 below the conductor 610. Electrical conductors 546 and 548 are electrically connected to other circuit elements. 26A to 26C, the conductor 546 functions as a plug or wiring. , conductor 548 are collectively referred to as conductor 540.

[0576] 26A to 26C, for clarity, the conductor 546 and the conductor 5 48 is embedded in the insulator 586, and the insulator covering the conductor 620 and the insulator 630. The edge member 650 is omitted.

[0577] The capacitor element 600 shown in FIGS. 19, 20, and 26A to 26C is a planar type. However, the shape of the capacitive element is not limited to this. For example, the capacitive element 600 may be any of the capacitors shown in FIGS. A cylindrical capacitive element 600B shown in FIG. 27C may also be used.

[0578] FIG. 27A is a top view of the capacitance element 600B, and FIG. 27B is a dashed line view of the capacitance element 600B. 27C is a cross-sectional view taken along the dashed line W3-L4 of the capacitance element 600B. FIG.

[0579] In FIG. 27B, a capacitive element 600B is formed by an insulator 58 having a conductor 540 embedded therein. 6, an insulator 631 having an opening, and an insulator 651 which functions as one of a pair of electrodes. The pair of electrodes includes a conductor 610 that functions as the other of the pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0580] Also, in FIG. 27C, for clarity, the insulators 586, 650, and The body 651 and are omitted.

[0581] The insulator 631 can be formed using, for example, a material similar to that of the insulator 586.

[0582] In addition, the insulator 631 is filled with a conductor 611 so as to be electrically connected to the conductor 540. The conductor 611 is made of the same material as the conductors 330 and 518, for example. It can be used.

[0583] The insulator 651 can be formed using, for example, a material similar to that of the insulator 586.

[0584] As described above, the insulator 651 has an opening that overlaps with the conductor 611. is doing.

[0585] The conductor 610 is formed on the bottom and side of the opening. 10 overlaps the conductor 611 and is electrically connected to the conductor 611.

[0586] The conductor 610 can be formed by etching the insulator 651. A mouth is formed, and then a conductor 610 is formed by sputtering, ALD, or the like. Then, CMP (Chemical Mechanical Polishing) The conductor 610 is left in the opening by a method such as a method of forming a film on the insulator 651. The conductor 610 can then be removed.

[0587] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor.

[0588] The conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled. There are.

[0589] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0590] The cylindrical capacitive element 600B shown in FIGS. 27A to 27C is a planar capacitive element. The capacitance value can be made higher than 600 A. By applying the capacitance element 600B as the capacitance C1, capacitance C2, etc. described in the embodiment, This allows the voltage across the capacitor to be maintained for a long period of time.

[0591] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0592] (Fourth embodiment) In this embodiment, the semiconductor device can be used for the OS transistor described in the above embodiment. CAC-OS (Cloud-Aligned Composite Silicon) is a metal oxide Oxide Semiconductor), and CAAC-OS(c-axis Al Ignition Crystalline Oxide Semiconductor This section explains the composition of the system.

[0593] <Metal oxide composition> CAC-OS or CAC-metal oxide is a material that has the function of conductivity in some parts. The material has an insulating function in part and a semiconductor function in the whole. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used, the conductive function is the function of allowing electrons (or holes) to flow as carriers, and the insulating function is the function of allowing electrons (or holes) to flow as carriers. The insulating function is the function of preventing the flow of electrons that act as carriers. By making these functions work complementarily, the switching function (On / Off) The function of making it possible to make CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, each function is separated. By combining these, the functions of both can be maximized.

[0594] In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region are formed at the nanoparticle level in the material. The conductive and insulating regions may be separated by a thin film. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0595] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and an insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0596] In addition, CAC-OS and CAC-metal oxide have different band gaps. For example, CAC-OS or CAC-metal oxide e is a component with a wide gap due to the insulating region and a narrow gap due to the conductive region. In this configuration, when a carrier is flowed, In the component with a narrow gap, carriers mainly flow. The component having a narrow gap acts complementary to the component having a wide gap. Carriers also flow to the wide gap component in conjunction with the CA component. C-OS or CAC-metal oxide is used for the channel formation region of the transistor. When the transistor is turned on, the transistor has a high current driving capability, i.e., a large on-state current. High field effect mobility can be obtained.

[0597] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called atrix composite.

[0598] <Metal oxide structure> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS and polycrystalline oxide semiconductors. , nc-OS(nanocrystalline oxide semiconductor or), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

[0599] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. 28A. FIG. 28A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides.

[0600] As shown in Figure 28A, IGZO can be broadly divided into amorphous and It is classified into Crystalline and Crystal. , Amorphous includes completely amorphous Also, some Crystalline products use CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (C Crystal The classification of ine includes single crystal, poly crystal, and Completely amorphous crystals are excluded. Includes single crystal and poly crystal.

[0601] The structure within the bold frame in Figure 28A is amorphous and crystalline. It is an intermediate state between crystalline and noncrystalline, and is a new boundary region (New crystalline The structure belongs to the Amorphous and Crystal phases. al. That is, the structure is in the boundary region between the energetically unstable Amor It can be said that the structure is completely different from amorphous or crystal. can be done.

[0602] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). Here, the quartz glass and Crystal XRD scan of IGZO (also called crystalline IGZO) with a crystal structure classified as ine The spectra are shown in Figures 28B and 28C. Figure 28B shows quartz glass, and Figure 28C shows crystalline. The XRD spectrum of IGZO. The composition of the crystalline IGZO shown in Figure 28C is I The atomic ratio of n:Ga:Zn is approximately 4:2:3. The thickness of the ZO is 500 nm.

[0603] As shown by the arrow in FIG. 28B, the shape of the peak in the XRD spectrum of the quartz glass is almost the same as that of the On the other hand, as shown by the arrow in Figure 28C, crystalline IGZO has a The shape of the peak in the XRD spectrum is asymmetric. In other words, the shape of the peak in the XRD spectrum is If it is not symmetrical, it cannot be said to be amorphous. =31° or nearby, and specify the crystal phase (IGZO crystal phase) The reason for the asymmetric shape of the peak in the XRD spectrum is that the crystal phase It is presumed that this is due to microcrystals.

[0604] Specifically, in the XRD spectrum of crystalline IGZO shown in FIG. 28C, The crystallites have a peak at or near 2θ=31°. When the oxide semiconductor film is evaluated from an X-ray diffraction image, as shown in FIG. In addition, the spectrum width on the lower angle side becomes wider than the peak at or near 2θ=34°. This is because the oxide semiconductor film contains microcrystals with a peak at or near 2θ=31°. This suggests that there is.

[0605] The crystalline structure of the film was also investigated by nano-beam electron diffraction (NBED). Diffraction patterns observed by electron microdiffraction (electron microdiffraction) The IGZ film formed at room temperature was The diffraction pattern of the IGZO film is shown in Figure 28D. Zn=1:1:1 [atomic ratio] oxide target was used for sputtering. In the ultrafine electron beam diffraction method, the probe diameter is set to 1 nm, and the electron beam diffraction was held.

[0606] As shown in Figure 28D, the diffraction pattern of the IGZO film formed at room temperature shows a halo rather than a Therefore, the IGZO film formed at room temperature is in a crystalline state. It is neither an amorphous state nor an amorphous state, but an intermediate state, and it cannot be concluded that it is an amorphous state. It is estimated that this is not possible.

[0607] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0608] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In CAAC-OS, clear grain boundaries (grain boundaries) are observed even near the strain. It is not possible to confirm the grain boundary (also called grain boundary distortion) due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high SiO2 content in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by, for example, increasing the thickness.

[0609] The crystal structure in which clear grain boundaries are confirmed is called multi-crystal structure. The grain boundaries act as recombination centers, and carriers This may result in a decrease in the on-state current of the transistor or a decrease in the field-effect mobility. Therefore, the CAAC-OS, which does not have clear grain boundaries, is suitable for transistors. CAAC-OS is one of the crystalline oxides with a crystal structure suitable for semiconductor layers. For example, In-Zn oxide and In- Ga—Zn oxide is more suitable than In oxide because it can suppress the generation of grain boundaries.

[0610] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure consisting of layers containing M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). (also called layer structure). Indium and element M are mutually substitutable. When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) layer Also, when indium in the In layer is substituted with element M, (In,M) It can also be expressed as a layer.

[0611] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries occurs. In addition, the crystallinity of oxide semiconductors can be affected by impurities and defects. Therefore, CAAC-OS is an oxidized material with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is designed to withstand the high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for an OS transistor, This allows for greater freedom.

[0612] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0613] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has pores or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS.

[0614] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductors in The compound may have two or more of the c-OS and CAAC-OS.

[0615] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0616] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0617] In addition, an oxide semiconductor with a low carrier concentration is preferably used for the transistor. When the carrier concentration of the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is In this specification and the like, the impurity concentration is low, and the defect level density is low. A low defect level density is sometimes referred to as high purity intrinsic or substantially high purity intrinsic. It may also be referred to as true or substantially true.

[0618] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0619] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. This may be the case.

[0620] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, it is effective to reduce It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0621] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0622] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, they are oxidized. Defect levels are formed in semiconductors, which is why defects in silicon and carbon in oxide semiconductors The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (concentration obtained by SIMS) was 2 × 10 18 atoms / cm 3 The following is preferably is 2 x 10 17 atoms / cm 3 The following applies.

[0623] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may be included. Transistors using oxide semiconductors, which are widely used in semiconductors, tend to be normally on. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, the alkali metal or alkali metal in the oxide semiconductor obtained by SIMS The concentration of earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 at oms / cm 3 Do the following:

[0624] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor becomes a semiconductor. Therefore, the transistor used in the oxide semiconductor tends to be normally on. In this case, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The concentration is 5×1019 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Below, More preferably 5×10 17 atoms / cm 3 The following applies.

[0625] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Less than.

[0626] By using an oxide semiconductor with sufficiently reduced impurities for a channel formation region of a transistor, This makes it possible to impart stable electrical properties.

[0627] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do. [Example]

[0628] In this embodiment, in the memory cell AM of the arithmetic circuit MAC1 described in the second embodiment, To check whether the product of the first data and the second data is calculated properly, A prototype was constructed and various measurements and calculations were carried out.

[0629] <Measurements and Calculations> The multiplication circuit AME shown in FIG. 29A is a part of an arithmetic circuit that was actually fabricated as a prototype. This corresponds to the memory cell AM of the arithmetic circuit MAC1 described in the second embodiment. The transistor M1 and the capacitor CP included in E are the same as those in the memory cell AM shown in FIG. This corresponds to the transistor M1 and the capacitor C1 included in the multiplication circuit AME. The transistors M2-1 and M2-2 are included in the memory cell AM shown in FIG. This corresponds to the transistor M2 included in the The gates of the transistors M2-2 are electrically connected in series, and the gates of the transistors M2-2 are electrically connected to each other. In this embodiment, the transistors M2-1 and M2-2 are collectively referred to as transistors 29A corresponds to the wiring BL in FIG. The wiring BW shown in FIG. 29A corresponds to the wiring WD in FIG. 9, and the wiring VX shown in FIG. 29A corresponds to the wiring C in FIG. 9. 9. The wiring WW shown in FIG. 29A corresponds to the wiring WL in FIG.

[0630] Furthermore, the transistor M1 included in the multiplication circuit AME has a back gate, The back gate is electrically connected to a wiring BG.

[0631] The transistor M1 is an OS transistor containing an In-Ga-Zn oxide in the channel formation region. The channel length of the transistor M1 (hereinafter referred to as L length) is The thickness is set to 0.35 μm, and the channel width (hereinafter referred to as W length) is set to 0.35 μm. The transistor M2 is a Si transistor containing single crystal silicon in the channel forming region. The L length of transistors M2-1 and M2-2 is set to 8 μm. The W length is set to 0.32 μm.

[0632] FIG. 29B shows a cell array with a prototype multiplication circuit AME, photographed using an optical microscope. In the cell array CA3, the multiplication circuit AME is a 9x16 The multiplication circuit AME of the cell array CA3 is arranged in a matrix. The pads EP1 to EP6 are electrically connected to the respective electrode pads. The electrode pad EP1 is electrically connected to the wiring WW, and the electrode pad EP2 is electrically connected to the wiring BW. The electrode pad EP3 is electrically connected to the wiring VX, and the electrode pad EP4 is electrically connected to the wiring BG. The electrode pad EP5 is electrically connected to the wiring VY, and the electrode pad EP6 is electrically connected to the wiring VR.

[0633] In the multiplication circuit AME, the data write, data hold, and data read operations are Each of the actions was performed.

[0634] When writing data to the multiplication circuit AME, connect 5V to the wire WW, 0V to the wire VX, and wire BG. A voltage of -6V was applied to the wire VY, 3V to the wire VR, and 0V to the wire VR. The data includes a voltage V range of 0V to 2.5V in increments of 0.1V. Wand the potential is Given from line BW.

[0635] When the data written to the multiplication circuit AME is held, the wire WW is set to 0V and the wire BW is set to 0 V, wiring VX is 0V, wiring BG is -6V, wiring VY is 0V, wiring VR is 0V, and multiplication A voltage was applied to the circuit AME.

[0636] When reading the data written from the multiplication circuit AME, 0V is applied to the wire WW and 0V is applied to the wire BW. A voltage of 0V was applied to the wiring BG, -6V to the wiring VY, and 0V to the wiring VR. The potential VX is set to a value in the range of 0V to 3.0V in increments of 0.1V. X It was decided.

[0637] In the multiplication circuit AME, write operation, data retention, and read operation are performed. When this happens, the wiring WW, wiring BW, wiring VX, wiring BG, wiring VY, and wiring VR are The applied potentials are summarized in the table below.

[0638] [Table 2]

[0639] When reading the data written to the multiplication circuit AME, the data is transferred from the wiring VY to the The current flowing through the wiring VR via the source-drain of the transistor M2 was measured.

[0640] Figure 30A shows the potential V W and potential V X and source-drain current I DS (V W , V X )'s characteristics From Figure 30A, V X is fixed at an arbitrary potential, and V W By increasing I mean, IDS (V W , V X ) increased. W Increasing This corresponds to shifting the threshold of M2 to the negative side. W is fixed at an arbitrary potential, V X By increasing I DS (V W , V X ) was found to increase. V W is set to 1.5V, and V X When is set to 1.5V, I DS (V W , V X ) is approximately 1.3μ It was estimated as A.

[0641] where V W0 is set to 1.5V, and V X0 If is 1.5V, then I DS (V W0 , V X0 ) = 1.3μA. Furthermore, V W0 The voltage change is ΔV W When I DS ( V W0 +ΔV W , V X0 ), V X0 The voltage change is ΔV X When I DS (V W0 , V X0 +ΔV X ), and V W0 The voltage change is ΔV W Given V X0 The voltage change is ΔV X When I DS (V W0 +ΔV W , V X0 +ΔV X )of And ΔI yis defined as follows:

[0642]

number

[0643] In addition, V W0 +ΔV W is the voltage given by the wiring BW, so ΔV W Voltage range The range is between -1V and 1V. X0 +ΔV X is the voltage given by the wiring BW Therefore, ΔV X The voltage range is between -1.5V and 1.5V.

[0644] Then, using equations (E1), (E2), (E7), and (E8), ΔI y Calculate Then the formula becomes as follows:

[0645]

number

[0646] Here, by setting k to 1 / 2 (normalizing it to an appropriate value), ΔI y and ΔV W and ΔV X The relationship between ΔV and ΔV can be expressed in FIG. W and ΔV X Product of Depending on y Therefore, the multiplication circuit AME is used to The current flowing between the source and drain of the transistor M2 is I DS (V W0 , V X0 ), I DS ( V W0 +ΔV W , V X0 ), I DS (V W0, V X0 +ΔV X ), I DS (V W0 +ΔV W , V X0 +ΔV X ) and calculate the difference current ΔI y Calculate By doing so, ΔV W and ΔV X The product can be found.

[0647] Figure 31 shows the results of the multiplication circuit AME under the temperature conditions of 85°C, 27°C, and -40°C. 0.5V (ΔV W =-1.0V), 2.5V(ΔV W (=1.0V) The temperature dependence of the read current obtained by writing a value and then performing a read operation. As can be seen from Figure 31, the slope at 85°C is 40% higher than at 27°C. At -40°C, the slope was reduced by 30%. The results for each case at 0°C show the temperature dependence of the saturated mobility. Although the slopes are different, each ΔV W ΔI in y and ΔV X The correlation with By properly normalizing the correlation according to the temperature, the slope can be easily corrected. It is thought that this can be done.

[0648] 32A and 32B show the state of the transistor M after storing data at the node NM. 32A is a graph showing the change over time in the amount of current flowing between the source and drain of the transistor 2. As a fixed condition, ΔV X is set to 1.0 V (the potential of the wire VX is set to 2.5 V), and the measurement As a fixed condition, ΔV Xwas set to -1.0 V (the potential of the wiring VX was set to 0.5 V). In each of FIGS. 32A and 32B, the potential held at the node NM is set to 0.5 V (ΔV W =- 1.0V), 1.0V(ΔV W =-0.5V), 1.5V(ΔV W =0V), 2.0V( ΔV W =0.5V), 2.5V(ΔV W = 1.0V) for each of the four conditions. In this case, the current I flows between the source and drain of the transistor M2. y was measured.

[0649] As shown in Figures 32A and 32B, 1.0 x 10 2 seconds to 1.0 x 10 5 Within seconds Under each condition, the current I flows between the source and drain of transistor M2. y but The results showed no change. Note that under each condition in Figure 32A, 5 seconds The differential current ΔI y The rate of change was less than 4.8%. In this case, 1.08 x 10 5 Differential current ΔI up to seconds y The rate of change was less than 4%.

[0650] FIG. 33A shows that 0.5V (ΔV W =-1.0V), 1. 0V(ΔV W =-0.5V), 2.0V(ΔV W =0.5V), 2.5V(ΔV W =1. 0V), and then write the differential current ΔI y The multiplication obtained by reading 33A is a graph showing the multiplication characteristics of the circuit AME. ΔIy =1.0×V X , ΔI y =0.5×V X , ΔI y =-0.5×V X , ΔI y =-1 .0×V X From FIG. 33A, the multiplication circuit AME The calculation results are ΔI y =1.0×V X , ΔI y =0.5×V X , ΔI y =-0.5×V X , ΔI y =-1.0×V X It was found that the results roughly matched the linear functions of

[0651] FIG. 33B shows that 0.5V (ΔV W =-1.0V), 1. 0V(ΔV W =-0.5V), 2.0V(ΔV W =0.5V), 2.5V(ΔV W =1. 0V) and then perform a read operation. 33B is a graph showing the degree of variation in the writing. V X is set to 1.0V (the potential of the wiring VX is set to 2.5V). After that, a read operation is performed to obtain the differential current ΔI y Repeat the calculation 50 times and take the average of the 50 times. The ΔV W The differential current ΔI y This was set as one set, and each ΔI W About 50 sets Minute differential current ΔI y Measurements were carried out.

[0652] In FIG. 33B, the horizontal axis represents the differential current ΔIy The vertical axis shows the cumulative frequency. From Figure 33B, the variation in data writing is generally in the range of -0.4% to 0.4%. It fits within.

[0653] In addition, for the 12 multiplier circuits AME, 0.5V (ΔV W =-1.0V), 1.0V(ΔV W =-0.5V), 2.0V(ΔV W =0.5V), 2 .5V(ΔV W =1.0V) was written, the data read from each multiplier circuit AME ΔI y The degree of element variation is shown in Figure 34. W Δ in V X From Figure 34, it is shown that ΔV X =0 (greater than -0.02 and 0.0 2), ΔI y The element variation of each ΔV W , ΔV X About 5 %. In addition, ΔI y ΔV of element variation X The dependence on , ΔV W This shows a tendency that is independent of the absolute value of ΔI y Variation in elements The causes of this are, for example, variations in the saturation mobility of Si transistors, This is due to the fact that the drain current in the saturation region of It is considered that the contribution of the element variation σ meas is (ΔV W ,ΔV X )=(+1,+1), σ meas =0.023, (ΔV W ,ΔVX )=( +1,-1), σ meas =0.025, (ΔV W ,ΔV X )=(-1,+1) When σ meas =0.034, (ΔV W ,ΔV X )=(-1,-1), σ mea s =0.032.

[0654] Also, ΔI in Figure 34 y To confirm the validity of the cause of the device variation, a Monte Carlo solution The results of the analysis are shown in Figures 35A to 35D. In the circuit configuration of FIG. 29A, (ΔV W ,ΔV X )=(+1,+1), Simulations for (+1,-1), (-1,+1), and (-1,-1) The element variations obtained by the analysis are shown in Figs. Ratsuki σ sim is (ΔV W ,ΔV X )=(+1,+1), σ sim =0.051 , (ΔV W ,ΔV X )=(+1,-1), σ sim =0.038, (ΔV W ,ΔV X )=(-1,+1), σ sim =0.025, (ΔV W ,ΔV X )=(-1,- 1) When σ sim =0.017. The element variation obtained by measurement was σ meas teeth , as shown in Figure 34, it is between 0.023 and 0.034, so it can be obtained by Monte Carlo analysis. Measured element variation σ sim The values ​​are generally consistent, ranging from 0.017 to 0.051. It was confirmed that:

[0655] Next, a three-layer fully connected arithmetic circuit using the cell array CA3 of FIG. 29B is The inference accuracy of the artificial neural network model was calculated. The neural network model is shown in Figure 36. The neural network consists of an input layer, a hidden layer, and The input layer has 784 neurons, the hidden layer has 100 neurons, and the output layer has 784 neurons. The output layer has 10 neurons.

[0656] The neural network is implemented on a computer using the programming language Python. We implemented the neural network and ran it on the handw...

Claims

1. a cell, a first wiring, a second wiring, a third wiring, and a fourth wiring; The cell includes a first transistor, a second transistor, and a capacitance element, the first transistor and the second transistor each include an oxide semiconductor in a channel formation region; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; one of a pair of electrodes of the capacitance element is electrically connected to a gate of the second transistor; the other of the pair of electrodes of the capacitance element is electrically connected to the fourth wiring; an arithmetic circuit having a function of operating the second transistor in a subthreshold region and causing a current corresponding to the product of the weighting coefficient and data to flow between the source and drain of the second transistor;

2. a cell, a first wiring, a second wiring, a third wiring, and a fourth wiring; The cell includes a first transistor, a second transistor, and a capacitance element, the first transistor and the second transistor each include an oxide semiconductor in a channel formation region; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; one of a pair of electrodes of the capacitance element is electrically connected to a gate of the second transistor; the other of the pair of electrodes of the capacitance element is electrically connected to the fourth wiring; a function of holding a potential corresponding to a weighting coefficient in one of a pair of electrodes of the capacitance element; a function of inputting a potential corresponding to data to the fourth wiring; a function of operating the second transistor in a subthreshold region to cause a current corresponding to the product of the weighting coefficient and the data to flow between the source and drain of the second transistor.

3. a cell, a first wiring, a second wiring, a third wiring, and a fourth wiring; The cell includes a first transistor, a second transistor, and a capacitance element, the first transistor and the second transistor each include an oxide semiconductor in a channel formation region; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; one of a pair of electrodes of the capacitance element is electrically connected to a gate of the second transistor; the other of the pair of electrodes of the capacitance element is electrically connected to the fourth wiring; a function of operating the second transistor in a subthreshold region to cause a current corresponding to a weighting coefficient to flow between a source and a drain of the second transistor, and holding a potential corresponding to the weighting coefficient in one of a pair of electrodes of the capacitor; a function of inputting a potential corresponding to data to the fourth wiring; a function of operating the second transistor in a subthreshold region to cause a current corresponding to the product of the weighting coefficient and the data to flow between the source and drain of the second transistor.

4. In any one of claims 1 to 3, A plurality of the cells are included, an arithmetic circuit having a function of adding currents corresponding to the product of the weighting coefficient and the data output from each of the plurality of cells;

5. In any one of claims 1 to 4, The weighting coefficients are analog data or multi-valued data.

6. In any one of claims 1 to 5, The data is analog data or multi-valued data.

7. a first cell, a second cell, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring; the first cell includes a first transistor, a second transistor, and a first capacitance element; the second cell includes a third transistor, a fourth transistor, and a second capacitive element; the first transistor, the second transistor, the third transistor, and the fourth transistor each include an oxide semiconductor in a channel formation region; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; one of a pair of electrodes of the first capacitor element is electrically connected to a gate of the second transistor; the other of the pair of electrodes of the first capacitor is electrically connected to the fourth wiring; a gate of the third transistor is electrically connected to the fifth wiring; one of a source and a drain of the third transistor is electrically connected to the second wiring; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the third wiring; one of a pair of electrodes of the second capacitor is electrically connected to a gate of the fourth transistor; the other of the pair of electrodes of the second capacitor is electrically connected to the sixth wiring; a function of operating the second transistor in a subthreshold region to cause a first current corresponding to a product of a first weighting coefficient and first data to flow between a source and a drain of the second transistor; and a function of operating the fourth transistor in a subthreshold region to cause a second current corresponding to a product of a second weighting coefficient and second data to flow between the source and drain of the fourth transistor.

8. a first cell, a second cell, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring; the first cell includes a first transistor, a second transistor, and a first capacitance element; the second cell includes a third transistor, a fourth transistor, and a second capacitive element; the first transistor, the second transistor, the third transistor, and the fourth transistor each include an oxide semiconductor in a channel formation region; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; one of a pair of electrodes of the first capacitor element is electrically connected to a gate of the second transistor; the other of the pair of electrodes of the first capacitor is electrically connected to the fourth wiring; a gate of the third transistor is electrically connected to the fifth wiring; one of a source and a drain of the third transistor is electrically connected to the second wiring; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the third wiring; one of a pair of electrodes of the second capacitor is electrically connected to a gate of the fourth transistor; the other of the pair of electrodes of the second capacitor is electrically connected to the sixth wiring; a function of holding a potential corresponding to a first weighting coefficient in one of a pair of electrodes of the first capacitor; a function of inputting a potential corresponding to first data to the fourth wiring; a function of holding a potential corresponding to a second weighting coefficient in one of a pair of electrodes of the second capacitor; a function of inputting a potential corresponding to second data to the sixth wiring; a function of operating the second transistor in a subthreshold region to cause a first current corresponding to a product of the first weighting coefficient and the first data to flow between a source and a drain of the second transistor; a function of operating the fourth transistor in a subthreshold region to cause a second current corresponding to a product of the second weighting coefficient and the second data to flow between the source and drain of the fourth transistor.

9. a first cell, a second cell, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring; the first cell includes a first transistor, a second transistor, and a first capacitance element; the second cell includes a third transistor, a fourth transistor, and a second capacitive element; the first transistor, the second transistor, the third transistor, and the fourth transistor each include an oxide semiconductor in a channel formation region; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the second transistor is electrically connected to the second wiring; the other of the source and the drain of the second transistor is electrically connected to the third wiring; one of a pair of electrodes of the first capacitor element is electrically connected to a gate of the second transistor; the other of the pair of electrodes of the first capacitor is electrically connected to the fourth wiring; a gate of the third transistor is electrically connected to the fifth wiring; one of a source and a drain of the third transistor is electrically connected to the second wiring; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the third wiring; one of a pair of electrodes of the second capacitor is electrically connected to a gate of the fourth transistor; the other of the pair of electrodes of the second capacitor is electrically connected to the sixth wiring; a function of operating the second transistor in a subthreshold region to cause a current corresponding to a first weighting factor to flow between a source and a drain of the second transistor, and holding a potential corresponding to the first weighting factor in one of a pair of electrodes of the first capacitor; a function of inputting a potential corresponding to first data to the fourth wiring; a function of operating the fourth transistor in a subthreshold region to cause a current corresponding to a second weighting factor to flow between a source and a drain of the fourth transistor, and holding a potential corresponding to the second weighting factor in one of a pair of electrodes of the second capacitor; a function of inputting a potential corresponding to second data to the sixth wiring; a function of operating the second transistor in a subthreshold region to cause a first current corresponding to a product of the first weighting coefficient and the first data to flow between a source and a drain of the second transistor; a function of operating the fourth transistor in a subthreshold region to cause a second current corresponding to a product of the second weighting coefficient and the second data to flow between the source and drain of the fourth transistor.

10. In any one of claims 7 to 9, The arithmetic circuit, wherein the first weighting coefficient and the second weighting coefficient are analog data or multi-value data.

11. In any one of claims 7 to 10, The arithmetic circuit, wherein the first data and the second data are analog data or multi-value data.

12. In any one of claims 1 to 11, The arithmetic circuit includes an oxide containing indium as the oxide semiconductor.

13. In any one of claims 1 to 12, The subthreshold region is an operating region in which the voltage between the gate and the source of a transistor is lower than the threshold voltage.

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