Liquid crystal display device

Abstract

To provide a liquid crystal display device that is highly mass-producible. A liquid crystal display device includes an opposing substrate, a light-shielding film, a first color filter, and a second color filter. , a third color filter, a counter electrode, and a spacer, and The third color filters are overlapped with each other and are formed on the liquid crystal display with an organic layer that acts as a spacer. The spacer can be formed from the laminate, which is suitable for mass production.

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device using thin film transistors at least in pixel portions. [Background technology]

[0002] In recent years, semiconductor thin films (thickness of about tens to hundreds of nm) formed on substrates with insulating surfaces have been used for The technology of using the thin film transistor in the channel forming region is attracting attention. Transistors are widely used in electronic devices such as ICs and electro-optical devices, especially in image display devices. Development as a switching element is being rushed.

[0003] As a switching element for an image display device, a thin film transistor using an amorphous semiconductor film in the channel formation region is Film transistors, or thin film transistors using polycrystalline semiconductor films in the channel formation region, etc. As a method for forming a polycrystalline semiconductor film, a pulsed excimer laser beam is used. The beam is processed into a linear shape by an optical system, and the linear beam is scanned over the amorphous silicon film to illuminate it. A technique for crystallizing the material by irradiating it with light is known.

[0004] In addition, a microcrystalline semiconductor film is used in a channel formation region as a switching element of an image display device. Thin film transistors that have been used in the prior art are used (Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 4-242724 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-49832 Summary of the Invention [Problem to be solved by the invention]

[0006] A thin film transistor using a polycrystalline semiconductor film in the channel formation region uses an amorphous semiconductor film as the channel. The field-effect mobility is two orders of magnitude higher than that of the thin-film transistor used in the panel formation region, and This has the advantage that the pixel section of the display device and its peripheral driving circuit can be integrally formed on the same substrate. However, compared with the case where an amorphous semiconductor film is used for the channel formation region, The process becomes more complicated due to the crystallization of the film, which reduces yield and increases costs. There is a problem that...

[0007] In addition, there is a problem that the surfaces of the crystal grains in the microcrystalline semiconductor film are easily oxidized. When the crystal grains in the channel formation region are oxidized, an oxide film is formed on the surface of the crystal grains, The oxide film becomes an obstacle to the movement of carriers, and the electrical characteristics of the thin film transistor deteriorate. There is a problem.

[0008] In view of the above-mentioned problems, the present invention provides a thin-film transistor having good electrical characteristics and high reliability. The present invention proposes a liquid crystal display device having a liquid crystal display element and a method for mass-producing the liquid crystal display device. This will be the challenge. [Means for solving the problem]

[0009] In a liquid crystal display device having an inverse staggered thin film transistor, The gate insulating film is formed on the gate electrode, and the channel forming region is formed on the gate insulating film. A microcrystalline semiconductor film (also called a semi-amorphous semiconductor film) that functions as a A buffer layer is formed on the crystalline semiconductor film, and a pair of source and drain regions is formed on the buffer layer. The source and drain regions are formed so as to expose portions of the source and drain regions. A pair of source and drain electrodes are formed in contact with the source region. The source and drain regions are regions in contact with the source and drain electrodes, and regions in contact with the source and drain electrodes. The source electrode and the drain electrode are not in contact with each other. A part of the source region and the drain region and a part of the buffer layer are exposed. The source electrode and the drain electrode are overlapped on the edge of the microcrystalline semiconductor film and the source region and the drain region. In addition, the source and drain regions must not be formed outside the ends of the source and drain electrodes. The edge of the region, as well as the edge of the buffer layer, are formed.

[0010] The edges of the source electrode and the drain electrode do not coincide with the edges of the source region and the drain region, The ends of the source and drain regions are formed outside the ends of the source and drain electrodes. By this, the distance between the ends of the source electrode and the drain electrode becomes larger, It is possible to prevent leakage current and short circuits between the source electrode and the drain electrode. The electric field is not concentrated at the gate electrode and the drain electrode and at the ends of the source and drain regions. This can prevent leakage current between the source electrode and the drain electrode.

[0011] The buffer layer has a recess in a part thereof, and the side surface of the recess and the source region and the drain region are The buffer layer has a recess in a part thereof, and the edge of the source region and the edge of the drain region are aligned. The distance between the source and drain regions is large, so the distance that carriers travel between the source and drain regions is large. Since the length of the gate electrode is long, the leakage current between the source region and the drain region can be reduced.

[0012] In addition, a buffer layer is formed between the microcrystalline semiconductor film and the source and drain regions. The microcrystalline semiconductor film functions as a channel formation region. The semiconductor film is prevented from being oxidized and functions as a high-resistance region. A buffer layer is formed between the source region and the drain region using an amorphous semiconductor film having a high resistivity. For these reasons, the thin film transistor of the present invention has high field effect mobility and In the case of negative gate voltage, the leakage current is small and the drain breakdown voltage is is high.

[0013] The buffer layer may be an amorphous semiconductor film, or may be a film containing nitrogen, hydrogen, or a halogen. It is preferable that the amorphous semiconductor film contains at least one of nitrogen, When the microcrystalline semiconductor film contains either hydrogen or halogen, the crystal grains contained in the microcrystalline semiconductor film It is possible to reduce oxidation.

[0014] The buffer layer can be formed by a plasma CVD method, a sputtering method, or the like. After forming the amorphous semiconductor film, the amorphous semiconductor film is irradiated with nitrogen plasma, hydrogen plasma, or hydrogen plasma. The amorphous semiconductor film can be nitrided, hydrogenated, or halogenated by treating it with halogen plasma. can.

[0015] By providing a buffer layer on the surface of the microcrystalline semiconductor film, the crystal grains contained in the microcrystalline semiconductor film can be Since oxidation can be reduced, deterioration of the electrical characteristics of thin film transistors can be reduced. This can be done.

[0016] Unlike polycrystalline semiconductor films, microcrystalline semiconductor films are formed directly on a substrate as microcrystalline semiconductor films. Specifically, silicon hydride is used as a raw material gas and a plasma CVD apparatus is used. The microcrystalline semiconductor film formed by the above method has a thickness of 0.5 nm to 2 The term "polycrystalline semiconductor" also includes a microcrystalline semiconductor film containing 0 nm crystal grains in an amorphous semiconductor. Unlike when a conductive film is used, there is no need to perform a crystallization process after forming the semiconductor film. The number of steps in manufacturing a film transistor can be reduced, and the yield of liquid crystal display devices can be improved. It is possible to increase the efficiency and reduce costs. The plasma has a high electron density, which facilitates dissociation of silicon hydride, which is the source gas. By using the plasma CVD method using microwaves with a frequency of 1 GHz or more, Compared with microwave plasma CVD methods using frequencies from several tens to several hundreds of MHz, it is possible to easily produce microcrystalline semiconductor films. It can be easily produced and the film formation speed can be increased. This makes it possible to improve the mass productivity of display devices.

[0017] Furthermore, a thin film transistor (TFT) is manufactured using a microcrystalline semiconductor film. The liquid crystal display device is manufactured by using the microcrystalline semiconductor film in the pixel portion and further in the driver circuit. The thin film transistors used in this study have a field effect mobility of 1 to 20 cm 2 / V·sec and amorphous It has a field effect transport that is 2 to 20 times larger than that of thin-film transistors that use semiconductor films in the channel formation region. Therefore, a part or the whole of the driver circuit is formed on the same substrate as the pixel section, and the system A moon panel can be formed.

[0018] The liquid crystal display device includes a liquid crystal element. A panel in a state where the IC including the controller is mounted on the panel. Furthermore, the present invention relates to a method for manufacturing a liquid crystal display device, in which the liquid crystal element is completely The element substrate corresponds to one embodiment before forming the liquid crystal element. Specifically, the element substrate includes only the pixel electrodes of the liquid crystal elements. Alternatively, after forming a conductive film that will become a pixel electrode, It may be in a state before pixel electrodes are formed by chipping, or any other state may be used.

[0019] In this specification, the liquid crystal display device includes an image display device, a liquid crystal display device, and It also refers to connectors, such as FPC (Flexible Printed Circuit). printed circuit) or TAB (Tape Automated Bonding tape or TCP (Tape Carrier Package) ) attached to the module, and a printed wiring board is attached to the end of the TAB tape or TCP. or a liquid crystal element is mounted on the IC by the COG (Chip On Glass) method. The liquid crystal display device also includes all modules on which an integrated circuit is directly mounted. [Effects of the Invention]

[0020] The present invention provides a liquid crystal display having thin film transistors with good electrical characteristics and high reliability. Display devices can be mass-produced. [Brief explanation of the drawings]

[0021] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 2]1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 5] 1A to 1C are top views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 9] 1A to 1C are top views illustrating a method for manufacturing a liquid crystal display device of the present invention. [Figure 10] 1 is a top view illustrating a microwave plasma CVD apparatus according to the present invention. [Figure 11] 1 is a cross-sectional view illustrating a multi-tone mask applicable to the present invention. [Figure 12] FIG. 1 is a perspective view illustrating a liquid crystal display panel according to the present invention. [Figure 13] 1 is a perspective view illustrating an electronic device using a liquid crystal display device of the present invention. [Figure 14] 1A and 1B are diagrams illustrating electronic devices using a liquid crystal display device of the present invention. [Figure 15] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 16] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 17] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 18] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 19] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 20] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 21] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 22] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 23] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 24] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 25] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 26] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 27] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 28] 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a liquid crystal display panel according to the present invention. [Figure 30] 1 is a block diagram illustrating a configuration of a liquid crystal display device according to the present invention. [Figure 31] FIG. 2 is an equivalent circuit diagram illustrating the configuration of a drive circuit of the liquid crystal display device of the present invention. [Figure 32] FIG. 2 is an equivalent circuit diagram illustrating the configuration of a drive circuit of the liquid crystal display device of the present invention. [Figure 33] FIG. 2 is a top view illustrating the layout of a drive circuit of the liquid crystal display device of the present invention. [Figure 34] 10A and 10B are diagrams showing the results of measuring a microcrystalline semiconductor film by Raman spectroscopy. [Figure 35] FIG. 1 is a diagram showing a model used in device simulation. [Figure 36] FIG. 10 is a diagram showing current-voltage characteristics obtained by device simulation. [Figure 37] FIG. 10 is a diagram showing the electron concentration distribution of a thin film transistor obtained by device simulation. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described with reference to the drawings. and the present invention may be practiced in various different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention. Therefore, it should not be construed as being limited to the description of this embodiment mode.

[0023] (Embodiment 1) In this embodiment mode, a manufacturing process of a thin film transistor used in a liquid crystal display device will be described. 1 to 12. FIGS. 1 to 4 and 6 to 8 show the structure of a thin film transistor. 5 and 9 are cross-sectional views showing the manufacturing process, and FIG. 5 and FIG. 9 are cross-sectional views showing the thin film transistor and FIG. 2 is a top view of a connection region of a pixel electrode.

[0024] Thin film transistors with microcrystalline semiconductor films have higher field-effect mobility when they are n-type than when they are p-type. Since the thin film transistors are formed on the same substrate, they are more suitable for use in the drive circuit. It is desirable to align all of the n A description will be given using a channel-type thin film transistor.

[0025] As shown in FIG. 1A, a gate electrode 51 is formed on a substrate 50. The substrate 50 is aluminoborosilicate glass, aluminoborosilicate glass, or aluminosilicate glass Alkali-free glass substrates and ceramic substrates manufactured by the fusion method or float method. In addition, a plastic substrate or the like that has heat resistance that can withstand the processing temperature of this manufacturing process should be used. In addition, a substrate with an insulating film on the surface of a metal substrate such as a stainless steel alloy can be used. If the substrate 50 is a mother glass, the size of the substrate is 1st generation (320mm x 40 0mm), 2nd generation (400mm x 500mm), 3rd generation (550mm x 650mm) , 4th generation (680mm x 880mm or 730mm x 920mm), 5th generation (1 000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm) ×2460mm), 9th generation (2400mm×2800mm, 2450mm×3050mm m), 10th generation (2950mm x 3400mm), etc. can be used.

[0026] The gate electrode 51 is made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode 51 is formed by sputtering. A conductive film is formed on the substrate 50 by a coating method or a vacuum deposition method, and a photolithography is performed on the conductive film. A mask is formed by a technique or an inkjet method, and the conductive film is etched using the mask. In addition, in order to improve the adhesion of the gate electrode 51 and to the underlying layer, As a barrier metal to prevent diffusion, a nitride film of the above metal material is formed between the substrate 50 and the gate electrode 5 1. Here, the resist mask formed using the first photomask The conductive film formed on the substrate 50 is etched using the etching method to form the gate electrode 51 .

[0027] In addition, since an insulating film, a semiconductor film, wiring, etc. are formed on the gate electrode 51, Therefore, it is desirable to process the end so that it is tapered. In this process, wiring connected to the gate electrode can also be formed at the same time.

[0028] Next, on the gate electrode 51, gate insulating films 52a and 52b, a microcrystalline semiconductor film 53, and a buffer layer 54 are formed. The semiconductor layer 55 is doped with an impurity element that provides one conductivity type, and the conductive films 65a to Next, a resist 80 is applied onto the conductive film 65c. In both cases, the gate insulating films 52a and 52b, the microcrystalline semiconductor film 53, and the buffer layer 54 are continuously formed. Furthermore, it is preferable to form the gate insulating films 52a and 52b and the microcrystalline semiconductor film 5 3, a buffer layer 54 and a semiconductor film 55 to which an impurity element that gives one conductivity type is added are continuously formed. It is preferable to form at least the gate insulating films 52a and 52b, the microcrystalline semiconductor The film 53 and the buffer layer 54 are successively formed without being exposed to the atmosphere, thereby preventing atmospheric deposition. The interfaces of the layers can be formed without being contaminated by impurity elements floating in the atmosphere or by chemicals. Therefore, variations in the characteristics of the thin film transistors can be reduced.

[0029] The gate insulating films 52a and 52b are formed by oxidizing the insulating film 52a using a CVD method, a sputtering method, or the like. The insulating film can be formed of a silicon film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Here, the gate insulating films 52a and 52b are made of a silicon oxide film or a silicon oxynitride film and a nitride film. The gate insulating film is formed by laminating a silicon nitride film or a silicon nitride oxide film in this order. The film is not made into two layers, but from the substrate side, a silicon nitride film or a silicon oxynitride film and a silicon oxide film or an oxide film are It can be formed by stacking three layers in the order of a silicon nitride film and a silicon nitride film or a silicon nitride oxide film. The gate insulating film can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride film. It can be formed of a single layer of silicon dioxide film.

[0030] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. Rutherford Backscattering (RBS) ering spectrometry and hydrogen forward scattering (HFS) n Forward Scattering) as the concentration range Oxygen 50-70 atomic %, nitrogen 0.5-15 atomic %, silicon 25-35 atomic %, hydrogen The silicon nitride oxide film is a film containing silicon dioxide in a range of 0.1 to 10 atomic percent. The nitrogen content is higher than the oxygen content, and the measurement is performed using RBS and HFS. In this case, the concentration range is 5 to 30 atomic % for oxygen, 20 to 55 atomic % for nitrogen, and 25 % to 35 atomic % and hydrogen in the range of 10 to 30 atomic %. When the total number of atoms constituting silicon or silicon nitride oxide is 100 atomic %, the ratio of nitrogen, oxygen, silicon The content ratio of hydrogen and oxygen is within the above range.

[0031] The microcrystalline semiconductor film 53 has an intermediate structure between an amorphous structure and a crystalline structure (including a single crystal and a polycrystal). The semiconductor is a film containing a semiconductor that has a third state that is stable in terms of free energy. Conductive, crystalline with short-range order and lattice distortion, with a grain size of 0.5 to Columnar or needle-like crystals of 20 nm are growing in the normal direction to the substrate surface. Microcrystalline silicon is a typical example of a microcrystalline semiconductor. The Raman spectrum shows the 521 cm -1 On the lower wavenumber side than That is, the 521 cm -1 and amorphous silicon 480cm -1 The Raman spectrum of microcrystalline silicon has a peak between these two. At least 1 atomic percent of hydrogen or halogen is added to terminate dangling bonds. In addition, rare earth elements such as helium, argon, krypton, and neon are also included. By incorporating gas elements to further promote lattice distortion, stability is increased and a good microcrystalline semiconductor is obtained. Such a microcrystalline semiconductor film is described in, for example, U.S. Pat. This is disclosed in US Pat. No. 9,134.

[0032] This microcrystalline semiconductor film is produced by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz. Alternatively, it can be formed by a microwave plasma CVD apparatus with a frequency of 1 GHz or more. Typically, it is formed by diluting silicon hydride such as SiH4 or Si2H6 with hydrogen. In addition to silicon hydride and hydrogen, helium, argon, krypton, and neon can also be used. The microcrystalline semiconductor film can be formed by diluting the semiconductor film with one or more rare gas elements selected from the group consisting of: In these cases, the flow rate ratio of hydrogen to silicon hydride is 50 times or more and 1000 times or less, Preferably, the ratio is 50 to 200 times, more preferably 100 times. Instead of this, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be used. Cut.

[0033] In addition, the microcrystalline semiconductor film requires intentional addition of impurity elements for the purpose of valence electron control. It exhibits weak n-type electrical conductivity and functions as the channel formation region of thin film transistors. For the microcrystalline semiconductor film, an impurity element imparting p-type conductivity is added simultaneously with or after the film formation. By adding impurities after the film formation, it becomes possible to control the threshold voltage. The element is typically boron, and impurity gases such as B2H6 and BF3 are added at 1 ppm to 1 It is advisable to mix it into the silicon hydride at a ratio of 0 to 100 ppm, preferably 1 to 100 ppm. and the boron concentration is, for example, 1×10 14 ~6×10 16 atoms / cm 3 It would be good to stomach.

[0034] The oxygen concentration of the microcrystalline semiconductor film is set to 5×10 19 cm -3 Below, 1×10 19 cm - 3 In the following, the concentrations of nitrogen and carbon are 3×10 18 cm -3 It is preferable to By reducing the concentrations of oxygen, nitrogen, and carbon mixed into the microcrystalline semiconductor film, This can prevent the body film from becoming n-type.

[0035] The microcrystalline semiconductor film 53 has a thickness of more than 0 nm and 200 nm or less, preferably 1 nm or more and 100 nm or less. The microcrystalline semiconductor film 53 is formed to a thickness of 5 nm or less, preferably 5 nm to 50 nm. The microcrystalline semiconductor film 53 functions as a channel formation region of the thin film transistor. By setting the thickness between 5nm and 50nm, the thin film transistor formed later will be a fully depleted type. The deposition rate of the microcrystalline semiconductor film 53 is 1 / 10 to 1 / 20 of the deposition rate of the amorphous semiconductor film. Because it is 1 / 100 slower, the throughput can be improved by making the film thinner. Since the microcrystalline semiconductor film is made of microcrystals, it has lower resistance than an amorphous semiconductor film. For this reason, a thin film transistor using a microcrystalline semiconductor film in a channel formation region has low current-voltage characteristics. The slope of the rising part of the curve showing the switching response becomes steeper, Furthermore, the channel formation region of the thin film transistor is made of microcrystalline semiconductor. By using a thin film, it is possible to suppress fluctuations in the threshold voltage of the thin film transistor. Therefore, a liquid crystal display device with little variation in electrical characteristics can be manufactured.

[0036] In addition, the microcrystalline semiconductor film has a higher mobility than the amorphous semiconductor film. For switching, a thin film transistor in which a channel formation region is formed using a microcrystalline semiconductor film By using the above, the area of ​​the channel forming region, that is, the area of ​​the thin film transistor, can be reduced. This reduces the area of ​​the thin film transistor per pixel, It is possible to increase the aperture ratio of the pixel, which makes it possible to fabricate a device with high resolution. can.

[0037] The buffer layer 54 is formed by plasma CVD using silicon hydride such as SiH4 or Si2H6. The silicon hydride can be formed by adding helium, argon, crypto Diluting with one or more rare gas elements selected from fluorine and neon to form an amorphous semiconductor film The flow rate of the silicon hydride is 1 to 20 times, preferably 1 to 10 times. Hereinafter, more preferably, hydrogen is used at a flow rate of 1 to 5 times, and the amorphous semiconductor containing hydrogen is Furthermore, by using the silicon hydride and nitrogen or ammonia, In this way, an amorphous semiconductor film containing nitrogen can be formed. Gases containing fluorine, chlorine, bromine, or iodine (F2, Cl2, Br2, I2, HF, HC HCl, HBr, HI, etc.) to produce amorphous materials containing fluorine, chlorine, bromine, or iodine. A semiconductor film can be formed. Note that instead of silicon hydride, SiH2Cl2, Si HCl3, SiCl4, SiF4, etc. can be used.

[0038] The buffer layer 54 is formed by sputtering with hydrogen or a rare gas using an amorphous semiconductor as a target. An amorphous semiconductor film can be formed by pulverizing the ammonium, nitrogen, Alternatively, by including N2O in the atmosphere, an amorphous semiconductor film containing nitrogen can be formed. In addition, if the atmosphere contains gases containing fluorine, chlorine, bromine, or iodine (F2, C By incorporating fluorine, An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed.

[0039] The buffer layer 54 is formed on the surface of the microcrystalline semiconductor film 53 by plasma CVD or spat After forming an amorphous semiconductor film by a pulverizing method, the surface of the amorphous semiconductor film is irradiated with hydrogen plasma. , nitrogen plasma, or halogen plasma to hydrogenate the surface of the amorphous semiconductor film; The surface of the amorphous semiconductor film may be nitrided or halogenated. Treatment with fluorine, neon plasma, argon plasma, krypton plasma, etc. may also be used.

[0040] The buffer layer 54 is preferably formed of an amorphous semiconductor film that does not contain crystal grains. Therefore, high frequency plasma CVD method with a frequency of several tens to several hundreds of MHz or microwave plasma CVD method is used. When forming the film using the Zuma CVD method, the film formation conditions are adjusted so that the film becomes an amorphous semiconductor film that does not contain crystal grains. It is preferable to control the conditions.

[0041] The buffer layer 54 is partially etched in the subsequent process of forming the source and drain regions. In this case, a part of the buffer layer 54 may remain after etching. It is preferable to form the film with a thickness of 150 nm or more and 400 nm or less. It is preferable to form a thin film transistor having a high applied voltage (for example, about 15 V). In the display device, when the buffer layer 54 is formed to have a thickness within the above range, the breakdown voltage Therefore, even if a high voltage is applied to the thin film transistor, the thin film transistor will deteriorate. This can be avoided.

[0042] The buffer layer 54 is doped with an impurity element such as phosphorus or boron that imparts one conductivity type. In particular, it is preferable that boron contained in the microcrystalline semiconductor film is not included in order to control the threshold voltage. Alternatively, phosphorus contained in a semiconductor film to which an impurity element that imparts one conductivity type is added is used as a buffer. It is preferable that the layer 54 is not mixed with the GaN layer 54. As a result, the region where leakage current occurs due to the PN junction By eliminating the impurities that give one conductivity type, the leakage current can be reduced. Between the semiconductor film to which the element is added and the microcrystalline semiconductor film, one conductivity type such as phosphorus or boron is added. By forming an amorphous semiconductor film to which no impurity elements are added, It is possible to prevent the diffusion of impurities contained in the source and drain regions. be.

[0043] The surface of the microcrystalline semiconductor film 53 is covered with an amorphous semiconductor film and a film containing hydrogen, nitrogen, or halogen. By forming an amorphous semiconductor film containing the crystal grains, the natural surface of the crystal grains contained in the microcrystalline semiconductor film 53 can be prevented. It is possible to prevent oxidation. In particular, in the region where the amorphous semiconductor and the microcrystalline grains come into contact, When these cracks come into contact with oxygen, the crystal grains are oxidized and become silicon oxide. However, by forming a buffer layer on the surface of the microcrystalline semiconductor film 53, In addition, by forming a buffer layer, it is possible to prevent oxidation of the microcrystalline grains. Etching residues generated when forming the gate and drain regions are mixed into the microcrystalline semiconductor film. This can prevent this from happening.

[0044] The buffer layer 54 may be formed using an amorphous semiconductor film or a film containing hydrogen, nitrogen, or halide. The energy gap of the amorphous semiconductor film is The energy gap of amorphous semiconductor films is larger than that of conductive films (1.6 eV or more, 1.8 e V or less, and the energy gap of the microcrystalline semiconductor film is 1.1 eV or more and 1.5 eV or less), The resistance is high and the mobility is low, which is 1 / 5 to 1 / 10 of that of a microcrystalline semiconductor film. In the thin film transistor to be formed, a source region and a drain region and a microcrystalline semiconductor film The buffer layer formed between the microcrystalline semiconductor film and the substrate functions as a high resistance region, and the microcrystalline semiconductor film is This allows the off-current of the thin film transistor to be reduced. When the thin film transistor is used as a switching element of a liquid crystal display device, The contrast of the device can be improved.

[0045] The semiconductor film 55 to which an impurity element that imparts one conductivity type is added is an n-channel thin film transistor. When forming a transistor, phosphorus is added as a typical impurity element, and hydrogenation All you need to do is add impurity gases such as PH3 to silicon. Also, p-channel thin film transistors In the case of forming silicon hydride, boron may be added as a typical impurity element. Adding impurity gas such as B2H6 is sufficient. The semiconductor film 55 can be formed of a microcrystalline semiconductor film or an amorphous semiconductor. The semiconductor film 55 to which an impurity element that imparts one conductivity type is added is The amorphous semiconductor film is doped with an impurity element that gives one conductivity type, and the amorphous semiconductor film is doped with an impurity element that gives one conductivity type. The buffer layer 54 may be formed by laminating an impurity element that imparts one conductivity type to the buffer layer 54 side. An amorphous semiconductor film is formed by adding an impurity element that gives one conductivity type. By forming a microcrystalline semiconductor film with a crystalline structure, the resistance changes stepwise, and the carriers flow. The doping of impurity elements that give one conductivity type The semiconductor film 55 is formed to a thickness of 2 nm to 50 nm. The throughput can be improved by thinning the film thickness of the semiconductor film to which the element is added. do.

[0046] Here, the gate insulating films 52a and 52b are doped with an impurity element that imparts one conductivity type. A plasma CVD apparatus capable of continuously depositing the semiconductor film 55 is shown in FIG. FIG. 10 is a schematic diagram showing the upper cross section of the plasma CVD apparatus, and shows the structure of the common chamber 1120. Load chamber 1110, unload chamber 1115, reaction chamber (1) to reaction chamber (4) 1111 to 1111 1120 and each chamber. Gate valves 1122 to 1127 is provided, and is configured so that the processes performed in each chamber do not interfere with each other. The substrates are loaded into cassettes 1128 and 1129 in the loading chamber 1110 and unloading chamber 1115. The reaction chambers (1) to (4) 1111 to 1112 are transferred by the transfer means 1121 of the common chamber 1120. In this system, a reaction chamber can be assigned to each deposition film type. A plurality of different coatings can be formed successively without exposure to the atmosphere.

[0047] In each of the reaction chambers (1) to (4), the gate insulating films 52a and 52b, the microcrystalline semiconductor A conductor film 53, a buffer layer 54, and a semiconductor film doped with an impurity element that imparts one conductivity type. In this case, different types of films are continuously formed by switching the source gas. In this case, after forming the gate insulating film, silane or the like is added to the reaction chamber. silicon hydride is introduced, the remaining oxygen and silicon hydride are reacted, and the reaction product is discharged outside the reaction chamber. By doing so, the residual oxygen concentration in the reaction chamber can be reduced. The oxygen concentration in the microcrystalline semiconductor film can be reduced. This can prevent the oxidation of the crystal grains.

[0048] Alternatively, the gate insulating films 52a and 52b and the microcrystalline semiconductor film 52a and 52b are formed in the reaction chamber (1) and the reaction chamber (3). 53 and a buffer layer 54 are formed, and one conductivity type is imparted in the reaction chamber (2) and the reaction chamber (4). The semiconductor film 55 is formed by adding only the impurity element that gives one conductivity type. By forming the film in this way, the impurity elements that give one conductivity type remaining in the chamber are mixed into other films. This can prevent the intrusion of

[0049] In this way, in a microwave plasma CVD device with multiple chambers connected, the insulating films 52a and 52b, the microcrystalline semiconductor film 53, the buffer layer 54, and the insulating film 52b that provides one conductivity type; Since the semiconductor film 55 to which the impurity element is added can be formed, mass productivity can be improved. In addition, even if one reaction chamber is undergoing maintenance or cleaning, the remaining reaction chambers can be used. This allows film formation processing to be performed in the reception room, improving the tact time of film formation. The interface between each layer is formed without being contaminated by gas components or contaminating impurity elements floating in the air. This makes it possible to reduce variations in the characteristics of thin film transistors.

[0050] Also, gate insulating films 52a and 52b are formed in reaction chamber (1), and a microcrystalline semiconductor is formed in reaction chamber (2). The conductive film 53 and the buffer layer 54 are formed, and an impurity element that gives one conductivity type is added in the reaction chamber (3). The doped semiconductor film 55 can be formed. The gate insulating film 52b is formed of a silicon nitride film or a silicon oxynitride film. In the case of forming the gate insulating film 52a, five reaction chambers are provided. In the reaction chamber (1), silicon oxide of the gate insulating film 52a is formed. In the reaction chamber (2), the silicon nitride film or silicon oxynitride film of the gate insulating film 52b is formed. A silicon nitride oxide film is formed in the reaction chamber (3), a microcrystalline semiconductor film is formed in the reaction chamber (4), and A buffer layer is formed in the reaction chamber (5), and a semiconductor layer to which an impurity element that gives one conductivity type is added is formed. A conductive film may be formed. In addition, since the film formation rate of a microcrystalline semiconductor film is slow, a plurality of reaction chambers may be used. For example, a microcrystalline semiconductor film may be formed by depositing gate insulating films 52a and 52b in the reaction chamber (1). A microcrystalline semiconductor film 53 is formed in the reaction chambers (2) and (3), and a buffer is formed in the reaction chamber (4). The layer 54 is formed by adding an impurity element that gives one conductivity type to the semiconductor in the reaction chamber (5). In this way, the microcrystalline semiconductor film 53 may be formed simultaneously in a plurality of reaction chambers. By doing so, the throughput can be improved. It is preferable to coat with the type of film to be deposited.

[0051] By using a plasma CVD apparatus with such a configuration, it is possible to produce similar types of films or films of the same type in each reaction chamber. It is possible to form various types of films, and they can be formed continuously without exposure to the atmosphere. This allows the film to be deposited without being contaminated by residues from previous films or impurities floating in the air. , each lamination interface can be formed.

[0052] The plasma CVD apparatus shown in FIG. 10 is provided with a separate load chamber and unload chamber. However, it may be combined into one chamber and used as a load / unload chamber. A standby chamber may be provided. By preheating the substrate in the standby chamber, the time required for film formation in each reaction chamber can be reduced. Since the heating time can be shortened, the throughput can be improved.

[0053] The film forming processes are described below. These film forming processes are performed by controlling the gas supply according to the purpose. All you have to do is select the gas to be supplied from the section.

[0054] Here, a silicon oxynitride film is formed on the gate insulating film 52a, and a nitride film is formed on the gate insulating film 52b. A method for forming a silicon oxide film will be given as an example.

[0055] First, the inside of the processing vessel of the reaction chamber of the microwave plasma CVD device was filled with fluorine radicals. The fluorine radicals are generated by a plasma generator installed outside the reaction chamber. Fluorocarbon, nitrogen fluoride, or fluorine is introduced into the bioreactor, dissociated, and reacted to form fluorine radicals. By introducing the gas into the reaction chamber, the inside of the reaction chamber can be cleaned.

[0056] After cleaning with fluorine radicals, a large amount of hydrogen is introduced into the reaction chamber to The concentration of residual fluorine in the chamber can be reduced by reacting it with hydrogen. Therefore, it is possible to reduce the amount of fluorine that gets mixed into the protective film that is later formed on the inner wall of the reaction chamber. Therefore, the thickness of the protective film can be reduced.

[0057] Next, an oxynitride film is deposited as a protective film on the inner wall surface of the processing vessel of the reaction chamber. The pressure inside the container is set to 1 to 200 Pa, preferably 1 to 100 Pa, and the plasma ignition gas and and one or more rare gases such as helium, argon, xenon, krypton, etc. Furthermore, one of the rare gases and hydrogen are introduced. In particular, plasma ignition It is preferable to use helium as the gas, and more preferably helium and hydrogen.

[0058] The ionization energy of helium is as high as 24.5 eV, but it is reduced to about 20 eV. Because of the metastable state, ionization is possible at approximately 4 eV during discharge. The discharge initiation voltage is low and the discharge is easy to maintain. Therefore, it is possible to maintain a uniform plasma. This makes it possible to reduce power consumption.

[0059] In addition, rare gases such as helium, argon, xenon, and krypton can be used as plasma ignition gases. In addition to the rare gas, oxygen gas may be introduced into the treatment volume. By introducing it into the chamber, it becomes easier to ignite the plasma.

[0060] Next, turn on the power supply and set the power supply output to 500-6000W, preferably 4 Next, the source gas is supplied to the gas supply unit and plasma is generated. Specifically, nitrous oxide, a rare gas, and silane are introduced into the vessel as raw material gases. By introducing the silicon oxynitride gas, a silicon oxynitride film is formed as a protective film on the inner wall surface of the processing vessel. The flow rate of silicon hydride is 50 to 300 sccm, and the flow rate of nitrous oxide is 500 to 6000 The flow rate is set to 100 sccm, and the thickness of the protective film is set to 500 to 2000 nm.

[0061] Next, the supply of the source gas is stopped, the pressure in the processing vessel is reduced, and the power supply device is turned off. After that, the substrate is introduced onto a support table in the processing chamber.

[0062] Next, a silicon oxynitride film is formed on the substrate as a gate insulating film 52a by the same process as that for the protective film. The film is deposited.

[0063] When a silicon oxynitride film of a predetermined thickness is deposited, the supply of the source gas is stopped, and the pressure in the processing vessel is power down and turn off the power supply.

[0064] Next, the pressure in the processing vessel is set to 1 to 200 Pa, preferably 1 to 100 Pa, and the plasma deposition As fire gas, one of the rare gases such as helium, argon, xenon, krypton, etc. In addition to the above, raw material gases silane, nitrous oxide, and ammonia are introduced. Nitrogen may be introduced as the gas instead of ammonia. Next, turn on the power supply. The power supply output should be 500 to 6000W, preferably 4000 to 6000W. Next, a source gas is introduced into the processing chamber from the gas supply unit, and the substrate 113 is heated. A silicon nitride oxide film is formed as a gate insulating film on the silicon oxynitride film of 0. Next, The supply of gas is stopped, the pressure in the processing chamber is reduced, and the power supply is turned off to restart the film formation process. Exit the service.

[0065] Through the above steps, the protective film on the reaction chamber wall is made of a silicon oxynitride film, and the silicon oxynitride film is formed on the substrate. By successively forming a silicon nitride oxide film and a silicon oxide film, silicon oxide, etc., is formed in the upper silicon nitride oxide film. It is possible to reduce the amount of impurities mixed in. It can generate microwaves as a power supply. By forming the above film by microwave plasma CVD using a power supply device that can The plasma density becomes high and a film with high voltage resistance can be formed. By using this, it is possible to reduce the variation in the threshold voltage of the transistor. In addition, the resistance to static electricity has been improved, and it will not break down even if a high voltage is applied. It is possible to fabricate transistors that are less likely to break down over time. In addition, a transistor with less hot carrier damage can be fabricated. It is possible.

[0066] In addition, the gate insulating film is made of silicon oxynitride formed by a microwave plasma CVD device. In the case of a single layer film, the above-mentioned method for forming a protective film and the method for forming a silicon oxynitride film are used. The flow rate ratio of nitrous oxide to ore is 50 times or more and 300 times or less, preferably 50 times or more and 200 times or less. If the thickness is 50 times or less, a silicon oxynitride film with high withstand voltage can be formed.

[0067] Next, a microcrystalline semiconductor film and an amorphous semiconductor film as a buffer layer are formed in succession by plasma CVD. First, the film is formed by the same process as the gate insulating film. The interior of the chamber is cleaned. Next, a silicon film is deposited inside the processing vessel as a protective film. The pressure in the treatment vessel is set to 1 to 200 Pa, preferably 1 to 100 Pa, and a plasma ignition As the gas, one or more of rare gases such as helium, argon, xenon, krypton, etc. Hydrogen may be introduced together with the rare gas.

[0068] Next, turn on the power supply and set the power supply output to 500-6000W, preferably 4 Next, the source gas is supplied to the gas supply unit and plasma is generated. Specifically, silicon hydride gas and water are introduced into the vessel as raw material gases. By introducing the nitrogen gas, a microcrystalline silicon film is formed as a protective film on the inner wall surface of the processing vessel. In addition to silicon hydride gas and hydrogen gas, helium, argon, krypton, and neon are also available. A microcrystalline semiconductor film can be formed by diluting the semiconductor with one or more rare gas elements selected from the group consisting of: In these cases, the flow rate ratio of hydrogen to silicon hydride is preferably 5 times or more and 1000 times or less. Preferably, the ratio is 50 to 200 times, and more preferably 100 to 150 times. The thickness of the protective film at this time is set to 500 to 2000 nm. Before the treatment, silicon hydride gas and hydrogen gas may be introduced into the treatment chamber in addition to the rare gas.

[0069] In addition to silicon hydride gas and hydrogen gas, helium, argon, krypton, and neon The amorphous semiconductor film is formed as a protective film by diluting it with one or more rare gas elements selected from the group consisting of: It can be formed.

[0070] Next, the supply of the source gas is stopped, the pressure in the processing vessel is reduced, and the power supply device is turned off. After that, the substrate is introduced onto a support table in the processing chamber.

[0071] Next, the surface of the gate insulating film 52b formed on the substrate may be subjected to hydrogen plasma treatment. By performing hydrogen plasma treatment before forming the crystalline semiconductor film, the gate insulating film and the microcrystalline It is possible to reduce the lattice distortion at the interface of the semiconductor film, and the gate insulating film and the microcrystalline semiconductor This improves the interface characteristics of the conductor film, which is then used for the thin film transistors to be formed later. The electrical characteristics of the capacitor can be improved.

[0072] In the hydrogen plasma treatment, the amorphous semiconductor protective film formed in the treatment chamber is The protective film is etched by subjecting the semiconductor film or the microcrystalline semiconductor film to hydrogen plasma treatment. A small amount of semiconductor is deposited on the surface of the gate insulating film 52b. As a result, the gate insulating film and the microcrystalline semiconductor film are deposited. It is possible to reduce the lattice distortion at the interface of the semiconductor film, and the gate insulating film and the microcrystalline semiconductor This improves the interface characteristics of the conductor film, which is then used for the thin film transistors to be formed later. The electrical characteristics of the capacitor can be improved.

[0073] Next, a microcrystalline silicon film is deposited on the substrate by the same process as that for the protective film. The thickness of the film is set to be greater than 0 nm and less than 50 nm, preferably greater than 0 nm and less than 20 nm. .

[0074] After a microcrystalline silicon film of a predetermined thickness is deposited, the supply of the source gas is stopped, and the inside of the processing chamber is The pressure is reduced, and the power supply is turned off to complete the microcrystalline semiconductor film formation process. .

[0075] Next, the pressure in the processing vessel is reduced and the flow rate of the source gas is adjusted. The flow rate of silicon hydride is significantly reduced compared to the film formation conditions for a microcrystalline semiconductor film. 1 to 20 times, preferably 1 to 10 times, more preferably 1 to 5 times Alternatively, hydrogen gas is not introduced into the processing chamber, and silicon hydride gas is introduced. By reducing the flow rate of hydrogen relative to the silicon hydride in this way, the buffer The deposition rate of the amorphous semiconductor film can be improved. In addition, one or more rare gases selected from helium, argon, krypton, and neon Then, turn on the power supply and set the output of the power supply to 500-600. 0 W, preferably 4000 to 6000 W, to generate plasma 200, and The deposition rate of an amorphous semiconductor film is higher than that of a microcrystalline semiconductor film. Therefore, the pressure inside the processing chamber can be set low. is set to 200 to 400 nm.

[0076] After the amorphous semiconductor film has been deposited to a predetermined thickness, the supply of the source gas is stopped, and the processing vessel is The pressure inside the chamber is reduced, the power supply is turned off, and the amorphous semiconductor film deposition process is completed. do.

[0077] The microcrystalline semiconductor film 53 and the amorphous semiconductor film that is the buffer layer 54 are ignited with plasma. Specifically, the microcrystalline semiconductor film 53 may be formed by using a hydrogenated gas, which is a source gas for forming the microcrystalline semiconductor film 53. The flow rate ratio of hydrogen to silicon is gradually reduced to form the microcrystalline semiconductor film 53 and the buffer layer 54. By this method, the microcrystalline semiconductor film 53 and the buffer film 54 are stacked. Impurities do not accumulate at the interface of the layer 54, and an interface with little distortion can be formed. The electrical characteristics of the thin film transistor can be improved.

[0078] When forming the microcrystalline semiconductor film 53, microwave plasma CV having a frequency of 1 GHz or more is used. It is preferable to use the D device. Microwave plasma has a high electron density and can Many radicals are formed and supplied to the substrate 1130, so that the surface reaction of the radicals on the substrate This promotes the reaction and increases the deposition rate of microcrystalline silicon. 0MHz, typically 13.56MHz, or greater than 20MHz up to 120MHz High frequency bands in the VHF band up to about 60 Hz, typically 27.12 MHz and 60 MHz, are used. A microcrystalline semiconductor film can be formed by the plasma CVD method.

[0079] In the respective processes for producing the gate insulating film and the semiconductor film, the inner wall of the reaction chamber is coated with 500 to 1000 .mu.m. If a 2000 nm protective film is formed, the above cleaning process and protective film formation process You can omit the logic.

[0080] Next, conductive films 65a to 65c are formed on the semiconductor film 55 to which an impurity element imparting one conductivity type is added. The conductive films 65a to 65c are made of aluminum, copper, silicon, or titanium. Heat resistance improving elements or hillock prevention elements such as silicon, neodymium, scandium, and molybdenum It is preferable to form the aluminum alloy with a single layer or a multilayer structure containing aluminum. The film on the side in contact with the semiconductor film to which the impurity element that gives the conductivity is added is made of titanium, tantalum, or the like. , molybdenum, tungsten, or nitrides of these elements, and aluminum is deposited on top of them. It may also be a laminated structure in which aluminum or an aluminum alloy is formed. or aluminum alloy, the upper and lower surfaces are covered with titanium, tantalum, molybdenum, tungsten Alternatively, a laminated structure in which the conductive film is sandwiched between nitrides of these elements may be used. indicates a conductive film having a structure in which three conductive films 65a to 65c are stacked, and the conductive films 65a and 65c A laminated conductive film using an aluminum film as the conductive film 65b, a molybdenum film, and a conductive film 65a, 6 The conductive film 65c is a laminated conductive film using a titanium film and the conductive film 65b is an aluminum film. The layers 65a to 65c are formed by sputtering or vacuum deposition.

[0081] The resist 80 can be a positive resist or a negative resist. , shown using a positive resist.

[0082] Next, the resist 80 is irradiated with light using the multi-tone mask 59 as a second photomask. The resist 80 is exposed to light.

[0083] Here, exposure using the multi-tone mask 59 will be described with reference to FIG.

[0084] A multi-tone mask has three exposure levels: exposed, intermediately exposed, and unexposed. It is a mask that can be used in a single exposure and development process, and multiple (typically two types) ) thickness area. By using a mask, it is possible to reduce the number of photomasks.

[0085] Typical examples of multi-tone masks include a gray-tone mask 59a as shown in FIG. 11(A), There is a halftone mask 59b as shown in FIG. 11(C).

[0086] As shown in FIG. 11(A), the gray-tone mask 59a is made of a transparent substrate 163 and a The light-shielding portion 164 and the diffraction grating 165 are formed on the light-shielding portion 164. On the other hand, the diffraction grating 165 has slits, dots, meshes, etc. By setting the spacing between the light transmitting portions of the light source, such as the lens, to be equal to or less than the resolution limit of the light used for exposure, The diffraction grating 165 can control the transmittance of the light. , mesh, or non-periodic slits, dots, mesh can be used. .

[0087] The light-transmitting substrate 163 can be a light-transmitting substrate such as quartz. The portion 164 and the diffraction grating 165 are made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed.

[0088] When the gray-tone mask 59a is irradiated with exposure light, as shown in FIG. 11(B), the light-shielding portion In 164, the light transmittance 166 is 0%, and the light blocking portion 164 and the diffraction grating 165 are provided. In the unobstructed area, the light transmittance 166 is 100%. The light transmittance of the diffraction grating 165 can be adjusted in the range of 10 to 70%. This can be achieved by adjusting the spacing or pitch of the slits, dots, or meshes of the diffraction grating. It is Noh.

[0089] As shown in FIG. 11(C), the halftone mask 59b is formed on a light-transmitting substrate 163 and The semi-transmitting portion 167 and the light-shielding portion 168 are formed on the semi-transmitting portion 167. MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion 168 is formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. It is possible.

[0090] When the halftone mask 59b is irradiated with exposure light, as shown in FIG. 11(D), the light-shielding portion In 168, the light transmittance 169 is 0%, and the light-shielding portion 168 and the semi-transmitting portion 167 are provided. In the unshaded area, the light transmittance 169 is 100%. The light transmittance of the semi-transparent portion 167 can be adjusted in the range of 10 to 70%. This can be adjusted by the material of the semi-transparent portion 167.

[0091] By exposing the film using a multi-tone mask and then developing it, different film thicknesses are obtained as shown in Figure 1(B). A resist mask 81 having the following regions can be formed.

[0092] Next, a resist mask 81 is used to form the microcrystalline semiconductor film 53, the buffer layer 54, and the one-conductivity type The semiconductor film 55 to which the impurity element is added and the conductive films 65a to 65c are etched. As a result, a microcrystalline semiconductor film 61, a buffer layer 62, and a The semiconductor film 63 to which an impurity element imparting one conductivity type is added and the conductive films 85a to 85c are It should be noted that FIG. 2(A) corresponds to a cross-sectional view taken along line AB in FIG. 5(A). (However, the resist mask 86 is excluded).

[0093] The side surfaces of the microcrystalline semiconductor film 61 and the buffer layer 62 are inclined, so that the buffer layer A leakage current is generated between the source and drain regions formed on the microcrystalline semiconductor film 62 and the microcrystalline semiconductor film 61. In addition, the source electrode and the drain electrode are micro-connected. Therefore, it is possible to prevent the occurrence of leakage current between the microcrystalline semiconductor film 61 and the microcrystalline semiconductor film 62. The inclination angle of the end side surfaces of the film 61 and the buffer layer 62 is 30° to 90°, preferably 45°. By setting the angle at this angle, the source electrode or drain electrode due to the step shape can be prevented from being damaged. This can prevent breakage of the inner electrode.

[0094] Next, the resist mask 81 is ashed. As a result, the area of ​​the resist is reduced and the thickness is At this time, the resist in the thin film region (which overlaps with a part of the gate electrode 51) The resist mask 86 is then removed to form a separate resist mask 86, as shown in FIG. 6(B). It is possible.

[0095] Next, a semiconductor film doped with an impurity element that gives one conductivity type is formed using a resist mask 86. 63 and the conductive films 85a to 85c are etched and separated. As a result, a pair of conductive films 85a to 85c are separated as shown in FIG. Conductive films 89a to 89c and a pair of source and drain regions 89 can be formed. In this etching step, a part of the buffer layer 62 is also etched. The partially etched buffer layer is shown as buffer layer 88. The formation process and the recessed portion of the buffer layer can be formed in the same process. Since a part of the layer 88 is etched by the resist mask 86 whose area is reduced, the conductive layer 88 is The buffer layer 88 protrudes outward from the conductive films 85a to 85c.

[0096] Next, as shown in FIG. 2(C), a part of the conductive films 89a to 89c is etched to form the source electrodes and drain electrodes 92a to 92c are formed. When the conductive films 89a to 89c are wet-etched, the ends of the conductive films 89a to 89c are selectively As a result, the resist mask 86 and the conductive films 89a to 89c are etched away from each other. Therefore, the source and drain electrodes 92a to 92c can be formed with small source voltages. The ends of the source and drain electrodes 92a to 92c and the ends of the source and drain regions 89 are The source electrodes and drain electrodes 92a to 92c are not aligned but are misaligned, and the source electrodes and drain electrodes 92a to 92c are located outside the ends of the source electrodes and drain electrodes 92a to 92c. The ends of the source and drain regions 89 are formed. After this, the resist mask 86 is removed. do.

[0097] 2(C) corresponds to a cross-sectional view taken along line AB in FIG. 5(B). , the ends of the source and drain regions 89 are connected to the ends of the source and drain electrodes 92c. The end of the buffer layer 88 is located outside the source and drain electrodes. The electrode 92c is located outside the ends of the source and drain regions 89. One of the source and drain regions is shaped to partially surround the other of the source and drain regions ( Specifically, they are U-shaped and C-shaped. This increases the area of ​​the region where carriers move. This allows the amount of current to be increased, and the surface area of ​​the thin film transistor In addition, the microcrystalline semiconductor film 87 and the silicon dioxide film 88 are formed inside the gate electrode. Since the source electrode and the drain electrode 92c are overlapped, the unevenness at the end of the gate electrode is The influence of the coating is small, and the reduction in the coverage rate and the occurrence of leakage current can be suppressed. One of the source electrode and the drain electrode also functions as a source wiring or a drain wiring. .

[0098] As shown in FIG. 2C, the ends of the source and drain electrodes 92a to 92c and the source The ends of the source electrode and the drain region 89 are not aligned but are misaligned. Since the distance between the ends of the drain electrodes 92a to 92c is large, This prevents leakage current and short circuits, resulting in high reliability and high voltage resistance. Therefore, it is possible to fabricate thin film transistors with high efficiency.

[0099] Through the above steps, a channel-etch type thin film transistor 83 can be formed. Also, a thin film transistor can be formed using two photomasks.

[0100] The thin film transistor shown in this embodiment mode has a gate insulating film and a microcrystalline semiconductor film formed over a gate electrode. a buffer layer, a source region and a drain region, a source electrode and a drain electrode are laminated. The buffer layer covers the surface of the microcrystalline semiconductor film that functions as a channel formation region. A recess (groove) is formed in a part of the buffer layer, and the area other than the recess is a source region and That is, the recess formed in the buffer layer covers the source and drain regions. The distance that carriers travel between the source and drain regions is long, In addition, by etching a part of the buffer layer, the leakage current can be reduced. In order to form the recesses by the above method, the generation of the electrons in the process of forming the source and drain regions is prevented. Since the etching residue can be removed, the source and drain regions can be easily accessed through the residue. The occurrence of leakage current (parasitic channel) can be avoided.

[0101] In addition, the microcrystalline semiconductor film serving as a channel formation region and the source and drain regions A buffer layer is formed between the microcrystalline semiconductor film and the insulating film. The buffer layer formed of a high resistivity amorphous semiconductor film is Since the thin film transistor extends between the source region and the drain region, When the gate voltage is set to a negative voltage, the leakage current can be reduced. In addition, deterioration due to application of a high voltage can be reduced. Since an amorphous semiconductor film whose surface is terminated with hydrogen is formed as a buffer layer, It is possible to prevent oxidation of the crystalline semiconductor film and to form the source and drain regions. This can prevent etching residues generated in the deposition process from being mixed into the microcrystalline semiconductor film. Therefore, the thin film transistor has high electrical characteristics and an excellent drain withstand voltage.

[0102] The edges of the source electrode and the drain electrode are aligned with the edges of the source region and the drain region. The distance between the ends of the source electrode and the drain electrode increases due to the shifted shape. This makes it possible to prevent leakage current and short circuits between the source electrode and the drain electrode.

[0103] Next, as shown in FIG. 3(A), the source and drain electrodes 92a to 92c, the source region the source and drain regions 89, the buffer layer 88, the microcrystalline semiconductor film 87, and the gate insulating film 52. The insulating film 76 is formed on the gate insulating films 52a and 52b. The insulating film 76 can be resistant to organic matter, metal matter, water vapor, and the like floating in the air. The insulating film 76 is preferably a dense film because it is intended to prevent the intrusion of contaminating impurities. By using a silicon nitride film, the oxygen concentration in the buffer layer 88 can be reduced to 5×10 19 atoms / c m 3 Less than 1 × 10 19 atoms / cm 3 It can be as follows:

[0104] Next, a contact hole is formed in the insulating film 76, and a source electrode is formed in the contact hole. The pixel electrode 77 is formed in contact with the electrode or drain electrode 92c. This corresponds to the cross section AB in 5(C).

[0105] The pixel electrode 77 is made of indium oxide containing tungsten oxide, indium oxide containing tungsten oxide, Indium zinc oxide, indium oxide with titanium oxide, indium with titanium oxide Tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, oxide A conductive material with light-transmitting properties, such as silicon-doped indium tin oxide, can be used. Cut.

[0106] The pixel electrode 77 is made of a conductive composition containing a conductive macromolecule (also called a conductive polymer). The pixel electrode formed using the conductive composition can be formed using a sheet resistor. It is preferable that the resistance is 10000Ω / □ or less and the light transmittance at a wavelength of 550 nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that

[0107] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0108] In this manner, an element substrate that can be used in a liquid crystal display device can be formed.

[0109] As shown in FIG. 2A, a microcrystalline semiconductor film 61, a buffer layer 62, and a layer imparting one conductivity type are provided. After forming the semiconductor film 63 to which the impurity element is added and the conductive films 85a to 85c, 4(A), the conductive films 85a to 85c are etched using a resist mask 86. Here, the conductive films 85a to 85c are wet etched using the resist mask 86. When the conductive films 85a to 85c are isotropically etched by etching, the conductive films 85a to 85c are selectively etched. As a result, the source and drain electrodes 92a to 92c, which have a smaller area than the resist mask 86, are 92c can be formed.

[0110] Next, as shown in FIG. 4B, a resist mask 86 is used to apply an impurity to impart one conductivity type. The semiconductor film 63 to which the element is added is etched. Here, the semiconductor film 63 is etched by dry etching. When the semiconductor film 63 to which the impurity element that gives the conductivity type is added is anisotropically etched, The source and drain regions 89 can be formed with an area approximately equal to that of the resist mask 86. Cut.

[0111] The ends of the source and drain electrodes 92a to 92c and the source and drain regions 89 The ends of the source and drain electrodes 92a to 92c are not aligned but are shifted. The distance between the ends of the source and drain electrodes is large, preventing leakage current and short circuits. Therefore, a thin film transistor with high reliability and high withstand voltage can be manufactured. It is possible.

[0112] As shown in FIGS. 1 to 4, the conductive film is etched by wet etching, and then by dry etching. By etching a semiconductor film to which an impurity element that gives one conductivity type is added, The edges of the source and drain electrodes and the source and drain regions are formed without using a photomask. The edges of the regions may not coincide and may be of different construction.

[0113] Next, a method for manufacturing a thin film transistor different from the above will be described with reference to FIGS. 6 to 9. Here, the source electrode or drain electrode and the source wiring or drain wiring are described. The different forms from the line are shown below.

[0114] As shown in FIG. 6A, a gate electrode 51 is formed on a substrate 50. Next, the gate electrode 51 is 1, gate insulating films 52a and 52b, a microcrystalline semiconductor film 53, a buffer layer 54, and a one-conductivity type A semiconductor film 55 to which an impurity element that imparts conductivity is added and a conductive film 65a are formed in this order. Then, a resist is applied onto the conductive film 65a, and a multi-tone mask shown in FIG. 1(A) is used to form a resist pattern of a desired thickness. A resist mask 81 having different regions is formed.

[0115] Next, a resist mask 81 is used to form the microcrystalline semiconductor film 53, the buffer layer 54, and the one-conductivity type The semiconductor film 55 to which the impurity element to be added and the conductive film 65a are etched and separated. As a result, as shown in FIG. 6B, a microcrystalline semiconductor film 61, a buffer layer 62, and a single conductivity type The semiconductor film 63 and the conductive film 85a are formed by adding an impurity element that imparts FIG. 6B corresponds to a cross-sectional view taken along line AB in FIG. 9A (however, the resist mask 86 is omitted). except).

[0116] Next, the resist mask 81 is ashed to form a separated resist mask 86 . Next, a semiconductor film doped with an impurity element that gives one conductivity type is formed using a resist mask 86. 63 and the conductive film 85a are etched and separated. As a result, as shown in FIG. A pair of conductive films 89a and a pair of source and drain regions 89 can be formed. In this etching step, a part of the buffer layer 62 is also etched. The etched buffer layer is shown as buffer layer 88. Here, a portion of buffer layer 88 However, since the resist mask 86 is partially etched with a reduced area, the outside of the conductive film 85a As shown in this embodiment, the buffer layer 88 is formed in a shape that protrudes to the side of the buffer layer. Since the surface has a stepped shape, the coverage of the insulating film to be formed later is increased. Therefore, the leakage current between the pixel electrode formed on the insulating film and the thin film transistor is reduced. It can be reduced.

[0117] Next, the resist mask 86 is ashed. As a result, as shown in FIG. The area of ​​the resist mask is reduced and the thickness is reduced. By etching a part of the conductive film 89a using The source electrode and the drain electrode 92a are formed. The ends of the source electrode and the drain electrode 92a and The edges of the source and drain regions 89 do not coincide with each other and are misaligned. 1 is used to anisotropically etch the exposed portion of the conductive film 89a by dry etching. Thereafter, the resist mask 91 is removed.

[0118] As a result, the source electrode and drain electrode 92a having a smaller area than the conductive film 89a are formed. After that, the resist mask 91 is removed. Note that FIG. 7B shows the same pattern as that shown in FIG. 9B. As shown in FIG. 9B, the ends of the source and drain regions 89 are It can be seen that the electrodes are located outside the ends of the source and drain electrodes 92a. The ends of the phototransistor layer 88 are connected to the source and drain electrodes 92a and the source and drain regions. The source electrode and the drain electrode 92a are located outside the gate region 89. The electrodes are not connected to the electrodes formed in the adjacent pixels. The resist mask 86 is ashed to form a resist mask 91, which is used to form the source electrode and the drain electrode. The inner electrode 92a was formed, but as shown in the steps shown in FIGS. 6, and wet etching is performed to form source and drain electrodes 92a to 92c. That's fine.

[0119] As shown in FIG. 7B, the ends of the source and drain electrodes 92a and the source and drain regions The edges of the drain region 89 are not aligned but are misaligned, so that the source electrode and the drain electrode Since the distance between the ends of the electrodes 92a is large, leakage current and short-circuit current between the source electrode and the drain electrode are reduced. This makes it possible to prevent breakdown of the thin film transistor, which is highly reliable and has a high breakdown voltage. It is possible to create a

[0120] Next, as shown in FIG. 7(C), the source and drain electrodes 92a, the source and drain regions The insulating film 76 is formed on the drain region 89, the buffer layer 88, and the gate insulating film 52b. The insulating film 76 can be formed in the same manner as the gate insulating films 52a and 52b.

[0121] Next, as shown in FIG. 8(A), a contact hole is formed in the insulating film 76, and the contact The source electrode or the drain electrode 92a is in contact with the source electrode or the drain electrode 92a at the hole, and the stacked wiring Lines 93b and 93c are formed. Note that FIG. 8A corresponds to the cross-sectional view taken along line AB in FIG. 9C. The wirings 93b and 93c are connected to the source electrodes or drain electrodes formed in the adjacent pixels. The wiring connects the electrodes.

[0122] Next, as shown in FIG. 8(B), a source electrode or a drain electrode is formed in the contact hole. The pixel electrode 77 is formed in contact with the other side of the inner electrode 92a. ) corresponds to the cross section AB of the

[0123] Through the above steps, a channel-etch type thin film transistor 84 can be formed. The channel-etch type thin film transistor requires fewer manufacturing steps and can reduce costs. In addition, by forming a channel formation region using a microcrystalline semiconductor film, the 2 / V Therefore, when this thin film transistor is used as a pixel element, a field effect mobility of 1.0 s can be obtained. As a switching element for the pixel, a driving circuit for the scanning line (gate line) is also formed. It can be used as an element.

[0124] According to this embodiment mode, a thin film transistor with highly reliable electrical characteristics can be manufactured. .

[0125] (Embodiment 2) In this embodiment mode, a liquid crystal display device including the thin film transistor described in Embodiment 1 will be described. The following is a summary:

[0126] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In VA type LCD devices, the liquid crystal molecules are aligned with the panel surface when no voltage is applied. In this embodiment, pixels are divided into several regions. The molecules are divided into sub-pixels (sub-pixels) and tilted in different directions. This is called multi-domain or multi-domain design. In the following explanation, multi-domain design A liquid crystal display device that takes into consideration the above will be described.

[0127] 16 and 17 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of the substrate side on which the element electrodes are formed, and shows a cross-sectional structure corresponding to the cutting line AB shown in the figure. This is shown in FIG. 15. Also, FIG. 17 is a plan view of the substrate side on which the counter electrode is formed. The following description will refer to these figures.

[0128] FIG. 15 shows a configuration of a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state after the liquid crystal is injected.

[0129] The opposing substrate 601 has a light-shielding film 632 and a first adhesive film 642 formed at a position where the spacer 642 is to be formed. A color film 634, a second color film 636, a third color film 638, and a counter electrode 640 are formed. This structure allows the heights of the protrusions 644 and spacers 642 to be different for controlling the alignment of the liquid crystal. An alignment film 648 is formed on the pixel electrode 624, and similarly, an alignment film 648 is formed on the counter electrode 640. An alignment film 646 is also formed on the first and second electrodes 642. A liquid crystal layer 650 is formed between them.

[0130] Although the spacers 642 are shown as columnar spacers here, bead spacers may also be scattered. Furthermore, the spacers 642 are formed on the pixel electrodes 624 formed on the substrate 600. Good too.

[0131] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. The pixel electrode 624 covers the TFT 628, the wiring, and the storage capacitor 630. A contact hole 6 penetrates the insulating film 620 and an insulating film 622 covering the insulating film 620. The TFT 628 is the thin film transistor shown in Embodiment Mode 1. The storage capacitor 630 can be connected to the gate wiring 602 of the TFT 628. The first capacitor wiring 604, the gate insulating film 606, and the wirings 616 and 618 are formed in the same manner as above. The second capacitor wiring 617 is formed in the same manner as above.

[0132] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0133] 16 shows the structure on the substrate 600. The pixel electrode 624 is made of the material shown in the first embodiment. The pixel electrode 624 is provided with a slit 625. The slit 625 is formed by This is to control the

[0134] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. The TFT 628 and the TFT 629 are both connected to the wiring 616. A pixel is composed of a pixel electrode 624 and a pixel electrode 626. 24 and pixel electrode 626 are sub-pixels.

[0135] 17 shows the structure on the opposing substrate side. An opposing electrode 640 is formed on a light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. On the counter electrode 640, a protrusion 644 for controlling the alignment of the liquid crystal is formed. A spacer 642 is formed in accordance with the position of 32.

[0136] The equivalent circuit of this pixel structure is shown in Figure 18. TFT628 and TFT629 are both gate The wiring 602 and the wiring 616 are connected. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected. By making the potentials different, the liquid crystal element 651 and the liquid crystal element 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, The viewing angle is widened by precisely controlling the orientation of the crystals.

[0137] When a voltage is applied to the pixel electrode 624 in which the slit 625 is provided, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated manner, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0138] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 19 to 22. do.

[0139] 19 and 20 show the pixel structure of a VA type liquid crystal panel. FIG. 19 is a plan view showing a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The explanation will be given with reference to these two figures.

[0140] This pixel structure has multiple pixel electrodes in one pixel, and each pixel electrode has a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed in a multi-domain, the signal applied to each pixel electrode is independently controlled. It has a configuration that controls it independently.

[0141] The pixel electrode 624 is connected to the TFT 628 through the contact hole 623 using the wiring 618. The pixel electrode 626 is connected to the wiring 619 through a contact hole 627. The gate wiring 602 of the TFT 628 is connected to the TFT 629 using a The gate wiring 603 of the 9 is separated so that different gate signals can be applied. On the other hand, the wiring 616 that functions as a data line is common to the TFT 628 and the TFT 629. The capacitor wiring 690, the gate insulating film 606, and the wiring 618 are used as the first A capacitor element is formed, and a second capacitor is formed by a capacitor wiring 690, a gate insulating film 606, and a wiring 619. The thin film transistors shown in Embodiment 1 are used for the TFTs 628 and 629. It can be used as appropriate.

[0142] The pixel electrodes 624 and 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of applying voltages to the pixel electrodes 624 and 626 is controlled by the TFT 62. The orientation of the liquid crystal is controlled by varying the polarity of the TFT 629. The equivalent circuit is shown in FIG. 22. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is The gate wiring 602 and the gate wiring 603 are connected to different gates. By giving a signal, the operation timing of TFT628 and TFT629 can be made different. can.

[0143] On the counter substrate 601, a light-shielding film 632, a second colored film 636, and a counter electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. This prevents the alignment of the liquid crystal from being disturbed. FIG. 21 shows the structure of the opposing substrate side. The opposing electrode 640 is This electrode is shared between the pixels, and has a slit 641 formed therein. The slits 641 and the slits 625 on the pixel electrode 624 and pixel electrode 626 sides are alternately interlocked. By arranging the electrodes in a way that matches the orientation of the liquid crystal, an oblique electric field can be generated effectively and the orientation of the liquid crystal can be controlled. This allows the liquid crystal to be oriented in different directions depending on the location, resulting in a wide viewing angle. is spreading.

[0144] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped with each other. The first liquid crystal element and the second liquid crystal element are formed in one pixel. It is a multi-domain structure with multiple children.

[0145] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0146] FIG. 23 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, The opposing substrate 601 is placed on top of the other substrate and liquid crystal is injected. A light-emitting film 632, a second coloring film 636, a flattening film 637, etc. are formed. It is located on the plate 600 side, and is not provided on the opposing substrate 601 side. A liquid crystal layer 650 is formed between the layers 601 .

[0147] On the substrate 600, a first pixel electrode 607 and a capacitance wiring connected to the first pixel electrode 607 are provided. 604 and the TFT 628 shown in Embodiment 1 are formed. The same material as that of the pixel electrode 77 shown in Embodiment 1 can be used. The electrode 607 is formed in a shape that is partitioned into approximately the shape of a pixel. A gate insulating film 606 is formed on the capacitor wiring 604 .

[0148] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is the data line that carries the video signal in the LCD panel and is a wiring that extends in one direction. At the same time, it is connected to the source region 610 and serves as one of the source and drain electrodes. 8 is the other electrode of the source and drain, and is a wiring connected to the second pixel electrode 624. do.

[0149] An insulating film 620 is formed on the wiring 616 and the wiring 618. In addition, on the insulating film 620, In a contact hole 623 formed in the insulating film 620, a second The pixel electrode 624 is formed in the same manner as the pixel electrode 77 shown in the first embodiment. It is formed using the same material.

[0150] In this way, the TFT 628 and the second pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the first pixel electrode 607 and the second pixel electrode 624. It is completed.

[0151] 24 is a plan view showing the configuration of the pixel electrode. The pixel electrode 624 has a slit 625. The slits 625 are provided to control the orientation of the liquid crystal. occurs between the first pixel electrode 607 and the second pixel electrode 624. A gate insulating film 606 is formed between the first pixel electrode 624 and the second pixel electrode 624. The thickness of 606 is 50 to 200 nm, which is sufficiently large compared with the thickness of the liquid crystal layer, which is 2 to 10 μm. Since the substrate 600 is thin, an electric field is generated in a direction substantially parallel to the substrate 600 (horizontal direction). The orientation of the liquid crystal is controlled by the electric field applied to the substrate. In this case, the liquid crystal molecules are horizontal in any state, so the color does not change depending on the viewing angle. The influence of contrast and the like is small, and the viewing angle is widened. Since both the first pixel electrode 7 and the second pixel electrode 624 are light-transmitting electrodes, the aperture ratio can be improved. Cut.

[0152] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0153] 25 and 26 show the pixel structure of an IPS type liquid crystal display device. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0154] FIG. 25 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, The opposing substrate 601 is placed on top of the other substrate and liquid crystal is injected. A light-emitting film 632, a second coloring film 636, a flattening film 637, etc. are formed. Since it is on the plate 600 side, it is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the layers 601 .

[0155] On the substrate 600, a common potential line 609 and the TFT 628 shown in the first embodiment are formed. The common potential line 609 is formed at the same time as the gate wiring 602 of the thin film transistor 628. This can be done.

[0156] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is the data line that carries the video signal in the LCD panel and is a wiring that extends in one direction. At the same time, it is connected to the source region 610 and serves as one of the source and drain electrodes. 8 is the other electrode of the source and drain, and is a wiring connected to the second pixel electrode 624. do.

[0157] A second insulating film 620 is formed on the wiring 616 and the wiring 618. In this case, a contact hole 623 formed in the insulating film 620 is connected to the wiring 618. The pixel electrode 624 is the same as the pixel electrode 77 shown in the first embodiment. As shown in FIG. 26, the pixel electrode 624 is formed of the same material. The wire 609 is formed so as to generate a horizontal electric field together with the comb-shaped electrode formed at the same time. The comb-teeth of the electrode 624 are alternately interdigitated with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed like this.

[0158] When an electric field is generated between the potential applied to the pixel electrode 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. The molecules are rotated horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast and results in a wider viewing angle.

[0159] In this way, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode 624 are formed by the contact hole 633. are connected via

[0160] Next, the configuration of a TN type liquid crystal display device will be described.

[0161] 27 and 28 show the pixel structure of a TN type liquid crystal display device. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0162] The pixel electrode 624 is connected to the TFT 628 via the wiring 618 through the contact hole 623. The wiring 616, which functions as a data line, is connected to the TFT 628. Any of the TFTs shown in the first embodiment can be applied to 28.

[0163] The pixel electrode 624 is formed using the pixel electrode 77 shown in the first embodiment.

[0164] On the counter substrate 601, a light-shielding film 632, a second colored film 636, and a counter electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. The liquid crystal layer 650 is disposed between the pixel electrode 624 and the counter electrode 640. It is formed.

[0165] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0166] The counter electrode 640 can be made of the same material as the pixel electrode 624. 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. .

[0167] In the liquid crystal display devices shown in FIGS. 15 to 28, the substrate 600 or the counter substrate 60 1. Color filters and a shielding film (black matrix) to prevent disclination ) may be formed on the substrate 600. A polarizing plate is attached to the surface opposite to the polarizing plate, and a counter electrode 640 is formed on the counter substrate 601. A polarizing plate is attached to the surface opposite to the surface where the polarizing plate is attached.

[0168] Through the above steps, a liquid crystal display device can be manufactured. The off-state current is low and thin film transistors with highly reliable electrical characteristics are used. The liquid crystal display device has high contrast and high visibility. Since a thin film transistor using a crystalline semiconductor film in the channel formation region is used, High quality liquid crystal display devices can be mass-produced.

[0169] (Embodiment 3) Next, a structure of a display panel, which is one mode of a liquid crystal display device of the present invention, will be described below.

[0170] In FIG. 12A, only a signal line driver circuit 6013 is formed separately and is formed on a substrate 6011. 6 shows a configuration of a display panel connected to a pixel portion 6012. The driver circuit 6014 uses a thin film transistor in which a microcrystalline semiconductor film is used for a channel formation region. The thickness of the thin film transistor is higher than that of the thin film transistor using a microcrystalline semiconductor film in the channel formation region. By forming a signal line driver circuit using transistors that can obtain field effect transfer, This makes it possible to stabilize the operation of the signal line driver circuit, which requires a higher drive frequency than the signal line driver circuit. The signal line driver circuit 6013 is a transistor using a single crystal semiconductor for a channel forming region. thin-film transistors that use a polycrystalline semiconductor in the channel formation region, or thin-film transistors that use SOI The pixel portion 6012, the signal line driver circuit 6013, and the scanning The power supply potential, various signals, etc. are respectively connected to the line driver circuit 6014 via the FPC 6015. Supplied.

[0171] The signal line driver circuit and the scanning line driver circuit may both be formed on the same substrate as the pixel portion. stomach.

[0172] In addition, when a driver circuit is formed separately, the substrate on which the driver circuit is formed is not necessarily the same as the substrate on which the pixel portion is formed. It is not necessary to attach it to the substrate on which it is formed, but it can be attached to, for example, an FPC. In FIG. 12B, only a signal line driver circuit 6023 is separately formed on a substrate 6021. A liquid crystal display panel in which the formed pixel portion 6022 and a signal line driver circuit 6023 are connected The pixel portion 6022 and the scanning line driver circuit 6024 are formed by using a microcrystalline semiconductor film as a channel. The signal line driver circuit 6023 is formed using the thin film transistor used in the panel formation region. The pixel section 6022 is connected to the signal line driver 6025. The power supply potential, various signals, etc. are supplied to the driving circuit 6023 and the scanning line driving circuit 6024. Supplied via FPC6025.

[0173] Further, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed using a microcrystalline semiconductor film. The thin film transistor used in the channel forming region is formed on the same substrate as the pixel portion, and the rest It may be formed separately and electrically connected to the pixel portion. The analog switch 6033a of the circuit is connected to the pixel portion 6032 and the scanning line driver circuit 6034. The signal line driver circuit is formed on the same substrate 6031 as the shift register 6033b. The pixel area 6032 shows the configuration of a liquid crystal display panel formed on different substrates and bonded together. The scanning line driver circuit 6034 is a thin film transistor using a microcrystalline semiconductor film in a channel formation region. The shift register 6033b of the signal line driver circuit is formed by using an FPC The pixel portion 6032 is connected to the signal line driver circuit 6035. and the scanning line driver circuit 6034, the potential of the power supply, various signals, etc. are respectively connected to the FPC 6035. Supplied via.

[0174] As shown in FIG. 12, the liquid crystal display device of the present invention has a structure in which a part or all of the driving circuit is provided in the pixel section. A thin film transistor using a microcrystalline semiconductor film in a channel formation region is used on the same substrate as the It can be formed.

[0175] The method for connecting the separately formed substrate is not particularly limited, and may be a known COG method. The method of connection may be a wire bonding method, a TAB method, or the like. The positions are not limited to those shown in FIG. 12, as long as electrical connection is possible. Alternatively, a controller, a CPU, a memory, etc. may be separately formed and connected.

[0176] The signal line driver circuit used in the present invention has only a shift register and an analog switch. In addition to shift registers and analog switches, buffers, level shifters, It may have other circuits such as a gate, a source follower, etc. It is not necessary to provide a switching switch. For example, a decoder circuit may be used instead of a shift register. You can use another circuit that can select the signal line like this, or instead of an analog switch A latch or the like may also be used.

[0177] A block diagram of a liquid crystal display device of the present invention is shown in FIG. A pixel section 700 having a plurality of pixels each having a liquid crystal element, and a scanning line driving circuit 70 for selecting each pixel. 2 and a signal line driver circuit 703 that controls the input of a video signal to a selected pixel. .

[0178] In FIG. 30, a signal line driving circuit 703 includes a shift register 704 and an analog switch 707. The shift register 704 has a clock signal (CLK), a start pulse The clock signal (CLK) and start pulse signal (SP) are input. ) is input, a timing signal is generated in the shift register 704, and an analog The signal is input to switch 705 .

[0179] A video signal is also applied to the analog switch 705. The analog switch 705 outputs the video signal in accordance with the input timing signal. The signal is sampled and supplied to the signal line of the subsequent stage.

[0180] Next, the configuration of the scanning line driving circuit 702 will be described. The device has a level shifter 706 and a buffer 707. In the scanning line driver circuit 702, a clock signal is input to the shift register 706. The selection signal is generated by inputting the (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer 707 and is applied to the corresponding scanning line. The gates of the transistors of one line of pixels are connected to the scan line. And because the transistors of the pixels in one line must all be turned on at once, The ferroelectric capacitor 707 is capable of passing a large current.

[0181] A full-color LCD display device receives video signals corresponding to R (red), G (green), and B (blue). , and supplies the samples to the corresponding signal lines. The number of terminals for connecting the analog switch 705 to the pixel section 7 This is equivalent to about one-third of the number of terminals required to connect the signal lines of the analog switch. By forming the analog switch 705 on the same substrate as the pixel section 700, the analog switch 705 can be connected to the pixel Compared to when the terminals are formed on a substrate different from the portion 700, the terminals used for connecting the separately formed substrate are This reduces the number of connections, reduces the probability of connection failure, and increases yield.

[0182] The scanning line driving circuit 702 in FIG. 30 includes a shift register 706 and a buffer 707. However, the scanning line driver circuit 702 may be configured with a shift register 706 .

[0183] It should be noted that the configuration shown in FIG. 30 is merely one mode of the liquid crystal display device of the present invention, and the signal lines The configuration of the drive circuit and the scanning line drive circuit is not limited to this.

[0184] Next, thin film transistors using microcrystalline semiconductor films with the same polarity in their channel formation regions are An embodiment of a shift register including the above will be described with reference to FIGS. 31 and 32. The shift register shown in FIG. 31 has a configuration of a shift register according to the present embodiment. The first flip-flop is composed of flip-flops (flip-flops 701-1 to 701-n). The first clock signal, the second clock signal, the start pulse signal, and the reset signal are input. It works.

[0185] The connection relationship of the shift register in Fig. 31 will be explained. The shift register in Fig. 31 has i-stage The first flip-flop 701-i (one of the flip-flops 701-1 to 701-n) In either case, the first wiring 501 shown in FIG. 32 is connected to the seventh wiring 717-i-1, The second wiring 502 shown in FIG. 32 is connected to the seventh wiring 717-i+1, and the The third wiring 503 is connected to the seventh wiring 717-i, and the sixth wiring 50 shown in FIG. 6 is connected to the fifth wiring 715.

[0186] In addition, the fourth wiring 504 shown in FIG. 32 is connected to the second wiring 7 in the odd-numbered flip-flops. 12, and in the even-numbered flip-flops, it is connected to the third wiring 713, and The fifth wiring 505 shown in FIG.

[0187] However, the first wiring 501 shown in FIG. 32 of the first stage flip-flop 701-1 is The second wiring 711 is connected to the n-th stage flip-flop 701-n shown in FIG. 502 is connected to the sixth wiring 716 .

[0188] The first wiring 711, the second wiring 712, the third wiring 713, and the sixth wiring 716 are They may be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 714 and the fifth wiring 715 are respectively connected to the first power supply line and the second power supply line. You can call.

[0189] Next, the details of the flip-flop shown in FIG. 31 are shown in FIG. 32. The flip-flop includes a first thin film transistor 171, a second thin film transistor 172, a third thin film transistor 173, and a the first thin film transistor 173, the fourth thin film transistor 174, the fifth thin film transistor 1 75, the sixth thin film transistor 176, the seventh thin film transistor 177 and the eighth thin film transistor In this embodiment, the first thin film transistor 171 and the second thin film transistor 178 are The second thin film transistor 172, the third thin film transistor 173, and the fourth thin film transistor 174, the fifth thin film transistor 175, the sixth thin film transistor 176, the seventh thin film transistor The eighth thin film transistor 177 and the eighth thin film transistor 178 are n-channel transistors. When the gate-source voltage (Vgs) exceeds the threshold voltage (Vth), the transistor becomes conductive. It shall be as follows.

[0190] Next, the connection configuration of the flip-flop shown in FIG. 32 will be described below.

[0191] The first electrode (either the source electrode or the drain electrode) of the first thin film transistor 171 is The second electrode (source electrode) of the first thin film transistor 171 is connected to the fourth wiring 504. The other of the drain electrodes is connected to a third wiring 503 .

[0192] The first electrode of the second thin film transistor 172 is connected to the sixth wiring 506, and the second thin film A second electrode of the transistor 172 is connected to a third wiring 503 .

[0193] The first electrode of the third thin film transistor 173 is connected to the fifth wiring 505, and the The second electrode of the transistor 173 is connected to the gate electrode of the second thin film transistor 172. The gate electrode of the third thin film transistor 173 is connected to a fifth wiring 505 .

[0194] The first electrode of the fourth thin film transistor 174 is connected to the sixth wiring 506, and the fourth thin film The second electrode of the transistor 174 is connected to the gate electrode of the second thin film transistor 172. The gate electrode of the fourth thin film transistor 174 is connected to the gate electrode of the first thin film transistor 171. connected to the ground electrode.

[0195] The first electrode of the fifth thin film transistor 175 is connected to the fifth wiring 505, and the fifth thin film The second electrode of the transistor 175 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the fifth thin film transistor 175 is connected to the first wiring 501 .

[0196] The first electrode of the sixth thin film transistor 176 is connected to the sixth wiring 506, and the sixth thin film The second electrode of the transistor 176 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the sixth thin film transistor 176 is connected to the gate electrode of the second thin film transistor 172. connected to the ground electrode.

[0197] The first electrode of the seventh thin film transistor 177 is connected to the sixth wiring 506, and the The second electrode of the transistor 177 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the seventh thin film transistor 177 is connected to the second wiring 502. The first electrode of the thin film transistor 178 is connected to the sixth wiring 506, and the eighth thin film transistor a second electrode of the second thin film transistor 178 connected to the gate electrode of the second thin film transistor 172; The gate electrode of the eighth thin film transistor 178 is connected to the first wiring 501 .

[0198] The gate electrode of the first thin film transistor 171 and the gate electrode of the fourth thin film transistor 174 are a first electrode of the fifth thin film transistor 175; a second electrode of the sixth thin film transistor 176; The connection point of the second electrode of the seventh thin film transistor 177 and the second electrode of the seventh thin film transistor 178 is the node 143. Furthermore, the gate electrode of the second thin film transistor 172, the gate electrode of the third thin film transistor The second electrode of the fourth thin film transistor 173, the second electrode of the sixth thin film transistor 174, The connection point of the gate electrode of the eighth thin film transistor 176 and the second electrode of the eighth thin film transistor 178 is The code is 144.

[0199] The first wiring 501, the second wiring 502, the third wiring 503, and the fourth wiring 504 are , may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Furthermore, the fifth wiring 505 may be called the first power supply line and the sixth wiring 506 may be called the second power supply line. good.

[0200] FIG. 33 shows an example of a top view of the flip-flop shown in FIG.

[0201] The conductive film 901 includes a portion that functions as a first electrode of the first thin film transistor 171. , and is connected to the fourth wiring 504 via a wiring 951 formed at the same time as the pixel electrode.

[0202] The conductive film 902 includes a portion that functions as a second electrode of the first thin film transistor 171. The pixel electrode is connected to the third wiring 503 via a wiring 952 formed at the same time as the pixel electrode.

[0203] The conductive film 903 is a gate electrode of the first thin film transistor 171 and a gate electrode of the fourth thin film transistor 172. The gate electrode of the gate electrode 174 is included.

[0204] The conductive film 904 is a first electrode of the second thin film transistor 172, a second electrode of the sixth thin film transistor a first electrode of the fourth thin film transistor 174; a first electrode of the eighth thin film transistor 176; The sixth wiring 506 includes a portion that functions as the first electrode of the transistor 178. .

[0205] The conductive film 905 includes a portion that functions as a second electrode of the second thin film transistor 172. The pixel electrode is connected to the third wiring 503 via a wiring 954 formed at the same time as the pixel electrode.

[0206] The conductive film 906 is a gate electrode of the second thin film transistor 172 and a gate electrode of the sixth thin film transistor 173. The gate electrode of the gate electrode 176 is included.

[0207] The conductive film 907 includes a portion that functions as a first electrode of the third thin film transistor 173. , and is connected to the fifth wiring 505 via wiring 955.

[0208] The conductive film 908 is a second electrode of the third thin film transistor 173 and a second electrode of the fourth thin film transistor 174. The wiring 9 includes a portion that functions as the second electrode of the pixel electrode 174 and is formed at the same time as the pixel electrode. It is connected to the conductive film 906 via 56.

[0209] The conductive film 909 includes a portion that functions as a gate electrode of the third thin film transistor 173. , and is connected to the fifth wiring 505 via wiring 955.

[0210] The conductive film 910 includes a portion that functions as a first electrode of the fifth thin film transistor 175. , and is connected to the fifth wiring 505 via a wiring 959 formed at the same time as the pixel electrode.

[0211] The conductive film 911 is a second electrode of the fifth thin film transistor 175 and a second electrode of the seventh thin film transistor 176. The wiring 9 includes a portion that functions as the second electrode of the pixel electrode 177 and is formed at the same time as the pixel electrode. It is connected to the conductive film 903 via 58.

[0212] The conductive film 912 includes a portion that functions as a gate electrode of the fifth thin film transistor 175. , and is connected to the first wiring 501 via a wiring 960 formed at the same time as the pixel electrode.

[0213] The conductive film 913 includes a portion that functions as a second electrode of the sixth thin film transistor 176. The pixel electrode is connected to the conductive film 903 via a wiring 957 formed at the same time as the pixel electrode.

[0214] The conductive film 914 includes a portion that functions as a gate electrode of the seventh thin film transistor 177. , and is connected to the second wiring 502 via a wiring 962 formed at the same time as the pixel electrode.

[0215] The conductive film 915 includes a portion that functions as a gate electrode of the eighth thin film transistor 178. The pixel electrodes are connected to the conductive film 912 via wirings 961 formed at the same time as the pixel electrodes.

[0216] The conductive film 916 includes a portion that functions as a second electrode of the eighth thin film transistor 178. The pixel electrode is connected to the conductive film 906 via a wiring 953 formed at the same time as the pixel electrode.

[0217] Note that parts of the microcrystalline semiconductor films 981 to 988 are the first to eighth thin film transistors, respectively. The thin film transistor functions as a channel forming region.

[0218] The circuits shown in FIGS. 30 to 32 are formed by thin film transistors using a microcrystalline semiconductor in a channel formation region. By configuring the circuit with transistors, it is possible to operate the circuit at high speed. The cases where an amorphous semiconductor film is used for the channel formation region and where a microcrystalline semiconductor film is used for the channel formation region are shown. When compared with the case where a microcrystalline semiconductor film is used for the channel formation region, Since the field effect mobility of the transistor is large, the transistor This makes it possible to increase the driving frequency of the scanning line driving circuit 702. Since it can operate at high speed, it is possible to increase the frame frequency or It is also possible to realize insertion and the like.

[0219] When increasing the frame frequency, the screen data is generated according to the direction of the image movement. In other words, it is desirable to perform motion compensation and interpolate the data. In addition, by increasing the frame frequency and interpolating image data, the display characteristics of moving images are improved. For example, double the frequency (for example, 120 Hz, 100 Hz) and display a smoother image. Hz) or more, and more preferably four times (for example, 480 Hz, 400 Hz) or more. This reduces blurring and afterimages in moving images. The circuit 702 can also be operated at a higher drive frequency to increase the frame frequency. This can be done.

[0220] When inserting a black screen, image data or data for black display is supplied to the pixel unit 700. As a result, it becomes similar to impulse driving, and afterimages can be reduced. In this case, the scanning line driving circuit 702 is also operated at a higher driving frequency. This allows you to insert a black screen.

[0221] Furthermore, the channel width of the thin film transistor of the scanning line driving circuit 702 can be increased, and multiple By arranging a number of scanning line driving circuits, a higher frame frequency can be achieved. For example, a frame rate of 8 times (e.g., 960 Hz, 800 Hz) or more When a plurality of scanning line driving circuits are arranged, the scanning lines of even rows are driven by the The scanning line driving circuit for driving the odd-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the other side. By placing it on the opposite side, it is possible to achieve a higher frame frequency. For example, the channel width of the second thin film transistor 172 is 300 μm or more. More preferably, it is 1000 μm or more.

[0222] Note that the circuits shown in FIGS. 30 to 32 can be implemented by using a microcrystalline semiconductor in a channel formation region. By using thin film transistors, the layout area can be reduced. For this reason, the frame of the liquid crystal display device can be made smaller. Comparison of the case where a semiconductor film is used in the channel formation region and the case where a microcrystalline semiconductor film is used in the channel formation region Then, when a microcrystalline semiconductor film is used for a channel formation region, the current of the thin film transistor is higher. The large field effect transfer allows the channel width of thin film transistors to be reduced. As a result, it is possible to narrow the frame of the liquid crystal display device. The channel width of the transistor 172 is 3000 μm or less, more preferably 2000 μm or less. It is desirable that it is below.

[0223] 32, the second thin film transistor 172 is connected to the third wiring 503 at a low level. During this period, the second thin film transistor 172 is always in an on state. Therefore, a strong stress is applied to the second thin film transistor 172. This makes the transistor characteristics more susceptible to deterioration. The voltage gradually increases, and as a result, the current decreases. A second thin-film transistor is used to ensure sufficient current can be supplied even if the first transistor deteriorates. It is desirable that the channel width of the transistor 172 is large. It is desirable that the second thin film transistor is compensated for so as not to impede the circuit operation. A transistor is arranged in parallel with the second thin film transistor 172 and is connected to the second thin film transistor 172. It is desirable to make them less susceptible to deterioration by making them turn on at the same time. stomach.

[0224] However, there is a difference between the case where an amorphous semiconductor film is used for the channel formation region and the case where a microcrystalline semiconductor film is used for the channel formation region. When compared with the case where a microcrystalline semiconductor film is used for the channel formation region, Therefore, when a microcrystalline semiconductor film is used for a channel formation region, In this case, the channel width of the thin film transistor can be reduced. It can operate normally without the need for a compensation circuit. The area required for the gate can be reduced.

[0225] Next, the appearance and cross section of a liquid crystal display panel corresponding to one embodiment of the liquid crystal display device of the present invention will be described. 29A shows a microcrystal formed on a first substrate 4001. A thin film transistor 4010 having a crystalline semiconductor film and a liquid crystal element 4013 are mounted on the second substrate 40. 29(B) is a top view of the panel sealed with a sealant 4005 between the panel and the substrate 106. corresponds to a cross-sectional view taken along line AA' in FIG. 29(A).

[0226] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealing material 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driving circuit 4004 is a circuit board including a first substrate 4001, a sealing material 4005, and a second substrate 400. 6, the liquid crystal 4008 is sealed together with the sealant 4001. In a region different from the region surrounded by the material 4005, a polycrystalline silicon layer is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film is mounted. and a signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film in a channel formation region. 4001 is attached to the first substrate 4001. A signal line driver circuit may be formed using the transistors used in the formation region and then bonded together. In FIG. 29, a thin film formed of a polycrystalline semiconductor film included in the signal line driver circuit 4003 is Transistor 4009 is shown as an example.

[0227] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 29(B), the thin film transistor included in the pixel portion 4002 The thin film transistor 4010 is a thin film transistor using a microcrystalline semiconductor film. This corresponds to the thin film transistor used in the channel formation region.

[0228] The pixel electrode 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The liquid crystal element 4013 is electrically connected to the counter electrode 403 through a line 4040. 1 is formed on the second substrate 4006. The pixel electrode 4030, the counter electrode 4031 and the liquid crystal display The portion where the liquid crystal 4008 overlaps corresponds to the liquid crystal element 4013 .

[0229] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically Stainless steel, ceramics, and plastics can be used. is a FRP (Fiberglass-Reinforced Plastics) plate, P VF (Polyvinyl fluoride) film, polyester film, polyester film Aluminum foil or acrylic resin film can be used. A sheet sandwiched between F films or polyester films can also be used.

[0230] The spherical spacer 4035 is arranged to reduce the distance between the pixel electrode 4030 and the counter electrode 4031. The insulating film is selectively etched to control the cell gap. Alternatively, a spacer obtained by the above method may be used.

[0231] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section Various signals and potentials given to 4002 are transmitted through wirings 4014 and 4015. Powered by FPC4018.

[0232] In this embodiment, the connection terminal 4016 is connected to the pixel electrode 4030 of the liquid crystal element 4013. The lead wirings 4014 and 4015 are formed from the same conductive film as the wiring 40. It is formed of the same conductive film as 40.

[0233] The connection terminal 4016 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0234] Although not shown, the liquid crystal display device shown in this embodiment has an alignment film and a polarizing plate. Furthermore, a color filter and a shielding film may be provided.

[0235] In addition, in FIG. 29, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0236] This embodiment can be implemented in combination with the configurations described in other embodiments. be.

[0237] (Fourth embodiment) The liquid crystal display device obtained by the present invention is used to manufacture an active matrix liquid crystal module. That is, the present invention can be applied to all electronic devices that incorporate such a display unit. can.

[0238] Such electronic devices include cameras such as video cameras and digital cameras, head-mounted cameras, displays (goggle-type displays), car navigation systems, projectors, car Stereos, personal computers, personal digital assistants (mobile computers, mobile phones, etc.) Examples of such applications are shown in Figure 13.

[0239] FIG. 13(A) is a television device. The display module is as shown in FIG. The TV set can be completed by installing it in a housing. The display panel is also called a display module. 03 is formed, and other accessories include a speaker unit 2009 and an operation switch. In this way, the television device can be completed.

[0240] As shown in FIG. 13(A), a display panel 2002 using a liquid crystal element is mounted on a housing 2001. The receiver 2005 can receive general television broadcasts, and the modem 2004 By connecting to a wired or wireless communication network via It can also be used for two-way (between sender and receiver, or between receivers) information communication. The television set can be operated using a switch built into the housing or a separate remote control. This can be done by the remote control device 2006, and the information to be output is also displayed on this remote control device. A display unit 2007 may also be provided.

[0241] In addition to the main screen 2003, the television device also has a sub-screen 2008 for second display. It may be formed of a panel and may have a configuration for displaying the channel, volume, etc. The main screen 2003 is formed of a liquid crystal display panel with an excellent viewing angle, and the sub-screen is formed of a low-power It may be formed of a liquid crystal display panel that can display with electricity. In order to do this, the main screen 2003 is formed by a liquid crystal display panel, and the sub-screen is formed by a liquid crystal display panel. The sub-screen may be configured to be able to blink.

[0242] FIG. 14 is a block diagram showing the main components of a television device. A pixel portion 921 is formed on the display panel 920. A signal line driver circuit 922 and a scanning line driver circuit 923 are connected to the display panel 920. The display panel 900 may be mounted using the COG method.

[0243] As for the configuration of other external circuits, on the video signal input side, a signal received by a tuner 924 A video signal amplifier circuit 925 amplifies the video signal, and the signal output from the video signal amplifier circuit 925 is converted into red. a video signal processing circuit 926 that converts the video signals into color signals corresponding to the colors 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 2 It has a control circuit 927 for converting the input specifications of the driver IC. The control circuit 927 outputs signals to the scanning line side and the signal line side. In this case, a signal dividing circuit 928 is provided on the signal line side to divide the input digital signal into m parts. It may also be configured to supply the power.

[0244] Of the signals received by the tuner 924, the audio signal is sent to an audio signal amplifier circuit 929. The output is supplied to a speaker 933 via an audio signal processing circuit 930. 1 receives control information for the receiving station (receiving frequency) and volume from an input unit 932, and A signal is sent to the audio signal processing circuit 930.

[0245] Of course, the present invention is not limited to television devices, and may be applied to monitors of personal computers. In addition, it is used for large-area displays such as information display boards at train stations and airports, and advertising display boards on the street. It can also be used for a variety of purposes as a display medium.

[0246] FIG. 13(B) shows an example of a mobile phone 2201. This mobile phone 2201 has a display The display unit 2202 includes an operation unit 2203. By applying the liquid crystal display device described in the above embodiment, mass productivity can be improved. do.

[0247] The portable computer shown in FIG. 13C includes a main body 2401, a display unit 2402, etc. The liquid crystal display device described in the above embodiment mode is applied to the display portion 2402. This allows for improved mass productivity. [Example]

[0248] A microcrystalline silicon film was formed, and the crystallinity of the film was measured by Raman spectroscopy. The results are shown in FIG.

[0249] The conditions for forming the microcrystalline silicon film were RF power frequency of 13.56 MHz and film formation temperature of 280 The temperature was set to ℃, the ratio of hydrogen flow rate to silane gas flow rate was set to 100:1, and the film was formed at a pressure of 280 Pa. FIG. 34(A) shows the Raman scattering spectrum, and the power of the RF power supply during film formation was The results are a comparison of a microcrystalline silicon film at 100W and a microcrystalline silicon film at 300W. do.

[0250] The crystal peak position of single crystal silicon is 521 cm -1 In addition, amorphous Of course, no crystal peaks could be measured for silicon, and as shown in Figure 34(B), 0cm -1 The microcrystalline silicon film in this specification is a film having a rough surface. 481cm measured by a spectrometer -1 More than 520cm -1 The crystal peak position can be seen below. It refers to something that...

[0251] The crystal peak position of the microcrystalline silicon film when the RF power supply power during film formation was 100 W was 518.6 cm -1 and the full width at half maximum (FWHM) is 11.9 cm -1 and crystalline / amorphous The peak intensity ratio (Ic / Ia) is 4.1.

[0252] In addition, the crystal peak position of the microcrystalline silicon film when the power of the RF power source during film formation was 300 W was 51 4.8cm -1 and the full width at half maximum (FWHM) is 18.7 cm -1 and crystalline / amorphous The first peak intensity ratio (Ic / Ia) is 4.4.

[0253] As shown in Figure 34(A), the crystal peak position and half-width vary greatly depending on the RF power. This is because high power increases ion bombardment and inhibits grain growth, resulting in a tendency for grain size to become small. This is thought to be due to the fact that the microcrystalline silicon film used in the measurement of FIG. Since the power frequency of the VD device is 13.56 MHz, the crystalline / amorphous peak intensity ratio ( Ic / Ia) is 4.1 or 4.4, but the RF power frequency is 27MHz. It was also confirmed that the crystalline / amorphous peak intensity ratio (Ic / Ia) can be set to 6 if Therefore, RF power frequencies higher than 27 MHz, e.g., 2.45 GHz, Hz RF power frequency, the crystalline / amorphous peak intensity ratio (Ic / I a) can be increased. [Example]

[0254] In this example, the transistor characteristics and electron density distribution of the thin film transistor according to the present invention are described. The results of device simulations are shown below. We use the device simulator "ATLAS" made by ilvaco.

[0255] The device structure is shown in Figure 35. The insulating substrate 2301 is mainly made of silicon oxide (dielectric constant 4.1). The thickness of the insulating substrate 2301 is assumed to be 0.5 μm. In actual manufacturing processes, 0.5mm, 0.7mm, etc. are often used, but insulating base The thickness is sufficient so that the electric field at the bottom surface of the plate 2301 does not affect the thin film transistor characteristics. is defined as follows.

[0256] A gate electrode 23 made of molybdenum (thickness: 150 nm) is formed on an insulating substrate 2301. The work function of molybdenum is 4.6 eV.

[0257] On the gate electrode 2303, a silicon nitride film (dielectric constant 7.0, thickness 110 nm) and a silicon oxynitride film are formed. A gate insulating film 2305 with a laminated structure and a base film (dielectric constant 4.1, thickness 110 nm) is laminated. There are.

[0258] A μc-Si film 2307 and an a-Si film 2309 are stacked on a gate insulating film 2305. Here, the product of the μc-Si film 2307 with a thickness of 0 nm and the a-Si film with a thickness of 100 nm is layer, a 10 nm thick μc-Si film 2307, and a 90 nm thick a-Si film 2309. layer, a 50 nm thick μc-Si film 2307, and a 50 nm thick a-Si film 2309. layer, a 90 nm thick μc-Si film 2307, and a 10 nm thick a-Si film 2309. layer, the product of the μc-Si film 2307 having a thickness of 100 nm and the a-Si film 2309 having a thickness of 0 nm Each layer has its own set of conditions.

[0259] The a-Si film 2309 is a first a-Si(n + ) film 2311 and the second a-Si(n + In the area overlapping with the a-Si film 2313, an additional 50 nm of a-Si film is formed in addition to the above thickness. That is, the first a-Si(n + ) film 2311 and the second a-Si(n + ) membrane 2 In the area where 313 is not formed, the a-Si film 2309 is partially etched by 50 nm. It has a concave shape.

[0260] On the a-Si film 2309, a first a-Si(n + ) film 2311 (thickness 50 nm) and the second a-Si(n + ) film 2313 (thickness: 50 nm) are laminated. In the transistor, the first a-Si(n + ) film 2311 and the second a-Si(n + )film The distance between the electrode 2313 and the channel length L is 6 μm. The channel width W is set to 15 μm.

[0261] First a-Si(n + ) film 2311 and the second a-Si(n + ) membrane 2313 and on top of it, The source electrode 2315 and the drain electrode 231 are made of Butan-Mo (thickness 300 nm). 7 are laminated on the source electrode 2315 and the first a-Si(n + ) membrane 2311, and the drain electrode 2317 and the second a-Si(n + ) film 2313 is ohmic It is defined as contact.

[0262] FIG. 36 shows the structure of the μc-Si film and the a-Si film in the thin film transistor shown in FIG. The DC characteristics (Vg-Id characteristics, Vd 37 shows the results of the μc-Si film 2307 with a thickness of 10 nm and a Figure 37 shows the electron concentration distribution of the thin film transistor when the thickness of the -Si film is 90 nm. (A) shows the electron concentration distribution when the thin film transistor is in the on state (Vg is +10 V, Vd is 14 V). Figure 37(B) shows the electron concentration in the off state (Vg is -10 V, Vd is 14 V). The distribution results are shown.

[0263] From FIG. 36, it can be seen that the off-current decreases as the thickness of the a-Si film increases. In addition, by making the thickness of the a-Si film 50 nm or more, the drain current when Vg is -20 V is The current is 1×10 -13 It can be less than A.

[0264] It can also be seen that the on-current increases as the thickness of the μc-Si film increases. By making the μc-Si film thicker than 10 nm, the drain current at Vg of 20 V is Flow 1×10 -5 It can be A or higher.

[0265] As can be seen from FIG. 37(A), in the on-state, the electron density is higher in the μc-Si film than in the a-Si film. In other words, the electron density is high in the μc-Si film, which has high electrical conductivity. Therefore, in the on state, electrons flow easily and the drain current increases.

[0266] As shown in FIG. 37(B), in the off state, the electron density is higher in the a-Si film than in the μc-Si film. In other words, the electron density is high in the a-Si film with low electrical conductivity. In the off state, electrons do not flow easily, and the thin film using the a-Si film for the channel formation region It can be seen that the drain current is the same as that of a transistor.

[0267] From the above, as shown in Figure 35, a μc-Si film is formed on the gate insulating film, and μc a-Si is formed on the -Si film, and a source region and a drain region are formed on the a-Si film. The thin film transistor can reduce the off-current and increase the on-current. It can be seen that...

Claims

[Claim 1] a gate electrode; a gate insulating film formed on the gate electrode; a microcrystalline semiconductor film formed on the gate insulating film; a buffer layer formed on the microcrystalline semiconductor film and having a recess; a source region and a drain region formed on the buffer layer; a source electrode and a drain electrode in contact with the source region and the drain region, the source electrode and the drain electrode do not overlap with edges of the microcrystalline semiconductor film and the source region and the drain region, 10. A liquid crystal display device comprising a thin film transistor, wherein ends of the source region and drain region overlapping the gate electrode are aligned with the side surfaces of the recessed portion of the buffer layer.

Images