Semiconductor Devices

Abstract

A semiconductor device with a simplified manufacturing process is provided. [Solution] The present invention relates to a semiconductor device, and more specifically, includes a substrate including a logic cell region and a peripheral region around the logic cell region, a logic element including source and drain patterns on the logic cell region of the substrate, an upper active contact on the source and drain patterns connected to one of the source and drain patterns, a lower active contact below the source and drain patterns connected to another of the source and drain patterns, a conductive structure penetrating the peripheral region of the substrate, peripheral upper wiring above the peripheral region of the substrate connected to the conductive structure, and peripheral lower wiring below the peripheral region of the substrate connected to the conductive structure, and a lower surface of the conductive structure may be located at a lower level than a lower surface of the lower active contact.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a field effect transistor. [Background technology]

[0002] Semiconductor devices include integrated circuits configured with MOS (Metal Oxide Semiconductor) field effect transistors (FETs). As the size and design rules of semiconductor devices continue to shrink, the scale down of MOS field effect transistors is also accelerating. As the size of MOS field effect transistors shrinks, the operating characteristics of semiconductor devices may deteriorate. Therefore, various methods are being researched to overcome the limitations of high integration of semiconductor devices and to form semiconductor devices with better performance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Registration No. 11,961,802 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device whose manufacturing process is simplified.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. [Means for solving the problem]

[0006] A semiconductor device according to some embodiments of the present invention includes a substrate including a logic cell region and a peripheral region around the logic cell region; a logic element including source and drain patterns on the logic cell region of the substrate; an upper active contact on the source and drain patterns connected to one of the source and drain patterns; a lower active contact below the source and drain patterns connected to another of the source and drain patterns; a conductive structure penetrating the peripheral region of the substrate; a peripheral upper wiring above the peripheral region of the substrate connected to the conductive structure; and a peripheral lower wiring below the peripheral region of the substrate connected to the conductive structure, wherein a lower surface of the conductive structure may be located at a lower level than a lower surface of the lower active contact.

[0007] A semiconductor device according to some embodiments of the present invention includes a substrate including a logic cell region and a peripheral region around the logic cell region; source and drain patterns on the logic cell region of the substrate; a channel pattern between the source and drain patterns, the channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a gate electrode on the channel pattern; a gate capping pattern on an upper surface of the gate electrode; a first interlayer insulating film covering the source and drain patterns on an upper surface of the substrate; a second interlayer insulating film covering an upper surface of the first interlayer insulating film and an upper surface of the gate capping pattern; a third interlayer insulating film covering a lower surface of the substrate; a first insulating layer and a second insulating layer covering an upper surface of the second interlayer insulating layer and stacked in sequence; a first insulating layer and a second insulating layer covering a lower surface of the third interlayer insulating layer and stacked in sequence; a conductive structure penetrating the peripheral region of the substrate and the first insulating layers; a peripheral upper wiring penetrating the first and second upper insulating layers above the peripheral region and connected to the conductive structure; and a peripheral lower wiring penetrating the first, second, and third lower insulating layers below the peripheral region and connected to the conductive structure, wherein the conductive structure may at least partially penetrate the first upper insulating layer and the first lower insulating layer.

[0008] A semiconductor device according to some embodiments of the present invention includes a redistribution substrate and first and second semiconductor chips stacked vertically on the redistribution substrate, the first semiconductor chip including: a substrate including a logic cell region and a peripheral region around the logic cell region; source and drain patterns on the logic cell region of the substrate; a channel pattern between the source and drain patterns, the channel pattern including a plurality of semiconductor patterns stacked apart from each other; upper active contacts on the source and drain patterns connected to one of the source and drain patterns; lower active contacts below the source and drain patterns connected to another of the source and drain patterns; a conductive structure penetrating the peripheral region of the substrate; peripheral upper wiring connected to the conductive structure on the peripheral region of the substrate; and peripheral lower wiring connected to the conductive structure below the peripheral region of the substrate, and the conductive structure, the peripheral upper wiring, and the peripheral lower wiring can electrically connect the redistribution substrate and the second semiconductor chip. [Effects of the Invention]

[0009] A semiconductor device according to an embodiment of the present invention may include a conductive structure penetrating a peripheral region of a substrate. The conductive structure may be connected to a peripheral upper interconnection on the peripheral region and a peripheral lower interconnection below the peripheral region. In other words, the peripheral upper interconnection, the conductive structure, and the peripheral lower interconnection may be electrically connected to each other and may penetrate vertically through the semiconductor device, thereby performing the role of a through silicon via (TSV). That is, according to an embodiment of the present invention, a process for forming a through via that penetrates vertically through the semiconductor device may be omitted. Since the conductive structure may be formed together with the process of forming interconnections on the backside of the semiconductor device, the manufacturing process may be simplified. [Brief explanation of the drawings]

[0010] [Figure 1] 1 and 2 are conceptual diagrams for explaining a semiconductor device according to an embodiment of the present invention. [Figure 2] 1 and 2 are conceptual diagrams for explaining a semiconductor device according to an embodiment of the present invention. [Figure 3] 1 is a plan view illustrating a semiconductor device according to some embodiments of the present invention; [Figure 4] FIG. 4 is a plan view showing in detail the logic cell and the peripheral region of FIG. [Figure 5A] FIG. 5 is a cross-sectional view taken along line AA' in FIG. [Figure 5B] FIG. 5 is a cross-sectional view taken along line BB' in FIG. [Figure 5C] FIG. 5 is a cross-sectional view taken along line CC' in FIG. [Figure 5D] FIG. 5 is a cross-sectional view taken along the line DD' in FIG. [Figure 5E] FIG. 5 is a cross-sectional view taken along line EE' in FIG. [Figure 6] 5B is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention, and corresponds to FIG. 5E. FIG. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. [Figure 8] FIG. 8 is an enlarged view showing a portion P1 in FIG. 7. [Figure 9A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11D] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13D] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14D] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14E] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15D] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15E] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16D] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16E] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17A] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17B] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17C] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17D] 9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17E]9A to 17E are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0012] 1 and 2 are conceptual diagrams for explaining a semiconductor device according to an embodiment of the present invention.

[0013] 1, a single height cell (SHC) may be provided. A first power wiring M1_R1 and a second power wiring M1_R2 may be provided on a substrate 100. For example, the first power wiring M1_R1 may be a path through which a source voltage or a ground voltage is provided. The second power wiring M1_R2 may be a path through which a drain voltage or a power voltage is provided.

[0014] A single-height cell SHC may be defined between the first power wiring M1_R1 and the second power wiring M1_R2. The single-height cell SHC may include a first active region AR1 and a second active region AR2. For example, one of the first active region AR1 and the second active region AR2 may be a PMOSFET region. The other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. In other words, the single-height cell SHC may have a CMOS structure provided between the first power wiring M1_R1 and the second power wiring M1_R2.

[0015] Each of the first active region AR1 and the second active region AR2 may have a first width W1 in a first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first power wiring M1_R1 and the second power wiring M1_R2.

[0016] The single-height cell SHC can constitute one logic cell. As used herein, a logic cell can refer to a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell can include transistors for constituting the logic element and wiring that connects the transistors to each other.

[0017] 2, a double height cell (DHC) may be provided. A first power wiring M1_R1, a second power wiring M1_R2, and a third power wiring M1_R3 may be provided on a substrate 100. The first power wiring M1_R1 may be disposed between the second power wiring M1_R2 and the third power wiring M1_R3. For example, the third power wiring M1_R3 may be a path through which a source voltage is provided.

[0018] A double-height cell DHC may be defined between the second power wiring M1_R2 and the third power wiring M1_R3, and may include two first active regions AR1 and two second active regions AR2.

[0019] The first active region AR1 may be adjacent to the first power wiring M1_R1. One of the second active regions AR2 may be adjacent to the second power wiring M1_R2. The other of the second active regions AR2 may be adjacent to the third power wiring M1_R3. In a plan view, the first power wiring M1_R1 may be located between two first active regions AR1.

[0020] The length of the double-height cell DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be approximately twice the first height HE1 of FIG. 1. For example, the first active regions AR1 of the double-height cell DHC may be bundled together to operate as a single PMOSFET region. Therefore, the channel size of the PMOS transistor of the double-height cell DHC may be larger than the channel size of the PMOS transistor of the single-height cell SHC of FIG. 1.

[0021] For example, the channel size of the PMOS transistor of the double-height cell DHC can be approximately twice the channel size of the PMOS transistor of the single-height cell SHC, which allows the double-height cell DHC to operate at a higher speed than the single-height cell SHC.

[0022] In this specification, the double-height cell DHC shown in Figure 2 can be defined as a multi-height cell. Although not shown in the drawing, the multi-height cell can include a triple-height cell whose cell height is approximately three times that of the single-height cell SHC.

[0023] Fig. 3 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. Fig. 4 is a plan view showing in detail a logic cell and a peripheral region of Fig. 3. Figs. 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' in Fig. 4, respectively.

[0024] 3 and 4, a first semiconductor chip 10 according to the present invention may include a substrate 100. The substrate 100 may include a logic cell region LCR and a peripheral region PR surrounding the logic cell region LCR. A plurality of logic cells LC may be disposed on the logic cell region LCR. For example, the logic cells LC may be the single-height cells SHC described with reference to FIG. 1. Logic elements constituting a logic circuit may be disposed on the logic cells LC. The peripheral region PR refers to a region surrounding the logic cell region LCR and may be, for example, an edge portion of the substrate 100. Conductive structures BP may be disposed on the peripheral region PR. The conductive structures BP may be spaced apart from each other along first and second directions D1 and D2 parallel to the bottom surface of the substrate 100 in a plan view. Although the conductive structures BP are arranged along a rectangular frame in FIG. 3, this is not limiting and the arrangement of the conductive structures BP may be freely changed. The substrate 100 may be a semiconductor substrate containing silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate.

[0025] 4 and 5A to 5E, logic elements may be disposed on a logic cell region LCR (or logic cell (LC in FIG. 3)) of the substrate 100. The logic elements may include channel patterns CH1 and CH2, source / drain patterns SD1 and SD2, and a gate electrode GE, which will be described later. The logic cell region LCR may include a first active region AR1 and a second active region AR2. Each of the first and second active regions AR1 and AR2 may extend in a second direction D2. For example, the first active region AR1 may be a PMOSFET region, and the second active region AR2 may be an NMOSFET region. In this specification, the first direction D1 and the second direction D2 may refer to directions parallel to the bottom surface 100L of the substrate 100, and the third direction D3 may refer to a direction perpendicular to the bottom surface 100L of the substrate 100.

[0026] The substrate 100 may include a first active pattern AP1 on the first active region AR1 and a second active pattern AP2 on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 may be defined by trenches TR formed in the substrate 100. The first and second active patterns AP1 and AP2 may extend in a second direction D2.

[0027] An isolation layer ST may be provided between the first and second active patterns AP1 and AP2. The isolation layer ST may fill the trench TR. A lower surface STL of the isolation layer ST may be coplanar with the lower surfaces of the first and second active patterns AP1 and AP2. That is, the lower surface STL of the isolation layer ST may be located at the same level as the lower surface 100L of the substrate 100. For example, the isolation layer ST may include a silicon oxide layer. The isolation layer ST may not cover the first and second channel patterns CH1 and CH2, which will be described later.

[0028] A first channel pattern CH1 may be provided on the first active pattern AP1. A second channel pattern CH2 may be provided on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are stacked in order. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (e.g., a third direction D3).

[0029] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon, more specifically, single-crystal silicon. Alternatively, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0030] A plurality of first source / drain patterns SD1 may be provided on the first active pattern AP1. A plurality of first recesses RS1 may be formed on the first active pattern AP1. Each of the first source / drain patterns SD1 may be provided in the first recess RS1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., n-type). A first channel pattern CH1 may be located between adjacent first source / drain patterns SD1 in the second direction D2. For example, stacked first to third semiconductor patterns SP1, SP2, and SP3 of the first channel pattern CH1 may connect adjacent first source / drain patterns SD1 in the second direction D2 to each other.

[0031] A plurality of second source / drain patterns SD2 may be provided on the second active pattern AP2. A plurality of second recesses RS2 may be formed on the second active pattern AP2. Each of the second source / drain patterns SD2 may be provided in the second recess RS2. The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., p-type). A second channel pattern CH2 may be located between adjacent second source / drain patterns SD2 in the second direction D2. For example, stacked first to third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 may connect adjacent second source / drain patterns SD2 in the second direction D2 to each other.

[0032] The first and second source / drain patterns SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the top surface of each of the first and second source / drain patterns SD1 and SD2 may be higher than the top surface of the third semiconductor pattern SP3. As another example, the top surface of at least one of the first and second source / drain patterns SD1 and SD2 may be located at substantially the same level as the top surface of the third semiconductor pattern SP3.

[0033] The first source / drain patterns SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Therefore, the pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 therebetween. The second source / drain patterns SD2 may include the same semiconductor element (e.g., Si) as the substrate 100.

[0034] The first source / drain pattern SD1 may contain impurities (e.g., boron, gallium, or indium) to make it p-type. The impurity concentration of the first source / drain pattern SD1 may be 1E18 atoms / cm 3 ~5E22atom / cm 3 It could be.

[0035] Each of the second source / drain patterns SD2 may include silicon (Si). The second source / drain patterns SD2 may further include impurities (e.g., phosphorus, arsenic, or antimony) that cause the second source / drain patterns SD2 to have n-type conductivity. The impurity concentration of the second source / drain patterns SD2 is 1E18 atoms / cm. 3 ~5E22atom / cm 3 It could be.

[0036] Gate electrodes GE may be provided on the first and second channel patterns CH1 and CH2. Each of the gate electrodes GE may extend in a first direction D1 across the first and second channel patterns CH1 and CH2. Each of the gate electrodes GE may overlap the first and second channel patterns CH1 and CH2 in the vertical direction. The gate electrodes GE may be spaced apart from each other in a second direction D2.

[0037] Each of the gate electrodes GE may include a first inner electrode PO1 between the first and second active patterns AP1 and AP2 and the first semiconductor pattern SP1, a second inner electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer electrode PO4 on the third semiconductor pattern SP3.

[0038] The gate electrodes GE may be provided on the top, bottom, and sidewalls of each of the first to third semiconductor patterns SP1, SP2, and SP3. For example, the transistor of the present invention may be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrodes GE three-dimensionally surround the channel.

[0039] Inner spacers ISP may be provided between the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE and the second source / drain pattern SD2 on the second active region AR2. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the second source / drain pattern SD2 via the inner spacers ISP. The inner spacers ISP may prevent leakage current from the gate electrode GE.

[0040] A pair of gate spacers GS may be provided on both sidewalls of each outer electrode PO4 of the gate electrode GE. The gate spacers GS may extend in a first direction D1 along the gate electrode GE. For example, the gate spacers GS may include at least one of SiCN, SiCON, and SiN. Alternatively, the gate spacers GS may include a multi-layer structure including at least two of SiCN, SiCON, and SiN. For example, the gate spacers GS may include a Si-containing insulating material. The gate spacers GS may function as an etch stop layer when forming active contacts AC, which will be described later. The gate spacers GS allow the active contacts AC to be formed in a self-aligned manner.

[0041] A gate capping pattern GP may be provided on each of the gate electrodes GE. Each of the gate capping patterns GP may extend in a first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material having etch selectivity with respect to the first and second interlayer insulating layers 110 and 120, which will be described later. For example, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0042] A gate insulating film GI may be provided between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI may cover the top, bottom, and sidewalls of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI may cover the top surface of the isolation film ST below the gate electrode GE. For example, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, and / or a high-k film. Alternatively, the gate insulating film GI may have a stacked structure of a silicon oxide film and a high-k film. The high-k film may include a high-k material having a higher dielectric constant than a silicon oxide film. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0043] A first interlayer insulating film 110 may be provided on the substrate 100. The first interlayer insulating film 110 may cover sidewalls of the gate spacers GS and the first and second source / drain patterns SD1 and SD2 in the logic cell region LCR. The top surface of the first interlayer insulating film 110 may be substantially coplanar with the top surfaces of the gate capping patterns GP and the gate spacers GS, but is not limited thereto.

[0044] A second interlayer insulating film 120, a first upper insulating layer 130, and a second upper insulating layer 140 may be sequentially provided on the first interlayer insulating film 110. For example, the first and second interlayer insulating films 110 and 120 and the first and second upper insulating layers 130 and 140 may include silicon oxide films.

[0045] A pair of isolation structures DB may be provided on both sides of the logic cell LC, facing each other in the second direction D2. Each of the isolation structures DB may extend parallel to the gate electrode GE in the first direction D1. Each of the isolation structures DB may extend through the first interlayer insulating film 110 and the second interlayer insulating film 120 and into the first and second active patterns AP1 and AP2. The isolation structure DB may penetrate a portion of each of the first and second active patterns AP1 and AP2. The isolation structure DB may electrically isolate the logic cell LC from other adjacent cells (e.g., a logic cell and a tab cell).

[0046] Upper active contacts AC may be provided through the first interlayer insulating film 110 and the second interlayer insulating film 120 to be electrically connected to portions of the first and second source / drain patterns SD1 and SD2. In a plan view, each of the upper active contacts AC may have a bar shape extending in the first direction D1. For example, each of the upper active contacts AC may include a conductive pattern and a barrier pattern surrounding the conductive pattern. The barrier pattern may cover sidewalls and a bottom surface of the conductive pattern.

[0047] A metal-semiconductor compound layer SC may be provided between the upper active contact AC and the first source / drain pattern SD1 or between the upper active contact AC and the second source / drain pattern SD2. Each of the active contacts AC may be electrically connected to the first and second source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0048] Gate contacts GC may be provided through the second interlayer insulating film 120 and the gate capping pattern GP to be electrically connected to the gate electrode GE. Each of the gate contacts GC may include a conductive pattern and a barrier pattern surrounding the conductive pattern. For example, the gate contacts GC may have substantially the same structure as the upper active contact AC. In a plan view, each of the gate contacts GC may be disposed to overlap the first active region AR1 and the second active region AR2, respectively.

[0049] A first upper metal layer M1 and a second upper metal layer M2 may be disposed on the second interlayer insulating film 120, but the present invention is not limited thereto. For example, a plurality of additional upper metal layers may be stacked on the first and second upper metal layers M1 and M2. However, for ease of explanation, the present specification will be described based on a semiconductor device including only the first upper metal layer M1 and the second upper metal layer M2. Furthermore, the second upper metal layer M2 may refer to the uppermost upper metal layer among the plurality of upper metal layers M1 and M2.

[0050] The first and second upper metal layers M1 and M2 may include upper wirings M1_V, M1_I, M2_V, and M2_I located on the logic cell region LCR of the substrate 100, and peripheral upper wirings M1_I', M2_V', and M2_I' located on the peripheral region PR of the substrate 100. The upper wirings M1_V, M1_I, M2_V, and M2_I may be electrically connected to the upper active contacts AC and the gate contacts GC, and the peripheral upper wirings M1_I', M2_V', and M2_I' may be electrically connected to a conductive structure BP, which will be described later.

[0051] More specifically, the first upper metal layer M1 may be provided in the first upper insulating layer 130. The first upper metal layer M1 may include first upper wirings M1_I and M1_V provided on the logic cell region LCR and a first peripheral upper wiring M1_I' provided on the peripheral region PR. The first upper wirings M1_I and M1_V may include a first upper line pattern M1_I and a first upper via M1_V. The first peripheral upper wiring M1_I' may also be referred to as the first peripheral upper line pattern M1_I'.

[0052] The first upper line patterns M1_I may extend parallel to each other in the second direction D2, and may be spaced apart from each other along the first direction D1. The first upper vias M1_V may be disposed between the first upper line patterns M1_I and the upper active contacts AC and between the first upper line patterns M1_I and the gate contacts GC. For example, the first upper line patterns M1_I and the first upper vias M1_V thereunder may be formed together using a dual damascene process.

[0053] The second upper metal layer M2 may be provided in the second upper insulating layer 140. The second upper metal layer M2 may include second upper wirings M2_I and M2_V provided on the logic cell region LCR and second peripheral upper wirings M2_I' and M2_V' provided on the peripheral region PR. The second upper wirings M2_I and M2_V may include a second upper line pattern M2_I and a second upper via M2_V. The second peripheral upper wirings M2_I' and M2_V' may include a second peripheral upper line pattern M2_I' and a second peripheral upper via M2_V'.

[0054] The second upper line patterns M2_I may extend parallel to each other in the first direction D1 and may be spaced apart from each other in the second direction D2. The second upper via M2_V may be disposed between the second upper line pattern M2_I and the first upper line pattern M1_I. For example, the second upper line pattern M2_I and the second upper via M2_V thereunder may be formed together using a dual damascene process.

[0055] A power transmission network layer PDN may be provided on the lower surface 100L of the substrate 100. The power transmission network layer PDN may include, but is not limited to, first to third lower insulating layers 160, 170, and 180 and first to third lower metal layers LM1, LM2, and LM3 provided in the first to third lower insulating layers 160, 170, and 180, respectively. For example, the power transmission network layer PDN may include only the first and second lower metal layers LM1 and LM2, or an additional lower metal layer may be disposed on the lower surface of the third lower metal layer LM3. However, for ease of explanation, the present specification will be described assuming that the power transmission network layer PDN includes the first to third lower metal layers LM1, LM2, and LM3. Furthermore, the third lower metal layer LM3 may refer to the lowermost lower metal layer among the plurality of lower metal layers LM1, LM2, and LM3.

[0056] The first to third lower metal layers LM1, LM2, and LM3 may include lower wirings LM1_I, LM1_V, LM2_I, LM2_V, LM3_I, and LM3_V provided on the lower surface of the logic cell region LCR, and peripheral lower wirings LM1_I', LM2_V', LM2_I', LM3_V', and LM3_I' provided on the lower surface of the peripheral region PR, respectively. For example, the first lower metal layer LM1 provided in the first lower insulating layer 160 may include first lower wirings LM1_I and LM1_V arranged on the lower surface of the logic cell region LCR, and a first peripheral lower wiring LM1_I' arranged on the lower surface of the peripheral region PR. Similarly, the second and third lower metal layers LM2 and LM3 may each include second and third lower wirings LM2_I, LM2_V, LM3_I, and LM3_V arranged on the lower surface of the logic cell region LCR and second and third peripheral lower wirings LM2_I', LM2_V', LM3_I', and LM3_V' arranged on the lower surface of the peripheral region PR.

[0057] The first lower via LM1_V may be disposed between the first lower line pattern LM1_I and a lower active contact BAC (described later). For example, the first lower line pattern LM1_I and the first lower via LM1_V thereon may be formed together using a dual damascene process.

[0058] The second lower via LM2_V may be disposed between the first lower line pattern LM1_I and the second lower line pattern LM2_I to electrically connect them. Similarly, the third lower via LM3_V may be disposed between the second lower line pattern LM2_I and the third lower line pattern LM3_I to electrically connect them. For example, the second lower line pattern LM2_I and the second lower via LM2_V thereon, and the third lower line pattern LM3_I and the third lower via LM3_V thereon may be formed together using a dual damascene process.

[0059] The power transmission network layer PDN may include first and second power wirings VSS and VDD that apply a power voltage (e.g., a power supply or a ground voltage). The first and second power wirings VSS and VDD may extend parallel to each other in the second direction D2 and may be provided in the first to third lower insulating layers 160, 170, and 180. For example, the first and second power wirings VSS and VDD may be disposed in the third lower insulating layer 180 and may be electrically connected to the first to third lower wirings LM1_I, LM1_V, LM2_I, LM2_V, LM3_I, and LM3_V.

[0060] A third interlayer insulating film 150 may be provided between the substrate 100 and the power transmission network layer PDN. The interlayer insulating film 150 may be in contact with the lower surface 100L of the substrate 100 and the isolation film ST. For example, the third interlayer insulating film 150 and the first and second lower insulating layers 160 and 170 may include silicon oxide films.

[0061] Lower active contacts BAC may be provided, penetrating the third interlayer insulating film 150 and the substrate 100 and extending to the first and second source / drain patterns SD1 and SD2. The lower active contacts BAC may be connected to portions of the first and second source / drain patterns SD1 and SD2 that are not connected to the upper active contacts AC. For example, the lower active contacts BAC may be connected to the first lower via LM1_V of the first lower metal layer LM1. For example, each of the lower active contacts BAC may have a conductive pillar shape that vertically and electrically connects the first and second power wirings VSS and VDD to the first and second source / drain patterns SD1 and SD2. A source voltage or a drain voltage may be applied to the first and second source / drain patterns SD1 and SD2 through the lower active contacts BAC.

[0062] 4 and 5E, first and second interlayer insulating films 110 and 120 may cover an upper surface 100U of a peripheral region PR of a substrate 100. First and second upper insulating layers 130 and 140 may be provided on the first and second interlayer insulating films 110 and 120. A third interlayer insulating film 150 may be disposed on a lower surface 100L of the peripheral region PR of the substrate 100. First to third lower insulating layers 160, 170, and 180 may be disposed on a lower surface of the third interlayer insulating film 150.

[0063] A conductive structure BP may be provided that penetrates the peripheral region PR of the substrate 100. The conductive structure BP may penetrate the peripheral region PR of the substrate 100 and extend vertically onto the upper surface 100U and the lower surface 100L of the substrate 100. The conductive structure BP may penetrate the first to third interlayer insulating layers 110, 120, and 150, and may at least partially penetrate each of the first upper insulating layer 130 and the first lower insulating layer 160.

[0064] The conductive structure BP may be connected to the first and second peripheral upper wirings M1_I', M2_I', M2_V' and the first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', LM3_V'. In other words, the first and second peripheral upper wirings M1_I', M2_I', M2_V' may be connected to the upper surfaces of the conductive structure BP, and the first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', LM3_V' may be connected to the lower surfaces of the conductive structure BP. In a plan view, the conductive structure BP may overlap the corresponding first and second peripheral upper wirings M1_I', M2_I', M2_V' and the first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', LM3_V'.

[0065] Although not shown in the drawings, as another example, the conductive structure BP may be extended vertically to penetrate a portion of the second upper insulating layer 140 and the second lower insulating layer 170, thereby eliminating the first peripheral upper wiring M1_I' and the first peripheral lower wiring LM1_I'.

[0066] For example, the conductive structure BP may have a circular shape in plan view, but is not limited thereto. For example, the width W1 of the conductive structure BP in the first direction D1 may be 400 nm or more and 600 nm or less. For example, if the conductive structure BP has a circular shape in plan view, the width W1 of the conductive structure BP in the first direction D1 may refer to the diameter of the conductive structure BP.

[0067] For example, the conductive structure BP may include at least one of copper, aluminum, tungsten, molybdenum, and cobalt. The conductive structure BP may further include a metal nitride layer (not shown) covering the sidewall. For example, the metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0068] Each of the first peripheral upper line patterns M1_I' may cover an upper surface of the conductive structure BP and may be directly connected to the conductive structure BP. For example, the first peripheral upper line pattern M1_I' may have a square shape in a plan view. For example, the width W2 in the first direction D1 of each of the first peripheral upper line patterns M1_I' may be larger than the width W1 in the first direction D1 of the conductive structure BP. For example, the width W2 in the first direction D1 of the first peripheral upper line pattern M1_I' may be greater than or equal to 500 nm and less than or equal to 700 nm.

[0069] The second peripheral upper line patterns M2_I' may be disposed on the first peripheral upper line patterns M1_I'. For example, the second peripheral upper line patterns M2_I' may have a square shape in a plan view. Furthermore, each of the second peripheral upper line patterns M2_I' may overlap with a corresponding one of the first peripheral upper line patterns M1_I' in a plan view. The second peripheral upper vias M2_V' may electrically connect the first peripheral upper line patterns M1_I' and the second peripheral upper line patterns M2_I' to each other. For example, a plurality of second peripheral upper vias M2_V' may be disposed on each of the first peripheral upper line patterns M1_I'.

[0070] Each of the first peripheral lower line patterns LM1_I' may cover a lower surface of the conductive structure BP and may be directly connected to the conductive structure BP. For example, the first peripheral lower line pattern LM1_I' may have a square shape in a plan view. For example, the width W3 in the first direction D1 of each of the first peripheral lower line patterns LM1_I' may be greater than the width W1 in the first direction D1 of the conductive structure BP. For example, the width W3 in the first direction D1 of the first peripheral lower line pattern LM1_I' may be greater than or equal to 500 nm and less than or equal to 700 nm.

[0071] The second and third peripheral lower line patterns LM2_I' and LM3_I' may be sequentially arranged below the first peripheral lower line pattern LM1_I'. For example, the second and third peripheral lower line patterns LM2_I' and LM3_I' may have a square shape in a plan view. Furthermore, each of the second and third peripheral lower line patterns LM2_I' and LM3_I' may overlap with the corresponding first peripheral lower line pattern LM1_I' in a plan view. The second and third peripheral lower vias LM2_V' and LM3_V' may be arranged between the first peripheral lower line pattern LM1_I' and the second peripheral lower line pattern LM2_I', and between the second peripheral lower line pattern LM2_I' and the third peripheral lower line pattern LM3_I', respectively.

[0072] 6 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention, and corresponds to FIG. 5E. In the following embodiments, detailed descriptions of technical features that overlap with those previously described with reference to FIG. 4 and FIG. 5A to FIG. 5E will be omitted, and differences will be described in detail.

[0073] 6, the first external connection terminals 210 may be disposed on the first and second peripheral upper wirings M1_I', M2_I', and M2_V'. More specifically, the first external connection terminals 210 may be directly connected to the uppermost peripheral upper wiring (i.e., the second peripheral upper line pattern M2_I') among the first and second peripheral upper wirings M1_I', M2_I', and M2_V'.

[0074] The second external connection terminals 220 may be disposed under the first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', and LM3_V'. More specifically, the second external connection terminals 220 may be directly connected to the lowest peripheral lower wiring (i.e., the third peripheral lower line pattern LM3_I') among the first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', and LM3_V'.

[0075] The first and second external connection terminals 210 and 220 may electrically and physically connect external devices connected to the top and bottom of the semiconductor device, respectively. For example, the first and second external connection terminals 210 and 220 may be solder balls or solder bumps.

[0076] Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 8 is an enlarged view of part P1 of Figure 7. In the following embodiments, detailed descriptions of technical features that overlap with those described above with reference to Figures 4 and 5A to 5E will be omitted, and differences will be described in detail.

[0077] 7, a redistribution substrate 300 may be provided. The redistribution substrate 300 is a redistribution substrate manufactured through a redistribution process and may include a redistribution insulating layer 310 and a redistribution conductive pattern 320. For example, the redistribution insulating layer 310 may include a silicon-based insulating material, and the redistribution conductive pattern 320 may include at least one of copper and titanium.

[0078] First and second semiconductor chips 10 and 20 may be stacked vertically on the redistribution substrate 300. A third semiconductor chip 30 may be further disposed on the redistribution substrate 300, spaced horizontally from the first and second semiconductor chips 10 and 20. The first semiconductor chip 10 may be the semiconductor device described above with reference to FIGS. 3 to 5E. The second and third semiconductor chips 20 and 30 may be, for example, logic chips, memory chips, or capacitors.

[0079] A second external connection terminal 220 may be disposed between the redistribution substrate 300 and the first semiconductor chip 10, and a first external connection terminal 210 may be disposed between the first semiconductor chip 10 and the second semiconductor chip 20. A third external connection terminal 230 may be disposed between the redistribution substrate 300 and the third semiconductor chip 30. The third external connection terminal 230 may electrically connect the chip pads 35 of the third semiconductor chip 30 to the redistribution conductive pattern 320. The first and second external connection terminals 210 and 220 may electrically connect the first and second semiconductor chips 10 and 20 to the redistribution substrate 300.

[0080] 7 and 8, the lower surface BP_L of the conductive structure BP may be located at a level lower than the upper surface of the first lower insulating layer 160. For example, the lower surface BP_L of the conductive structure BP may be located at a first level LV1 between the upper and lower surfaces of the first lower insulating layer 160 and may be coplanar with the lower surface of the first lower via LM1_V. The first level LV1 may be vertically lower than a second level LV2 on which the lower surface BAC_L of the lower active contact BAC connected to the first source / drain pattern SD1 is located.

[0081] An upper surface BP_U of the conductive structure BP may be located at a level higher than a lower surface of the first upper insulating layer 130. For example, the upper surface BP_U of the conductive structure BP may be located at a fourth level LV4 between the upper and lower surfaces of the first upper insulating layer 130 and may be coplanar with an upper surface of the first upper via M1_V. The fourth level LV4 may be vertically higher than the third level LV3 on which an upper surface AC_U of the upper active contact AC connected to the second source / drain pattern SD2 is located.

[0082] According to an embodiment of the present invention, the vertically stacked first and second peripheral upper wirings M1_I', M2_I', M2_V', conductive structure BP, and first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', LM3_V' may electrically connect the upper and lower ends of the first semiconductor chip 10. That is, the vertically connected first and second peripheral upper wirings M1_I', M2_I', M2_V', conductive structure BP, and first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', LM3_V' may function as through silicon vias (TSVs). In other words, even if a separate, integral through via that penetrates vertically through the first semiconductor chip 10 is not formed, electrical signals connected from the redistribution substrate 300 can be transmitted to the second semiconductor chip 20 through the first and second peripheral upper wirings M1_I', M2_I', M2_V', the conductive structure BP, and the first to third peripheral lower wirings LM1_I', LM2_I', LM2_V', LM3_I', LM3_V'.

[0083] 9A to 17E illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. Specifically, FIGS. 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A are cross-sectional views corresponding to FIG. 5A, and FIGS. 11B, 12B, 13B, 14B, 15B, 16B, and 17B are cross-sectional views corresponding to FIG. 5B. FIGS. 11C, 12C, 14C, 15C, 16C, and 17C are cross-sectional views corresponding to FIG. 5C, and FIGS. 9B, 10B, 13C, 14D, 15D, 16D, and 17D are cross-sectional views corresponding to FIG. 5D. FIGS. 9C, 11D, 13D, 14E, 15E, 16E, and 17E are cross-sectional views corresponding to FIG. 5E.

[0084] 3 and 9A to 9C, a substrate 100 may be provided that includes a logic cell region LCR and a peripheral region PR surrounding the logic cell region LCR. The logic cell region LCR may include first and second active regions AR1 and AR2. Active layers ACL and sacrificial layers SAL may be alternately stacked on an upper surface 100U of the substrate 100. The active layers ACL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layers SAL may include another of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0085] The sacrificial layer SAL may include a material having an etching selectivity with respect to the active layer ACL. For example, the active layer ACL may include silicon (Si), and the sacrificial layer SAL may include silicon germanium (SiGe). The concentration of germanium (Ge) in each sacrificial layer SAL may be about 10 at% to about 30 at%.

[0086] A mask pattern may be formed on the first and second active regions AR1 and AR2 of the logic cell region LCR. The mask pattern may have a bar shape spaced apart from each other in a first direction D1 and extending in a second direction D2 in the logic cell region LCR, and may cover the sacrificial layer SAL and the active layer ACL in the peripheral region PR. A patterning process using the mask pattern may be performed to form trenches TR defining first and second active patterns AP1 and AP2. The trenches TR may extend in the second direction D2 and be spaced apart from each other in the logic cell region LCR. The first active pattern AP1 may be formed on the first active region AR1. The second active pattern AP2 may be formed on the second active region AR2. In a plan view, the first and second active patterns AP1 and AP2 may have line shapes extending parallel to each other in the second direction D2.

[0087] A stack pattern STP may be formed on each of the first and second active patterns AP1 and AP2. Each stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. For example, the stack pattern STP may be formed by the etching process that forms the first and second active patterns AP1 and AP2.

[0088] Thereafter, an isolation layer ST may be formed to fill the trench TR. For example, an insulating layer covering the first and second active patterns AP1 and AP2 and the stack pattern STP may be formed on the upper surface 100U of the substrate 100, and the insulating layer may be recessed to form the isolation layer ST. The stack pattern STP may be exposed on the isolation layer ST. In other words, the stack pattern STP may protrude vertically from the isolation layer ST. The isolation layer ST may include an insulating material such as a silicon oxide layer.

[0089] 10A and 10B, sacrificial patterns PP may be formed across stack patterns STP in the logic cell region LCR of the substrate 100. Each sacrificial pattern PP may be formed in a line or bar shape extending in a first direction D1. The sacrificial patterns PP may be spaced apart from each other in a second direction D2. The sacrificial patterns PP may not be formed in the peripheral region PR of the substrate 100.

[0090] Specifically, forming the sacrificial pattern PP may include forming a sacrificial layer on the logic cell region LCR of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may include polysilicon.

[0091] A pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP. Forming the gate spacers GS may include conformally forming a gate spacer layer on the logic cell region LCR of the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer layer may be a multi-layer including at least two of SiCN, SiCON, and SiN.

[0092] 11A to 11D, a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. While forming the first and second recesses RS1 and RS2, the isolation layers ST on both sides of each of the first and second active patterns AP1 and AP2 may be further recessed (see FIG. 11C).

[0093] Specifically, the first recess RS1 may be formed by etching the stack pattern STP on the first active pattern AP1 using the hard mask pattern MP and the gate spacer GS as an etching mask in the logic cell region LCR of the substrate 100. The first recess RS1 may be formed between a pair of adjacent sacrificial patterns PP. The second recess RS2 in the stack pattern STP on the second active pattern AP2 may be formed in the same manner as forming the first recess RS1. During the process of forming the first and second recesses RS1 and RS2, the stack pattern STP on the peripheral region PR of the substrate 100 may be removed.

[0094] After the first recesses RS1 are formed, the active layers (ACL in FIG. 10A) sequentially stacked between adjacent first recesses RS1 may be referred to as first to third semiconductor patterns SP1, SP2, and SP3, respectively. Similarly, after the second recesses RS2 are formed, the active layers (not shown) sequentially stacked between adjacent second recesses RS2 may be referred to as first to third semiconductor patterns SP1, SP2, and SP3, respectively. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 may form a first channel pattern CH1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 may form a second channel pattern CH2.

[0095] 12A to 12C, first source / drain patterns SD1 may be formed in the first recesses RS1. Specifically, the first source / drain patterns SD1 may be formed by performing a seed growth process using the inner walls of the first recesses RS1 as a seed layer. The first source / drain patterns SD1 may be grown using the first to third semiconductor patterns SP1, SP2, and SP3 exposed by the first recesses RS1 and the substrate 100 as seeds. For example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain patterns SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. While the first source / drain pattern SD1 is being formed, impurities (e.g., boron, gallium, or indium) may be implanted in situ to cause the first source / drain pattern SD1 to have p-type conductivity. Alternatively, after the first source / drain pattern SD1 is formed, impurities may be implanted into the first source / drain pattern SD1.

[0096] Second source / drain patterns SD2 may be formed in the second recesses RS2. Specifically, the second source / drain patterns SD2 may be formed by performing a selective epitaxial growth (SEG) process using the inner walls of the second recesses RS2 as a seed layer. For example, the second source / drain patterns SD2 may include the same semiconductor element (e.g., Si) as the substrate 100.

[0097] During the formation of the second source / drain pattern SD2, impurities (e.g., phosphorus, arsenic, or antimony) may be implanted in situ to cause the second source / drain pattern SD2 to have n-type conductivity. Alternatively, after the second source / drain pattern SD2 is formed, impurities may be implanted into the second source / drain pattern SD2.

[0098] In one embodiment of the present invention, before forming the second source / drain pattern SD2, a portion of the sacrificial layer SAL exposed through the second recess RS2 may be replaced with an insulating material to form inner spacers ISP, resulting in the formation of inner spacers ISP between the second source / drain pattern SD2 and the sacrificial layer SAL.

[0099] 13A to 13D, a first interlayer insulating film 110 may be formed to cover the logic cell region LCR and the peripheral region PR of the substrate 100. The first interlayer insulating film 110 may cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern (MP in FIG. 12A), and the gate spacer GS in the logic cell region LCR. As an example, the first interlayer insulating film 110 may include a silicon oxide film.

[0100] The first interlayer insulating film 110 may be planarized until the top surface of the sacrificial pattern (PP in FIG. 12A) is exposed. Planarization of the first interlayer insulating film 110 may be performed using an etch-back or CMP (Chemical Mechanical Polishing) process. During the planarization process, the hard mask pattern (MP in FIG. 12A) may be entirely removed. As a result, the top surface of the first interlayer insulating film 110 may be coplanar with the top surface of the sacrificial pattern (PP in FIG. 12A) and the top surface of the gate spacer GS.

[0101] Thereafter, the exposed sacrificial pattern (PP in FIG. 12A) may be selectively removed. By removing the sacrificial pattern (PP in FIG. 12A), an outer region ORG exposing the first and second channel patterns CH1 and CH2 may be formed (see FIG. 13C). Removing the sacrificial pattern PP may include wet etching using an etchant that selectively etches polysilicon.

[0102] The sacrificial layer (SAL in FIG. 12A) exposed through the outer region ORG may be selectively removed to form the inner region IRG (see FIG. 13C). Specifically, an etching process that selectively etches the sacrificial layer SAL may be performed to remove only the sacrificial layer SAL while leaving the first to third semiconductor patterns SP1, SP2, and SP3 intact. The etching process may have a high etching rate for silicon germanium, which has a relatively high germanium concentration.

[0103] 13C, the sacrificial layer (SAL in FIG. 10B) is selectively removed, so that only the first to third semiconductor patterns SP1, SP2, and SP3 stacked on the first and second active patterns AP1 and AP2 remain. First to third inner regions IRG1, IRG2, and IRG3 are formed through the regions from which the sacrificial layer (SAL in FIG. 10B) is removed.

[0104] Specifically, a first inner region IRG1 may be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second inner region IRG2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner region IRG3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0105] 14A to 14E, a gate insulating film GI may be conformally formed on the exposed first, second, and third semiconductor patterns SP1, SP2, and SP3. A gate electrode GE may be formed on the gate insulating film GI. The gate electrode GE may include first, second, and third inner electrodes PO1, PO2, and PO3 formed in first, second, and third inner regions IRG1, IRG2, and IRG3, respectively, and an outer electrode PO4 formed in the outer region ORG. A gate capping pattern GP may be formed on the gate electrode GE.

[0106] A second interlayer insulating film 120 may be formed on the logic cell region LCR and the peripheral region PR of the substrate 100. The second interlayer insulating film 120 may cover the gate capping pattern GP and the first interlayer insulating film 110. For example, the second interlayer insulating film 120 may include a silicon oxide film.

[0107] An upper active contact AC electrically connected to the first and second source / drain patterns SD1 and SD2 may be formed through the second interlayer insulating film 120 and the first interlayer insulating film 110. A gate contact GC electrically connected to the gate electrode GE may be formed through the second interlayer insulating film 120 and the gate capping pattern GP.

[0108] For example, forming each of the upper active contact AC and the gate contact GC may include forming a barrier pattern and forming a conductive pattern on the barrier pattern. The barrier pattern may be conformally formed and may include a metal film / metal nitride film. The conductive pattern may include a low-resistivity metal.

[0109] An isolation structure DB may be formed through the first and second interlayer insulating layers 110 and 120 and the gate electrode GE. The isolation structure DB may extend into the active pattern AP1 or AP2 through the gate electrode GE. The isolation structure DB may include a silicon-based insulating material such as a silicon oxide layer or a silicon nitride layer.

[0110] 15A to 15E, a first upper insulating layer 130 may be formed on the logic cell region LCR and the peripheral region PR of the substrate 100. The first upper insulating layer 130 may cover the second interlayer insulating layer 120. For example, the first upper insulating layer 130 may include a silicon-based insulating material.

[0111] A first upper metal layer M1 may be formed in the first upper insulating layer 130. For example, forming the first upper metal layer M1 may include forming first upper interconnections M1_I and M1_V provided in the logic cell region LCR and a first peripheral upper interconnection M1_I' provided in the peripheral region PR. For example, forming the first upper interconnections M1_I and M1_V may include forming contact holes and trenches penetrating the first upper insulating layer 130 and depositing a conductive material to fill the contact holes and the trenches. For example, forming the first peripheral upper interconnection M1_I' may include forming trenches penetrating the first upper insulating layer 130 and depositing a conductive material to fill the trenches. For example, the first upper interconnections M1_I and M1_V and the first peripheral upper interconnection M1_I' may be formed simultaneously.

[0112] A second upper insulating layer 140 may be formed on the first upper insulating layer 130. The second upper insulating layer 140 may cover the first upper insulating layer 130. As an example, the second upper insulating layer 140 may include a silicon-based insulating material.

[0113] A second upper metal layer M2 connected to the first upper metal layer M1 may be formed in the second upper insulating layer 140. For example, forming the second upper metal layer M2 may include forming second upper interconnections M2_I, M2_V provided in the logic cell region LCR and second peripheral upper interconnections M2_I', M2_V' provided in the peripheral region PR. For example, forming the second upper interconnections M2_I, M2_V may include forming contact holes and trenches through the second upper insulating layer 140 and depositing a conductive material to fill the contact holes and the trenches. For example, forming the second peripheral upper interconnections M2_I', M2_V' may include forming contact holes and trenches through the second upper insulating layer 140 and depositing a conductive material to fill the contact holes and the trenches. For example, the second upper interconnections M2_I, M2_V and the second peripheral upper interconnections M2_I', M2_V' may be formed simultaneously.

[0114] 16A to 16E, the substrate 100 may be inverted to expose a lower surface 100L of the substrate 100. The exposed portion of the substrate 100 may be removed. For example, a planarization process may be performed to remove the portion of the substrate 100, thereby reducing the thickness of the substrate 100. Furthermore, the upper surface of the isolation layer ST may be exposed. Thereafter, a third interlayer insulating layer 150 may be formed on the lower surface 100L of the substrate 100. The third interlayer insulating layer 150 may be formed under the logic cell region LCR and the peripheral region PR of the substrate 100.

[0115] Thereafter, in the logic cell region LCR, the third interlayer insulating film 150 and the substrate 100 may be patterned using a mask pattern, and back trenches BTR may be formed. The back trenches BTR may extend along a first direction D1 and may be spaced apart from each other along a second direction D2.

[0116] 17A to 17E, bottom active contacts BAC may be formed. Forming the bottom active contacts BAC may include depositing a conductive material in the back trenches (BTRs in FIG. 16A).

[0117] A first lower insulating layer 160 may be formed on the lower surface of the third interlayer insulating layer 150. The first lower insulating layer 160 may be formed on the back surface of the logic cell region LCR and the peripheral region PR of the substrate 100. For example, the first lower insulating layer 160 may include a silicon-based insulating material.

[0118] A conductive structure BP may be formed penetrating the peripheral region PR of the substrate 100. Forming the conductive structure BP may include forming a through-hole penetrating the first lower insulating layer 160, the substrate 100, the first to third interlayer insulating films 110, 120, and 150, and a portion of the first upper insulating layer 130 to expose the first peripheral upper wiring M1_I′, and depositing a conductive material to fill the through-hole. During the process of depositing the conductive material, the conductive material does not need to be filled to the same level as the bottom surface of the first lower insulating layer 160. For example, the conductive material may be filled to a level between the top and bottom surfaces of the first lower insulating layer 160.

[0119] For example, in the process of manufacturing a semiconductor device including lower insulating layers 160, 170, and 180 and lower active contacts BAC, which will be described later, forming a through via that penetrates the substrate 100 may be difficult in the manufacturing process. For example, the manufacturing process may be difficult because a first through via must be formed through the back surface of the substrate 100, and a second through via must be formed through the lower insulating layers 160, 170, and 180 to connect the first and second through vias to each other. However, according to an embodiment of the present invention, as will be described later, a conductive structure BP is integrally formed in the peripheral region PR of the substrate 100 before forming the first lower metal layer LM1, and can be connected to the peripheral upper wirings M1_I′, M2_I′, and M2_V′ and the peripheral lower wirings LM1_I′, LM2_I′, LM2_V′, LM3_I′, and LM3_V′ to function as a through via, thereby relatively simplifying the manufacturing process.

[0120] Subsequently, a first lower metal layer LM1 may be formed in the first lower insulating layer 160. For example, forming the first lower metal layer LM1 may include forming first lower interconnections LM1_I and LM1_V provided on the logic cell region LCR and a first peripheral lower interconnection LM1_I' provided on the peripheral region PR. For example, forming the first lower interconnections LM1_I and LM1_V may include forming contact holes and trenches through the first lower insulating layer 160 and depositing a conductive material to fill the contact holes and the trenches. For example, forming the first peripheral lower interconnection LM1_I' may include forming trenches through the first lower insulating layer 160 and depositing a conductive material to fill the trenches. During the formation of the first peripheral lower interconnection LM1_I', the trenches may expose the lower surfaces of the conductive structures BP, and the first peripheral lower interconnection LM1_I' may be directly connected to the conductive structures BP. For example, the first lower wirings LM1_I and LM1_V and the first peripheral lower wiring LM1_I' may be formed simultaneously.

[0121] 4 and 5A to 5E, a second lower insulating layer 170 may be formed on the back surface of the first lower insulating layer 160. The second lower insulating layer 170 may cover the first lower insulating layer 160. For example, the second lower insulating layer 170 may include a silicon-based insulating material.

[0122] A second lower metal layer LM2 connected to the first lower metal layer LM1 may be formed in the second lower insulating layer 170. For example, forming the second lower metal layer LM2 may include forming second lower interconnections LM2_I, LM2_V provided under the logic cell region LCR and second peripheral lower interconnections LM2_I', LM2_V' provided under the peripheral region PR. For example, forming the second lower interconnections LM2_I, LM2_V may include forming contact holes and trenches through the second lower insulating layer 170 and depositing a conductive material to fill the contact holes and the trenches. For example, forming the second peripheral lower interconnections LM2_I', LM2_V' may include forming contact holes and trenches through the second lower insulating layer 170 and depositing a conductive material to fill the contact holes and the trenches. For example, the second lower interconnections LM2_I, LM2_V and the second peripheral lower interconnections LM2_I', LM2_V' may be formed simultaneously.

[0123] A third lower insulating layer 180 may be formed on the back surface of the second lower insulating layer 170. The third lower insulating layer 180 may cover the second lower insulating layer 170. For example, the third lower insulating layer 180 may include a silicon-based insulating material.

[0124] A third lower metal layer LM3 connected to the second lower metal layer LM2 may be formed in the third lower insulating layer 180. For example, forming the third lower metal layer LM3 may include forming third lower wirings LM3_I and LM3_V provided under the logic cell region LCR and third peripheral lower wirings LM3_I' and LM3_V' provided under the peripheral region PR. First and second power wirings VSS and VDD may be formed during the process of forming the third lower wirings LM3_I and LM3_V. The first and second power wirings VSS and VDD may be formed in the third lower insulating layer 180 and may be electrically connected to the first to third lower wirings LM1_I, LM1_V, LM2_I, LM2_V, LM3_I, and LM3_V. A power transmission network layer PDN may be formed by forming the first to third lower metal layers LM1, LM2, and LM3.

[0125] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0126] 100 boards LCR logic cell area PR Peripheral Areas AC upper active contact BAC Lower Active Contact BP conductive structure

Claims

1. a substrate including a logic cell region and a peripheral region around the logic cell region; a logic element including source and drain patterns on the logic cell region of the substrate; an upper active contact on the source and drain patterns, the upper active contact being connected to one of the source and drain patterns; a lower active contact connected to another one of the source and drain patterns under the source and drain patterns; a conductive structure extending through the peripheral region of the substrate; a peripheral upper wiring connected to the conductive structure on the peripheral region of the substrate; a peripheral lower interconnection connected to the conductive structure under the peripheral region of the substrate; A semiconductor device, wherein a lower surface of the conductive structure is located at a level lower than a lower surface of the lower active contact.

2. a lower surface of the substrate is parallel to a first direction; The semiconductor device according to claim 1 , wherein the width of the conductive structure in the first direction is equal to or greater than 400 nm and equal to or less than 600 nm.

3. the first and second upper insulating layers are stacked in sequence on the upper surface of the substrate and cover upper surfaces of the upper active contacts; The semiconductor device according to claim 1 , wherein the conductive structure at least partially penetrates the first upper insulating layer.

4. The peripheral upper wiring is a first peripheral upper line pattern directly connected to the conductive structure in the first upper insulating layer; a second peripheral upper line pattern electrically connected to the first peripheral upper line pattern in the second upper insulating layer, The semiconductor device according to claim 3 , wherein the conductive structure overlaps the first and second upper peripheral line patterns in a plan view.

5. a lower surface of the substrate is parallel to a first direction; The semiconductor device according to claim 4 , wherein the width of the first peripheral upper line pattern in the first direction is greater than the width of the conductive structure in the first direction.

6. a first upper via that partially penetrates the first upper insulating layer and is connected to the upper active contact; The semiconductor device of claim 3 , wherein an upper surface of the conductive structure is coplanar with an upper surface of the first upper via.

7. 2. The semiconductor device of claim 1, wherein a top surface of said conductive structure is at a level higher than a top surface of said upper active contact.

8. a first lower insulating layer on the lower surface of the substrate, the first lower insulating layer covering a lower surface of the lower active contact; The semiconductor device according to claim 1 , wherein the conductive structure at least partially penetrates the first lower insulating layer.

9. the peripheral lower wiring includes a first peripheral lower line pattern directly connected to the conductive structure in the first lower insulating layer; The semiconductor device according to claim 8 , wherein the conductive structure overlaps with the first lower periphery line pattern in a plan view.

10. a first lower via that partially penetrates the first lower insulating layer and is connected to the lower active contact; The semiconductor device of claim 8 , wherein a lower surface of the conductive structure is coplanar with a lower surface of the first lower via.

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