Multiply-and-accumulate circuit

Abstract

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an object, a method of operation, or a method of manufacturing. is a process, machine, manufacture, or composition of matter. Therefore, one embodiment of the present invention disclosed in this specification more specifically relates to The technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, and imaging devices. Devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, and their driving Examples include methods, methods for producing them, or methods for inspecting them. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "brain-morphic," "brain-inspired," etc. The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the von Neumann architecture, which has a high power consumption, parallel processing is possible with extremely low power consumption. It is expected that this will be possible.

[0004] The information processing model that mimics a neural network with "neurons" and "synapses" is called artificial neural network. Artificial neural networks (ANNs) are used to This makes it possible to make inferences with accuracy comparable to or even exceeding that of humans. In the network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation. is.

[0005] A memory cell using OS transistors is used as a circuit for performing multiply-and-accumulate operations. The invention is disclosed in, for example, Patent Document 1. The transistor has a metal oxide semiconductor in the channel formation region. It has been reported that the off-state current is extremely small (for example, References 1 and 2). In addition, various semiconductor devices using OS transistors have been manufactured. (For example, Non-Patent Documents 3 and 4) The manufacturing process of an OS transistor is the same as that of a conventional Si transistor. The OS transistor can be integrated into the CMOS process of the Si transistor. It is possible to laminate the layers on top of each other (for example, Non-Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168099 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] When multiplying and accumulating data using a digital circuit, the digital data that becomes the multiplier (multiplier data) and The multiplication of the digital data (multiplicand data) that becomes the multiplicand is executed in a digital multiplication circuit. Then, the digital data (product data) obtained by the multiplication is added in a digital addition circuit. The digital multiplication is performed and digital data (sum of products data) is obtained as the result of this sum of products operation. It is preferable that the calculation circuit and the digital addition circuit are capable of handling multi-bit calculations. However, in this case, the respective circuits of the digital multiplication circuit and the digital addition circuit are This may increase the circuit size, leading to an increase in the circuit area of ​​the entire arithmetic circuit and an increase in power consumption. There is a risk.

[0009] Also, when calculations are performed on a processor, the resulting data is stored as digital data. For example, when performing a multiply-and-accumulate operation, the digital multiplier circuit The product data obtained by this is stored in a digital memory and then multiplied by a digital adder circuit. When calculating the sum data, the product data is read out. After the sum-of-products data is calculated, the sum-of-products data is stored in a digital memory. When performing summation, the digital memory is used for each multiplication and addition of digital data. In particular, when performing computations on artificial neural networks, Since multiplication and addition of digital data are performed repeatedly, the data in the digital memory This increases the frequency of data accesses to the digital memory. The speed of data reading affects the processing speed of calculations. Among the power consumption required to perform repeated calculations such as The majority of power consumption is consumed by data input and data readout.

[0010] In addition, by combining the calculation circuit that performs the neural network calculations with the sensor, This may enable electronic devices to recognize various information. By combining a light sensor (e.g., a photodiode) with the arithmetic circuit, Pattern recognition such as face recognition and image recognition can be performed from the image data obtained by the sensor. However, since the electrical signal obtained from the optical sensor is weak, To input the electrical signal into the arithmetic circuit, it is necessary to amplify the electrical signal using an amplifier circuit. If the arithmetic circuit is composed of a digital circuit, the electrical signal is converted into an analog-digital signal. Therefore, the light received from the optical sensor must be converted into a digital signal using a digital conversion circuit. In order to input the electrical signal to the arithmetic circuit, the electrical signal is processed by various circuits. Therefore, the power consumption of the circuit may become large.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing a product-sum operation. An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0012] Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. An object of one embodiment of the present invention is to provide an electronic device including the semiconductor device. do.

[0013] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0014] (1) One aspect of the present invention is a battery comprising a first cell, a second cell, a first circuit, a second circuit, a third circuit, The semiconductor device has a fourth circuit, a first wiring, a second wiring, and a third wiring. The first cell has a first capacitance, and the second cell has a second capacitance. The first circuit is also connected to the fifth circuit. , and a sixth circuit, and the third circuit has a sensor. The first cell is connected to The first terminal of the first capacitor of the first cell is electrically connected to the first circuit, and the first terminal of the first capacitor of the first cell is electrically connected to the third wiring. The second cell is electrically connected to the first circuit via a second wiring. The first terminal of the second capacitor of the two cells is electrically connected to the third wiring. , electrically connected to the fourth circuit, the third circuit is electrically connected to the fourth circuit, and the third wiring is The fourth circuit is electrically connected to the second circuit and the third wiring. and setting the third circuit and the third wiring in either a conductive state or a non-conductive state. The first cell has a function of setting the other of the first and second input potentials to the third wiring. a function of maintaining a first potential at the second terminal of the first capacitor when the The function of passing the voltage between the first cell and the first wiring and the function of changing the first input potential of the third wiring to the second input potential. When the first capacitor is turned on, the first potential held at the second terminal of the first capacitor changes to the second potential, The second cell has a function of passing a current corresponding to the second potential between the first cell and the first wiring. When the first input potential is input to the third wire, the second terminal of the second capacitor holds the third potential. a function of causing a current corresponding to the third potential to flow between the second cell and the second wiring; and a function of causing a current corresponding to the third potential to flow between the second cell and the second wiring. When the first input potential of the capacitor changes to the second input potential, the The third potential changes to a fourth potential, and a current corresponding to the fourth potential flows between the second cell and the second wiring. When the potential of the third wiring is the first input potential, the first circuit and the first A first current flows between the first circuit and the wiring, and a second current flows between the first circuit and the second wiring. When the potential of the third wiring is the second input potential, a third current flows between the first circuit and the first wiring. The fourth current flows between the first circuit and the second wiring. The fifth circuit is When the potential of the wiring is the second input potential, a first current amount I1 flows through the first wiring. , the sixth circuit, when the potential of the third wiring is the second input potential, a second current of I flows through the first wiring. The first circuit has the function of passing the third input voltage when the potential of the third wiring is the second input voltage. The amount of current I3 and the amount of fourth current I4 are obtained, and the amount of current I1-I2-I3+I4 is obtained. The second circuit has a function of generating the fifth potential and a function of inputting the fifth potential to the second circuit. The function to generate the sixth potential according to the internal data input, and the function to use the fifth potential as the first input potential. or the sixth potential as a second input potential to the fourth circuit. The third circuit has the function of generating a seventh potential before the sensor acquires information, and the function of detecting the seventh potential before the sensor acquires information. a function of generating an eighth potential according to the received information, and a function of using the seventh potential as a first input potential or a function of using the seventh potential as a second input potential and a function of outputting the eighth potential as a second input potential to the fourth circuit.

[0015] (2) Alternatively, in the above-mentioned (1), one aspect of the present invention is the third circuit including a first transistor and a second transistor. The second transistor, the third transistor, and the fourth transistor may be included. In particular, the first terminal of the sensor is electrically connected to the first terminal of the first transistor. The second terminal of the transistor is connected to the first terminal of the second transistor and the gate of the third transistor. and a first terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to the first terminal of the third transistor and the second terminal of the fourth transistor. The terminal is preferably electrically connected to the third wiring via a fourth circuit.

[0016] (3) Alternatively, in the above-mentioned (2), one aspect of the present invention is the sensor having a photodiode. In particular, the output terminal of the photodiode may be electrically connected to the first terminal of the sensor. Preferably, they are connected.

[0017] (4) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the first cell is the first cell has a fifth transistor and a sixth transistor, and the second cell has a seventh transistor and In particular, the first terminal of the fifth transistor is , electrically connected to the second terminal of the first capacitor and the gate of the sixth transistor, a first terminal of the seventh transistor electrically connected to the first wiring, and a first terminal of the seventh transistor a second terminal of the second capacitor and a gate of the eighth transistor; The first terminal of the resistor is preferably electrically connected to the second wiring.

[0018] (5) Alternatively, in one aspect of the present invention, in any one of the above (1) to (4), the second circuit The digital-to-analog converter may be included. The digital signal corresponding to the internal data input to the digital-to-analog conversion circuit is converted into the sixth voltage. It is preferable to convert the signal into a decimal point and output it to the fourth circuit.

[0019] (6) Alternatively, in one aspect of the present invention, in any one of the above (1) to (5), the third circuit The second cell may be positioned above the first cell and the second cell.

[0020] (7) Another aspect of the present invention is a semiconductor device including any one of the semiconductor devices (1) to (6) above and a housing. , and the semiconductor device is an electronic device having a function of performing product-sum operations.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are all semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. , may themselves be semiconductor devices or may contain semiconductor devices.

[0022] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0023] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0024] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0025] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are directly connected (i.e., there is no other This includes cases where the device is connected without any element or other circuit in between.

[0026] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0028] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" can be used as a circuit element, wiring, etc. " refers to wiring with resistance, transistors with current flowing between the source and drain, and diodes. Therefore, the term "resistive element" is used to refer to "resistor," "Load" or "area with a resistance value" and conversely, "resistance" or The terms "load" and "area having a resistive value" can be replaced with terms such as "resistive element." The resistance value is preferably, for example, 1 mΩ or more and 10 Ω or less, and more preferably The resistance can be set to 5 mΩ or more and 5 Ω or less, and more preferably 10 mΩ or more and 1 Ω or less. , for example, 1 Ω or more, 1×10 9 It may be set to Ω or less.

[0029] In this specification, the term "capacitance element" refers to a capacitance element having a capacitance value higher than 0 F. a circuit element having a capacitance value, a wiring area having a capacitance value, a parasitic capacitance, a gate of a transistor Therefore, in this specification, a "capacitive element" refers to a pair of Not only circuit elements including electrodes and dielectrics included between the electrodes, but also wiring and wiring The parasitic capacitance that appears between the gate and the source or drain of the transistor. Also, the term "capacitance element," "parasitic capacitance," and "gate capacitance" are included. Terms such as "amount" can be replaced with terms such as "capacity" and vice versa. The term "capacitance element," "parasitic capacitance," "gate capacitance," etc. In addition, the term "pair of electrodes" in "capacitance" can be used to refer to "pair of conductors" or "pair of The capacitance value can be expressed as: For example, the capacitance can be set to 0.05 fF or more and 10 pF or less. It may be set to 10 μF or more.

[0030] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are rephrased as follows: In addition, in this specification and the like, when describing the connection relationship of transistors, , "one of the source or drain" (or first electrode, or first terminal), "source or drain The term "second electrode" or "second terminal" is used. Depending on the structure, in addition to the three terminals mentioned above, a back gate may also be present. In this case, in this specification, either the gate or the back gate of the transistor is referred to as the first gate. The other of the gate or back gate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" are interchangeable. In addition, when a transistor has three or more gates, In this case, the respective gates are referred to as the first gate, the second gate, the third gate, and so on in this specification. It is sometimes called as such.

[0031] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0032] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the earth potential (ground potential), then "voltage" can be rephrased as "potential." Round potential does not necessarily mean 0V. Also, potential is relative. By changing the reference potential, the potential applied to the wiring, the potential applied to the circuit, etc. The potential, the potential output from the circuit, etc. also changes.

[0033] In addition, in this specification, the terms "high level potential" and "low level potential" are used to refer to For example, if two wires are both at a high level potential, When it says "acts as a wire supplying the The high level potentials do not have to be equal to each other. If both are described as "functioning as wiring that supplies low-level potential," The low level potentials provided by the respective switches may not be equal to each other.

[0034] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged body" The statement "electrical conduction is occurring in the opposite direction" means "electrical conduction is occurring in the negatively charged body." Therefore, in this specification and the like, unless otherwise specified, the term "current" is used. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire, etc. is the direction in which positive carriers move, and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, statements such as "current flows from element A to element B" should be interpreted as "current flows from element B to element This can be rephrased as "current flows through element A" or "current flows through element A." A statement such as "current is input" can be rephrased as "current is output from element A" Let's say.

[0035] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0036] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0037] The terms "above" and "below" mean that the positional relationship of the components is directly above or directly below, and For example, the expression "electrode B on insulating layer A" does not necessarily mean that the electrodes are in contact with each other. In this case, electrode B does not need to be formed directly on insulating layer A. This does not exclude the inclusion of other components between the two.

[0038] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0039] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, terms such as "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where multiple "electrodes" and "wiring" are integrally formed. For example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. The same applies. Furthermore, the term "terminal" can refer to a plurality of "electrodes," "wiring," "terminals," etc. This includes cases where they are formed as one unit. For example, "electrode" can be used in place of "wiring" or can be a part of a "terminal", and for example, a "terminal" can be a "wiring" or an "electrode". In addition, terms such as "electrode," "wiring," and "terminal" may be used in some cases. This may be replaced with terms such as "area."

[0040] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In addition, the opposite is also true, and terms such as "signal line" can be used to refer to "power line". In some cases, it may be possible to change the term to "potential" or "voltage" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0041] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. As a result, for example, the density of defect states in the semiconductor increases, the carrier mobility decreases, When the semiconductor is an oxide semiconductor, the crystallinity may be reduced. Impurities that change the properties of a conductor include, for example, elements of Group 1, Group 2, and Group 13. Elements of Group 14, Group 15, and transition metals other than the main component are included. element (including water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, there are impurities that change the properties of the semiconductor. Examples of the elements include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, and the like, excluding hydrogen. Oxygen and the like.

[0042] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0043] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0045] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0046] According to one embodiment of the present invention, a semiconductor device capable of performing a product-sum operation can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0047] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. According to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0048] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, it may not have [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 5] 5A and 5B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 7] 7A and 7B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the semiconductor device. [Figure 9] FIG. 9 is a timing chart showing an example of the operation of the semiconductor device. [Figure 10] FIG. 10 is a timing chart showing an example of the operation of the semiconductor device. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 13] FIG. 13 is a block diagram showing a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 16] 16A and 16B are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 17]17A and 17B are timing charts showing an example of the operation of a circuit included in a semiconductor device. [Figure 18] 18A and 18B are diagrams illustrating a hierarchical neural network. [Figure 19] FIG. 19 is a block diagram showing a configuration example of a semiconductor device. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 22] 22A to 22C are cross-sectional views showing examples of the structure of a transistor. [Figure 23] 23A and 23B are cross-sectional views showing examples of the structure of a transistor. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 25] 25A and 25B are cross-sectional views showing examples of the structure of a transistor. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] FIG. 27A is a top view showing an example of the configuration of a capacitive element, and FIGS. 27B and 27C are cross-sectional perspective views showing the example of the configuration of a capacitive element. [Figure 28] 28A is a top view showing an example of the configuration of a capacitive element, FIG. 28B is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 28C is a cross-sectional perspective view showing an example of the configuration of a capacitive element. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] FIG. 30A is a diagram illustrating the classification of IGZO crystal structures, FIG. 30B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 30C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 31] FIG. 31A is a perspective view showing an example of a semiconductor wafer, FIG. 31B is a perspective view showing an example of a chip, and FIGS. 31C and 31D are perspective views showing an example of an electronic component. [Figure 32] 32A to 32F are perspective views of a package and a module that house an imaging device. [Figure 33] FIG. 33 is a perspective view showing an example of an electronic device. [Figure 34] 34A to 34C are perspective views showing an example of an electronic device. [Figure 35] 35A to 35C are schematic diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0050] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can feed the neural network with existing information and generate results. The process of determining the combined strength is sometimes called "learning."

[0051] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information from the input is sometimes called "inference" or "cognition."

[0052] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0053] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. In addition, when written as an OS transistor, In other words, the transistor may be a transistor having a metal oxide or an oxide semiconductor. .

[0054] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0055] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0056] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0057] The contents described in the embodiments refer to the following in each embodiment (or example): The content described using various figures or the text in the specification be.

[0058] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0059] The embodiments described in this specification will be described with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0060] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0061] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This may include variations in signal, voltage, or current.

[0062] (Embodiment 1) In this embodiment, an example of an arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described. Reveal.

[0063] <Configuration example 1 of an arithmetic circuit> The arithmetic circuit MAC1 shown in FIG. 1 is a configuration example of an arithmetic circuit capable of multiply-and-accumulate operations and function operations. The arithmetic circuit MAC1 calculates the first data stored in a memory cell (to be described later) and the input A multiplication and accumulation operation is performed on the input second data, and an activation function is calculated using the result of the multiplication and accumulation operation. The first data and the second data are, for example, analog It can be multi-valued data or multi-valued data (discrete data).

[0064] The arithmetic circuit MAC1 also has a sensor, and the information obtained by the sensor is The information can be treated as the second data for the product-sum operation. Optical sensors, pressure sensors, gyro sensors, acceleration sensors, and auditory sensors using photodiodes A temperature sensor, a humidity sensor, etc. can be applied.

[0065] The arithmetic circuit MAC1 uses the information obtained by the sensor, but not by the storage device. The data stored in advance in the That is, the arithmetic circuit MAC1 can handle information obtained from the sensor or the internal data. The device has a function of selecting either of the first and second data as the second data.

[0066] The arithmetic circuit MAC1 includes, for example, a memory cell array CA, a circuit CMS, and a circuit WD D, circuit XLD, circuit SCA, circuit SWC, circuit WLD, circuit IVTC, and circuit It has ACTV and.

[0067] The memory cell array CA includes memory cells AM[1,1] to AM[m,n]. , memory cells AMr[1] to AMr[m]. In CA, memory cells AM[1,1] to AM[m,n] are arranged in m rows and n columns ( m is an integer of 1 or more, and n is an integer of 1 or more.) The memory cells AMr[1] to AMr[m] are arranged in the memory cell array CA It is placed in the n+1th column of the

[0068] The memory cells AM[1,1] to AM[m,n] have a function of retaining first data. The memory cells AMr[1] to AMr[m] have the function of performing a multiply-and-accumulate operation. The reference data also has the function of storing the reference data required for the first data and Like the first data, the second data may be analog data or multi-valued data (discrete data). This can be done.

[0069] The memory cell AM[1,1] is connected to the wiring WD[1], the wiring BL[1], and the wiring WL[1]. and the wiring XL[1]. Also, the memory cell AM[m,1] is , wiring WD[1], wiring BL[1], wiring WL[m], wiring XL[m], The memory cell AM[1, n] is electrically connected to the wiring WD[n] and the wiring BL [n], the wiring WL[1], and the wiring XL[1] are electrically connected to the The memory cell AM[m,n] is composed of wiring WD[n], wiring BL[n], wiring WL[m], The memory cell AMr[1] is electrically connected to the wiring XL[m]. WDr, the wiring BLr, the wiring WL[1], and the wiring XL[1] are electrically connected to The memory cell AMr[m] is connected to the wiring WDr, the wiring BLr, and the wiring WL[m]. and the wiring XL[m].

[0070] Memory cells AM[1,1] to AM[m,n] and memory cell AMr[1] Detailed circuit configuration examples of the memory cells AMr[m] to AMr[m] will be described later. .

[0071] The circuit CMS is electrically connected to the wirings BL[1] to BL[n] and the wiring BLr. The circuit CMS is connected to the wiring BL[1], the memory cell AM[1,1], the memory cell AM[2,1], and the memory cell AM[3,1]. A function to supply current to each of the channels AM[m,1] and a function to set the current to a constant current. The circuit CMS includes a wiring BL[n], a memory cell AM[1, n], a memory cell AM[2, n], a memory cell AM[3, n], a memory cell AM[4, n], a memory cell AM[5, n], a memory cell AM[6, n], a memory cell AM[7, n], a memory cell AM[8, n], a memory cell AM[9, n], a memory cell AM[1 ... A function to supply current to each rechargeable cell AM[m,n] and set the current to a constant current. The circuit CMS has a function of connecting the wiring BLr to the memory cell AMr[1] to the memory cell AMr[2]. A function to supply current to each cell AMr[m] and a function to set the current to a constant current In addition, the circuit CMS has a wiring BL[1] to a wiring BL[n]. The amount of the constant current flowing through the wiring BLr is subtracted from the amount of the constant current.

[0072] The circuit WDD is electrically connected to the wirings WD[1] to WD[n] and the wiring WDr. The circuit WDD stores data in each memory cell of the memory cell array CA. For example, the circuit WDD has a function of transmitting data for the purpose of The first data is transmitted to the wiring WD[n] as the data, and the first data is transmitted to the wiring WDr as the data. The reference data can be sent as

[0073] The circuit WLD is electrically connected to the wirings WL[1] to WL[m]. When writing data to a memory cell in the memory cell array CA, the LD It has the function of selecting the memory cell to be written to. When data is written to the memory cell in the i-th row of A (i is an integer between 1 and m), The circuit WLD applies a high-level potential to the wiring WL[i] and also applies a high-level potential to the wirings other than the wiring WL[i]. By applying a low-level potential to the wirings WL[1] to WL[m], the wirings become destinations for writing data. The memory cells AM[i,1] to AM[i,n] and the memory cell AMr[i] are You can choose.

[0074] As an example, the circuit SWC includes circuits SWT[1] to SWT[m].

[0075] Moreover, the circuit SCA includes, for example, circuits RPC[1] to RPC[m].

[0076] The first terminal of the circuit SWT[1] is electrically connected to the wire XL[1], and the circuit SWT[1] The second terminal of the circuit SWT[1] is electrically connected to the circuit RPC [1]. The first terminal of the circuit SWT[m] is electrically connected to the wire XL[m]. The second terminal of the circuit SWT[m] is electrically connected to the circuit XLD, and the second terminal of the circuit SWT[m] is electrically connected to the circuit XLD. The third terminal of the circuit SWT[m] is electrically connected to the circuit RPC[m].

[0077] Each of the circuits SWT[1] to SWT[m] has, for example, a first terminal and a second terminal. The first terminal and the third terminal are either in a conductive state or a non-conductive state, and the second terminal and the third terminal are in a conductive state. The other of the two functions is to turn the transistor into a conductive state or a non-conductive state.

[0078] Each of the circuits RPC[1] to RPC[m] is a circuit that receives information obtained by sensing. The circuit RPC[1] has a sensor that generates second data corresponding to the information. It has the function of applying a voltage according to the second data to the third terminal of the circuit SWT [1]. Then, the circuit RPC[m] applies a voltage according to the second data to the third terminal of the circuit SWT[m]. It has the function of

[0079] In the circuit SCA shown in FIG. 1, the circuits RPC[1] to RPC[m] are arranged in a row. However, the semiconductor device of one embodiment of the present invention is not limited to this. For example, instead of arranging the circuits RPC[1] to RPC[m] in a single column, Similarly, the circuits SWT[1] to SWT[m] may be arranged in a row. Alternatively, they may be arranged in a matrix.

[0080] A circuit SCA in which circuits RPC[1] to RPC[m] are arranged in a matrix, and The circuits SWT[1] to SWT[m] have a circuit SWC arranged in a matrix. The configuration of the arithmetic circuit MAC1 may be, for example, the configuration example shown in FIG. 1 shows an excerpt of the circuit SA, the circuit SWC, and the circuit SCA.

[0081] The arithmetic circuit MAC1 shown in FIG. 2 includes circuits SWT[1] to SWT[2] above the memory cell array CA. The circuit SWT[m] is arranged in a matrix on the circuit SWC. On the other hand, the circuit SCA is arranged in a matrix of circuits RPC[1] to RPC[m]. The circuit SWC is located not above the memory cell array CA but above the Alternatively, it may be located below the memory cell array CA (not shown).

[0082] The circuit XLD is connected between the first terminal of the circuit SWT[1] and the second terminal of the circuit SWT[1]. The memory cells AM[1,1] to AM[1 , n] and the memory cell AMr[1], and has a function of inputting a voltage according to the second data In addition, the circuit XLD is connected to the first terminal of the circuit SWT[m] and the second terminal of the circuit SWT[m]. The memory cells AM[m,1] to AM[m,2] of the memory cell array CA are connected via the A function for inputting a voltage according to second data to the memory cell AM[m, n] and the memory cell AMr[m]. Possess the ability.

[0083] The circuit IVTC includes wirings BL[1] to BL[n] and wirings OL[1] to OL The circuit IVTC is electrically connected to the wiring BL[1]. The function of converting the current flowing through the circuit IVTC into a voltage, etc., and outputting the voltage to the wiring OL[1]. The circuit IVTC has a function of inputting a signal from the wiring BL[n] to the circuit IV The function of converting the amount of current flowing through TC into a voltage, etc., and outputting that voltage to wiring OL[n] It has the function.

[0084] The circuit ACTV includes wiring OL[1] to wiring OL[n] and wiring NIL[1] to wiring NIL[n]. IL[n] and the ACTV are electrically connected to the line OL[1]. The voltage output from the circuit IVTC is input to the circuit ACTV. It has the function of performing calculations according to a predefined function system. For example, sigmoid function, tanh function, softmax function, ReLU function, threshold function These functions are the activation functions in neural networks. applied as a number.

[0085] <<Memory cell configuration example>> Next, memory cells AM[1,1] to AM[1,2] included in the memory cell array CA are Regarding configuration examples of AM[m,n] and memory cells AMr[1] to AMr[m] ,explain.

[0086] FIG. 3 is a circuit diagram showing an example of the configuration of the memory cell array CA and the circuit CMS. The memory cell array CA and the circuit CMS have a function for calculating the sum of products of the first data and the second data. Possess the ability.

[0087] In the memory cell array CA shown in FIG. 3, memory cells AM[1,1] to Each of the memory cells AM[m, n], AMr[1] to AMr[m] is a It includes a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0088] Furthermore, memory cells AM[1,1] to AM[m,n] and memory cells AM The size of the transistor Tr11 included in the memory cells AMr[1] to AMr[m] (for example, For example, the channel length, channel width, transistor configuration, etc. are preferably equal to each other. In addition, the memory cells AM[1,1] to AM[m,n] and the memory cell A The size of the transistor Tr12 included in the memory cells Mr[1] to AMr[m] is Preferably they are equal to each other.

[0089] By making the transistors the same size, the voltage of each transistor Therefore, the memory cells AM[1,1] to AM[2,3] can be made substantially equal in electrical characteristics. The cell AM[m, n] and each of the memory cells AMr[1] to AMr[m] The size of the transistor Tr11 included therein is made equal, and the memory cells AM[1, 1] to memory cells AM[m,n], and memory cells AMr[1] to AMr By making the size of the transistor Tr12 included in each of [m] equal, The memory cells AM[1,1] to AM[m,n] and the memory cells AMr[ When the memory cells AMr[1] to AMr[m] are under the same conditions, The same operation can be performed. The potentials of the source, drain, gate, etc. of transistor Tr11, the source and drain of transistor Tr12 , the potential of the gate, the memory cells AM[1,1] to AM[m,n], and The voltages input to the memory cells AMr[1] to AMr[m], etc. Refers to...

[0090] Unless otherwise specified, the transistor Tr11 functions as a switching element. That is, the gate voltage and source voltage of the transistor Tr11 are , and the drain voltage is within the range in which the transistor Tr11 operates as a switching element. This includes the case where the transistor Tr is properly biased to the voltage 11 may operate in the saturation region when in the on state, or may operate in the linear region. There may be a mixture of cases where the device operates in the saturation region.

[0091] Unless otherwise specified, transistor Tr12 operates in the saturation region when on. That is, the gate voltage of each of the above-mentioned transistors is The bias voltage, source voltage, and drain voltage are set appropriately to voltages within the range of operation in the saturation region. This includes cases where the

[0092] The transistor Tr11 is preferably an OS transistor. The channel forming region of the transistor Tr11 contains at least one of indium, gallium, and zinc. It is more preferable that the transistor Tr11 contains an oxide containing ions. The channel forming region is made of indium, element M (element M is, for example, aluminum, Sodium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, (Examples include one or more selected from the group consisting of tungsten, magnesium, etc.) The transistor Tr11 may be an oxide containing at least one of zinc and silicon. It is more preferable that the transistor has the structure described in the fifth aspect.

[0093] By using an OS transistor as the transistor Tr11, the transistor T Since the leakage current of r11 can be suppressed, a multiply-and-accumulate circuit with high calculation accuracy can be realized. In addition, by using an OS transistor as the transistor Tr11, When the transistor Tr11 is in a non-conducting state, the holding node (for example, the node N[1,1], Node N[m,1], Node N[1,n], Node N[m,n], Node Nr[1], node Nr[m], etc.) to the write word line (for example, wiring WD[1] The leakage current to the wiring WD[n], wiring WDr, etc. can be made extremely small. In other words, the number of refresh operations of the potential of the retention node can be reduced, so that the multiply-and-accumulate operation The power consumption of the circuit can be reduced.

[0094] In addition, by using an OS transistor for transistor Tr12, Since it can be fabricated at the same time as the master transistor 11, the fabrication process of the sum-of-products operation circuit can be shortened. In addition, the channel formation region of the transistor Tr12 may be covered with oxide. The channel forming region may contain silicon (in this specification, silicon is not included in the channel forming region). The transistors that contain silicon are called silicon transistors. For example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon , polycrystalline silicon, single crystal silicon, etc. may also be used.

[0095] Incidentally, when semiconductor devices are highly integrated into chips, the chips contain a large number of circuits. Heat may be generated by driving the device. This heat may cause the temperature of the transistor to rise. This changes the characteristics of the transistor, causing changes in field-effect mobility, a decrease in operating frequency, etc. OS transistors have higher heat resistance than Si transistors, The field-effect mobility is less likely to change due to temperature changes, and the operating frequency is also less likely to decrease. In other words, OS transistors tend to maintain their electrical characteristics even at high temperatures. Therefore, by using OS transistors, it is possible to perform calculations, processing, etc. even in high temperature environments. Therefore, when configuring a semiconductor device that is resistant to heat generated by driving, As the transistor, an OS transistor is preferably used.

[0096] In FIG. 3, the transistor Tr11 and the transistor Tr12 have back gates The connection configuration of the back gate is not shown, but the back gate The electrical connection destination of the gate can be determined at the design stage. In a transistor that uses a gate and a buffer, in order to increase the on-current of the transistor, For example, the gate of the transistor Tr11 may be electrically connected to the gate of the transistor Tr12. and the back gate may be electrically connected, or the gate of the transistor Tr12 and The back gate may be electrically connected. In a transistor, to vary the threshold voltage of the transistor or In order to reduce the off-state current of the transistor, and the transistor is electrically connected to the external circuit. A potential may be applied to the back gate of the transistor.

[0097] The transistor Tr11 and the transistor Tr12 shown in FIG. However, the semiconductor device of one embodiment of the present invention is not limited to this. The transistor Tr11 and the transistor Tr12 shown in FIG. It may also be a transistor having a single gate structure, that is, a structure without a gate. In addition, some of the transistors have a back gate, and some of the transistors The capacitor may have a configuration without a back gate.

[0098] The transistor Tr11 and the transistor Tr12 shown in FIG. However, the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor Tr11 and some or all of the transistor Tr12 may be p-channel. It may be replaced with a channel transistor.

[0099] The above-mentioned examples of the changes in the structure and polarity of the transistors are as follows: transistor Tr11, The present invention is not limited to the transistors Tr12 and Tr33, which will be described later. Transistor Tr34, transistors Tr41 to Tr44, and the specification or transistors shown in other drawings. The same is true for .

[0100] Memory cells AM[1,1] to AMr[m,n] and memory cells AMr[1] to AMr[m,n] In each of the memory cells AMr[m] and AMr[m], the first terminal of the transistor Tr11 is The first gate of the transistor Tr12 is electrically connected to the gate of the transistor Tr12. The first terminal of the capacitor C1 is electrically connected to the wiring VR. It is electrically connected to the 12 gates.

[0101] In the memory cell AM[1,1], the second terminal of the transistor Tr11 is connected to the wiring WD[ The gate of transistor Tr11 is electrically connected to wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[1]. The second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the loop AM[1,1], the first terminal of the transistor Tr11 and the second terminal of the transistor Tr12 The electrical connection point between the gate of the transistor and the first terminal of the capacitor C1 is called node N[1,1]. do.

[0102] In the memory cell AM[m,1], the second terminal of the transistor Tr11 is connected to the wiring WD[ The gate of transistor Tr11 is electrically connected to wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[1]. The second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the group AM[m,1], the first terminal of the transistor Tr11 and the second terminal of the transistor Tr12 The electrical connection point between the gate of the transistor m and the first terminal of the capacitor C1 is called node N[m,1]. do.

[0103] In the memory cell AM[1,n], the second terminal of the transistor Tr11 is connected to the wiring WD[ n], and the gate of transistor Tr11 is electrically connected to wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[n]. The second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the group AM[1,n], the first terminal of the transistor Tr11 and the second terminal of the transistor Tr12 The electrical connection point between the gate of the transistor and the first terminal of the capacitor C1 is called node N[1,n]. do.

[0104] In the memory cell AM[m,n], the second terminal of the transistor Tr11 is connected to the wiring WD[ The gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[n]. The second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the group AM[m, n], the first terminal of the transistor Tr11 and the second terminal of the transistor Tr12 The electrical connection point between the gate of the transistor and the first terminal of the capacitor C1 is called node N[m,n]. do.

[0105] In the memory cell AMr[1], the second terminal of the transistor Tr11 is connected to the wiring WDr. The gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the line BLr, and the capacitance C The second terminal of the memory cell AMr[1] is electrically connected to the wiring XL[1]. 1], a first terminal of a transistor Tr11, a gate of a transistor Tr12, The electrical connection point with the first terminal of the capacitor C1 is the node Nr[1]. The current flowing from the line BLr to the second terminal of the transistor Tr12 is I AMr[1] Let's say.

[0106] In the memory cell AMr[m], the second terminal of the transistor Tr11 is connected to the wiring WDr. The gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the line BLr, and the capacitance C The second terminal of the memory cell AMr[1 is electrically connected to the wiring XL[m]. m], a first terminal of the transistor Tr11, a gate of the transistor Tr12, The electrical connection point with the first terminal of the capacitor C1 is the node Nr[m]. The current flowing from the line BLr to the second terminal of the transistor Tr12 is I AMr[2] Let's say.

[0107] The above-mentioned nodes N[1], N[m], Nr[1], and Nr[m] serves as the retention node for each memory cell.

[0108] The wiring VR is connected to the memory cells AM[1,1] to AM[m,n] and the memory cell A The first terminals of the transistors Tr12 of the memory cells Mr[1] to AMr[m] This is the wiring for passing current between the second terminals. Therefore, the wiring VR gives a predetermined potential. In this embodiment, the potential applied by the wiring VR is, for example, , a low level potential, a ground potential, or a potential lower than the ground potential.

[0109] <<Circuit CMS configuration example>> Next, an example of the configuration of the circuit CMS will be described.

[0110] In FIG. 3, the circuit CMS includes circuits CS1[1] to CS1[n] and a circuit CS2 [1] to circuit CS2[n], circuit CM, and switches SW3[1] to SW3 [n] and

[0111] The control terminals of the switches SW3[1] to SW3[n] are connected to the wiring Electrically connected to SL3.

[0112] The wiring SL3 is connected to the switch SW3[1] through the switch SW3[n]. , functioning as wiring for supplying a voltage for switching the non-conducting state.

[0113] Each of the circuits CS1[1] to CS1[n] is, for example, a current source circuit that supplies a constant current. As will be described in detail later, circuits CS1[1] to CS1[n] Each of these has the function of setting the amount of the constant current.

[0114] Each of the circuits CS1[1] to CS1[n] is a p-channel transistor. The circuit includes a transistor Tr33, a capacitor C6, and a switch SW1.

[0115] The transistor Tr33 is preferably a Si transistor. The silicon contained in the channel forming region of the transistor Tr33 is, for example, amorphous silicon. (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon , single crystal silicon, etc.

[0116] Furthermore, the transistors included in each of the circuits CS1[1] to CS1[n] It is preferable that the electrical characteristics of the transistors Tr33 are the same. The transistors Tr33 of the circuits CS1[1] to CS1[n] are equal in size to each other. It is preferable that

[0117] Furthermore, the transistor Tr33 of each of the circuits CS1[1] to CS1[n] is Unless otherwise specified, this includes the case where the device operates in the saturation region when in the on state. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors This includes the case where the device is properly biased to a voltage within the range where it operates in the saturation region. .

[0118] In each of the circuits CS1[1] to CS1[n], the transistor Tr33 The first terminal is electrically connected to the wiring VHE, and the gate of the transistor Tr33 is connected to the capacitor C6. a transistor Tr33 electrically connected to the first terminal and the first terminal of the switch SW1; The second terminal of the capacitor C6 is electrically connected to the second terminal of the switch SW1. The control terminal of the switch SW1 is electrically connected to the wiring VHE. It is electrically connected to the line SL1.

[0119] In the circuit CS1[1], the second terminal of the transistor Tr33 and the second terminal of the switch SW1 The second terminal is electrically connected to the first terminal of the switch SW3[1] and the wiring BL[1]. It has been done.

[0120] In the circuit CS1[n], the second terminal of the transistor Tr33 and the second terminal of the switch SW1 The second terminal is electrically connected to the first terminal of the switch SW3[n] and the wiring BL[n]. It has been done.

[0121] The wiring VHE functions as a wiring that applies a constant voltage. It is preferable to set the potential to a level.

[0122] The wiring SL1 is connected to the switches SW1 of the circuits CS1[1] to CS1[n]. It functions as a wiring that supplies a voltage for switching between a conductive state and a non-conductive state.

[0123] Each of the circuits CS1[1] to CS1[n] includes, for example, a transistor Tr33 Even if the source-drain voltage changes, the amount of current flowing between the source and drain is kept constant. Specifically, each of the circuits CS1[1] to CS1[n] has the following functions: Then, switch SW1 is turned on and transistor Tr33 is configured as a diode. At this time, the transistor Tr33 has a source-drain A current flows according to the source-drain (gate) voltage of the transistor Tr The potential of the gate of 33 becomes almost equal to the potential of the drain. The potential of the gate of the transistor Tr33 is maintained by the first terminal of the capacitor C6. By doing so, the gate-source voltage of transistor Tr33 can be kept constant. Therefore, when the transistor Tr33 operates in the saturation region, the drain potential changes. Even if the current is increased, the amount of current flowing between the source and drain is The amount of current can be kept constant.

[0124] In this specification and the like, the transistor is temporarily configured as a diode. Then, the potential of the gate of the transistor is made approximately equal to the potential of the drain. The gate and drain of the transistor are brought into a non-conductive state, and the source of the transistor is Maintaining a constant amount of drain-to-drain current is called "maintaining the current flowing between the source and drain of a transistor." "Setting (programming) the amount of current." Also, circuits CS1[1] to When the transistor is included in a circuit, such as each of the circuits CS1[n], "Setting (programming) the amount of current flowing into the circuit" and "The amount of current flowing out of the circuit" It is written as "setting (programming) the amount of current (flowing in)."

[0125] Each of the circuits CS2[1] to CS2[n] is, for example, a current source circuit that supplies a constant current. Each of the circuits CS2[1] to CS2[n] also functions as a circuit C As with each of the circuits S1[1] to CS1[n], the function of setting the amount of the constant current is Has.

[0126] Each of the circuits CS2[1] to CS2[n] is an n-channel transistor. The circuit includes a transistor Tr34, a capacitor C7, and a switch SW2.

[0127] The transistor Tr34 can be used as the transistor Tr11, for example. OS transistors, Si transistors, etc. can be applied. When a Si transistor is used for Tr34, the channel forming region of the transistor Tr34 The silicon contained in the silicon layer is, for example, amorphous silicon (called hydrogenated amorphous silicon). It can be microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. Cut.

[0128] Furthermore, the transistors included in each of the circuits CS2[1] to CS2[n] It is preferable that the electrical characteristics of the transistors 34 are the same. The transistors Tr34 of the circuits CS2[1] to CS2[n] are equal in size to each other. It is preferable that

[0129] Furthermore, the transistor Tr34 of each of the circuits CS2[1] to CS2[n] is Unless otherwise specified, this includes the case where the device operates in the saturation region when in the on state. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors This includes the case where the device is properly biased to a voltage within the range where it operates in the saturation region. .

[0130] In each of the circuits CS2[1] to CS2[n], the transistor Tr34 The first terminal is electrically connected to the line VLE, ​​and the gate of the transistor Tr34 is connected to the capacitor C7. A transistor Tr34 is electrically connected to the first terminal and the first terminal of the switch SW2. The second terminal of the capacitor C7 is electrically connected to the second terminal of the switch SW2. The control terminal of the switch SW2 is electrically connected to the wiring VLE. It is electrically connected to line SL2.

[0131] In the circuit CS2[1], the second terminal of the transistor Tr34 and the second terminal of the switch SW2 The second terminal is electrically connected to the second terminal of the switch SW3[1].

[0132] In the circuit CS2[n], the second terminal of the transistor Tr34 and the second terminal of the switch SW2 The second terminal is electrically connected to the second terminal of the switch SW3[n].

[0133] The wiring VLE functions as a wiring that applies a constant voltage. The constant voltage may be, for example, a low It is preferable to set the potential to a level.

[0134] The wiring SL2 is connected to the switches SW2 of the circuits CS2[1] to CS2[n]. It functions as a wiring that supplies a voltage for switching between a conductive state and a non-conductive state.

[0135] The circuits CS2[1] to CS2[n] are, for example, the circuits CS1[1] to CS2[n]. As with each of the circuits CS1[n], the source-drain voltage of the transistor Tr34 Even if the temperature changes, the amount of current flowing between the source and drain is kept constant. In each of the circuits CS2[1] to CS2[n], the switch SW2 is turned on. This sets the transistor Tr34 to a diode-connected state. Between the source and drain of transistor Tr34, there is a gate A current flows according to the voltage between the gate and the gate of the transistor Tr34. At this point, the switch SW2 is turned off and the transistor The potential of the gate of transistor Tr34 is maintained by the first terminal of capacitor C7. The gate-source voltage of transistor Tr34 can be kept constant. When the transistor Tr34 operates in the saturation region, the source-drain The amount of current flowing between the two terminals is kept constant at the amount of current that flows when switch SW2 is on. It is possible to do this.

[0136] The circuit CM functions as, for example, a current mirror circuit. Transistor Tr31 and transistors Tr32[1] to Tr32[n] and,

[0137] In addition, since the circuit CM functions as a current mirror circuit, transistor Tr3 1 and transistors Tr32[1] to Tr32[n] are respectively It is preferable that the electrical characteristics of the transistors are equal to each other. and the transistors Tr32[1] to Tr32[n] are mutually Preferably, they are all equal in size.

[0138] In addition, transistor Tr31, transistor Tr32[1] to transistor Tr3 Unless otherwise specified, each of 2[n] and operates in the saturation region when in the on state. That is, the gate voltage of each transistor and the The source and drain voltages are appropriately biased to voltages within the range in which the device operates in the saturation region. This includes cases where

[0139] Transistor Tr31 and transistors Tr32[1] to Tr32[ n] are electrically connected to the wiring VHE. The second terminal of transistor Tr31 is connected to the gate of transistor Tr31 and the ] to Tr31[n] and the wiring BLr. It continues.

[0140] The second terminal of the transistor Tr32[1] is connected to the second terminal of the switch SW3[1]. The second terminal of the transistor Tr34 of the CS2[1] circuit and the switch SW2 of the CS2[1] circuit The second terminal of the transistor Tr32[n] is electrically connected to the The terminal is connected between the second terminal of the switch SW3[n] and the terminal of the transistor Tr34 of the circuit CS2[n]. The second terminal is electrically connected to the second terminal of the switch SW2 of the circuit CS2[n]. do.

[0141] By configuring the circuit CM as shown in FIG. 3, the first terminal of the transistor Tr31 A current flowing between the second terminals of the transistors Tr32[1] to Tr32[2] is approximately equal to the current flowing between the second terminals of the transistors Tr32[3] to Tr32[4]. It can be passed between the first and second terminals of each of the transistors Tr32[n].

[0142] Switch SW1, switch SW2, switch SW3[1] to switch SW3[n] For example, an electrical switch such as an analog switch or a transistor may be used. In addition, the switches SW1, SW2, SW3[1] and For example, a mechanical switch may be used as the switch SW3[n]. The transistors SW1, SW2, SW3[1] to SW3[n] are When a transistor is applied, the transistor is an OS transistor or a Si transistor. It is possible.

[0143] The configuration of the circuit CM is not limited to the configuration shown in Fig. 3. The configuration of the circuit CM may be, for example, As shown in the circuit CM in FIG. 4, the transistor Tr31 and the transistor Tr35 are connected in series. The transistors Tr32[1] to Tr32[n] are connected by a code. and each of the transistors Tr36[1] to Tr36[n] are cascoded. As shown in Figure 4, the circuit CM is included in the current mirror circuit. The operation of the current mirror circuit is controlled by cascode-connecting the transistors. It can be made more stable.

[0144] In this embodiment, the switches SW1, SW2, and SW3[1] are Each of the switches SW3[n] is turned on when a high-level potential is input to the control terminal. When a low level potential is input, the transistor is in the OFF state.

[0145] <<Configuration example of the IVTC circuit>> Next, a configuration example of the circuit IVTC will be described.

[0146] FIG. 5A is a circuit diagram showing an example of the configuration of the circuit IVTC. , resistors RE[1] to RE[n], and operational amplifiers OP[1] to OP[n ] and switches SW4[1] to SW4[n].

[0147] The first terminal of the switch SW4[1] is electrically connected to the wiring BL[1], and the second terminal of the switch S The second terminal of W4[1] is connected to the first terminal of the resistor RE[1] and the inverting input of the operational amplifier OP[1]. The non-inverting input terminal of the operational amplifier OP[1] is electrically connected to the The output terminal of the operational amplifier OP[1] is electrically connected to VdL. The terminal and the wiring OL[1] are electrically connected. Together with the amplifier OP[1], a current-voltage conversion circuit is formed.

[0148] Similarly, the first terminal of the switch SW4[n] is electrically connected to the wiring BL[n]. The second terminal of the switch SW4[n] is connected to the first terminal of the resistor RE[n] and the operational amplifier OP[n]. The inverting input terminal of the switch SW4[1] is electrically connected to the inverting input terminal of the switch SW4[2]. The control terminal of each switch SW4[n] is electrically connected to a line SL4.

[0149] The wiring SL4 is, for example, a wiring for controlling the conduction state of the switches SW4[1] to SW4[n]. The wiring functions as a wiring for supplying a voltage for switching between a conductive state and a non-conductive state.

[0150] The non-inverting input terminal of the operational amplifier OP[n] is electrically connected to the wiring VdL. The output terminal of the amplifier OP[n] is electrically connected to the second terminal of the resistor RE[n] and the wiring OL[n]. is connected to.

[0151] The wiring VdL functions as a wiring that applies a constant voltage, for example. , for example, it can be ground potential, low level potential, etc.

[0152] That is, the circuit IVTC includes resistors RE[1] to RE[n] and an operational amplifier OP[1 ] to operational amplifier OP[n] and wiring VdL form n current-voltage conversion circuits. It is being done.

[0153] The switches SW4[1] to SW4[n] may be, for example, switches S W1, switch SW2, switch SW3[1] to switch SW3[n], etc. In this specification, the switch SW4[1] can be used. Each of the switches SW1, SW2, SW3, SW4[n] is a 3[1] to switch SW3[n], when a high-level potential is input to the control terminal When a low level potential is input, the transistor is turned on, and when a low level potential is input, the transistor is turned off.

[0154] The circuit IVTC that can be applied to the arithmetic circuit MAC1 is not limited to the circuit IVTC shown in FIG. 5A. For example, as shown in FIG. 5B, the circuit IVTC of FIG. 5A is provided with the circuit IVTC. The resistors RE[1] to RE[n] are connected to the loads LE[1] to LE[n], respectively. The loads LE[1] to LE[n] may be changed to, for example, diodes. Even when these circuit elements are used, the load LE [1] to load LE[n] and operational amplifier OP[1] to operational amplifier OP[n] , n current-voltage conversion circuits can be configured.

[0155] <<Example of circuit SWC configuration>> Next, a configuration example of the circuit SWC will be described.

[0156] FIG. 6 is a circuit diagram showing an example of the configuration of the circuit SWC, the circuit SCA, and the circuit XLD. In the circuit SWC shown in FIG. 6, each of the circuits SWT[1] to SWT[m] is , a switch SW5a, and a switch SW5b.

[0157] In the circuit SWT[1], the first terminal of the switch SW5a is connected to the wiring XL[1] and the The control terminal of the switch SW5a is electrically connected to the first terminal of the switch SW5b. , the control terminal of the switch SW5b is electrically connected to the wiring SL5B. are actively connected.

[0158] In the circuit SWT[m], the first terminal of the switch SW5a is connected to the wiring XL[m]. , and the first terminal of the switch SW5b. The terminal is electrically connected to the line SL5, and the control terminal of the switch SW5b is connected to the line SL5B. is electrically connected to

[0159] The wiring SL5 is, for example, a wiring The wiring supplies the voltage to switch the switch SW5a between the conductive state and the non-conductive state. In addition, the wiring SL5B functions as, for example, the circuits SWT[1] to SWT[m ], a voltage for switching the switch SW5b between the conductive state and the non-conductive state. It also functions as a wiring that supplies the voltage supplied to the wiring SL5 and wiring SL5B. When a digital signal is used, the signal applied to the wiring SL5 is the signal applied to the wiring SL5B. The logic of the signal can be inverted.

[0160] The switches SW5a and SW5b may be, for example, switches SW1, Switches that can be applied to switches SW2, SW3[1] to SW3[n], etc. In this embodiment, the switch SW5a and the switch Switch SW5b is connected to switch SW1, switch SW2, switch SW3[1], and As with switch SW3[n], when a high-level potential is input to the control terminal, the switch is turned on. and when a low level potential is input, the transistor is turned off.

[0161] <<Example of circuit SCA configuration>> Next, an example of the configuration of the circuit SCA will be described.

[0162] In the circuit SCA shown in FIG. 6, each of the circuits RPC[1] to RPC[m] is For example, transistor Tr41, transistor Tr42, and transistor Tr4 3, a transistor Tr44, and a circuit SNC.

[0163] The size of the transistor Tr41 included in the circuits RPC[1] to RPC[m] (e.g., channel length, channel width, transistor configuration, etc.) are preferably equal to each other. In addition, the transistors Tr included in the circuits RPC[1] to RPC[m] It is preferable that the sizes of the circuits RPC[1] to RPC[42 are equal to each other. It is preferable that the sizes of the transistors Tr43 included in each of the transistors Tr43 included in the transistors Tr43 are equal to each other. , the size of the transistor Tr44 included in the circuits RPC[1] to RPC[m] As described above, it is preferable to set the transistor sizes to be equal to each other. By doing so, the electrical characteristics of each transistor can be made approximately equal. As a result, each of the circuits RPC[1] to RPC[m] is operated under the same conditions. In some cases, it is possible to perform almost the same operation. The same conditions here are, for example, , the source, drain, and gate of each of the transistors Tr41 to Tr44. The voltages input to the circuits RPC[1] to RPC[m] It refers to the following:

[0164] Unless otherwise specified, the transistors Tr41 and Tr42 are This includes the case where the transistor Tr4 functions as a switching element. 1, and the gate voltage, source voltage, and drain voltage of transistor Tr42 are The range in which the transistors Tr41 and Tr42 operate as switching elements is This includes the case where the transistor Tr4 is properly biased to the 1, and the transistor Tr42 may operate in the saturation region when in the on state, and The operation may be performed in both the linear region and the saturation region.

[0165] In addition, unless otherwise specified, the transistors Tr43 and Tr44 are This includes the case where the transistor operates in the saturation region when it is in the on state. The gate, source, and drain voltages of each transistor are set to operate in the saturation region. This includes when properly biased to a voltage in the range.

[0166] The transistors Tr41 to Tr44 are, for example, n-channel transistors. In addition, transistors Tr41 to Tr4 4, for example, an OS transistor that can be applied to the transistor Tr12, Alternatively, it may be a Si transistor.

[0167] The circuit SNC converts the information obtained by sensing into the amount of current, and The sensor includes a photodiode that outputs the amount of light emitted from the sensor. Optical sensors, pressure sensors, gyro sensors, acceleration sensors, and auditory sensors using diodes. It can be a temperature sensor, a humidity sensor, etc. In particular, as the circuit SNC, a light sensor By applying the circuit SCA, it is possible to make it part of the image sensor. Example of a configuration in which a circuit SNC including a photodiode PD is applied to the circuit SCA in 6. Specifically, the input terminal of the photodiode PD is connected to the first terminal of the circuit SNC. The output terminal of the photodiode PD is electrically connected to the second terminal of the circuit SNC. In addition, FIG. 7A shows the circuits RPC[1] to RPC[m]. The circuit SWC is also shown to show the electrical connections between them.

[0168] The photodiode PD included in the circuit SCA of FIG. 7A detects the intensity of the received light. The amount of induced current is determined by the amount of reverse bias applied to the photodiode PD. Since the photodiode PD in Figure 7A is driven by The current flows from the output terminal of the power PD to the input terminal. Note that the circuit configuration in FIG. 7A is an example. In some cases, the circuit SCA is connected to the first terminal of the circuit SNC, and the input terminal of the photodiode PD is connected to the first terminal of the circuit SNC. The output terminal of the photodiode PD is electrically connected to the first terminal of the circuit SNC. An electrically connected configuration may also be used.

[0169] In each of the circuits RPC[1] to RPC[m], the first terminal of the circuit SNC is , the second terminal of the circuit SNC is electrically connected to the wiring VBE, and the first terminal of the transistor Tr41 is electrically connected to the wiring VBE. The gate of the transistor Tr41 is electrically connected to the wiring TXL The second terminal of the transistor Tr41 is electrically connected to the first terminal of the transistor Tr42. The terminal is electrically connected to the gate of the transistor Tr43. The gate of the transistor Tr42 is electrically connected to the wiring RSL. The first terminal of the transistor Tr43 is electrically connected to the wiring VRS. The first terminal of the transistor Tr44 is electrically connected to the line VDE. The gate of the transistor Tr44 is electrically connected to the wiring VBE. In particular, the gate of the transistor Tr43, the first terminal of the transistor Tr42, and the The electrical connection point with the second terminal of the starter transistor 41 is referred to as node NS.

[0170] In the circuit RPC[1], the second terminal of the transistor Tr43 is connected to the transistor The second terminal of Tr44 and the second terminal of switch SW5b of circuit SWT[1] are electrically connected is connected.

[0171] In the circuit RPC[m], the second terminal of the transistor Tr43 is connected to the transistor The second terminal of Tr44 and the second terminal of the switch SW5b of the circuit SWT[m] are electrically connected is connected.

[0172] The wiring VDE functions as a wiring that supplies a constant voltage, for example. For example, the wiring VDE functions as a wiring that supplies a constant voltage. is higher than the potential given by the wiring VSE.

[0173] Connection configuration of transistor Tr43 and transistor Tr44, and wiring VDE and wiring The transistor Tr43 and the transistor T r44 functions as a source follower circuit.

[0174] The wiring TXL is, for example, a transistor Tr41 that is switched between a conductive state and a non-conductive state. It functions as wiring for performing the

[0175] The wiring RSL is, for example, a resistor RSL for switching the transistor Tr42 between a conductive state and a non-conductive state. It functions as wiring for performing the

[0176] The wiring VBE functions as a wiring for supplying a constant voltage, for example. In each of the circuits PC[1] to RPC[m], the transistor Tr44 has a first terminal It is preferable that the power supply function as a constant current source, so that a constant current flows between the first terminal and the second terminal. The potential given by the line VBE is the difference between the potential given by the wiring VBE and the potential given by the wiring VSE. It is preferable that the threshold voltage of the transistor Tr44 is set to be larger than the threshold voltage of the transistor Tr44. stomach.

[0177] For example, the wiring AND functions as a wiring that supplies a constant voltage. AND functions as a wiring for supplying a voltage to drive the circuit SNC. For example, if the circuit SNC includes a photodiode PD, as shown in Figure 7A, Since it is necessary to apply a reverse bias to the photodiode PD, the constant voltage given by the wire AND It is preferable that the voltage be lower than the reset potential.

[0178] For example, the wiring VRS functions as a wiring that supplies a constant voltage. VRS supplies a potential for initialization (hereinafter referred to as a reset potential) to node NS. It functions as wiring for

[0179] Each of the circuits RPC[1] to RPC[m] performs an initial operation before sensing. As the initial operation, for example, a low level potential is input to the wiring TXL, and A high-level potential is input to the wiring RSL, which turns off the transistor Tr41. As a result, the transistor Tr42 is turned on. The gate (node ​​NS) and the wiring VRS are in a conductive state, and the gate of the transistor Tr43 A reset potential is input to the node NS.

[0180] At this time, the source followers of the transistors Tr43 and Tr44 The circuit generates a voltage corresponding to the reset potential of the gate (node ​​NS) of the transistor Tr43. The potential is the electrical connection between the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44. The signal is output from the connection point to the second terminal of the switch SW5b.

[0181] When each of the circuits RPC[1] to RPC[m] performs sensing, for example, A high level potential is input to the wiring TXL, and a low level potential is input to the wiring RSL. As a result, the transistor Tr41 is turned on and the transistor Tr42 is turned off. Therefore, the gate (node ​​NS) of the transistor Tr43 and the second terminal of the circuit SNC The gate (node ​​NS) of the transistor Tr43 is connected to the circuit SNC. The amount of charge supplied corresponds to the information obtained by sensing.

[0182] Then, a source follower circuit of the transistor Tr43 and the transistor Tr44 Therefore, the potential of the gate (node ​​NS) of the transistor Tr43 according to the amount of charge increases. The second terminal of the transistor Tr43 and the second terminal of the transistor Tr44 are electrically connected to each other. That is, the potential is output to the second terminal of the switch SW5b. It is treated as the second data to be input.

[0183] Note that the circuits RPC[1] to RP[2] in FIG. 6 are included in the semiconductor device of one embodiment of the present invention. The circuit configuration of each of C[m] may be changed depending on the situation. For example, the circuit of FIG. Each of the circuits RPC[1] to RPC[m] has a capacitance C8 at the node NS. Each of the circuits RPC[1] to RPC[m] shown in FIG. The first terminal of the capacitor C8 is electrically connected to NS, and the second terminal of the capacitor C8 is electrically connected to the wiring CVL. Each of the circuits RPC[1] to RPC[m] has a By providing the capacitor C8, the potential input to the node NS can be held for a long time. 7B shows the circuit RPC[1] to circuit RPC[m] in the same manner as in FIG. 7A. The circuit SWC is also shown to show the electrical connections to each of them.

[0184] The wiring CVL functions as a wiring that applies a constant voltage, for example. VL is one of the wiring VDE, wiring VSE, wiring AND, wiring VBE, and wiring VRS The wiring may be the same as the first wiring.

[0185] <<Example of circuit XLD configuration>> Next, a configuration example of the circuit XLD will be described.

[0186] The circuit XLD shown in FIG. 6 includes, as an example, a circuit LGC, a circuit LS, and a circuit MUX. Has.

[0187] The circuit LGC is electrically connected to the circuit LS by the wirings LXS[1] to LXS[m]. The circuit LS is connected to the wiring DXS[1] to the wiring DXS[m]. The wirings LXS[1] to LXS[m] are electrically connected to the circuit MUX. The wiring DXS[1] to the wiring DXS[m] are bus wirings for transmitting digital signals. It may function.

[0188] The circuit MUX is connected to the second terminal of each of the circuits SWT[1] to SWT[m]. a function for supplying a voltage (digital signal) corresponding to the reference data or the second data; Specifically, for example, the circuit MUX converts the digital signal input to the line DXS[1] into A digital signal is output to the second terminal of the switch SW5a of the circuit SWT[1]. For example, the circuit MUX can be a digital-to-analog conversion circuit. The potential corresponding to the digital signal input to the first switch SW5a of the circuit SWT[m] is It can be a digital-to-analog conversion circuit that outputs to two terminals.

[0189] The circuit LS has a function of level-shifting the input potential to a desired potential, for example. Specifically, for example, the circuit LS converts the potential input from the wiring LXS[1] into a desired The level is shifted to the potential, and the level-shifted potential is output to the wiring DXS[1]. Therefore, the number of wires LXS[1] can be set to the same as the number of wires DXS[1]. Similarly, for example, the circuit LS adjusts the potential input from the wiring LXS[m] to a desired potential. The level-shifted potential is output to the wiring DXS[m]. The number of wires XS[m] can be set to the same as the number of wires DXS[m].

[0190] For example, the circuit LGC sequentially holds the data DT input to the circuit LGC and outputs the desired At the same time, or sequentially, in parallel to the wiring LXS[1] to wiring LXS[m] The data DT here is output from the circuit SWC The reference data or the second data is input to the wirings XCL[1] to XCL[m] via the That is, the circuit LGC can be implemented as a data bus. ], a voltage according to the reference data or a voltage according to the second data is supplied to the circuit LG C holds the reference data or the second data received from outside, and Alternatively, the second data is transmitted to the wirings LXS[1] to LXS[m] at a predetermined timing. A specific example of the circuit configuration of the circuit LGC will be described later.

[0191] If there is no need to level-shift the voltage output from the circuit LGC, In the circuit XLD, the circuit LS is not provided, and the wirings LXS[1] to LXS[m] are and each of the wirings DXS[1] to DXS[m] are directly and electrically connected to each other. That's fine.

[0192] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0193] FIG. 8 shows a timing chart of an example of the operation of the arithmetic circuit MAC1. The route is the wiring WL[1], the wiring WL[2], and the wiring WL[3] at times T01 to T15 and in the vicinity thereof. [2], wiring WL[m] (in this operation example, m is an integer of 4 or more), wiring SL1 , wiring SL2, wiring SL3, wiring SL4, wiring SL5, wiring SL5B, wiring RSL, wiring TXL, wiring WD[1], wiring WDr, node N[1,1], node N[2,1], node Node N[m,1], Node Nr[1], Node Nr[2], Node Nr[m], Wiring XL[ 1], wiring XL[2], and wiring XL[m]. A high level potential is denoted as "High" and a low level potential is denoted as "Low."

[0194] <<From time T01 to time T02>> Between time T01 and time T02, the wiring WL[1] to wiring WL[m] A low-level potential is input to the wirings SL1 to SL4. A high-level potential is input to the wiring SL5, and a low-level potential is input to the wiring SL5B. In addition, the wiring WD[1] and wiring WDr are connected to the ground potential (GND in Figure 8). (as shown) is entered.

[0195] A high-level potential is input to the wiring SL5, and a low-level potential is input to the wiring SL5B. Therefore, in the circuit SWC, the circuits SWT[1] to SWT[m] include The switch SW5a is turned on, and the power supplies included in the circuits SWT[1] to SWT[m] are turned on. Therefore, the switch SW5b connected to the wiring XL[1] to the wiring XL[m] is turned off. Each of these is in a conductive state with the circuit XLD and in a non-conductive state with the circuit SCA. Thus, the voltage from the circuit XLD is supplied to each of the wirings XL[1] to XL[m]. Here, for example, from the circuit XLD to the wiring XL[1] to the wiring XL[m] The voltage supplied to each of these is called the reference potential (V RFP It is written as follows.) .

[0196] Between time T01 and time T02, nodes N[1,1] to N [m, n] and the potentials of the nodes Nr[1] to Nr[m] The potential is set to the ground potential (denoted as GND in FIG. 8).

[0197] <<From time T02 to time T03>> Between time T02 and time T03, the wiring SL1 and the wiring SL2 are at a high level. As a result, in the circuit CMS, the circuits CS1[1] to C The switches SW1 and circuits CS2[1] to C The switch SW2 included in each of S2[n] is turned on.

[0198] In addition, between time T02 and time T03, the wiring SL3 and the wiring SL4 A low-level potential is continuously input from before time T02, and the wiring SL5 A high level potential continues to be input to the wiring SL5 from time T01 onwards, and a low level potential continues to be input to the wiring SL5 from time T02 onwards. A level potential is input.

[0199] <<From time T03 to time T04>> Between time T03 and time T04, a high-level potential is input to the wiring WL[1]. As a result, in the memory cell array CA, the memory cells AM[1,1] and The data included in each of the memory cells AM[1, n] and AMr[1] A high level potential is applied to the gate of transistor Tr11, and each transistor Tr 11 is turned on.

[0200] In addition, between time T03 and time T04, the wiring WD[1] is at ground potential. MoV PR -V W[1,1] At this time, a large potential is input to the memory cell AM[1,1 ] transistor Tr11 is in the on state, so the wiring WD[1] and node N[1 , 1] is in a conductive state, and the first terminal (node The node N[1,1] has a potential V above ground. PR -V W[1,1] A large potential is input .

[0201] In this example, V PR is the potential corresponding to the reference data, and V W[1,1] teeth This potential corresponds to the first data stored in the memory cell AM[1,1].

[0202] In addition, between time T03 and time T04, the wiring WDr is charged with a potential higher than the ground potential V PR A large potential is input. At this time, the transistor Tr1 of the memory cell AMr[1] Since 1 is in the on state, there is conduction between the wiring WDr and node Nr[1]. The first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1] is connected to a potential higher than the ground potential. Rimo V PR A large potential is input.

[0203] Between time T03 and time T04, memory cells AM[1,2] to AM[3] Since the transistor Tr11 of the memory cell AM[1,n] is also in the on state, In this case, the memory cells AM[1] to AM[n] are connected to the wirings WD[2] to WD[n]. By inputting the first data to the memory cells AM[1, n], the node N[1, 2 ] to node N[1, n], a potential according to the first data can be written. In the operation example, the memory cells AM[1,1] to AM[1,2] electrically connected to the wiring WD[1] are memory cell AM[m,1] and memory cell AMr[1 ] to memory cells AMr[m], and other memory cells A description of the operation will be omitted.

[0204] In addition, between time T03 and time T04, the wiring WL[2] to wiring WL[m ] has been input with a low level potential since before time T03. In the cell array CA, the memory cells AM[2, 1] to memory cells AM[m,1], and memory cells AMr[2] to AMr A low level potential is applied to the gate of the transistor Tr11 included in each of [m]. The transistors Tr11 are turned off. The data input to the nodes WD[1] and WDr is Node N[m,1] and nodes Nr[2] to Nr[m] are written to. do not have.

[0205] Here, the transactions of the memory cell AM[1,1] and the memory cell AMr[1] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of the transistor Tr12 in AM[1,1] is I A M[1,1],1 When I AM[1,1],1 can be expressed by the following formula:

[0206]

number

[0207] k is the channel length, channel width, mobility, and gate insulating film thickness of the transistor Tr12. It is a constant determined by the capacitance etc. th is the threshold voltage of transistor Tr12. The constant k is not only for the memory cell AM[1,1] but also for other memory cells AM, This also applies to the memory cell AMr. The threshold voltage of the transistor Tr12 of the other memory cells AM and AMr is The voltage value is also V th Let's say.

[0208] The first terminal of the memory cell AMr[1] is connected to the wiring BLr via the second terminal of the transistor Tr12 of the memory cell AMr[1]. The current flowing through one terminal is I AMr[1],2 Similarly, when AMr[1],2 Next It can be expressed by the following formula.

[0209]

number

[0210] <<From time T04 to time T05>> Between time T04 and time T05, a low-level potential is input to the wiring WL[1]. As a result, in the memory cell array CA, the memory cells AM[1,1] and The data included in each of the memory cells AM[1, n] and AMr[1] A low level potential is applied to the gate of transistor Tr11, and each transistor Tr 11 is turned off.

[0211] In the memory cell AM[1,1], the transistor Tr11 is turned off. Therefore, the first terminal (node ​​N[1,1]) of the capacitor C1 of the memory cell AM[1,1] is connected to the ground potential. V rather than rank PR -V W[1,1] A large potential is maintained. ], the transistor Tr11 is turned off, and the memory cell AMr[ The first terminal (node ​​Nr[1]) of the capacitor C1 of PR A large potential is maintained It will be held.

[0212] <<From time T05 to time T06>> Between time T05 and time T06, a high-level potential is input to the wiring WL[2]. As a result, in the memory cell array CA, the memory cells AM[2,1] and The memory cells AM[2,n] and AMr[2] are included in each of the memory cells AM[2,n] and AMr[2]. A high level potential is applied to the gate of transistor Tr11, and each transistor Tr 11 is turned on.

[0213] In addition, between time T05 and time T06, the wiring WD[1] is at ground potential. MoV PR -V W[2,1] At this time, a large potential is input to the memory cell AM[2,1 ] transistor Tr11 is in the on state, so the wiring WD[1] and node N[2 , 1] is in a conductive state, and the first terminal (node The node N[2,1] has a V PR -V W[2,1] A large potential is input .

[0214] In this example, V W[2,1] is the second value stored in memory cell AM[2,1]. The potential corresponds to one data point.

[0215] Between time T05 and time T06, the wiring WDr is charged to a potential V PR A large potential is input. At this time, the transistor Tr1 of the memory cell AMr[2] Since 1 is in the on state, there is conduction between the wiring WDr and node Nr[2]. The first terminal (node ​​Nr[2]) of the capacitor C1 of the memory cell AMr[2] is connected to a potential higher than the ground potential. Rimo V PR A large potential is input.

[0216] In addition, between time T05 and time T06, the wiring WL[1] and the wiring WL[ A low-level potential has been continuously input to the wirings WL[3] to WL[m] since before time T05. Therefore, in the memory cell array CA, the first row and the third to mth rows are The memory cells AM[1,1], AM[3,1], and AM [m,1], memory cell AMr[1], and memory cells AMr[3] to AMr[4]. A low-level potential is applied to the gate of transistor Tr11 included in each of r[m]. The transistors Tr11 and Tr12 are in the off state. The data input to the line WD[1] and the wiring WDr are connected to the node N[1,1] and Nodes N[3,1] to N[m,1], node Nr[1], and node Nr[3] Furthermore, no data is written to node Nr[m].

[0217] Here, the transactions of the memory cell AM[2,1] and the memory cell AMr[2] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of the transistor Tr12 in AM[2,1] is I A M[2,1],1 When I AM[2,1],1 can be expressed by the following formula:

[0218]

number

[0219] Also, the line BLr is connected to the second terminal of the transistor Tr12 of the memory cell AMr[2]. The current flowing through the first terminal is I AMr[2],2 Similarly, when AMr[2], 2 can be expressed by the following formula:

[0220]

number

[0221] <<From time T06 to time T07>> Between time T06 and time T07, a low-level potential is input to the wiring WL[2]. As a result, in the memory cell array CA, the memory cells AM[2,1] and The memory cells AM[2,n] and AMr[2] are included in each of the memory cells AM[2,n] and AMr[2]. A low level potential is applied to the gate of transistor Tr11, and each transistor Tr 11 is turned off.

[0222] In the memory cell AM[2,1], the transistor Tr11 is turned off. Therefore, the first terminal (node ​​N[2,1]) of the capacitor C1 of the memory cell AM[2,1] is connected to the ground potential. V rather than rank PR -V W[2,1] A large potential is maintained. ], the transistor Tr11 is turned off, and the memory cell AMr[ 2], the first terminal (node ​​Nr[2]) of the capacitor C1 is V PR A large potential is maintained It will be held.

[0223] In addition, between time T06 and time T07, the above-mentioned time T03 to time T05 Similarly to the operation between the memory cells AM[3,1] to AM[m-1,n], A potential corresponding to the first data is held at the first terminal of each capacitor C1. For example, the first terminal (node ​​N[3,1]) of the capacitor C1 of the memory cell AM[3,1] is , V above ground potential PR -V W[3,1] A high potential is maintained, and the memory cell AM[m-1 The first terminal (node ​​N[m-1,1]) of the capacitor C1 of PR - V W[m-1,1] A high potential is maintained.

[0224] In this example, V W[3,1] is the second value stored in memory cell AM[3,1]. The potential corresponding to 1 data is V W[m-1,1] is stored in memory cell AM[m-1,1] The potential corresponds to the first data held.

[0225] <<From time T07 to time T08>> Between time T07 and time T08, a high-level potential is input to the wiring WL[m]. As a result, in the memory cell array CA, the memory cells AM[m,1] The memory cells AM[m, n] and AMr[m] are included in each of the A high level potential is applied to the gate of transistor Tr11, and each transistor Tr 11 is turned on.

[0226] In addition, between time T07 and time T08, the wiring WD[1] is at ground potential. MoV PR -V W[m,1] At this time, a large potential is input to the memory cell AM[m,1 ] is in the ON state, so the wiring WD[1] and the node N[m , 1] is in a conductive state, and the first terminal (node The node N[m,1]) has a potential V above ground. PR -V W[m,1] A large potential is input .

[0227] In this example, V W[m,1] is the first value stored in memory cell AM[m,1]. The potential corresponds to one data point.

[0228] Between time T07 and time T08, the wiring WDr is charged to a potential V PR At this time, the transistor Tr1 of the memory cell AMr[m] Since 1 is in the ON state, the line WDr and node Nr[m] are in a conductive state. The first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m] is connected to a potential higher than the ground potential. Rimo V PR A large potential is input.

[0229] In addition, between time T07 and time T08, the wiring WL[1] to wiring WL[m -1] has been continuously supplied with a low level potential since before time T07. In the memory cell array CA, memory cells A arranged from the 1st row to the m-1th row M[1,1] to memory cells AM[m-1,1], A low level is applied to the gate of transistor Tr11 included in each of the AMr[m-1] A potential is applied to each transistor Tr11, and the transistor Tr11 is in the off state. The data input to the wiring WD[1] and wiring WDr is transferred to the node N[ 1,1] to node N[m-1,1], and node Nr[1] to node Nr[m-1]. It will never be sucked in.

[0230] Here, the transactions of the memory cells AM[m,1] and AMr[m] are Consider the current flowing from the second terminal to the first terminal of the transistor Tr12. The current flowing to the first terminal through the second terminal of transistor Tr12 of AM[m,1] is I A M[m,1],1 When I AM[m,1],1 can be expressed by the following formula:

[0231]

number

[0232] Also, the line BLr is connected to the second terminal of the transistor Tr12 of the memory cell AMr[m] via the second terminal of the transistor Tr12 of the memory cell AMr[m]. The current flowing through the first terminal is I AMr[m],2 Similarly, when AMr[m], 2 can be expressed by the following formula:

[0233]

number

[0234] <<From time T08 to time T09>> Between time T08 and time T09, a low-level potential is input to the wiring WL[m]. As a result, in the memory cell array CA, the memory cells AM[m,1] The memory cells AM[m, n] and AMr[m] are included in each of the A low level potential is applied to the gate of transistor Tr11, and each transistor Tr 11 is turned off.

[0235] In the memory cell AM[m,1], the transistor Tr11 is turned off. Therefore, the first terminal (node ​​N[m,1]) of the capacitor C1 of the memory cell AM[m,1] is connected to the ground potential. V rather than rank PR -V W[m,1] A large potential is maintained. ], the transistor Tr11 is turned off, and the memory cell AMr[ The first terminal (node ​​Nr[m]) of the capacitor C1 of PR A large potential is maintained It will be held.

[0236] Here, the first terminal of the transistor Tr33 of the circuit CS1[1] included in the circuit CMS Let us consider the current flowing between the first and second terminals. In this example, the amount of this current is I1 It is written as follows.

[0237] Between time T08 and time T09, the switch SW1 of the circuit CS1[1] is turned on. ON state, switch SW3[1] is OFF state, switch SW4[1] of circuit IVTC is OFF Since this state is the first terminal - second terminal of transistor Tr33 of circuit CS1[1] The amount of current I1 flowing between them can be written as follows according to Kirchhoff's law: can.

[0238]

number

[0239] In addition, the transistor Tr33 in the circuit CS1[1] is configured as a diode. The first terminal of the transistor Tr33 of the circuit CS1[1] is connected to a high level as a constant voltage. The wiring VHE that gives the transistor potential is electrically connected, so the transistor of the circuit CS1[1] The potential of the gate (second terminal) of transistor Tr33 is the first terminal-second terminal of transistor Tr33. It is determined by the amount of current I1 flowing between the electrodes.

[0240] Also, the first terminal of the transistor Tr34 of the circuit CS2[1] included in the circuit CMS - Consider the current flowing between the second terminal. In this example, the amount of this current is I2. Write it down.

[0241] Between time T08 and time T09, the switch SW2 of the circuit CS2[1] is turned on. In the ON state, the switch SW3[1] is in the OFF state, so the transistor of the circuit CS2[1] The amount of current flowing between the first and second terminals of transistor Tr34 is ] is approximately equal to the amount of current flowing between the first and second terminals of

[0242] In addition, since the circuit CM is configured as a current mirror circuit, transistor Tr3 The amount of current flowing between the first and second terminals of 2[1] is the first terminal of transistor Tr31. -The amount of current flowing between the second terminals is approximately equal to the amount of current flowing between the first terminal and the second terminal.

[0243] The amount of current flowing between the first and second terminals of the transistor Tr31 is Since this is the sum of the currents flowing through the memory cells AMr[1] to AMr[m], The amount of current I2 flowing between the first and second terminals of transistor Tr34 of CS2[1] is It can be written as follows:

[0244]

number

[0245] In addition, the transistor Tr34 in the circuit CS2[1] is configured as a diode. The first terminal of the transistor Tr34 of the circuit CS2[1] is connected to a high level as a constant voltage. The wiring VLE that gives the transistor potential is electrically connected, so the transistor of the circuit CS2[1] The potential of the gate (second terminal) of transistor Tr34 is the first terminal-second terminal of transistor Tr34. It is determined by the amount of current I2 flowing between the electrodes.

[0246] <<From time T09 to time T10>> Between time T09 and time T10, a low-level potential is input to the wiring SL1. A low-level potential is input to the wiring SL2. The switch SW1 included in each of the circuits S1[1] to CS1[n] is in the off state. The switches SW2 included in each of the circuits CS2[1] to CS2[n] are is in the off state.

[0247] Therefore, the transistor of the circuit CS1[1] between time T09 and time T10 The potential of the gate of transistor Tr33 is held by the first terminal of capacitor C6, and the potential of circuit CS2 The potential of the gate of the transistor Tr34 in [1] is held by the first terminal of the capacitor C7. This maintains the gate-source voltage of transistor Tr33 in circuit CS1[1]. Therefore, a current I1 always flows between the first and second terminals of the transistor Tr33. Similarly, the gate of the transistor Tr34 in the circuit CS2[1] is set to Since the voltage between the terminals of the transistor Tr34 and the source is maintained, The current is set to I2 at all times. In other words, the circuit CS[1] has a The amount of current I1 flowing out of S[1] is set, and the amount of current I2 flowing out of circuit CS[2] is set. The amount of current flowing in, I2, is set.

[0248] <<From time T10 to time T11>> Between time T10 and time T11, a high-level potential is input to the wiring RSL. As a result, the circuits RPC[1] to RPC[m] included in the circuit SCA Each transistor Tr42 is turned on.

[0249] The transistor Tr42 of each of the circuits RPC[1] to RPC[m] is in the on state. By this, the nodes NS of the circuits RPC[1] to RPC[m] are A reset potential is supplied to the line VRS.

[0250] <<From time T11 to time T12>> Between time T11 and time T12, a low-level potential is input to the wiring RSL. As a result, the circuits RPC[1] to RPC[m] included in the circuit SCA The transistor Tr42 included in each of them is turned off.

[0251] The transistor Tr42 of each of the circuits RPC[1] to RPC[m] is in the off state. By this, to each node NS of the circuit RPC[1] to the circuit RPC[m] The supply of the reset potential from the wiring VRS is stopped.

[0252] The operation between time T10 and time T12 described above causes the The circuits RPC[1] to RPC[m] are initialized.

[0253] At this time, the source followers of the transistors Tr43 and Tr44 The circuit connects the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44 A potential corresponding to the potential of the node NS is output from the transistor Tr43. A potential corresponding to the reset potential is output from the second terminal and the second terminal of the transistor Tr44. As an example, the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44 are connected to each other. The potential output from the second terminal is the same as that of the second terminal from time T01 to time T09. V supplied to line XL[1] to wiring XL[m] RFP The potential is approximately equal to Specifically, for example, wiring VRS, wiring VDE, wiring VSE, wiring VBE, etc. By adjusting the potential applied by the RFP A potential approximately equal to

[0254] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is input to the wiring TXL. As a result, the circuits RPC[1] to RPC[m] included in the circuit SCA Each transistor Tr41 is turned on.

[0255] The transistor Tr41 of each of the circuits RPC[1] to RPC[m] is in the on state. By this, a current corresponding to the information sensed by the circuit SNC flows through the transistor. This causes the current to flow between the first and second terminals of the starter transistor 41. Each node NS of RPC[m] is charged with an amount of charge according to the information.

[0256] <<From time T13 to time T14>> Between time T13 and time T14, a low-level potential is input to the wiring TXL. As a result, the circuits RPC[1] to RPC[m] included in the circuit SCA The transistor Tr41 included in each of them is turned off.

[0257] The transistor Tr41 of each of the circuits RPC[1] to RPC[m] is in the off state. By this, to each node NS of the circuit RPC[1] to the circuit RPC[m] The current from the circuit SNC is stopped.

[0258] By the operation between time T12 and time T14 described above, the node NS is connected to the circuit S It is possible to hold an amount of charge according to the information sensed by the NC.

[0259] At this time, the source followers of the transistors Tr43 and Tr44 The circuit connects the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44 A potential corresponding to the potential of the node NS is output from the transistor Tr43. The second terminal of the transistor Tr44 is sensed by the circuit SNC. A potential corresponding to the received information is output.

[0260] <<From time T14 to time T15>> Between time T14 and time T15, a high-level potential is input to the line SL3. A high-level potential is input to the wiring SL4, a low-level potential is input to the wiring SL5, and A high level potential is input to the line SL5B. The switches SW3[1] to SW3[n] are turned on. In this case, the switches SW4[1] to SW4[n] are turned on. In WC, the switches SW5a included in the circuits SWT[1] to SWT[m] is turned off, and the switches SW 5b is turned on.

[0261] The switch SW5a included in the circuits SWT[1] to SWT[m] is in the off state. The switch SW5b included in the circuits SWT[1] to SWT[m] is turned on. As a result, each of the wirings XL[1] to XL[m] is connected to the circuit XLD. This results in a non-conductive state and a conductive state with the circuit SCA. Each of XL[m] includes the circuits RPC[1] to RPC[m]. A potential corresponding to the information acquired by the circuit SNC is input. The potential input from the circuit RPC[1] to the wiring XL[1] is V higher than the ground potential. RFP +V X [1] The potential input from the circuit RPC[2] to the wiring XL[2] is set to a high potential. V rather than rank RFP +V X[2] The high potential is input from the circuit RPC[m] to the wiring XL[m]. The applied potential is V above ground potential. RFP +V X[m] A high potential is used.

[0262] In this example, the potential V X[1] ~V X[m] is the voltage corresponding to the second data It is ranked 1st.

[0263] Between time T14 and time T15, the potential of the wiring XL[1] is the reference potential. RuV RFP From V RFP +V X[1]Therefore, the memory cell AM[1] and the memory The second terminal of each capacitor C1 of the resistor AMr[1] is V RFP +V X[1] is applied At this time, the node N[1,1] and the node Nr[1] are electrically floating. Because the node N[1,1] and the node Nr The potential of each of [1] changes.

[0264] In each of the memory cells AM[1] and AMr[1], the transistor The increase in the potential of the gate of the data transistor Tr12 is due to the change in the potential of the line XL[1]. The capacitance coupling coefficient is determined by the capacitance of the capacitor C1. , is calculated based on the gate capacitance and parasitic capacitance of the transistor Tr12. To avoid the complexity of the explanation, the increase in the potential of the wiring XL[1] is also The increase in the gate potential is also assumed to be the same value. This corresponds to the capacitive coupling coefficients of the memory cell AMr[1] and the memory cell AMr[2] being set to 1. In this operation example, the memory cells AM[1, 1], and for memory cells other than memory cell AMr[1], The explanation will be given assuming the number 1.

[0265] Since the capacitance coupling coefficient is set to 1, the memory cell AM[1,1] and the memory cell AMr The potential of the second terminal of each capacitor C1 in [1] is V RFP From V RFP +V X[1] Change to By this operation, the potentials of the node N[1,1] and the node Nr[1] are V X[1] Rise.

[0266] Here, the second terminal of the transistor Tr12 of the memory cell AM[1,1] is connected to the wiring BL. The current flowing through the first terminal is I AM[1,1],3 When I AM[1.1],3 can be expressed by the following formula:

[0267]

number

[0268] Similarly, the second terminal of the transistor Tr12 of the memory cell AMr[1] is connected to the wiring BLr. The current flowing through the first terminal is I AMr[1],4 When I AMr[1],4 Next It can be expressed by the following formula.

[0269]

number

[0270] In addition, the memory cell AM[2,1] and the memory cell AMr[2] also have capacitive coupling. Since the coefficient is set to 1, the potential of the second terminal of the capacitance C1 included in each is V RFP From V RFP +V X[2] By changing to The potential of r[2] is V X[2] Rise.

[0271] Here, the second terminal of the transistor Tr12 of the memory cell AM[2,1] is connected to the wiring BL. The current flowing through the first terminal is I AM[2,1],3 When I AM[2.1],3 can be expressed by the following formula:

[0272]

number

[0273] Similarly, the second terminal of the transistor Tr12 of the memory cell AMr[2] is connected to the wiring BLr. The current flowing through the first terminal is I AMr[2],4 When I AMr[2],4 Next It can be expressed by the following formula.

[0274]

number

[0275] In addition, the memory cell AM[m,1] and the memory cell AMr[m] also have capacitive coupling Since the coefficient is set to 1, the potential of the second terminal of the capacitance C1 included in each is V RFP From V RFP +V X[m] By changing to The potential of r[m] is V X[m] Rise.

[0276] Here, the second terminal of the transistor Tr12 of the memory cell AM[m,1] is connected to the wiring BL. The current flowing through the first terminal is I AM[m,1],3 When I AM[m.1],3 can be expressed by the following formula:

[0277]

number

[0278] Similarly, the second terminal of the transistor Tr12 of the memory cell AMr[2] is connected to the wiring BLr. The current flowing through the first terminal is I AMr[m],4 When I AMr[m],4 Next It can be expressed by the following formula.

[0279]

number

[0280] Between time T14 and time T15, the line BL[1] is connected to the memory cell AM[1 When the total amount of current flowing through memory cells AM[m,1] to AM[m,1] is I3, The quantity I3 can be written as follows:

[0281]

number

[0282] In addition, since the circuit CM is configured as a current mirror circuit, The amount of current flowing between the first and second terminals of the transistor Tr32[1] is The amount of current flowing between the first and second terminals of the transistor 31 is approximately equal to the amount of current flowing between the first and second terminals of the transistor 31. The amount of current flowing between the first and second terminals of the transistor Tr31 is This is the sum of the currents flowing through the memory cells AMr[1] to AMr[m]. During the time period up to time T15, the first transistor Tr32[1] included in the circuit CM When the amount of current flowing between the terminal and the second terminal is I4, the amount of current I4 is calculated as follows: It can be described.

[0283]

number

[0284] Between time T14 and time T15, the switches SW3[1] to S W3[n] and switches SW4[1] to SW4[n] are turned on. The circuit IVTC receives power from the circuit CMS and the memory cell array CA through the wiring BL. Specifically, for example, a current I1 flows out of the circuit CS1[1], and A current I2 flows into transistor Tr32[1] in the circuit CM. A current I4 flows between the memory cells AM[1,1] and AM[ The sum of the currents flowing through each of the wires BL[1] and BL[m, 1] is I3. The amount of current flowing through OL[1] is I S When [1] is set, the amount of current I S [1] is Kirchhoff This can be written as follows using Pfaff's law:

[0285]

number

[0286] From equation (1.17), the amount of current I input from wiring BL[1] to circuit IVTC S [1 ] is the potential V according to the first data W[1,1] ~V W[m,1] And, according to the second data The potential V X[1] ~V X[m] In other words, the sum of the products of the first and second data is proportional to The sum of products is the amount of current I S It can be expressed as [1].

[0287] <Operation example 2 of the arithmetic circuit> The operation of the semiconductor device of one embodiment of the present invention is shown in the timing chart of FIG. The operation of the semiconductor device according to one embodiment of the present invention can be changed depending on the situation. This can be done.

[0288] The operation shown in the timing chart of FIG. 8 is performed between time T01 and time T14. , the circuit XLD is connected to the wiring XL[1] to the wiring XL[m] via V RFP It is an action of giving However, between time T01 and time T14, the circuit RPC included in the circuit SNC [1] to the circuit RPC[m] respectively apply a potential to the wiring XL[1] to the wiring XL[m]. The action may be to

[0289] Specifically, for example, the operation of the semiconductor device of one embodiment of the present invention is performed in accordance with the timing shown in FIG. The operation of the timing chart of FIG. 9 may be performed by always connecting the wiring SL5 At the point where a low level potential is input to the wiring SL5B and a high level potential is always input to the wiring SL5B, , which is different from the operation of the timing chart of FIG. 8. XL[m] and the circuit XLD are always in a non-conductive state, and the wiring XL[1] to the wiring XL[m] and the circuit SCA are always in a conductive state.

[0290] In the operation of the timing chart of FIG. 9, between time T01 and time T02, A high-level potential is input to the wiring RSL. A reset potential is supplied to the nodes NS of the circuits PC[1] to RPC[m]. Between time T02 and time T12, a low-level potential is input to the wiring RSL, and the circuit A reset potential is maintained at the nodes NS of the circuits RPC[1] to RPC[m]. Between time T01 and time T12, transistor Tr43 and transistor The source follower circuit of transistor Tr44 connects the second terminal of transistor Tr43 and the The second terminal of the transistor Tr44 outputs a potential corresponding to the reset potential of the node NS. A high-level potential is applied to the wiring SL5B, and the switch SW5b is in the on state. Therefore, the potential corresponding to the reset potential of the node NS is applied to the wirings XL[1] to XL[m ]. In the timing chart of FIG. 9, the signals are output to the wiring XL[1] to the wiring XL[ m] is the potential output by the circuit XLD in the timing chart of FIG. and similar V RFP It states that:

[0291] In the operation of the timing chart of FIG. 9, between time T12 and time T13, In other words, a high-level potential is input to the wiring TXL. The nodes NS of the circuits RPC[1] to RPC[m] are sensed by the circuit SNC. After time T13, the wiring TX A low level potential is input to L, and a low level potential is input to the nodes NS of the circuits RPC[1] to RPC[m]. The charge amount is maintained. After time T13, the transistor Tr43, The source follower circuit of the transistor Tr44 The charge held at node NS is supplied from the terminal and the second terminal of transistor Tr44. A high level potential is applied to the wiring SL5B, and the switch SW 5b is in the ON state, the potential according to the amount of charge held at the node NS is The signals are output to the wirings XL[1] to XL[m]. , the potential output to the wiring XL[1] is V RFP +V X[1] and output to wiring XL[2] The potential is V RFP +V X[2] The potential output to the wiring XL[m] is V RFP + V X[m] It states that:

[0292] <Operation example 3 of the arithmetic circuit> The operation of the semiconductor device of one embodiment of the present invention is shown in the timing charts in FIGS. Instead of the above operation, the operation shown in the timing chart of FIG. 10 may be adopted.

[0293] In the operation of the timing chart of FIG. 10, a high-level potential is always input to the wiring SL5, and At the same time, a low-level potential is always input to the wiring SL5B, which is the timing chart of FIG. Therefore, the wiring XL[1] to the wiring XL[m] and the circuit XLD are always The wiring XL[1] to the wiring XL[m] and the circuit SCA are always in a non-conductive state. It is as follows.

[0294] Since the wiring XL[1] to the wiring XL[m] and the circuit SCA are always in a non-conductive state, In the operation of the timing chart of Figure 10, the circuit RPC[1] included in the circuit SCA Therefore, the circuit RPC[m] does not operate. For example, a low-level potential is always input to the wiring RSL and the wiring TXL.

[0295] The operation of the timing chart of FIG. 10 is the same as that of the wirings XL[1] to XL[m]. 8 and 9 in that the supply of potential to the This is different from the behavior of the timing chart.

[0296] In the operation of the timing chart of FIG. 10, from before time T01 to time T14 Between the wirings XL[1] to XL[m], the wirings XL[1] to XL[m] are connected from the circuit XLD through the circuit SWC. At each of these potentials V RFPis being supplied.

[0297] In the operation of the timing chart of FIG. 10, after time T14, the wiring XL[ 1] from the circuit XLD through the circuit SWC, V RFP +V X[1] is being supplied Similarly, the wiring XL[2] is connected to the V RF P +V X[2] Similarly, the power supply is supplied from the circuit XLD via the circuit SWC. , V RFP +V X[m] is being supplied.

[0298] As described above, in the semiconductor device of one embodiment of the present invention, the wiring XL[1 ] to the wiring XL[m], a circuit for outputting a potential to be input to the wiring XL[m] is a circuit XLD or a circuit S In other words, in the semiconductor device of one embodiment of the present invention, the circuit SWC can be selected from The second data may be information acquired from a sensor or other device provided outside the arithmetic circuit. Select whether to use the internal data stored in a storage device that is connected to the computer as the second data, and Calculations can be performed.

[0299] After performing either the operation example 2 or the operation example 3 of the arithmetic circuit, Without updating the first data written in the recell array CA (time T03 to time T08 By performing the other of the operation example 2 of the arithmetic circuit or the operation example 3 of the arithmetic circuit (without performing the operation of ... In each operation example, the results output from the wirings NIL[1] to NIL[n] are compared. For example, as shown in FIG. 7A, a photodiode is used as the SNC circuit. When the circuit SNC including the photodiode PD is applied, the photodiode PD is The image captured by the circuit and the internal data input from the circuit XLD in operation example 3 of the calculation circuit are In particular, the hierarchical content described in the fourth embodiment can be compared with the corresponding image. When performing image recognition using neural networks, etc., the operation example 2 of the arithmetic circuit and the By comparing the results output by each of the operation examples of the arithmetic circuit, the operation of the arithmetic circuit can be The voltage of each wiring in Example 2 (for example, wiring VBE, wiring VDE, wiring VSE, and wiring VR voltage given by S, voltages input to each of wires XL[1] to XL[n], etc.) This allows you to optimize the settings and reduce the signal amplitude (current, voltage, etc.). This allows inference to be performed in a short amount of time.

[0300] In the above-mentioned operation example 2 of the arithmetic circuit, the circuits RPC[1] to RPC[ m] is at the reset potential, the second terminal of the transistor Tr43, and the potential supplied from the second terminal of the transistor Tr44 is V RFP Also, the circuit As shown in Figure 7A, a circuit SNC including a photodiode PD was used. When a certain intensity of light is incident on the photodiode PD, the transistor Tr The potential supplied from the second terminal of transistor Tr43 and the second terminal of transistor Tr44 is approximately (between time T12 and time T13). That is, the calculation circuit MAC1 The potential of the wiring XL[1] to wiring XL[m] is obtained by the photodiode PD. According to the data, the potential V RFP This changes in proportion to time. The output voltage is proportional to the data acquisition time (between time T12 and time T13) by the PD. Therefore, the relative difference in the output signals becomes large enough to be used for inference judgment. If there is a problem, the inference can be terminated at that point, and the inference can be completed in a short time. be.

[0301] In this embodiment, the transistors included in the arithmetic circuit MAC1 are OS transistors. In the above, the case where a silicon transistor or a silicon transistor is used has been described. The transistors included in the arithmetic circuit MAC1 are not limited to those made of, for example, Ge. Transistors with active layers made of ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Which compound semiconductors are used as active layers? Which carbon nanotubes are used as active layers? A transistor having an active layer made of an organic semiconductor, or the like can be used.

[0302] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0303] (Embodiment 2) In this embodiment, a calculation circuit having a different configuration from the calculation circuit MAC1 described in the first embodiment is used. Explain about the road.

[0304] <Configuration example 2 of arithmetic circuit> The arithmetic circuit MAC2 shown in FIG. 11 includes memory cells AMb[1] and AMb[2] in the memory cell array CA. It differs from the arithmetic circuit MAC1 in that it has a memory cell AMb[n].

[0305] The memory cell AMb[1] is connected to the wiring BL[1], the wiring WD[1], the wiring XLb, and the wiring The memory cell AMb[n] is electrically connected to the line BL[ The wiring WD[n] is electrically connected to the wiring WD[n], the wiring XLb, and the wiring WLb.

[0306] A specific configuration example of the memory cells AMb[1] to AMb[n] is shown in FIG. 12. 12 shows the memory cells AMb[1] to AMb[n]. To show the electrical connection between them, memory cells AM[1,1] to AM[m, n], memory cells AMr[1] to AMr[m], a circuit WDD, and a circuit C Also shown are MS, circuit IVTC, and circuit ACTV.

[0307] As shown in FIG. 12, memory cells AMb[1] to AMb[n] are memory cells. The memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m,n] Therefore, the calculation circuit of FIG. In the circuit MAC2, each of the memory cells AMb[1] to AMb[n] is a It includes a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0308] In each of the memory cells AMb[1] to AMb[n], A first terminal of the transistor Tr12 is electrically connected to the line VRA.

[0309] In addition, in the memory cell AMb[1], the first terminal of the transistor Tr11 and the The electrical connection point between the gate of the transistor Tr12 and the first terminal of the capacitor C1 is called a node Nb[ In the memory cell AMb[n], the first The electrical connection point between the terminal, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is the node Nb[n].

[0310] The wiring WLb is used to write data to the memory cells AMb[1] to AMb[n]. When writing, the circuit WLD writes the following to the memory cells AMb[1] to AMb[n]: The line XLb functions as a line for supplying a selection signal. A constant potential is applied to the second terminal of the capacitor C1 of each of the memory cells AMb[1] to AMb[n]. The constant potential can be a ground potential, a low level potential, a high level potential, etc. Alternatively, the wiring XLb may be a wiring for supplying an arbitrary potential from the circuit XLD. It may also function as wiring for

[0311] The wirings VRA of the memory cells AMb[1] to AMb[n] are The memory cells AM[1,1] to AM[m,n], and the memory cells AMr[1] to AMr[m,n] Like each wiring VR of the memory cell AMr[m], Alternatively, the memory cells AMb[1] to AMb[2] may be set to a potential lower than the ground potential. Each wiring VRA of the cell AMb[n] may be a wiring that provides a high level potential. For example, a positive current flows from the memory cell AMb[1] to the wiring BL[1]. If you want to do this, the wiring VRA of the memory cell AMb[1] should be a wiring that applies a high-level potential. That's fine.

[0312] As an example of the operation of the arithmetic circuit MAC2 in FIG. 12, for example, in the timing chart of FIG. In the period from before time T01 to time T14, memory cells AMb[1] to AMb[2] are The node Nb[1] is connected to the transistor Tr12 of the cell AMb[n] so that the transistor Tr12 of the cell AMb[n] is turned off. The node Nb[n] is held at the ground potential, low level potential, or potential given by the wiring VR. In the timing chart of FIG. 8, between time T14 and time T15, Transistor Tr12 of each of memory cells AMb[1] to AMb[n] The amount of current I between the first and second terminals of BIAS [1]~I BIAS [n] flows In this way, a potential V BIAS [1]No To V BIAS [n]. For example, in this case, I BIAS [1] is expressed by the following formula: do.

[0313]

number

[0314] Therefore, between time T14 and time T15, for example, from the wiring BL[1] , the amount of current I flowing through the circuit IVTC to the wiring OL[1] S [1] is as follows: become.

[0315]

number

[0316] Equation (2.2) corresponds to an operation that further applies an arbitrary bias to the result of the multiply-and-accumulate operation. As will be described in detail in the fourth embodiment, it is possible to further apply an arbitrary bias to the result of the sum-of-products operation. The calculation is used for the calculation of a hierarchical neural network. It can be said that AC2 is suitable for performing calculations of a hierarchical neural network.

[0317] <Configuration example 3 of an arithmetic circuit> Next, an embodiment of the present invention different from the arithmetic circuit MAC1 in FIG. 1 and the arithmetic circuit MAC2 in FIG. A configuration example of an arithmetic circuit, which is a semiconductor device of this type, will be described.

[0318] The arithmetic circuit MAC3 shown in FIG. 13 is a circuit diagram of a circuit CMS. The current flowing through the calculation circuit MAC1 and the calculation circuit MAC2 is related to the result of the sum calculation. This differs from MAC2.

[0319] In the arithmetic circuit MAC3 of FIG. 13, the circuit CMS includes wirings BLO[1] to BLO[3]. It is electrically connected to the circuit IVTC via [n]. For this, please refer to the explanation of the arithmetic circuit MAC1 in FIG.

[0320] A specific example of the configuration of the circuit CMS is shown in Figure 14. Note that in Figure 14, the connection with the circuit CMS To illustrate the configuration, the circuit IVTC is also shown.

[0321] The circuit CMS shown in FIG. 14 is a circuit in which the switching element is removed from the circuit CMS shown in FIG. 3 described in the first embodiment. The second terminal of the switch SW3[1], the second terminal of the transistor Tr32[1], and the circuit CS2 [1] and the second terminal of the transistor Tr34 are electrically connected to the wiring BLO[1]. the second terminal of the transistor SW3[n], the second terminal of the transistor Tr32[n], and the circuit CS The second terminal of the transistor Tr34 of 2[n] is electrically connected to the wiring BLO[n]. It is composed of:

[0322] The circuit IVTC shown in FIG. 14 has a configuration similar to that of the circuit IVTC shown in FIG. 5A. The wirings BL[1] to BL[n] shown in FIG. 5A are respectively connected to wirings BLO[1] to BLO[n]. BLO[n] is replaced with the wiring BLO[1] to the wiring BLO[n]. These are the switches SW4[1] to S included in the circuit IVTC of FIG. 5A. W4 are electrically connected to the first terminals of the respective W4.

[0323] The circuit CMS and the circuit IVTC having the configuration shown in FIG. 14 are applied to the arithmetic circuit MAC3 of FIG. By using this, it is possible to perform the same operation as the arithmetic circuit MAC1 described in the first embodiment. can be done.

[0324] The configuration of the circuit CMS and the circuit IVTC included in the arithmetic circuit MAC3 in FIG. is not limited to the configuration shown in Fig. 14. For example, the arithmetic circuit MAC3 in Fig. 13 may be The circuit CMS and the circuit IVTC may have the configuration example shown in FIG.

[0325] The circuit CMS shown in FIG. 15 is the circuit CMS of FIG. 3 described in the first embodiment, except that a switch SW Specifically, the switch S The first terminal of W6[1] is connected to the second terminal of the switch SW3[1] and the second terminal of the transistor Tr32[ 1] and the second terminal of transistor Tr34. In addition, the second terminal of the switch SW6[1] is electrically connected to the wiring BLO[1]. The control terminals of the switches SW6[1] to SW6[n] are connected to the wiring S Electrically connected to L6.

[0326] The switches SW6[1] to SW6[n] may be, for example, switches S W1, switch SW2, switch SW3[1] to switch SW3[n], etc. In this specification, the switch SW6[1] can be used. Each of the switches SW1, SW2, SW3, SW4, SW5, SW6[n] is a 3[1] to switch SW3[n], when a high-level potential is input to the control terminal When a low level potential is input, the transistor is turned on, and when a low level potential is input, the transistor is turned off.

[0327] The circuit IVTC shown in FIG. 15 is the same as the circuit IVTC shown in FIG. 5A except that the switch SW4 The configuration does not include switches [1] to SW4[n]. Each of the operational amplifiers OP[1] to OP[n] included in the circuit IVTC The inverting input terminals of the .

[0328] That is, the circuit CMS of FIG. 15 is the same as the switch SW4 included in the circuit IVTC of FIG. [1] to switch SW4[n], respectively. The switch SW6[n] is provided.

[0329] In addition, using the circuit CMS and the arithmetic circuit MAC3 to which the circuit IVTC of FIG. 15 is applied, When the operations of the timing charts of FIGS. 8 to 10 described in the first embodiment are performed, Switches SW3[1] to SW3[n] and switches SW6[1] to SW6[n] n] are turned on or off at the same timing, so the wiring SL 3 and the wiring SL6 may be combined into one wiring.

[0330] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0331] (Embodiment 3) In this embodiment, the arithmetic circuits MAC1 to MAC2 described in the first and second embodiments are An example of the configuration of the circuit LGC provided in the circuit XLD of the arithmetic circuit MAC3 will be described.

[0332] 16A shows a specific example of the circuit configuration of the circuit LGC. When XS[m] is a bus line that transmits digital signals, it is input to the circuit LGC. The data DT (reference data and the second data) may be input as a digital signal. By treating the data DT as a digital signal, the circuit LGC functions as a logic circuit. It can be configured as follows.

[0333] The circuit LGC shown in FIG. 16A includes a shift register SR and latch circuits LTA[1] to LTA[2]. latch circuit LTA[m], latch circuit LTB[1] to latch circuit LTB[m], and switch The switches SW8[1] to SW8[m] are provided.

[0334] The shift register SR includes a line SPL, a line SCL, and lines SEL[1] to SE L[m] and is electrically connected to

[0335] The control terminals (clock The SEL[1] wiring (sometimes called an input terminal, enable signal input terminal, etc.) to wiring SEL[m] are electrically connected, and the latch circuits LTB[1] to LT The wiring LAT is electrically connected to each control terminal of B[m]. The input terminals D of the circuits LTA[1] to LTA[m] are connected to the wiring DAT. The outputs of the latch circuits LTA[1] to LTA[m] are electrically connected to each other. The input terminal Q is electrically connected to each of the wirings DL[1] to DL[m]. The input terminals D of the latch circuits LTB[1] to LTB[m] are connected to the wiring D L[1] to L[m] are electrically connected to the wirings DL[m] to DL[m]. The output terminal Q of each of the paths LTB[m] is connected to the switches SW8[1] to SW8[m]. m]. The second terminals of the switches SW8[m] are connected to the second terminals of the wirings LXS[1] to LXS[m]. are electrically connected to the respective switches SW8[1] to SW8[m]. The control terminals are electrically connected to the wirings SL8[1] to SL8[m]. do.

[0336] In addition, the switches SW8[1] to SW8[m] may be, for example, switches S W1, switch SW2, switch SW3[1] to switch SW3[n], etc. In this specification, the switch SW8[1] can be used. Each of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8[m] is a 3[1] to switch SW3[n], when a high-level potential is input to the control terminal When a low level potential is input, the transistor is turned on, and when a low level potential is input, the transistor is turned off.

[0337] Each of the wirings SL8[1] to SL8[m] is connected to a switch SW8[ Wiring for switching the conductive state and non-conductive state of switches SW8[m] to SW8[m]; It functions as such.

[0338] The wiring SPL is, for example, a wiring that transmits a start pulse signal to the shift register SR. It functions as:

[0339] The line SCL is, for example, a line that transmits a clock signal to the shift register SR. It functions as:

[0340] In addition, the wiring DAT functions as a wiring for transmitting data DT to the circuit LGC, for example. do.

[0341] Wiring SEL[1] to wiring SEL[m], wiring DL[1] to wiring DL[m], and wiring Each of the lines DAT can be a wiring for transmitting a digital signal. Lines SEL[1] to SEL[m], lines DL[1] to DL[m], and lines D Each of the lines SL8[1] to SL9[2] can be a bus line. 8 [m] can also be used as bus wiring.

[0342] The shift register SR, for example, converts potentials input to the wirings SPL and SCL. In accordance with the change, a high-level potential is sequentially output to the wirings SEL[1] to SEL[m]. The shift register SR has the following functions: A high-level potential cannot be output to two or more of the wirings SEL[1] to SEL When any one of the wirings SEL[1] to SE[m] outputs a high-level potential, The remaining wiring of L[m] outputs a low-level potential.

[0343] For example, when a high level potential is input to the wiring SPL as a start pulse signal, For example, when the potential changes from a low level potential to a high level potential due to the clock signal from the wiring SCL, When the line SEL[1] is turned on, the line SEL[1] outputs a high level potential. When a level potential is input, the potential again becomes low due to the clock signal from the wiring SCL. When the potential rises from the normal level to the high level, the wiring SEL[1] outputs the low level. Then, the line SEL[2] outputs a high level potential. When the bell potential is input, the clock signal from the wiring SCL is When the potential rises, the wiring SEL[1] and the wiring SEL[2] are at a low level voltage. The line SEL[3] outputs a low level potential, and the line SEL[4] outputs a high level potential.

[0344] In this way, every time the potential of the clock signal from the wiring SCL rises, The soft register SR sequentially supplies a high level voltage to one of the lines SEL[1] to SEL[m]. A high level potential can be output to the wiring, and a low level potential can be output to the other wirings.

[0345] Latch circuits LTA[1] to LTA[m] and latch circuits LTB[1] to Each of the latch circuits LTB[m] is turned on when a high-level potential is input to the control terminal. When the data is input to the input terminal D, it is enabled and the data is held. The latch circuit LTA[1] and the latch circuit LTA[2] have the function of outputting the data to the output terminal Q. The latch circuit LTA[m] and the latch circuit LTB[1] to the latch circuit LTB[m] are For example, when a low-level potential is input to the control terminal, the device is disabled. The data input to the input terminal D is not held, and the data is not output to the output terminal Q.

[0346] An example of the operation of the circuit LGC will now be described.

[0347] FIG. 17A is a timing chart showing an example of the operation of the circuit LGC. The chart shows the wiring SPL, wiring SCL, wiring SEL[1], wiring SEL[2], wiring SEL [m-1], wiring SEL[m], wiring SL8[1] to wiring SL8[m], and wiring LA The potential change at T is shown, and the wiring DAT, wiring LXS[1], wiring LXS[2], The data input to the wiring LXS[m-1] and wiring LXS[m] is shown. Wiring SPL, wiring SCL, wiring SEL[1], wiring SEL[2], wiring SEL[m] , the wiring SEL[m-1], the wiring SL8[1] to the wiring SL8[m], and the wiring LAT In this case, high level potential is written as "High" and low level potential is written as "Low". is doing.

[0348] The timing chart of FIG. 17A shows the period from time T31 to time T40 and the period around it. At the same time, the circuit LGC supplies the wiring LXS[1] to the wiring LXS[m] with At the same time, the data DT is output. For example, in FIG. It is assumed that this is performed between time T14 and time T15 in the timing chart.

[0349] Furthermore, at a time before time T31, a low level potential is input to the wiring LAT, and A low-level potential is input to each of the lines SL8[1] to SL8[m]. In addition, the shift register SR is configured such that each of the wirings SEL[1] to SEL[m] It is assumed that a low level potential is output to the

[0350] Between time T31 and time T32, a start pulse signal is input to the wiring SPL. A high-level potential is input to the line SCL. A pulse voltage The shift register SR receives the rising edge of the clock signal pulse voltage. By this, a high-level potential, which is the start pulse signal input to the wiring SPL, is obtained. .

[0351] Between time T32 and time T33, data DT[1] is input to the line DAT. In addition, a second pulse voltage is input to the wiring SCL as a clock signal. The shift register SR receives the rising edge of the second pulse voltage of the clock signal. By this, a high-level potential is output to the wiring SEL[1].

[0352] At this time, the latch circuit LTA[1] is enabled, so the signal input to the input terminal D The data DT[1] stored in the register is held and output to the output terminal Q. DT[1] is input to the input terminal D of the latch circuit LTB[1]. Since a low-level potential is input to the control terminal of the latch circuit LTB[1], the latch circuit L TB[1] holds the data DT[1] input to the input terminal D of the latch circuit LTB[1]. The latch circuit LTB[1] outputs the data DT[1] input to its output terminal Q. do not.

[0353] Between time T33 and time T34, data DT[2] is input to the line DAT. Also, a third pulse voltage is input to the wiring SCL as a clock signal. The shift register SR starts when the rising edge of the third pulse voltage of the clock signal is input. By this, a low level potential is output to the wiring SEL[1] and a high level potential is output to the wiring SEL[2]. Output.

[0354] At this time, the latch circuit LTA[1] is disabled, so the latch circuit LTA The data DT[2] input to the input terminal D of the latch circuit [1] is not held. A[1] continues to hold data DT[1] from before time T33, and the output terminal Q Output data DT[1] from

[0355] In addition, the latch circuit LTA[2] is enabled, so the signal input to input terminal D is The data DT[2] is held and output to the output terminal Q. [2] is input to the input terminal D of the latch circuit LTB[2]. Since a low-level potential is input to the control terminal of the circuit LTB[2], the latch circuit LTB [2] holds the data DT[2] input to the input terminal D of the latch circuit LTB[2]. and does not output the data DT[2] input to the output terminal Q of the latch circuit LTB[2]. stomach.

[0356] Between time T34 and time T35, data DT[3] to DT[m -2] are input sequentially, and the shift register SR is used to input the wiring SEL[3] to wiring SEL[4]. A high level potential is sequentially input to SEL[m-2]. This causes the latch LTA[3 ] to latch circuit LTA[m-2], respectively. 2] is held. In addition, each of the latches LTA[3] to LTA[m-2] The data DT[3] to DT[m-2] are output from the output terminal Q.

[0357] Between time T35 and time T36, the data DT[m-1] Also, the mth pulse voltage is input to the wiring SCL as a clock signal. The shift register SR receives the rising edge of the mth pulse voltage of the clock signal. By this, a low level potential is output to the wiring SEL[m-2] and a low level potential is output to the wiring SEL[m-1]. Outputs a high level potential.

[0358] At this time, the latch circuit LTA[m-2] is disabled, so the latch circuit L The data DT[m-1] input to the input terminal D of TA[m-2] is not held. The latch circuit LTA[m-2] continues to hold the data DT[m-2] from before time T35. The output terminal Q outputs data DT[m-2].

[0359] In addition, the latch circuit LTA[m-1] is enabled, so the signal input to the input terminal D The data DT[m-1] stored in the buffer is output to the output terminal Q. The data DT[m-1] is input to the input terminal D of the latch circuit LTB[m-1]. At this time, a low level potential is input to the control terminal of the latch circuit LTB[m-1]. Therefore, the latch circuit LTB[m-1] receives the signal input to the input terminal D of the latch circuit LTB[m-1]. The input data DT[m-1] is not held, and the output terminal of the latch circuit LTB[m-1] The data DT[m-1] input to Q is not output.

[0360] Between time T36 and time T37, data DT[m] is input to the line DAT. Also, the (m+1)th pulse voltage is input to the wiring SCL as a clock signal. The shift register SR is set to the rising edge of the (m+1)th pulse voltage of the clock signal. When this signal is input, a low-level potential is output to the wiring SEL[m-1], and a low-level potential is output to the wiring SEL[m]. Outputs a high level potential.

[0361] At this time, the latch circuit LTA[m-1] is disabled, so the latch circuit L The data DT[m] input to the input terminal D of TA[m-1] is not held. The circuit LTA[m-1] continues to hold the data DT[m-1] from before time T36. Subsequently, data DT[m-1] is output from output terminal Q.

[0362] In addition, the latch circuit LTA[m] is enabled, so the signal input to the input terminal D The data DT[m] is held and output to the output terminal Q. [m] is input to the input terminal D of the latch circuit LTB[m]. Since a low-level potential is input to the control terminal of the circuit LTB[m], the latch circuit LTB [m] holds the data DT[m] input to the input terminal D of the latch circuit LTB[m]. and does not output the data DT[m] input to the output terminal Q of the latch circuit LTB[m]. stomach.

[0363] Between time T38 and time T39, a high level potential is input to the wiring LAT. As a result, the control of each of the latch circuits LTB[1] to LTB[m] Since a high-level potential is input to the terminal, the latch circuits LTB[1] to LTB[ m] are enabled. The switching circuit LTB[m] receives the data DT[1] to DT[m] input to each input terminal D. data DT[m], and outputs data DT[1] to data DT[m] from each output terminal Q. Outputs [m].

[0364] Between time T39 and time T40, wiring SL8[1] to wiring SL8[m] As a result, a high-level potential is input to the switches SW8[1] to SW8[3]. [m] is turned on, and each of the latch circuits LTB[1] to LTB[m] The output terminal Q and the wiring LXS[1] to wiring LXS[m] are in a conductive state. Therefore, the circuit LGC receives the data DT from each of the wirings LXS[1] to LXS[m]. Data [1] to DT[m] can be output simultaneously.

[0365] The circuit LGC performs the operation of the timing chart shown in FIG. 17A. The data DT[1] to DT[m] input sequentially to the LGC are simultaneously parallelized. The signals can be output to wirings LXS[1] to LXS[m].

[0366] In the timing chart of FIG. 17A, the circuit LGC is connected to the wiring LXS[1] to the wiring LXS[2]. Although an example of outputting data DT simultaneously to each of the lines LXS[m] has been shown, the circuit LGC outputs data DT sequentially to each of the wirings LXS[1] to LXS[m]. In the timing chart of FIG. 17B, the circuit LGC is connected to the wirings LXS[1] to LXS[2]. This shows an example of the operation of sequentially outputting data DT to each of XS[m]. 17A. The operation before time T39 in the timing chart of FIG. 17B is The operation example from before time T31 to time T39 in the timing chart was performed. It shall be.

[0367] The timing chart of FIG. 17B shows the wiring SL8[1], the wiring SL8[2], the wiring SL8 [m-1] and the potential change in the wiring SL8[m], and the wiring LXS[1], Data input to wiring LXS[2], wiring LXS[m-1], and wiring LXS[m] The wiring SL8[1], wiring SL8[2], wiring SL8[m-1], In the wiring SL8[m], high-level potential is written as High, and low-level potential is written as The rank is listed as Low.

[0368] Between time T39 and time T40, a high level potential is input to the wiring SL8[1]. This causes the switch SW8[1] to turn on, and the latch circuit LTB[1] ] output terminal Q and wiring LXS[1] are in a conductive state, so wiring LXS[1] is connected The data DT[1] output from the output terminal Q of the latch circuit LTB is transmitted.

[0369] Between time T40 and time T41, a low level potential is input to the wiring SL8[1]. A high level potential is input to the wiring SL8[2]. [1] is turned off, and the switch SW8[2] is turned on. Since there is no conduction between the output terminal Q of the line LXS[1] and the line LXS[1], The data DT[1] output from the output terminal Q of the latch circuit LTB is not transmitted. , the output terminal Q of the latch circuit LTB[2] and the line LXS[2] are in a conductive state. , the data DT[2] output from the output terminal Q of the latch circuit LTB is sent to the wiring LXS[2]. will be sent.

[0370] Between time T41 and time T42, the wirings SL8[3] to SL8[m-2] A high level potential is sequentially input to each of the switches SW8[3] to S W8[m-2] are sequentially turned on. The data DT[3] to DT[m-2] are output to the output terminals Q of the circuit LTB[m-2]. The data DT[m-2] are output sequentially from the wiring LXS[3] to the wiring LXS[m-2], respectively. Be encouraged.

[0371] Between time T42 and time T43, the wiring SL8[m-2] is supplied with a low-level potential. is input, and a high-level potential is input to the wiring SL8[m-1]. The switch SW8[m-2] is turned off and the switch SW8[m-1] is turned on. The output terminal Q of the switch circuit LTB[m-2] is in a non-conductive state with the wiring LXS[m-2]. Therefore, the data D output from the output terminal Q of the latch circuit LTB is input to the wiring LXS[m-2]. T[m-2] is not transmitted. Also, the output terminal Q of the latch circuit LTB[m-1] and the wiring L Since the line LXS[m-1] is in a conductive state, the latch circuit LTB The data DT[m-1] output from the output terminal Q is transmitted.

[0372] Between time T43 and time T44, the wiring SL8[m-1] is supplied with a low-level potential. is input, and a high-level potential is input to the wiring SL8[m]. W8[m-1] is turned off and switch SW8[m] is turned on. Latch circuit Since there is no conduction between the output terminal Q of LTB[m-1] and the wiring LXS[m-1], The data DT[m- 1] is not transmitted. Also, the output terminal Q of the latch circuit LTB[m] and the wiring LXS[m] Since the connection state is established between the two, the output terminal Q of the latch circuit LTB is connected to the wiring LXS[m]. The resulting data DT[m] is then transmitted.

[0373] The circuit LGC operates until time T39 in the timing chart shown in FIG. 17A. After that, the operation of the timing chart shown in FIG. 17B is performed, and the circuit LGC The data DT[1] to DT[m] sequentially input to the wiring LXS[1] to the wiring LXS[m]. The signals can be output sequentially to the line LXS[m].

[0374] In the operation example of the timing chart shown in FIG. 17B, the wiring SL8[1] to the wiring SL8[2] SL8[m] are sequentially turned on, and data DT[1] to data DT[m] , and are sequentially output to the wirings LXS[1] to LXS[m]. ] to wiring SL8[m], and select the switch to be turned on from wiring LXS[1] to The operation may be to output the data DT to a wiring selected from the wiring LXS[m].

[0375] According to the above-described operation example, for example, from time T14 to time T Between 15 and 2015, the operation circuit MAC1, operation circuit MAC2, or operation circuit MAC3 A potential corresponding to the data DT is supplied to any one of the wirings XCL[1] to XCL[m]. It is possible.

[0376] 6 included in the semiconductor device of one embodiment of the present invention, the circuit LGC shown in FIG. Instead of the circuit LGC, the circuit configuration of the circuit LGC in FIG. 16A is changed depending on the situation. For example, the circuit LGC in FIG. 16A may be configured by using the switches SW8[1] to SW8[2] shown in FIG. Each of the switches SW8[m] and each of the wirings LXS[1] to LXS[m] A buffer circuit may be provided between the LGC and the SLCM. Switches SW8[1] to SW8[m] and wiring LXS[1] to wiring LXS[m]. Buffer circuits BF[1] to BF[m] are provided between the respective LXS[m] and the As shown in FIG. 16B, the circuit LGC is provided with a buffer circuit BF[1]. By providing the buffer circuit BF[m], the wiring LXS[1] The electrical signal (potential) output to the wiring LXS[m] can be stabilized.

[0377] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0378] (Fourth embodiment) In this embodiment, a hierarchical neural network that can perform an operation using a semiconductor device according to one embodiment of the present invention is described. This section explains the configuration of the network.

[0379] A hierarchical neural network, for example, has one input layer and one or more intermediate layers. It consists of a total of three or more layers, including a hidden layer and an output layer. The hierarchical neural network 100 shown in FIG. 8A is an example of such a network. The network 100 includes layers 1 through R (where R can be an integer greater than or equal to 4). In particular, the first layer corresponds to the input layer, and the Rth layer corresponds to the output layer. The other layers correspond to the hidden layers. The illustration shows a selection of layers (where k is an integer between 3 and R-1).

[0380] Each layer of the neural network 100 has one or more neurons. In the first layer, the neuron N1 (1) Neuron N p (1) (where p is 1 or more. ) and the (k-1)th layer has neurons N1 (k-1) or neurons N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer equal to or greater than 1), and is neuron N1 (R) Neuron N q (R) (Here, q is an integer greater than or equal to 1. )

[0381] In addition, in Figure 18A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neurons N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) is shown in the figure.

[0382] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) We are focusing on the following.

[0383] Figure 18B shows the k-th layer neuron N j (k) and neuron N j (k) The signal input to No. and Neuron N j (k) 10 shows the signal output from the

[0384] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron N j ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0385] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the next layer neuron. Layer N neurons i (k-1) and the k-th layer neuron N j (k) The synaptic weights between The coefficient is w i (k-1) j (k) Then, the k-th layer neuron N j (k) is entered into The signal can be expressed by equation (4.1).

[0386]

number

[0387] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1 ) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) · z m (k-1)is input. At this time, the k-th layer neuron N j (k) The signal input to The sum of the numbers j (k) is expressed as equation (4.2).

[0388]

number

[0389] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and neurons signal z1 (k-1) ~z m (k-1) The result of the sum of products of and is biased. When the bias is b, equation (4.2) can be rewritten as .

[0390]

number

[0391] Neuron N j (k) u j (k) Depending on j (k) Generates In. Neuron N j (k) Output signal z from j (k) is defined as follows:

[0392]

number

[0393] The function f(u j (k)) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0394] By the way, the signal output by the neuron in each layer, the weight coefficient w, or the bias b is The value may be an analog value or a digital value. For example, the digital value may be a binary value. It may be a ternary value, or a value with an even larger number of bits. For analog values, the activation function can be, for example, a linear ramp function or a sigmoid function. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function with a value of 1 or less can be used. The signal output by the neurons in each layer is It may be three or more values, in which case the activation function has three or more values, for example, outputs -1, 0, or A step function with a value of 0, 1, or 2 can be used. For example, an activation function that outputs five values ​​can be set to -2, -1, 0, 1, or A step function with a weighting factor of 2 may be used. Use a digital value for at least one of the number w or bias b. This allows for a reduction in circuit size, power consumption, or speed of operation. Also, the signals output by the neurons in each layer, the weight coefficients w, and Or, for at least one bias b, by using an analog value, The accuracy of the calculation can be improved.

[0395] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, equation (4.1), equation (4.2) (or equation (4.3)), equation (4.4) The output signal is generated using the sigma-based algorithm, and the output signal is output to the next layer. The signal output from the input layer is converted into the result calculated by the neural network 100. Equivalent.

[0396] The neural network 100 has a first layer (input layer), a hidden layer, and a final layer (output layer). The calculations performed by the calculation circuits MAC1 to MAC2 described in the first and second embodiments are This can be done by using the computation circuit MAC3.

[0397] In particular, as shown in equation (4.3), when you want to add bias to the result of the sum of products, In this case, the arithmetic circuit MAC2 described in the second embodiment can be used. The bias b of Eq. (2.1) and Eq. (2.2) is BIAS Equivalent to [1].

[0398] The circuits of the arithmetic circuits MAC1 to MAC3 described in the first and second embodiments The circuit XLD or the circuit SCA is applied as an input layer described in this embodiment, for example. Here, the second layer contains the neuron N1 (2) Neuron N r ( 2) (r is an integer greater than or equal to 1.) is included in the first layer. Consider the case where a signal is sent from a neuron to a neuron in the second layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 is The recells AM are arranged in a matrix of p rows and r columns.

[0399] Neuron N in the first layer (input layer) s[1] (1) (s[1] is an integer between 1 and p. ) is the received signal z s[1] (1) is output to all neurons in the second layer (hidden layer) Signal z s[1] (1) The potential output from the circuit XLD or the circuit SCA (second data), the signal z output from the first layer (input layer) s[1] (1) , wiring The memory cell AM[s[1] included in the memory cell array CA is connected via XL[s[1]]. , 1] to memory cell AM[s[1], r] and memory cell AMr[s[1]] It is possible.

[0400] At this time, the s[2]th column of the memory cell array CA (s[2] is an integer between 1 and r) ) to each memory cell AM, a weighting coefficient w s[1] (1) s[2] (2) is the first data By storing the data as a vector, the second layer (hidden layer) neurons N s[2] (2) In signal z s[1] (1) and weighting factor w s[1] (1) s[2] (2) By calculating the sum of products with Specifically, the current I flowing through the circuit IVTC S [s[2]] to signal z s[1] (1) and weighting factor w s[1](1) s[2] (2) We can calculate the sum of products with In addition, the activation function value is calculated from the result of the product sum by the ACTV circuit. Then, the value of the activation function is assigned to the neuron N s[2] (2) The output signal z s[2] (2 ) and can be output from the wiring NIL[s[2]].

[0401] Furthermore, the arithmetic circuits MAC1 to MAC2 described in the first and second embodiments 3 can be applied as the hidden layer mentioned above. Here, the (k-1)th layer When a signal is sent from a neuron contained in the k-th layer to a neuron contained in the k-th layer, In this case, the memory cell arrays of the arithmetic circuits MAC1 to MAC3 are The CA has a configuration in which memory cells AM are arranged in a matrix of m rows and n columns.

[0402] Neuron N in the (k-1)th layer i (k-1) is the signal z i (k-1) The k-th layer of the new Ron N1 (k) Neuron N n (k) The signal z is output. i (k-1) , times By using the potential (second data) output from the XLD, the potential output from the (k-1)th layer Signal z i (k-1) are transmitted to the memory cells included in the memory cell array CA via the wiring XL[i]. memory cells AM[i,1] to AM[i,n] and memory cell AMr[i] You can enter it.

[0403] At this time, a weighting coefficient w i (k- 1) j (k) is stored as the first data, and the kth layer neuron N j (k) In the signal z i (k-1) and weighting factor w i (k-1) j (k) By calculating the sum of products with Specifically, the current I flowing through the circuit IVTC S [j] to signal z i (k -1) and weighting factor w i (k-1) j (k) In addition, the circuit By using ACTV to calculate the activation function value from the result of the product sum, the activation function The value of is sent to the k-th layer neuron N j (k) The output signal z j (k) Then, wiring NIL[j] It can be output from

[0404] Furthermore, the arithmetic circuits MAC1 to MAC2 described in the first and second embodiments 3 can be applied as the output layer described above. Here, the (R-1)th layer is neuron N1 (R-1) Neuron N v (R-1) (v is an integer greater than or equal to 1. ) is included in the neurons in the (R-1)th layer and the neurons in the Rth layer. In this case, the arithmetic circuit MAC The memory cell array CA of the arithmetic circuit MAC3 has memory cells AM arranged in v rows and q columns. The elements are arranged in a matrix.

[0405] Neuron N in the (R-1) layer s[R-1] (R-1) (s[R-1] is between 1 and v ) is an integer of the signal z s[R-1] (R-1) neuron N1 in layer R (R) No To Neuron N q (R) The signal z is output. s[R-1] (R-1) Circuit XL By using the potential (second data) output from D, the signal output from the (R-1)th layer z s[R-1] (R-1) via the wiring XL[s[R-1]] to the memory cell array C A includes memory cells AM[s[R-1],1] to AM[s[R-1], n] and memory cell AMr[s[R-1]].

[0406] At this time, the s[R]th column of the memory cell array CA (s[R] is an integer between 1 and q) ) to each memory cell AM, a weighting coefficient w s[R-1] (R-1) s[R] (R) is the first By storing the data, the Rth layer neuron N s[R] (R) In No.z s[R-1] (R-1) and weighting factor w s[R-1] (R-1) s[R] (R) Product of Specifically, the current I flowing through the circuit IVTC can be calculated as S [s[R ]] to signal z s[R-1](R-1) and weighting factor w s[R-1] (R-1) s[R] ( R) In addition, the circuit ACTV can calculate the sum of products from the result of the sum of products. By calculating the value of the activation function, the value of the activation function is assigned to the neuron N in the Rth layer. s[R] (R) The output signal z s[R] (R) As a result, it can be output from the wiring NIL[s[R]] can.

[0407] In the arithmetic circuit described in this embodiment, the number of rows of memory cells AM is equal to the number of rows of the previous layer of memory cells AM. In other words, the number of rows of memory cells AM is the number of inputs to one neuron in the next layer. The number of output signals of the neurons in the previous layer corresponds to the number of the calculation circuits described in this embodiment. In the path, the number of columns of memory cells AM is the number of neurons in the next layer. The number of columns in AM corresponds to the number of output signals from the neurons in the next layer. The number of rows of the memory cell array of the arithmetic circuit and The number of columns and the number of memory cells are determined depending on the neural network you want to configure. The number of rows and columns should be determined and then the design can be carried out.

[0408] For example, the arithmetic circuit MAC1 described in the first embodiment is applied as the hidden layer. In this case, the weighting factor w i (k-1) j (k) is used as the first data, and the potential according to the first data is The memory cells AM in the same column are stored sequentially, and the (k-1)th layer neuron N i (k-1) Output signal z from i(k-1) is used as the second data, and a potential according to the second data is input to the circuit XL D, or by supplying from the circuit SCA to the wiring XL of each row, Amount of current flowing I S From signal z i (k-1) and weighting factor w i (k-1) j (k) and the sum of products The value is calculated, and the activation function value corresponding to that value can be calculated by the circuit ACTV. In other words, the activation function value is used as a signal to send the k-th layer neuron N j (k) The output signal z j (k) In addition, the circuit ACTV outputs a potential according to the value of the activation function. The k-th layer contains neurons N j (k) The output signal z j (k) Another calculation circuit MA By configuring it to input to C1, the other arithmetic circuit MAC1 can Neuron N is the output from the neuron s[k+1] (k+1) (s[k+1] is 1 or more and is an integer equal to or less than the total number of neurons in the k+1th layer.) s[ k+1] (k+1) can be calculated.

[0409] Specifically, the above-mentioned calculation is performed by using the calculation circuit MAC4 shown in FIG. The arithmetic circuit MAC4 in FIG. 19 can be used in the same manner as the arithmetic circuit MAC1 in FIG. The circuit XLD and the circuit MC1 in the arithmetic circuit MAC1-1 of the same configuration are The circuit SCA and the circuit SWC are not provided in the arithmetic circuit MAC1-2. The memory cell array CA of the arithmetic circuit MAC1-1 includes m×n memory cells AM and m The memory cells AMr and AMr are arranged in a matrix, and the memory cell array of the arithmetic circuit MAC1-2 CA has n × t (t is an integer greater than or equal to 1, and is the total number of neurons in the (k+1)th layer) The number of memory cells AM and n number of memory cells AMr are arranged in a matrix. In addition, each of the wirings NIL[1] to NIL[n] of the arithmetic circuit MAC1-1 are electrically connected to the wiring XL[1] to wiring XL[n] of the arithmetic circuit MAC1-2. do.

[0410] For example, in the arithmetic circuit MAC1-1 in FIG. 19, the neurons in the (k-1)th layer and the neurons in the kth layer The weight coefficient between the neurons is used as first data, and the memory cells AM of the memory cell array CA are [1,1] to memory cell AM[m,n] are stored, and the (k-1) layer neuron N s[ k-1] (k-1) Output signal z from s[k-1] (k-1) as the second data, By passing a potential according to the data from the circuit XLD or circuit SCA to the wiring XL of each row, , wiring BL[1] to wiring BL[n], wiring NIL[1] to wiring NIL Through each of [n], the k-th layer neuron N1 (k) Neuron N n (k) of Output signal z1 (k) ~z n (k) The output signal z1 (k) ~z n (k) The values ​​of the respective lines are connected from the circuit ACTV to the wiring NIL[1] to the wiring NIL[ n].

[0411] Here, in the arithmetic circuit MAC1-2 in FIG. 19, the neurons in the kth layer and the neurons in the (k+1)th layer are The weight coefficient between the neurons is used as first data, and the memory cells AM of the memory cell array CA are The potentials held in the memory cells AM[n,t] to AM[n,t] and supplied to the wirings XL of each row, That is, the kth layer neuron N1 (k) Neuron N n (k) Output signal z1 (k) ~z n (k) By using the second data, each of the wirings BL[1] to BL[t] Then, through each of the wirings NIL[1] to NIL[t], the (k+1)th layer Neuron N1 (k+1) Neuron N t (k+1) Each output signal z1 (k +1) ~z t (k+1) can be output.

[0412] As described above, the arithmetic circuits MAC1 to MAC3 are hierarchical neural networks. The number of rows and columns of the memory cell array CA can be determined according to the scale of the network. Also, by using at least one of the arithmetic circuits MAC1 to MAC3, the following is realized as shown in FIG. By connecting them as shown, the calculations according to the number of layers of the hierarchical neural network can be performed. It can be done.

[0413] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0414] (Embodiment 5) In this embodiment, the configuration example of the semiconductor device described in the above embodiment and the above embodiment will be described. A structural example of a transistor that can be applied to the semiconductor device described in the embodiment will be described.

[0415] <Configuration example of semiconductor device> FIG. 20 shows an example of the arithmetic circuits MAC1 to M explained in the above embodiment. 4 is a cross-sectional view of one of the circuits SNC and AC4, in which a photoelectric conversion element is provided as a photodiode. Specifically, the semiconductor device shown in FIG. 300, a transistor 500, a capacitor 600, and a photoelectric conversion element 700. FIG. 22A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 22B is a cross-sectional view of the transistor 500. 22C is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 22D is a cross-sectional view of the transistor 300 in the channel width direction. FIG. 1 is a cross-sectional view in the width direction of the panel.

[0416] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 500 has a small off-state current and a low field effect even at high temperatures. The transistor 500 has a characteristic that the resultant mobility does not change. The transistors included in the arithmetic circuits MAC1 to MAC4 described in the embodiment By applying this to a capacitor, a semiconductor device can be realized in which the operating capability does not decrease even at high temperatures. Utilizing the characteristics of a small off-state current, the transistor 500 is applied to the transistor Tr11. By doing so, the potential written in the memory cells AM, AMr, etc. can be maintained for a long time. In addition, the transistor 500 can be replaced with the transistor Tr41 and the transistor By applying this to Tr42, etc., the potential written to the node NS of the circuit RPC can be maintained for a long time. Also, the transistor 500 can be held for a period of time. By applying this to a transistor, the potential written to the first terminal of the capacitor C6 is maintained for a long time. Also, the transistor 500 can be replaced with a transistor included in the switch SW2. By applying this to the capacitor, the potential written to the first terminal of the capacitor C7 can be maintained for a long time. This can be done.

[0417] The transistor 500 is provided, for example, above the transistor 300, and the capacitance element 60 0 is provided above the transistor 300 and the transistor 500, for example. The capacitance element 600 is the same as the arithmetic circuits MAC1 to MA It can be a capacitance included in C4, etc. Depending on the circuit configuration, The capacitor element 600 shown is not necessarily provided.

[0418] The photoelectric conversion element 700 is provided above the capacitance element 600, for example.

[0419] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the arithmetic circuits MAC1 to MAC4 described in the above embodiments may include The present invention can be applied to transistors, etc. Specifically, for example, the transistor 300 is , the operational amplifiers OP[1] to OP[1] included in the circuit IVTC of FIG. 5A or FIG. 5B. [n], etc. Also, for example, a transistor The transistor 300 includes a transistor Tr31, a transistor Tr32[1], and a transistor Tr 32[n], transistor Tr33, transistor Tr34, transistor Tr35, These can be transistors Tr36[1] to Tr36[n]. In FIG. 20, the gate of the transistor 300 is connected to the transistor 300 via a pair of electrodes of the capacitor 600. 1 shows a configuration in which the transistor 500 is electrically connected to either the source or the drain. However, depending on the configuration of the arithmetic circuits MAC1 to MAC4, the transistor 30 One of the source and drain of the capacitor 600 is connected to the transistor 500 may be electrically connected to either the source or the drain of One of the source and drain of the transistor 300 is connected to the capacitor 600 via a pair of electrodes. 500, and may be electrically connected to the gate of the transistor 500. The terminals of the transistor 300 are the same as the terminals of the transistor 500 and the terminals of the capacitor 600. They may not be electrically connected to each other.

[0420] The substrate 311 is a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). It is preferable that

[0421] The transistor 300 is formed by forming a semiconductor region 313 on the upper surface thereof and a channel region thereof as shown in FIG. 22C. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, and This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0422] The transistor 300 may be either a p-channel type or an n-channel type. .

[0423] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Nitride), GaAlAs (Gallium Aluminum Arsenide), GaN (Gallium Nitride), etc. The effective mass can be increased by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, a structure using silicon with controlled conductivity may be used. This allows the transistor 300 to be a HEMT (High Electron Mobilit y Transistor).

[0424] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0425] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0426] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0427] The transistor 300 shown in FIG. 20 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the structure, driving method, etc. In the case of a unipolar circuit using only S transistors, as shown in FIG. The structure of the transistor 500 may be the same as that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail later.

[0428] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0429] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0430] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0431] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0432] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property that prevents diffusion of hydrogen and impurities is used in the region where the capacitor 500 is provided. It is preferable that

[0433] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0434] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0435] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. It can be reduced.

[0436] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductors 328 and 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0437] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring layer 11 from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0438] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0439] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0440] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0441] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0442] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0443] Moreover, a wiring layer (not shown) may be provided on the insulator 364 and the conductor 366.

[0444] The wiring layer including the conductor 356 and the wiring layer including the conductor 366 have been described above. However, the semiconductor device according to this embodiment is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be one or less. Alternatively, a wiring layer similar to the wiring layer including the conductor 366 may be provided. Two or more layers may be used.

[0445] On the insulator 364, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 uses a material that has a barrier property against oxygen, hydrogen, etc. It's nice.

[0446] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. The area where the transistor 300 is provided is converted into the area where the transistor 500 is provided by introducing hydrogen, impurities, etc. It is preferable to use a film that has a barrier property that prevents the diffusion of the insulator 3. The same materials as those in 24 can be used.

[0447] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0448] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0449] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0450] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. As the film 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0451] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0452] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0453] Above the insulator 516 is the transistor 500 .

[0454] As shown in FIGS. 22A and 22B, the transistor 500 includes an insulator 514 and an insulator 516. The conductor 503 is disposed so as to be embedded in the insulator 516, and the insulator 516 and the conductor 50 3, an insulator 520 disposed on the insulator 520, and an insulator 522 disposed on the insulator 520. An insulator 524 is disposed on the insulator 522, and an oxide 53 is disposed on the insulator 524. 530a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are spaced apart, and conductor 542a and conductor 54 2b, and an opening is formed between the conductors 542a and 542b. The edge 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the shape of the oxide 530c an insulator 550 disposed on the forming surface; and a conductor 560 disposed on the forming surface of the insulator 550; In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor It is written as body 542.

[0455] As shown in FIGS. 22A and 22B, the oxide 530a, the oxide 530b, and the conductive The insulator 544 is disposed between the conductor 542a and the insulator 580, and the conductor 542b. As shown in FIGS. 22A and 22B, the conductor 560 is preferably made of an insulator 560. 50, and a conductor 560a provided inside the conductor 560a. It is preferable to have a conductor 560b provided thereon. As shown, an insulator 574 is disposed over an insulator 580, a conductor 560, and an insulator 550. It is preferable that the

[0456] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0457] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, one embodiment of the present invention is not limited thereto. a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c The transistor 500 may have a layer structure or a stacked structure of four or more layers. Although the conductor 560 has a two-layer structure in the example, one embodiment of the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminate of three or more layers. 20, 22A, and 22B. 0 is an example, and is not limited to this structure. A register can be used.

[0458] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0459] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the gap formed between the conductor 560 and the conductors 542a and 542b is Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0460] Conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. The threshold voltage of the transistor 500 is controlled by changing them independently without linking them together. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 It is possible to increase the threshold voltage of 00 to be higher than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the conductor 560 This can reduce the drain current when the potential applied to is 0V.

[0461] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0462] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. Although a layered structure is shown, one embodiment of the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.

[0463] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the above-mentioned function (i.e., that is difficult for oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0464] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0465] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. In addition, if the conductivity of the wiring can be maintained high, the conductor 503a is not necessarily provided. Although the conductor 503b is illustrated as a single layer, it may have a multilayer structure. It may also be a laminate of titanium or titanium nitride and the above conductive material.

[0466] The insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0467] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. Reliability can be improved.

[0468] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0469] In addition, the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other and subjected to heat treatment. One or more of microwave treatment and RF treatment may be performed. By performing this, water or hydrogen in the oxide 530 can be removed. At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O + The reaction "H" occurs, and some of the hydrogen generated at this time is It combines with oxygen to form H2O, which is then removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may diffuse into the conductor 542a and the conductor 542b. The electrons may be trapped or captured (also called gettered).

[0470] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The microwave treatment may be performed at a pressure of 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0471] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably carried out at a temperature of, for example, 100° C. or higher and 450° C. or lower. The heat treatment is preferably performed at a temperature of 350° C. or higher and 400° C. or lower. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, and oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or nitrogen gas. After heat treatment in an active gas atmosphere, oxidizing gas was added at 10p to compensate for the oxygen that was released. The treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of an oxidizing gas. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0472] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. In other words, "V O +O→null” reaction. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in the substance 530 recombines with the oxygen vacancy to form V. O inhibits the formation of H It is possible.

[0473] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0474] The insulator 522 has a function of suppressing the diffusion of oxygen, impurities, and the like, and thus the oxide 53 The oxygen contained in the conductor 50 is preferably not diffused to the insulator 520 side. 3 can be prevented from reacting with oxygen contained in the insulator 524, oxide 530, etc. Cut.

[0475] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as (Sr, Sr)TiO3 (BST) are used as single layers or laminated layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film By using a high-k material as the insulator, the transistor behavior can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0476] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Use an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum or hafnium as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use a material such as aluminum aluminate. When formed, the insulator 522 prevents oxygen from being released from the oxide 530, It functions as a layer that prevents impurities such as hydrogen from entering the oxide 530 from the surrounding area.

[0477] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0478] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining an insulator with silicon oxide or silicon oxynitride, it is possible to obtain a thermally stable Furthermore, it is possible to obtain the insulator 520 having a laminated structure with a high relative dielectric constant.

[0479] 22A and 22B, the transistor 500 has a three-layer stack structure. As the second gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. Good too.

[0480] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor It is preferable to use a functional metal oxide. For example, the oxide 530 is In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryl Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, la tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. The In-M-Zn oxide that can be applied as a C-Axis Alignment Oxide (CAAC-OS) is ned Crystalline Oxide Semiconductor), CAC -OS(Cloud-Aligned Composite Oxide Semico The oxide 530 is preferably an In-Ga oxide. , In-Zn oxide, In oxide, etc. may also be used.

[0481] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. When the carrier concentration of the metal oxide is reduced, the impurity concentration in the metal oxide is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, Examples include rubber and silicon.

[0482] In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. In this case, oxygen vacancies may be formed in the metal oxide. When an oxygen atom is introduced, the oxygen vacancy and hydrogen bond to form V O May form H. V O H is for Donna It functions as a carrier and electrons are generated. It may combine with oxygen to produce electrons, which are carriers. Transistors using metal oxides containing a large amount of silicon tend to be normally on. In addition, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one aspect of the invention, V in oxide 530 O Reduce H as much as possible and use high purity intrinsic or It is preferable that V is substantially intrinsic with high purity. O Metal with sufficiently reduced H To obtain the oxide, impurities such as water and hydrogen must be removed from the metal oxide (dehydration, This is sometimes referred to as oxidation treatment.) and oxygen deficiency is compensated for by supplying oxygen to the metal oxide. It is important to note that this is sometimes referred to as oxygenation treatment. O Impurities such as H are not enough By using a metal oxide that has been reduced to a low level in the channel formation region of a transistor, stable current can be obtained. It can be given a special characteristic.

[0483] The defect where hydrogen has entered the oxygen vacancy can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, metal As a parameter of the oxide, instead of donor concentration, we use the capacitance assuming a state where no electric field is applied. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "energy concentration."

[0484] Therefore, when a metal oxide is used for the oxide 530, the hydrogen in the metal oxide should be as low as possible. Specifically, in the case of metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than 100%. Impurities such as hydrogen are sufficiently reduced. By using this metal oxide in the channel formation region of a transistor, stable electrical characteristics can be achieved. can be granted.

[0485] In addition, when a metal oxide is used for the oxide 530, the metal oxide has a band gap of It is a semiconductor that is intrinsic (also called type I) or substantially intrinsic, and has a channel The carrier concentration of the metal oxide in the formation region is 1×10 18 cm -3 It is preferable that it is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 Less than More preferably, 1×10 13 cm -3 More preferably, it is less than 1 x10 12 cm -3 It is more preferable that the metal oxide in the channel forming region is less than 1000 nm. The lower limit of the carrier concentration of the oxide is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0486] When a metal oxide is used for the oxide 530, the conductors 542a and 542b When the oxide 530 comes into contact with the conductor 542a, the oxygen in the oxide 530 is transferred to the conductor 542a and the conductor 542b. 2b, and the conductors 542a and 542b may be oxidized. The oxidization of the conductors 542a and 542b reduces the conductivity of the conductors 542a and 542b. It is highly likely that the oxygen in the oxide 530 will decrease. The conductors 542a and 542b absorb oxygen in the oxide 530 and diffuse into the oxide 530. This can be rephrased as "to do."

[0487] Furthermore, oxygen in the oxide 530 diffuses into the conductors 542a and 542b, Between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b A different layer may be formed between the conductor 542a and the conductor 542b. Since the conductor 54 also contains a large amount of oxygen, it is presumed that the different layer has insulating properties. The three-layer structure of the conductor 542b, the hetero layer, and the oxide 530b is a metal-insulator structure. -It can be considered as a three-layer structure consisting of semiconductors, and is MIS (Metal-Insulator Diodes with a MIS structure are called MIS-Semiconductor structures. This is sometimes called a bonded structure.

[0488] The different layer is formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. For example, the different layers may be a conductor 542a and a conductor 542b and an oxide 542b. It may be formed between 30c.

[0489] The metal oxide that functions as the channel forming region in the oxide 530 has a band gap It is preferable to use one having a value of 2 eV or more, preferably 2.5 eV or more. The use of metal oxides with wide band gaps reduces the off-state current of transistors. It is possible.

[0490] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from structures formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0491] The oxide 530 has a laminated structure made up of multiple oxide layers with different atomic ratios of metal atoms. Specifically, the metal oxide used for the oxide 530a has the following structure: The atomic ratio of element M in the constituent elements is It is preferable that the atomic ratio of the element M in the oxide 530a is larger than that of the element M in the oxide 530a. In the metal oxide, the atomic ratio of element M to In is In the oxide 5, the atomic ratio of element M to In is preferably larger than that of element M. In the metal oxide used in 30b, the atomic ratio of In to element M is It is preferable that the atomic ratio of In to element M in the metal oxide used in In addition, the oxide 530c is a metal that can be used for the oxide 530a or the oxide 530b. Metal oxides can be used.

[0492] Specifically, the oxide 530a has an atomic ratio of In, Ga, and Zn of In:Ga:Z. Metal oxides with n=1:3:4 or 1:1:0.5 may be used. 0b, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=4:2:3, or 1 In addition, a metal oxide of In, Ga, and Zn may be used as the oxide 530c. The atomic ratio of In:Ga:Zn is 1:3:4, and the atomic ratio of Ga and Zn is Ga:Zn Metal oxides with a ratio of Ga:Zn=2:1 or Ga:Zn=2:5 may be used. As a specific example of the case where c is a laminated structure, the atomic ratio of In, Ga, and Zn is In:Ga Zn=4:2:3 and In:Ga:Zn=1:3:4, and Ga and Zn The atomic ratio of Ga:Zn is 2:1, and the atomic ratio of In, Ga, and Zn is In:Ga:Zn= The atomic ratio of Ga and Zn is 4:2:3, and the atomic ratio of In and Ga is 2:5. The atomic ratio of In to Zn is 4:2:3. and a layered structure with an atomic ratio of Ga to Zn of In:Ga:Zn=4:2:3. do.

[0493] In addition, for example, the ratio of In atoms to the element M in the metal oxide used for the oxide 530a The atomic ratio of In to element M in the metal oxide used for oxide 530b is When the atomic ratio of In, Ga, and Zn in the oxide 530b is In:Ga:Zn = 5:1:6 or nearby, In:Ga:Zn = 5:1:3 or nearby, In:G In-Ga-Zn oxide with a composition of a:Zn=10:1:3 or similar is used. It is possible.

[0494] In addition to the above, the oxide 530b may have a composition of, for example, In:Zn=2: 1 composition, In:Zn=5:1 composition, In:Zn=10:1 composition, any of these Metal oxides having compositions close to one another can be used.

[0495] These oxides 530a, 530b, and 530c are formed by the above atomic ratio. For example, oxide 530a and oxide 530c are preferably mixed together. The metal oxides and oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to the composition The compound 530b has a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition in the vicinity thereof. It is preferable that the metal oxide has the following composition. The atomic ratio in the substance or the sputtering target. By increasing the In ratio in the composition of 0b, the on-current or field effect of the transistor can be improved. This is preferable because it can increase the fruit mobility and the like.

[0496] The energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of oxide b. The electron affinity of oxide 530a and oxide 530c is smaller than that of oxide 530b. It is preferable that:

[0497] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower conduction band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 The interface between oxide 530a and oxide 530b, and the interface between oxide 530b and oxide 530c are It is preferable to lower the defect level density of the resulting mixed layer.

[0498] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0499] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0500] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use an alloy of tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride have low resistance to hydrogen or oxygen. It is preferable because it has barrier properties.

[0501] 22A and 22B, the conductor 542a and the conductor 542b are formed in a single layer structure. However, it may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten It is also possible to laminate a titanium film and an aluminum film. Two-layer structure with aluminum film laminated on copper-magnesium-aluminum film Two-layer structure with copper film laminated on alloy film, two-layer structure with copper film laminated on titanium film, tungsten Alternatively, a two-layer structure may be used in which a copper film is laminated on an aluminum film.

[0502] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A three-layer structure in which a titanium film or a copper film is laminated and a titanium film or a titanium nitride film is further formed on top of that. Molybdenum film or molybdenum nitride film and a An aluminum film or a copper film is laminated on top of it, and a molybdenum film or a molybdenum nitride film is further laminated on top of it. There are three-layer structures that form a transparent film. Transparent conductive materials may also be used.

[0503] As shown in FIG. 22A, the oxide 530 is formed of the conductor 542a (conductor 542b). At the interface and its vicinity, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a functions as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between 3a and region 543b.

[0504] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are In such a case, a metal compound layer containing the component may be formed in the region 543a (region The carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. become.

[0505] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the oxide 542a and the conductor 542b. 30 and the side surface of the insulator 524, and is provided so as to be in contact with the insulator 522. Good too.

[0506] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Smoke, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc. may be used. Alternatively, silicon nitride oxide or silicon nitride may be used as the insulator 544. You can be there.

[0507] In particular, the insulator 544 may be an oxide of aluminum or hafnium, or both. Insulators including aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use an oxide containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. This is preferable because it is difficult to crystallize during the treatment. If b is a material that is resistant to oxidation or does not significantly decrease in conductivity even when it absorbs oxygen, it is an insulating material. The insulator 544 is not an essential component and may be appropriately designed depending on the desired transistor characteristics. stomach.

[0508] By including the insulator 544, impurities such as water and hydrogen contained in the insulator 580 are converted into acids. The oxide 530c is prevented from diffusing into the oxide 530b through the insulator 550. In addition, the excess oxygen contained in the insulator 580 can prevent the conductor 560 from being oxidized. It is possible.

[0509] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is disposed in contact with the inside (top and side surfaces) of the insulating member 550. Similar to the insulator 524, an insulator containing excess oxygen and releasing oxygen upon heating is used. It is preferable to form it using a

[0510] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0511] An insulator that releases oxygen when heated is used as the insulator 550, and is placed on the top surface of the oxide 530c. By providing the oxide 530b in contact with the insulator 550, the oxide 530c passes through the oxide 530b. In addition, oxygen can be effectively supplied to the channel forming region of the insulator 524. In addition, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0512] In addition, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, A metal oxide may be provided between the insulating material 550 and the conductor 560. It is preferable to suppress the diffusion of oxygen from the body 550 to the conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, it is possible to suppress the decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. Any material that can be used for the insulator 544 may be used.

[0513] Note that the insulator 550 may have a stacked structure similar to the second gate insulating film. As transistors become smaller and more highly integrated, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film is made of high-k material. By using a laminated structure of a thermally stable material and a thin film of a thin film, It is possible to reduce the gate potential during transistor operation. It may have a laminated structure.

[0514] The conductor 560 functioning as the first gate electrode has a two-layer structure in FIGS. 22A and 22B. Although the structure is shown as a single layer structure, it may also be a laminated structure of three or more layers.

[0515] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the conductor 56. Oa has the function of suppressing oxygen diffusion, so the oxygen contained in the insulator 550 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium, ruthenium oxide, or the like as the conductor 560a. An oxide semiconductor that can be used for the oxide 530 can be used. In that case, the conductor 560 By forming the conductive layer 560b by sputtering, the electrical resistance of the conductive layer 560a is reduced, and the conductive layer 560b is This is called an OC (Oxide Conductor) electrode. It is possible.

[0516] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. A conductive material containing rubber as a main component can be used. For example, it may be a laminated structure of titanium or titanium nitride and the above conductive material. stomach.

[0517] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. Preferably, the insulator 580 has an excess oxygen region. For example, the insulator 58 0, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material contains silicon, silicon oxide having pores, or resin. Silicon nitride and silicon oxynitride are preferred because they are thermally stable. However, silicon oxide with vacancies can easily form excess oxygen regions in later processes. This is preferable because it can

[0518] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. The oxide 530 can be efficiently supplied through the insulator 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0519] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is inserted through the opening in the insulator 580 and the conductor 542a and the conductor 542b. It is formed so as to be embedded in the region sandwiched between 542b.

[0520] In miniaturizing semiconductor devices, it is required to shorten the gate length. It is necessary to prevent the conductivity of the conductor 60 from decreasing. In this embodiment, the conductor 560 may have a shape with a high aspect ratio. The conductor 560 is provided so as to be embedded in the opening of the insulator 580. Even a shape with a high ratio can be formed without causing the conductor 560 to collapse during the process. Cut.

[0521] The insulator 574 is connected to the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. The insulator 574 is preferably provided in contact with the , insulator 550, and insulator 580 can be provided with excess oxygen regions. Oxygen can be supplied into the oxide 530 from the excess oxygen region.

[0522] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from the group consisting of ammonium, cadmium, and ammonium can be used. .

[0523] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier to impurities such as hydrogen. It can also function as a membrane.

[0524] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen. It is preferably reduced.

[0525] In addition, the openings formed in the insulators 581, 574, 580, and 544 Conductor 540a and conductor 540b are placed in the opening. The conductors 540a and 540b are provided facing each other with the conductor 560 in between. It has the same structure as the conductor 546 and the conductor 548 described later.

[0526] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material. The insulator 582 may be made of the same material as the insulator 514. For example, aluminum oxide may be used. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0527] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0528] An insulator 586 is provided on the insulator 582. The insulator 586 is The same materials as those of 320 can be used. In addition, these insulators have a relatively low dielectric constant. By using insulating materials, it is possible to reduce the parasitic capacitance that occurs between wiring. The edge 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0529] Also, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator The edge 574, the insulator 581, the insulator 582, and the insulator 586 are provided with the conductor 546 and Conductors 548 and the like are embedded.

[0530] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or the transistor The conductor 546 functions as a plug or wiring that connects to the transistor 300. The conductor 548 can be formed using the same material as the conductor 328 and the conductor 330. Cut.

[0531] After the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By encasing the transistor 500 in the insulator with high barrier properties, moisture, In addition, it is possible to prevent hydrogen from penetrating the transistors 500. The whole may be wrapped in an insulator that has high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, the insulator 514 or the insulator An opening is formed that reaches the insulator 522, and the above-mentioned barrier is formed so as to contact the insulator 514 or the insulator 522. If a highly flexible insulator is formed, the manufacturing process of the transistor 500 can be performed simultaneously. In addition, examples of insulators with high barrier properties against hydrogen or water include The same material as the insulator 522 may be used.

[0532] Next, a capacitor 600 is provided above the transistor 500. 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0533] Moreover, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 12 functions as a plug or wiring that connects to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The body 610 can be formed simultaneously.

[0534] The conductor 612 and the conductor 610 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film) Indium tin oxide, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It is also possible.

[0535] In FIG. 20, the conductor 612 and the conductor 610 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties and high adhesion to highly conductive conductors A thin conductor may be formed.

[0536] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0537] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0538] By using this structure, a semiconductor device using a transistor having an oxide semiconductor This can suppress the fluctuation of electrical characteristics and improve reliability. In semiconductor devices using transistors having compound semiconductors, miniaturization or high integration is being attempted. It is possible.

[0539] Next, another example of the structure of an OS transistor will be described, which is shown in FIGS. 20 and 21. do.

[0540] 23A and 23B are variations of the transistor 500 shown in FIGS. 22A and 22B. 23A is a cross-sectional view of a transistor 500 in the channel length direction, and FIG. 23A and 23B are cross-sectional views of the transistor 500 in the channel width direction. The structure shown in FIG. 1B is similar to that of the transistor 300 or other transistors included in the semiconductor device of one embodiment of the present invention. The present invention can also be applied to transistors.

[0541] The transistor 500 having the configuration shown in FIGS. 23A and 23B includes an insulator 402 and an insulator 22A and 22B in that it has a transistor 404. An insulator 552 is provided in contact with the side surface of the conductor 540a, and an insulator 552 is provided in contact with the side surface of the conductor 540b. The insulator 552 is provided in contact with the transistor shown in FIGS. 22A and 22B. 22A and 22B in that it does not have an insulator 520. The configuration of transistor 500 is different from that shown.

[0542] The transistor 500 having the configuration shown in FIGS. 23A and 23B has an insulator 512 on an insulator 512. In addition, an insulator 404 is provided on the insulator 574 and on the insulator 402. It is provided.

[0543] In the transistor 500 having the configuration shown in FIGS. 23A and 23B, the insulator 514, the insulator 516, insulator 522, insulator 524, insulator 544, insulator 580, and insulator 574 The insulator 404 covers these. 4 is the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the Side, side of insulator 524, side of insulator 522, side of insulator 516, side of insulator 514 The oxide 530 and the like are in contact with the side surface and the top surface of the insulator 402, respectively. 04 and is isolated from the outside by an insulator 402.

[0544] The insulators 402 and 404 are made of at least hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, the insulator 402 and the insulator 403 have a high function of suppressing the diffusion of water molecules. The insulator 404 is made of silicon nitride or silicon nitride oxide, which has a high hydrogen barrier property. It is preferable to use a material such as a silicon dioxide film, which prevents hydrogen and other impurities from diffusing into the oxide 530. Therefore, the deterioration of the characteristics of the transistor 500 can be suppressed. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0545] The insulator 552 includes the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 574. The insulator 552 is provided in contact with the insulator 544. The insulator 552 has a function of suppressing the diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of a material with a high hydrogen barrier property. Insulators such as silicon nitride, aluminum oxide, or silicon nitride oxide can be used. In particular, silicon nitride is a material with high hydrogen barrier properties, and is therefore suitable as the insulator 552. By using a material with a high hydrogen barrier property as the insulator 552, Impurities such as water or hydrogen pass through the insulator 580 and the like and the conductors 540a and 540b. In addition, the diffusion of the silicon dioxide into the oxide 530 can be suppressed. This can prevent oxygen from being absorbed by the conductors 540a and 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0546] FIG. 24 shows the transistor 500 and the transistor 300 shown in FIGS. 23A and 23B. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device in which the conductor 546 is An insulator 552 is provided on the surface.

[0547] Also, the transistor 500 shown in FIGS. 23A and 23B may be used as a transistor The transistor configuration may be changed. For example, transistor 500 in FIGS. 23A and 23B may be As a modification, the transistors shown in FIGS. 25A and 25B can be used. 5A is a cross-sectional view of the transistor in the channel length direction, and FIG. 25B is a cross-sectional view of the transistor in the channel length direction. The transistor shown in FIGS. 25A and 25B is a cross-sectional view in the width direction of the transistor. 23A and 23C, in that the oxide 530c1 and the oxide 530c2 are two-layer structures. This is different from the transistor shown in FIG. 3B.

[0548] The oxide 530c1 is formed on the top surface of the insulator 524, the side surface of the oxide 530a, and the side surface of the oxide 530b. The top surface and side surfaces, the side surfaces of the conductors 542a and 542b, the side surfaces of the insulator 544, and the insulating The oxide 530c2 contacts the side of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0549] The oxide 530c1 may be, for example, an In-Zn oxide. When the oxide 530c has a single layer structure, the oxide 530c can be used as the material 530c2. For example, the oxide 530c2 may be made of a material similar to the material that can be used for the oxide 530c2. In:Ga:Zn=1:3:4 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or A metal oxide with an atomic ratio of Ga:Zn=2:5 can be used.

[0550] By forming the oxide 530c into a two-layer structure of the oxide 530c1 and the oxide 530c2, In this case, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be used as a power MOS transistor, for example. Note that the oxide 53 included in the transistor having the structure shown in FIGS. 0c can also have a two-layer structure of oxide 530c1 and oxide 530c2.

[0551] The transistors having the configurations shown in FIGS. 25A and 25B may be, for example, The present invention can be applied to the transistor 300. For example, the transistor 300 As described above, the semiconductor device described in the above embodiment, for example, It can be applied to transistors included in the arithmetic circuits MAC1 to MAC4. Note that the transistors illustrated in FIGS. 25A and 25B are semiconductor devices according to one embodiment of the present invention. The present invention can be applied to transistors other than the transistor 300 and the transistor 500. This can be done.

[0552] FIG. 26 shows a transistor 500 having the configuration shown in FIG. 22A. 25A shows an example of the configuration of a semiconductor device in which the transistor 300 has the transistor configuration shown in FIG. 24, an insulator 552 is provided on the side surface of the conductor 546. As shown in FIG. 26, the semiconductor device of one embodiment of the present invention has a transistor 3 00 and transistor 500 are both OS transistors, while transistors 300 and Each of the transistors 500 can be configured differently.

[0553] Next, regarding the capacitance elements applicable to the semiconductor devices of FIGS. 20, 21, 24, and 26, I will explain.

[0554] FIG. 27 shows a capacitance that can be applied to the semiconductor devices shown in FIGS. A capacitor element 600A is shown as an example of the element 600. FIG. 27B is a cross-sectional view of the capacitance element 600A taken along the dashed line L3-L4. 27C is a cross-sectional view of the capacitance element 600A taken along the dashed line W3-L4. FIG.

[0555] The conductor 610 serves as one of a pair of electrodes of the capacitor 600A, and the conductor 620 serves as The insulator 630 functions as the other of the pair of electrodes of the capacitor 600A. It functions as a dielectric sandwiched between the electrodes.

[0556] The insulator 630 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, nitride Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The insulating layer may be formed of a single layer or a multilayer structure.

[0557] In this specification, hafnium oxynitride refers to a compound containing more oxygen than nitrogen as its composition. Hafnium nitride refers to a material with a high content of nitrogen rather than oxygen. Indicates materials with a high content of

[0558] For example, the insulator 630 may be made of a material with high dielectric strength, such as silicon oxynitride. A laminated structure with a high dielectric constant (high-k) material may also be used. 600A has a high dielectric constant (high-k) insulator, ensuring sufficient capacity. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the capacitance element 600A is Destruction can be suppressed.

[0559] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, or oxide nitrides having silicon and hafnium Nitrides containing fluorine are also included.

[0560] Alternatively, the insulator 630 may be, for example, aluminum oxide, hafnium oxide, or tantalum oxide. , zirconium oxide, lead zirconate titanate (PZT), strontium titanate (Sr Insulators containing high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST) For example, when the insulator 630 is a laminate, the insulating material may be a silicon dioxide. A three-layer laminate consisting of zirconium oxide, aluminum oxide, and zirconium oxide formed in this order. Zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide The insulator 630 may be a four-layer laminate formed in order. and zirconium may be used. As integration progresses, the thickness of the gate insulator and the dielectric used in the capacitor element becomes thinner, This may cause problems such as leakage current in the gate insulator and capacitor. By using high-k materials as insulators that function as dielectrics in capacitor elements, While maintaining the physical film thickness, the gate potential during transistor operation is reduced and the capacitance of the capacitor element is reduced. This makes it possible to secure

[0561] The capacitance element 600 is connected to the conductor 546 and the conductor 548 below the conductor 610. Electrical conductors 546 and 548 are electrically connected to other circuit elements. 27A to 27C, the conductor 546 functions as a plug or wiring. , conductor 548 are collectively referred to as conductor 540.

[0562] In addition, in FIG. 27, for clarity of illustration, the conductors 546 and 548 are not embedded. an insulator 586 covering the conductor 620 and the insulator 630; and an insulator 650 covering the conductor 620 and the insulator 630. is omitted.

[0563] 20, 21, 24, 26, 27A, 27B, and 27C. The capacitor 600 is a planar type, but the shape of the capacitor is not limited to this. The capacitor 600 may be a cylindrical capacitor 600B shown in FIGS. 28A to 28C. stomach.

[0564] FIG. 28A is a top view of the capacitance element 600B, and FIG. 28B is a dashed line view of the capacitance element 600B. 28C is a cross-sectional view taken along the dashed line W3-L4 of the capacitance element 600B. FIG.

[0565] In FIG. 28B, a capacitive element 600B is formed by an insulator 58 having a conductor 540 embedded therein. 6, an insulator 631 having an opening, and an insulator 651 which functions as one of a pair of electrodes. The pair of electrodes includes a conductor 610 that functions as the other of the pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0566] Also, in FIG. 28C, for clarity, the insulators 586, 650, and The body 651 and are omitted.

[0567] The insulator 631 can be formed using, for example, a material similar to that of the insulator 586.

[0568] In addition, the insulator 631 is filled with a conductor 611 so as to be electrically connected to the conductor 540. The conductor 611 is made of the same material as the conductors 330 and 518, for example. It can be used.

[0569] The insulator 651 can be formed using, for example, a material similar to that of the insulator 586.

[0570] As described above, the insulator 651 has an opening that overlaps with the conductor 611. is doing.

[0571] The conductor 610 is formed on the bottom and side of the opening. 10 overlaps the conductor 611 and is electrically connected to the conductor 611.

[0572] The conductor 610 can be formed by etching the insulator 651. A mouth is formed, and then a conductor 610 is formed by sputtering, ALD, or the like. Then, CMP (Chemical Mechanical Polishing) The conductor 610 is left in the opening by a method such as a method of forming a film on the insulator 651. The conductor 610 can then be removed.

[0573] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor.

[0574] The conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled. There are.

[0575] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0576] The cylindrical capacitor element 600B shown in FIG. 28 has a larger capacitance than the planar capacitor element 600A. The capacitance value can be increased.

[0577] Next, the capacitor element 600 shown in FIGS. 20, 21, 24, and 26 is provided above the capacitor element 600. The photoelectric conversion element 700 will now be described.

[0578] The photoelectric conversion element 700 includes, for example, a layer 767a, a layer 767b, a layer 767c, and a layer 767d and layer 767e.

[0579] The photoelectric conversion element 700 shown in FIGS. 20, 21, 24, and 26 is a photoelectric conversion element having an organic photoconductive film. In this example, the layer 767a is a lower electrode, the layer 767e is a light-transmitting upper electrode, and the layer 76 20, 21, and 24, the layers 767b, 767c, and 767d correspond to the photoelectric conversion section. 26. In place of the photoelectric conversion element 700 shown in FIG. 26, for example, a pn junction photodiode Alternatively, a photodiode, an avalanche photodiode, or the like may be used.

[0580] The bottom electrode, layer 767a, can be either the anode or the cathode, and the top electrode, layer 767b, can be either the anode or the cathode. The layer 767b, which is the electrode, can be the other of the anode and the cathode. In this configuration, layer 767a is the cathode and layer 767b is the anode.

[0581] The layer 767a is preferably a low-resistance metal layer, for example. The layer 767a may be made of, for example, aluminum, titanium, tungsten, tantalum, silver, or the like. Alternatively, a laminate of these may be used.

[0582] The layer 767e may be, for example, a conductive layer that has high light-transmitting properties with respect to visible light. Specifically, the layer 767e is preferably made of, for example, indium oxide, tin oxide, Zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide Lead oxide or graphene can be used. It can also be made into a

[0583] One of the layers 767b and 767d of the photoelectric conversion section is a hole transport layer, and the other is an electron transport layer. The layer 767c can be a photoelectric conversion layer.

[0584] The hole transport layer may be made of, for example, molybdenum oxide. For example, C 60 , C 70 or their derivatives. It is possible.

[0585] The photoelectric conversion layer is a mixed layer of n-type organic semiconductor and p-type organic semiconductor (bulk heterojunction). Synthetic structures) can be used.

[0586] In the semiconductor devices of FIGS. 20, 21, 24, and 26, the insulator 751 is an insulator 650, and layer 767a is provided on insulator 751. The insulating layer 752 is provided on the insulator 751 and on the layer 767a. 52 and on layer 767a.

[0587] Moreover, on the layer 767b, a layer 767c, a layer 767d, a layer 767e, and an insulator 753 are formed in this order. They are provided in a stacked manner.

[0588] The insulator 751 functions as an interlayer insulating film, for example. As with the insulator 324, it is preferable to use an insulator that has a barrier property against hydrogen. By using an insulator having a barrier property against hydrogen for the insulator 751, Therefore, the insulator 751 can be, for example, As the insulating layer 324, a material applicable to the insulator 324 can be used.

[0589] The insulator 752 functions as an element isolation layer, for example. However, it is provided to prevent short-circuiting with other photoelectric conversion elements located adjacent to it. For example, it is preferable to use an organic insulator as 752.

[0590] For example, the insulator 753 functions as a light-transmitting planarization film. Examples of the silicon oxide include silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride. Materials such as the following can be used.

[0591] Above the insulator 753, for example, a light-shielding layer 771, an optical conversion layer 772, and a microphone A lens array 773 is provided.

[0592] The light-shielding layer 771 provided on the insulator 753 prevents light from flowing into adjacent pixels. The light-shielding layer 771 may be made of a metal layer such as aluminum or tungsten. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated. good.

[0593] The optical conversion layer 772 provided on the insulator 753 and the light-shielding layer 771 is provided with a color filter. The color filters can be R (red), G (green), B (blue), and Y (yellow). ), C (cyan), M (magenta) and other colors are assigned to each pixel, You can get an image.

[0594] Furthermore, if a wavelength cut filter is used in the optical conversion layer 772, images in various wavelength regions can be It may be an imaging device that can obtain an image.

[0595] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 772, infrared In addition, the optical conversion layer 772 can be configured to block light having a wavelength shorter than the near-infrared wavelength. If a filter such as this is used, it can be used as a far-infrared imaging device. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. do.

[0596] Furthermore, if a scintillator is used for the optical conversion layer 772, it is possible to The imaging device can be used to obtain an image that visualizes the intensity of radiation such as X-rays that have passed through the subject. When radiation is incident on the scintillator, it emits visible light and ultraviolet light due to the photoluminescence phenomenon. The light is then converted into light (fluorescence) such as light rays. Image data is acquired by using the imaging device having the above configuration in a radiation detector or the like. Good too.

[0597] When exposed to radiation such as X-rays and gamma rays, the scintillator absorbs the energy. It includes substances that emit visible light, ultraviolet light, etc. For example, Gd2O2S:Tb, Gd2O2 S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF 2. CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics It is possible.

[0598] A microlens array 773 is provided on the light-shielding layer 771 and the optical conversion layer 772. The light passing through each lens of the microlens array 773 is incident on the optical conversion layer 772 directly below. The light passes through the microlens array 773 and is irradiated onto the photoelectric conversion element 700. By doing so, the collected light can be incident on the photoelectric conversion element 700, and therefore, the efficiency The microlens array 773 is transparent to visible light. It is preferable to form the insulating layer from a highly resistant resin or glass.

[0599] 20, 21, 24, and 26 show transistors 300 and A semiconductor device in which a photoelectric conversion element 700 using an organic photoconductive film is provided above a transistor 500. However, the semiconductor device of one embodiment of the present invention is not limited to this structure. The semiconductor device of one embodiment of the present invention is a back-illuminated type semiconductor device instead of the photoelectric conversion element 700. A pn junction type photoelectric conversion element may be provided.

[0600] FIG. 29 shows a back-illuminated transistor above the transistor 300 and the transistor 500. 29 shows an example of the configuration of a semiconductor device provided with a pn junction type photoelectric conversion element 700A. The semiconductor device shown in FIG. 1 includes a transistor 300, a transistor 500, and a capacitor 6 A structure SA having a photoelectric conversion element 700A is attached above the substrate 311 on which the photoelectric conversion element 700 is provided. It is a combined structure.

[0601] The structure SA includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array. 773 and the above explanations are to be taken into consideration.

[0602] The photoelectric conversion element 700A is a pn junction photodiode formed on a silicon substrate. It has a layer 765b corresponding to a p-type region and a layer 765a corresponding to an n-type region. The electric conversion element 700A is a buried photodiode, and the surface side of the layer 765a (current A thin p-type region (part of layer 765b) provided on the extraction side suppresses dark current. This can reduce noise.

[0603] The insulator 701, the conductor 741, and the conductor 742 function as bonding layers. The insulator 754 functions as an interlayer insulating film and a planarizing film. The insulator 756 has a function of suppressing the outflow of carriers. do.

[0604] The silicon substrate has grooves for separating pixels, and the insulator 756 is formed on the upper surface of the silicon substrate and The insulator 756 is provided in the groove. This can prevent carriers generated in the insulator from flowing to adjacent pixels. The insulator 756 also has a function of suppressing the intrusion of stray light. In addition, an anti-reflection film is formed between the upper surface of the silicon substrate and the insulator 756. may be provided.

[0605] The isolation layer is LOCOS (LOCal Oxidation of Silicon) Alternatively, the STI (Shallow Trench Ionization) method can be used. The insulator 756 may be formed by, for example, an oxide film. Inorganic insulating films such as silicon dioxide and silicon nitride, and organic insulating films such as polyimide and acrylic The insulator 756 may have a multi-layer structure.

[0606] The layer 765a (n-type region, corresponding to the cathode) of the photoelectric conversion element 700A is connected to the conductor 741. The layer 765b (p-type region, corresponding to the anode) is electrically connected to the conductor 742. The conductor 741 and the conductor 742 have a region buried in the insulator 701. The surfaces of the insulator 701, the conductor 741, and the conductor 742 are at the same height. It has been flattened to resemble a square.

[0607] Above the insulator 650, an insulator 691 and an insulator 692 are stacked in this order. The insulators 691 and 692 have openings, and the insulating material 691 is made of a material that fills the openings. A conductor 743 is formed on the surface.

[0608] For example, the material applicable to the insulator 751 can be used as the insulator 691. .

[0609] Furthermore, for the insulator 692, for example, a material applicable to the insulator 650 can be used. can.

[0610] The insulator 693 and the insulator 701 each function as a part of the bonding layer. The conductors 741, 742, and 743 are also part of the bonding layer. It functions as such.

[0611] The insulators 693 and 701 are, for example, silicon oxide and silicon oxynitride. , silicon oxynitride, silicon nitride, titanium nitride, etc. can be used. In order to join the body 693 and the insulator 701, the insulator 693 and the insulator 701 are made of the same material. Preferably, it consists of minutes.

[0612] The conductors 741, 742, and 743 are made of, for example, copper or aluminum. , tin, zinc, tungsten, silver, platinum, or gold can be used. In order to easily bond the conductors 741 and 743 and the conductors 742 and 743, copper It is preferable to use aluminum, tungsten, or gold.

[0613] Note that the conductor 741, the conductor 742, and the conductor 743 each have a multilayer structure including multiple layers. For example, the opening in which the conductor 741, the conductor 742, or the conductor 743 is provided may be A first conductor is formed on the side of the portion, and then a second conductor is formed to fill the opening. The first conductor may be, for example, a material having a barrier property against hydrogen, such as tantalum nitride. The second conductor may be, for example, a highly conductive conductor. For example, tungsten can be used.

[0614] A pre-process for bonding the bonding layer on the substrate 311 side to the bonding layer on the structural body SA side. In this process, the surfaces of the insulator 693 and the conductor 743 on the substrate 311 side are at heights of Similarly, on the side of the structure SA, the insulator 701 and the conductive The surfaces of the conductor 741 and the conductor 742 are flattened so that they are at the same height. do.

[0615] In the bonding process, the insulator 693 and the insulator 701 are bonded together, that is, the insulating layers are bonded together. When doing this, after giving it high flatness by polishing, etc., it is treated with hydrophilicity by oxygen plasma, etc. Hydrophilic bonding is a method in which the surfaces are brought into contact with each other to temporarily bond them together, and then the final bonding is achieved by dehydrating them through heat treatment. Hydrophilic bonding also has excellent mechanical properties because bonding occurs at the atomic level. A bond can be obtained.

[0616] Furthermore, for example, the junction between the conductor 741 and the conductor 743 and the junction between the conductor 742 and the conductor 744 When joining with 3, that is, joining conductors together, the surface oxide film and adsorption of impurities The layers are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact with each other. Alternatively, a surface activated bonding method can be used, in which the bonding is performed by combining temperature and pressure. In both cases, bonding occurs at the atomic level. Therefore, it is possible to obtain a bond that is excellent not only electrically but also mechanically.

[0617] By carrying out the above-mentioned bonding process, the conductor 743 on the substrate 311 side is The substrate SA can be electrically connected to the conductor 741 and the conductor 742. The insulator 693 on the plate 311 side and the insulator 701 on the structure SA side have the same mechanical strength. You can get a connection.

[0618] When the substrate 311 and the structure SA are bonded together, an insulating layer and a metal layer are formed on each bonding surface. For example, the surface activated bonding method and the hydrophilic bonding method may be combined. .

[0619] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then made hydrophilic. Alternatively, the surface of the metal layer may be treated with a hard metal such as gold. It is also possible to use an oxidized metal and then subject it to hydrophilic treatment. That's fine.

[0620] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0621] (Embodiment 6) In this embodiment, the semiconductor device can be used for the OS transistor described in the above embodiment. The metal oxide (hereinafter also referred to as an oxide semiconductor) will be described.

[0622] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that the material contains yttrium, tin, etc. Also, boron, silicon, titanium, etc. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Selected from among odymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. One or more of these may be included.

[0623] <Classification of crystal structures> First, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. 30A. FIG. 30A shows an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides.

[0624] As shown in FIG. 30A, oxide semiconductors are broadly divided into "amorphous" and "non-amorphous" oxide semiconductors. ) and "Crystalline" and "Crystal" Also, among "Amorphous" there are those that are completely amorphous. Also, "Crystalline" contains CAAC (ca xis-aligned crystalline), nc(nanocrystall ine), and CAC (Cloud-Aligned Composite) The classification of "Crystalline" includes single crystal, po Completely crystalline and completely amorphous are excluded. "Crystal" includes single crystal and poly crystal. Includes ystal.

[0625] The structures within the bold frame in Figure 30A are "Amorphous" and "Cr It is an intermediate state between "crystal" and "new crystal" In other words, the structure is in the It is completely different from the unstable "Amorphous" and "Crystal". This can be rephrased as a structure.

[0626] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). The crystallinity can be evaluated using the crystallinity spectrum. The GIXD (Grazing-Incidence) of CAAC-IGZO films The XRD spectrum obtained by the XRD measurement is shown in FIG. 30B (the vertical axis is the intensity The GIXD method is a thin film method or This is also called the Seemann-Bohlin method. The XRD spectrum obtained by the CAAC analysis shown in FIG. The composition of the IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 30B is 500 nm.

[0627] As shown in Figure 30B, the XRD spectrum of the CAAC-IGZO film shows clear crystalline Specifically, in the XRD spectrum of the CAAC-IGZO film, A peak indicating the c-axis orientation is detected near 2θ=31°. The peak around 2θ=31° is asymmetrical with respect to the angle at which the peak intensity is detected. .

[0628] The crystal structure of the film or substrate was also analyzed by nanobeam electron diffraction (NBED). Diffraction patterns (ultra-small) observed by electron diffraction It can be evaluated by the electron diffraction pattern. The folding pattern is shown in Figure 30C. Figure 30C shows the NB method in which the electron beam is incident parallel to the substrate. The diffraction pattern observed by ED is shown in Figure 30C. The composition of the film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0629] As shown in Figure 30C, the diffraction pattern of the CAAC-IGZO film shows multiple patterns indicating c-axis orientation. Several spots are observed.

[0630] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in FIG. 30A. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, the above-mentioned CAAC-OS Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-crystalline oxide semiconductors, and nc-OS. Amorphous-like oxide semiconductor (a-like OS) semiconductor), amorphous oxide semiconductor, etc.

[0631] Here, for details on the above-mentioned CAAC-OS, nc-OS, and a-like OS, , and provide an explanation.

[0632] [CAAC-OS] The CAAC-OS has multiple crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. , in the normal direction to the surface on which the CAAC-OS film is formed, or in the normal direction to the surface of the CAAC-OS film. The crystalline region is a region in which the atomic arrangement has periodicity. When viewed as a crystal arrangement, the crystalline region is also a region with a uniform lattice arrangement. The OS has a region where multiple crystalline regions are connected in the ab-plane direction, and this region has strain. The distortion may occur in a region where multiple crystal regions are connected. The area where the orientation of the lattice arrangement changes between a region with one lattice arrangement and a region with a different lattice arrangement. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that has not been

[0633] Each of the plurality of crystalline regions is made up of one or more minute crystals (maximum diameter 10 When a crystalline region is made up of a single microcrystal (crystals less than 1 nm in size), The maximum diameter of the crystalline region is less than 10 nm. When such crystal regions are formed, the size of the crystal regions may be on the order of several tens of nanometers.

[0634] In-M-Zn oxide (element M is aluminum, gallium, yttrium, sulphur, CAAC-OS is a material selected from the group consisting of aluminum, titanium, and other materials. A layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the O layer) are formed. A layered crystal structure (also called a layered structure) is formed by stacking a layer having an element (hereinafter referred to as an (M, Zn) layer) and a layer having an element (hereinafter referred to as an (M, Zn) layer). Indium and element M are mutually substitutable. The (M,Zn) layer may contain indium. The In layer contains the element M. The In layer may contain Zn. In high-resolution TEM images, this is observed as a lattice pattern.

[0635] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ phase In the out-of-plane XRD measurement using a can, two peaks indicating the c-axis orientation were observed. The peak indicating the c-axis orientation is detected at or near θ=31°. ) may vary depending on the type and composition of the metal elements that make up the CAAC-OS.

[0636] For example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) Note that one spot and another spot are the incident electron beams that have passed through the sample. The spot (also called the direct spot) is the center of symmetry, and the points are observed at positions that are point-symmetric. can be.

[0637] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is a hexagonal lattice. However, the unit cell is not necessarily a regular hexagon, and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. -In OS, clear grain boundaries were confirmed even near the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is close-packed in the ab-plane direction. The bond distance between atoms changes when metal atoms are substituted. , it is believed that this is because distortion can be tolerated.

[0638] The crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries act as recombination centers, trapping carriers and forming transistors. It is highly likely that this will cause a decrease in on-state current and a decrease in field effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystalline structure suitable for the semiconductor layer of a transistor. It is one of the crystalline oxides containing Zn to form CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are made of In oxide. This is preferable because it can suppress the generation of grain boundaries more effectively than oxides.

[0639] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, the CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. In addition, the crystallinity of oxide semiconductors may be reduced by the incorporation of impurities, the generation of defects, etc. Therefore, CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having a CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. C-OS is stable even under high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using CAAC-OS for OS transistors increases the flexibility of the manufacturing process. It becomes possible to

[0640] [nc-OS] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). In other words, nc-OS has a periodic atomic arrangement in the region of 3 nm or less. It has small crystals. The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. Since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, depending on the analytical method, nc-OS may be considered as a-like In some cases, it is difficult to distinguish between an nc-OS film and an amorphous oxide semiconductor. , Structural analysis was performed using an XRD instrument, and out-of-plane analysis using θ / 2θ scan was performed. In the XRD measurement, no peaks indicating crystallinity were detected. However, electron beam circuits using electron beams with probe diameters larger than nanocrystals (e.g., 50 nm or larger) are being used. When electron diffraction (also called selected area electron diffraction) is performed, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, the size of the nanocrystals is close to or smaller than that of the nanocrystals. Electron beam diffraction (nanobeam) using an electron beam with a probe diameter (for example, 1 nm to 30 nm) When electron diffraction is performed, a ring-shaped region is formed around the direct spot. An electron diffraction pattern may be obtained in which multiple spots are observed.

[0641] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has pores or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0642] <<Oxide semiconductor structure>> Next, the details of the above-mentioned CAC-OS will be explained. Regarding the formation of

[0643] [CAC-OS] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are 0.5 nm to 10 nm in size. Preferably, the material is unevenly distributed in a size of 1 nm to 3 nm or in the vicinity thereof. In the following, it is assumed th...

Claims

1. A multiply-accumulate circuit having a memory cell array, a first circuit, a second circuit, and a third circuit, the memory cell array has a function of being able to hold first data supplied from the first circuit; the second circuit has a sensor and has a function of generating second data corresponding to information obtained by sensing and transmitting the second data to the third circuit; the third circuit has a function of supplying the second data to the memory cell array; the memory cell array has a function of performing a product-sum operation using the first data and the second data and outputting the operation result; Multiply-accumulate circuit.

2. In claim 1, The memory cell array having at least one memory cell; The memory cell a first transistor, a second transistor, and a capacitor; The capacitor has a function of holding the first data and the second data in a first terminal of the capacitor. Multiply-accumulate circuit.

3. In claim 1, The second circuit includes: having at least one photodiode-based optical sensor; Multiply-accumulate circuit.

4. In claim 1, The third circuit includes: a first switch and a second switch; a function of supplying the second data to the memory cell array via the second switch; Multiply-accumulate circuit.

Images