Method for manufacturing a circuit on a substrate and a substrate having the circuit

Abstract

A method for manufacturing a circuit for a substrate in which excessive etching of the edge of the circuit is suppressed and the dimensional accuracy of the circuit is improved, and a substrate having such a circuit are provided. [Solution] The method is characterized by comprising a first step in which a first etching resist covering the surface of a first conductor is provided in a portion that will become a circuit intermediate; a second step in which the first conductor is etched to provide the circuit intermediate; a third step in which a first insulating resin is filled into the space provided after etching; a fourth step in which a second etching resist is provided on the surface of the circuit intermediate; and a fifth step in which the side surface of the circuit intermediate is half-etched while being protected by the first insulating resin to provide a first circuit and a second circuit.

Description

[Technical Field]

[0001] The present invention relates to a technique for improving the dimensional accuracy of circuits that constitute a substrate. [Background technology]

[0002] 2. Description of the Related Art Conventionally, a known method for forming a circuit on a substrate involves providing an etching resist on a conductor provided on the surface of a substrate and then etching the conductor to form the circuit. FIG. 3(e) of Patent Document 1 discloses a manufacturing method for manufacturing an upper interlayer circuit (referred to as upper wiring portion 311 in Patent Document 1) extending in the thickness direction of the substrate, a lower interlayer circuit (referred to as lower wiring portion 312 in Patent Document 1), and a planar circuit (referred to as interlayer connection portion 313 in Patent Document 1) extending in the planar direction as a circuit without a connection surface. As shown in FIGS. 3(a) and 3(b) of Patent Document 1, the circuit of Patent Document 1 protects the portion that will become the upper interlayer circuit with an etching resist, and then performs half etching to create the upper interlayer circuit. After that, the half-etched area is filled with insulating resin, and then the area that will become the lower interlayer circuit is protected with etching resist, as shown in Figure 3(c), and then half-etched to create the lower interlayer circuit. Thereafter, as shown in Figures 3(d) and 3(e), etching is performed while the portions that will become the lower interlayer circuit and the planar circuit are protected, thereby forming a circuit without a connecting surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2012 / 133380 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing method of Patent Document 1, the lower interlayer circuit is subjected to two etching processes, which causes the side surfaces of the lower interlayer circuit to be excessively etched, resulting in a convex shape with rounded edges. This makes it difficult to control the width of the circuit as desired, and there is a risk of disconnection when the circuit is miniaturized.

[0005] The present invention has been made in view of the above-mentioned background art, and provides a method for manufacturing a substrate that suppresses excessive etching of the edge of a circuit and improves the dimensional accuracy of the circuit. In other words, it provides a method for manufacturing a substrate that achieves finished accuracy close to the design value of the circuit. [Means for solving the problem]

[0006] As a result of thorough research into the above-mentioned problems, the inventors discovered that by protecting the surface portions of a circuit that have already been etched with an insulating resin, it is possible to prevent a second etching process from being performed on the surface portions, and by preventing the edges of the circuit from being over-etched, it is possible to improve dimensional accuracy, and thus completed the present invention.

[0007] More specifically, the surface portion of the circuit that has been etched once corresponds to the side surface of the circuit, and the purpose is to prevent excessive etching from the side surface of the circuit.

[0008] The method for manufacturing a substrate of the present invention (claim 1) for solving the above problem is characterized by comprising, as shown in Figures 3 to 5, a first step in which a first etching resist (40) covering the surface of a first conductor (60) is provided in a portion that will become a circuit intermediate body (20); a second step in which the first conductor (60) is etched to provide the circuit intermediate body (20); a third step in which a first insulating resin (30) is filled into the space (401) provided after etching; a fourth step in which a second etching resist (50) is provided on the surface of the circuit intermediate body; and a fifth step in which the side surface (203) of the circuit intermediate body is half-etched while protected by the first insulating resin (30), to provide a first circuit (21) and a second circuit (22). According to the substrate of the present invention, excessive etching of the edge of the circuit can be suppressed, and a manufacturing method for a circuit of a substrate with improved dimensional accuracy of the circuit, and a substrate having such a circuit can be obtained.

[0009] Furthermore, one embodiment (claim 2) of the method for manufacturing a substrate of the present invention is characterized in that, as shown in Figure 4(B), the second etching resist (50) in the fourth step is provided across the upper surface of the circuit intermediate body (20) and the upper surface of the first insulating resin (30).

[0010] Furthermore, a manufacturing method of a substrate of the present invention for solving the above-mentioned problems (claim 3) is characterized by comprising, as shown in Figures 9 to 11, a seventh step in which a first etching resist (40) covering the surface of a first conductor (60) is provided in a portion that will become a first circuit (21); an eighth step in which the first conductor (60) is etched to provide the first circuit (21); a ninth step in which a first insulating resin (30B) is filled into a space (402) provided after etching; a tenth step in which a second conductor (61) is provided over the surface of the first circuit (21) and the surface of the first insulating resin (30B); an eleventh step in which a second etching resist (50) is provided on the surface of the second conductor (61); and a twelfth step in which a side surface (214) of the first conductor is etched while being protected by the first insulating resin (30B) to provide a second circuit (22) connected to the first circuit (21).

[0011] Furthermore, one embodiment (claim 4) of the method for manufacturing a substrate of the present invention is characterized in that, as shown in Figure 10(B), the second etching resist (50) in the eleventh step is provided across the upper surface of the first circuit (21) and the upper surface of the first insulating resin (30B) with a second conductor (61) interposed therebetween.

[0012] Furthermore, a method for manufacturing a substrate (claim 5) of the present invention for solving the above problems includes, as shown in Figures 14 to 16, a seventh step of providing a first etching resist (40) covering the surface of a first conductor (60) in a portion that will become a first circuit (21C), an eighth step of etching the first conductor to provide the first circuit (21C), a fourteenth step of filling a space (402) provided after etching with a first insulating resin (30C), a fifteenth step of providing a protective coating (7) on the surface of the first circuit (21C), and The method is characterized by comprising: a sixteenth step of providing a second conductor (61) over the surface of the first circuit (21C), the surface of the first insulating resin (30C), and the surface of the protective coating (7); a seventeenth step of providing a second etching resist (50) on the surface of the second conductor (61); and an eighteenth step of etching the side (214C) and the surface of the first conductor (60) while being protected by the first insulating resin (30C) and the protective coating (7), thereby providing a second circuit (22C) connected to the first circuit (21C).

[0013] Furthermore, one embodiment (claim 6) of the method for manufacturing a substrate of the present invention is characterized in that the second etching resist (50) in the seventeenth step is provided across the upper surface of the protective coating (7) and the upper surface of the first insulating resin (30C) with the second conductor (61) interposed therebetween.

[0014] Furthermore, in one embodiment (claim 7) of the method for manufacturing a substrate of the present invention, the conductor is a rolled conductor.

[0015] Furthermore, one embodiment (claim 8) of the substrate manufacturing method of the present invention is characterized by comprising a step of using a substrate in a state after the manufacturing method described in claim 7 as the substrate, providing an electrolytic conductor on the surface of the substrate by plating, and a manufacturing method according to any one of claims 3 to 6.

[0016] Furthermore, one embodiment (claim 9) of the method for manufacturing a substrate of the present invention is characterized in that the first circuit (21, 21C, 21C1) is a planar circuit extending in the planar direction of the substrate, and the second circuit (22, 22C, 22C1) is an interlayer circuit extending in the thickness direction of the substrate.

[0017] Furthermore, one embodiment (claim 10) of the method for manufacturing a substrate of the present invention is characterized in that the first circuit (21, 21C, 21C1) and the second circuit (22, 22C, 22C1) are interlayer circuits extending in the thickness direction of the substrate.

[0018] Furthermore, the substrate (claim 11) of the present invention for solving the above problem is a substrate (1B) having a first circuit (21), a second circuit (22), and an insulator (3B), as shown in Figures 6(B) and 7, characterized in that in a cross section of a portion where the first circuit (21) and the second circuit (22) are adjacently superimposed, the width (W1) of the bottom of the first circuit (21) at the center side in the thickness direction of the substrate is greater than the width (W2) of the top part of the first circuit 21 at the surface side in the thickness direction of the substrate, the first circuit (21) and the second circuit (22) have a connection surface (23) between the conductors between the top part (211) of the first circuit and the bottom part (215) of the second circuit (22), and the connection surface (23) between the conductors is arranged in a state where there is a connection surface of the conductor extending in the planar direction but no connection surface of the conductor extending in the thickness direction.

[0019] Furthermore, in one embodiment (claim 12) of the substrate of the present invention, the insulator (3B) has a connection surface (301) between the insulating resins between the insulating resin (30B) of the first circuit that contacts the side surface (214) of the first circuit and the insulating resin (31B) of the second circuit that contacts the side surface (223) of the second circuit, and the connection surface (301) between the insulating resins is characterized in that the connection surface of the insulating resin extends in the planar direction, and the connection surface between the conductors and the connection surface between the insulating resins are on the same plane without any steps.

[0020] Furthermore, one embodiment (claim 13) of the substrate of the present invention is characterized in that, as shown in Figure 12 (B), a protective coating (7) is provided on the surface of the first circuit (21C), and the protective coating (7) is lower in height than the second circuit (22C).

[0021] Furthermore, one embodiment (claim 14) of the substrate of the present invention is characterized in that, as shown in Figure 11 (B), it has a third circuit (21') different from the first circuit (21), and in a cross section of the portion where the third circuit (21') and the second circuit (22) are adjacently superimposed, the second circuit (22) and the third circuit (21') have a connection surface (23A) between other conductors between the top part (221) of the second circuit (22) and the bottom part of the third circuit (21'), and the connection surface (23A) between other conductors is arranged in a state where there is a connection surface of the conductor extending in the planar direction but no connection surface of the conductor extending in the plate thickness direction.

[0022] Furthermore, in one embodiment (claim 15) of the substrate of the present invention, the insulator (3B) has a connection surface (301A) between the second insulating resin (31B) in contact with the side surface of the second circuit and the third insulating resin (30B') in contact with the side surface of the third circuit (21'), and the connection surface (301A) between the second insulating resins has a connection surface of the insulating resin extending in the planar direction, and the connection surface between other conductors and the connection surface of the second insulating resin are on the same plane without any steps.

[0023] Furthermore, one embodiment (claim 16) of the substrate of the present invention is characterized in that, as shown in Figure 7, the width (W3) of the bottom of the second circuit, which is located on the center side of the substrate in the thickness direction, is larger than the width (W4) of the top of the second circuit, which is located on the surface side of the substrate in the thickness direction.

[0024] Furthermore, one embodiment (claim 17) of the substrate of the present invention is characterized in that the width of the bottom of the third circuit (21') located on the central side of the substrate in the thickness direction is larger than the width of the top of the third circuit (21') located on the surface side of the substrate in the thickness direction.

[0025] Furthermore, one embodiment (claim 18) of the substrate of the present invention is characterized in that it further comprises a first rolled plate circuit (21) made of a rolled plate and a second rolled plate circuit (22) made of a rolled plate, as shown in Figure 1 (B), and the first rolled plate circuit (21) and the second rolled plate circuit (22) are an integral conductor with no connecting surface.

[0026] Furthermore, one embodiment (claim 19) of the substrate of the present invention is characterized in that, as shown in Figure 17, it has a reinforcing structure (29) in the same plane as the first circuit (21) of the rolled plate, and the first circuit (21) of the rolled plate and the reinforcing structure (29) are formed from the same rolled plate.

[0027] Furthermore, one embodiment (claim 20) of the substrate of the present invention is characterized in that, as shown in Figure 17(A), the reinforcing structure (29) is arranged so as to cover the portion where the first circuit (21C1) and the second circuit (22C1) are connected or the portion where the second circuit (22C1) and the third circuit are connected, with a second insulating resin (31) interposed therebetween. [Effects of the Invention]

[0028] According to the present invention, it is possible to provide a method for manufacturing a circuit for a substrate and a substrate having such a circuit, which can suppress excessive etching of the edge of the circuit and improve the dimensional accuracy of the circuit. [Brief explanation of the drawings]

[0029] [Figure 1] Figure (A) is a schematic diagram showing a plan view of a substrate according to a first embodiment of the present invention. Figure (B) is a schematic diagram showing the aa cross section of Figure (A). Figure (C-1) of Figure (C) is a schematic diagram showing the bb cross section of Figure (B), and Figure (C-2) is a schematic diagram showing the cc cross section of Figure (B). [Figure 2] 1(A) is a schematic diagram showing the bb cross section of FIG. 1(B), and FIG. 1(B) is a schematic diagram showing the cc cross section of FIG. 1(B). [Figure 3] 1A to 1C are diagrams showing a manufacturing process of a substrate according to a first embodiment of the present invention. [Figure 4] It is a figure showing the manufacturing process of the substrate of the first embodiment of the present invention. [Figure 5] It is a figure showing the manufacturing process of the substrate of the first embodiment of the present invention. [Figure 6] (A) The figure is a schematic view showing the state of the substrate of the second embodiment of the present invention in a plan view. (B) The figure is a schematic view showing the a-a cross section of (A) figure. (C-1) of (C) figure is a schematic view showing the b-b cross section of (B) figure, and (C-2) figure is a schematic view showing the c-c cross section of (B) figure. [Figure 7] (A) The figure is a schematic view showing the b-b cross section of FIG. 6(B), and (B) figure is a schematic view showing the c-c cross section of FIG. 6(B). [Figure 8] It is a cross-sectional view showing a modified example of the substrate of the second embodiment of the present invention. (A) The figure is a schematic view showing the b-b cross section of FIG. 6(B) in the modified example, and (B) figure is a schematic view showing the c-c cross section of FIG. 6(B) in the modified example. It is a schematic view showing the state of being cut in the plate thickness direction. [Figure 9] It is a figure showing the manufacturing process of the substrate of the second embodiment of the present invention. [Figure 10] It is a figure showing the manufacturing process of the substrate of the second embodiment of the present invention. [Figure 11] It is a figure showing the manufacturing process of the substrate of the second embodiment of the present invention. [Figure 12] (A) The figure is a schematic view showing the state of the substrate of the third embodiment of the present invention in a plan view. (B) The figure is a schematic view showing the a-a cross section of (A) figure. (C-1) of (C) figure is a schematic view showing the b-b cross section of (B) figure, and (C-2) figure is a schematic view showing the c-c cross section of (B) figure. [Figure 13] (A) The figure is a schematic view showing the b-b cross section of FIG. 12(B), and (B) figure is a schematic view showing the c-c cross section of FIG. 12(B). [Figure 14] It is a figure showing the manufacturing process of the substrate of the third embodiment of the present invention. [Figure 15] It is a figure showing the manufacturing process of the substrate of the third embodiment of the present invention. [Figure 16]10A to 10C are diagrams showing a manufacturing process of a substrate according to a third embodiment of the present invention. [Figure 17] Fig. 1A is a schematic diagram showing a cross section of a substrate according to a fourth embodiment of the present invention, cut in the thickness direction along a first circuit, and Fig. 1B is a schematic diagram showing the aa cross section of Fig. 1A. [Figure 18] Figure (A) is a schematic diagram showing the bb cross section of Figure 17(A), Figure (B) is a schematic diagram showing the cc cross section of Figure 17(A) and a schematic diagram showing the dd cross section of Figure 17(A). [Figure 19] 10A to 10C are diagrams showing a manufacturing process of a substrate according to a fourth embodiment of the present invention. [Figure 20] 10A to 10C are diagrams showing a manufacturing process of a substrate according to a fourth embodiment of the present invention. [Figure 21] 10A to 10C are diagrams showing a manufacturing process of a substrate according to a fourth embodiment of the present invention. [Figure 22] 10A and 10B are schematic diagrams showing a modified example of the substrate according to the fourth embodiment of the present invention, in which Fig. 10A is a schematic diagram showing a cross section of the modified substrate cut in the thickness direction along the first circuit, and Fig. 10B is a schematic diagram showing the aa cross section of Fig. 10A. [Figure 23] 1A and 1B are schematic diagrams showing a substrate manufactured by a conventional manufacturing method, in which FIG. 1A is a schematic diagram showing a plan view of the conventional substrate, FIG. 1B is a schematic diagram showing the aa cross section of FIG. 1A, FIG. 1C-1 is a schematic diagram showing the bb cross section of FIG. 1B, and FIG. 1C-2 is a schematic diagram showing the cc cross section of FIG. 1B. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, embodiments of a method for manufacturing a circuit on a substrate according to the present invention and a substrate having such a circuit will be described in detail with reference to the drawings. It should be noted that the method for manufacturing a circuit of a substrate and a substrate having that circuit described in the embodiments are merely examples used to explain the method for manufacturing a circuit of a substrate and a substrate having that circuit according to the present invention, and are not limited to these.

[0031] The substrate of the present invention has a circuit body made of a conductor and an insulator, and the circuit body and electronic components are connected so that electricity flows, thereby constituting an electronic device.

[0032] [First embodiment] (substrate) The structure of a substrate according to an embodiment of the present invention will be described with reference to Figure 1. A substrate 1A of the present invention has a circuit layer 4 including a circuit body 2 and an insulator 3. The substrate 1 of the present invention also has a circuit layer 4 and a base material 5, which are stacked one on top of the other.

[0033] <Circuit body> The circuit body 2 includes a first circuit 21 and a second circuit 22. The circuit body 2 is formed from a conductor, and is formed from a rolled conductor in the form of a rolled plate or an electrolytic conductor provided by plating. The circuit body 2 includes a circuit through which electricity flows and / or a circuit through which heat flows. The first circuit 21 is a planar circuit extending in the direction of the plane of the XY axes, and the second circuit 22 is an interlayer circuit extending in the direction of the thickness of the substrate on the Z axis.

[0034] A planar circuit is a circuit that extends in a plane direction and has interlayer circuits on at least one side and interlayer circuits on the other side that extend in the opposite direction from the one side. An interlayer circuit is a circuit that extends in the thickness direction of the board and connects circuits on different layers. In the embodiment of the present invention, for the sake of simplicity, only one interlayer circuit is illustrated. The first circuit 21 and the second circuit 22 are formed as a single conductor with no connecting surface, which has the effect of reducing the risk of poor connection due to thermal expansion of the conductor, since there is no connecting surface between the conductors.

[0035] <First Circuit> The planar circuit of the first circuit 21 has a top portion 211 of the planar circuit that forms a gentle curve recessed inward from the surface (upper surface) side of the substrate 1, and a top protrusion 212 that is an end portion of the boundary between the planar circuit and the insulating resin that protrudes toward the surface. This protruding top protrusion 212 is formed as a single continuous protrusion that surrounds a central portion 213 of the planar circuit when viewed from the plane of the substrate (in the XY axis direction). The top projection 212 is located at a position extending from the surface of the insulating resin 30 to the interior thereof. The side surface 214 of the planar circuit is in contact with the insulating resin 30 and forms a gently sloping surface that widens toward the bottom 215 of the planar circuit. This inclined surface structure is a shape that is realized by using the method for manufacturing the circuit of the substrate of the present invention, and is the result of the side surface of the first circuit 21 being left without being etched too much.

[0036] 23, in the conventional manufacturing method, when insulating resin 930 is provided after half etching is performed twice, end 924 of the circuit is over-etched, and the boundary between planar circuit 921 and insulating resin 930 has a shape with a curved surface that gently slopes downward toward the center (bottom) in the thickness direction of substrate 910. In other words, in the conventional method, during the second etching process, etching is excessively performed from the side of the circuit, and excessive etching occurs toward bottom 925 of planar circuit 921, which tends to narrow the width of the circuit. In the present invention, by etching the side surface 214 of the circuit (first circuit 21) while it is protected by insulating resin 30, it is possible to prevent the circuit from becoming too thin, making it easier to form the circuit width close to the design value, and reducing the risk of the circuit breaking. Note that in addition to cases where top protrusion 212 protrudes outward (upward) in the thickness direction, there are also cases where top protrusion 212 cannot be seen and top portion 211 becomes nearly flat, depending on the etching process conditions. However, unlike circuits manufactured by conventional manufacturing methods, it is possible to prevent the boundary between the planar circuit and the insulating resin from becoming a shape with a curved surface that slopes gently downward toward the center in the thickness direction, and the effect of preventing excessive etching remains unchanged.

[0037] As shown in FIG. 2(A), in the area where the first circuit 21 and the second circuit 22 are not overlapped, when the first circuit 21 is cut perpendicular to the direction extending in the planar direction of the planar circuit that is the first circuit 21, the cross section of the planar circuit has a trapezoidal shape with a concave upper edge. The width W1 of the bottom portion 215 of the first circuit 21 is larger than the width W2 of the top portion 211 of the first circuit 21 (the width between the top protrusions 212). Furthermore, the insulating resin 30 covering the side surface of the first circuit 21 has a lateral protrusion 305 formed thereon that protrudes toward the center portion 213 of the first circuit 21 (in the lateral direction) so as to cover the top of the top protrusion 212.

[0038] <<Second Circuit>> The interlayer circuit of the second circuit 22 has a flat top portion 221 of the interlayer circuit so as to be flush with the insulating resin 30 and the insulating resin 31. The bottom portion 222 of the second circuit 22 corresponds to an imaginary line 225 connecting the top protrusions 212. The side surface 223 of the second circuit 22 (interlayer circuit) that comes into contact with the insulating resin 30 forms a gently inclined surface that widens toward the bottom 222 of the interlayer circuit. This inclined surface structure is a shape that is realized by using the method for manufacturing the circuit of the substrate of the present invention, and is the result of the side surface 223 of the second circuit 22 being left without being etched too much.

[0039] 23, in the conventional manufacturing method, the edges of the circuit are over-etched, and the edge 927 of the boundary between the interlayer circuit and the insulating resin has a shape with a curved surface that gently slopes down toward the center in the thickness direction of the substrate 910. In other words, in the conventional method, etching is excessive from the side of the circuit, and etching is excessively performed toward the bottom 926 of the interlayer circuit, which tends to make the circuit thinner. In the present invention, by etching the side of the circuit (second circuit 22) while it is protected by insulating resin 30, it is possible to prevent the circuit from becoming too thin, making it easier to form the circuit width close to the design value, and reducing the risk of circuit breakage.

[0040] As shown in FIG. 2B, in the portion where the first circuit 21 and the second circuit 22 are adjacently superimposed, the cross section of the interlayer circuit when cut perpendicular to the direction extending in the planar direction of the planar circuit, which is the first circuit, is trapezoidal. The width W3 of the bottom portion 222 of the second circuit 22 is larger than the width W4 of the top portion 221 of the second circuit 22.

[0041] In this embodiment, in the portion where the first circuit 21 and the second circuit 22 are adjacently superimposed, the cross section of the planar circuit, which is the first circuit, when cut perpendicularly to the direction extending in the planar direction, is a trapezoid, and the side surface 214 of the first circuit and the side surface 223 of the second circuit 22 form a gently sloping surface. In other words, the width W2 of the first circuit 21 and the width W3 of the second circuit are equal to each other.

[0042] <Insulator> The insulator 3 includes an insulating resin 30 and an insulating resin 31 . The insulating resin 30 and the insulating resin 31 may be made of the same material or different materials as long as they do not conduct electricity. The insulating resin 30 and the insulating resin 31 have a connecting surface 32 that is inclined in the thickness direction.

[0043] <Insulating resin 30> Insulating resin 30 is arranged so as to contact side surface 214 of first circuit 21 , side surface 223 of the second circuit, side surface of insulating resin 31 , and substrate 5 . Insulating resin 30 is disposed so as to cover side surface 214 of first circuit 21 and side surface 223 of second circuit 22, and also serves to protect the side surfaces of the circuits from etching liquid during the circuit manufacturing process.

[0044] <Insulating resin 31> The insulating resin 31 is arranged so as to be in contact with the top portion 211 of the first circuit 21, the side surface 223 of the second circuit, and the side surface of the insulating resin 30. The insulating resin 31 is filled into the space left after etching in a state where the side surfaces of the circuit intermediate body 20 described below are covered with the insulating resin 30.

[0045] <Base material> The substrate 5 may be any substrate that supports the first circuit 21 and the second circuit 22, and may be a plate-shaped insulating plate made of a sheet of woven glass fiber and insulating resin, or the substrate may be a circuit layer including a circuit made of a conductor connected to the bottom 215 of the first circuit 21 so as to transmit electricity and / or heat.

[0046] (Regarding substrate manufacturing methods) A method for manufacturing the substrate 1A of the first embodiment will be described with reference to Fig. 3. Note that although each step is expressed by a number, such as first step, second step, and third step, the steps may not proceed in the numerical order, and it is not essential that the steps proceed in the numerical order.

[0047] First, as shown in Fig. 3(A), a conductor 60 is provided on the entire surface of the substrate 5. The conductor 60 corresponds to a first conductor, and may be either a rolled conductor or an electrolytic conductor. A first etching resist 40 covering the surface of the conductor 60 is provided on the portions of the circuit intermediate body 20 that will become the first circuit 21 and the second circuit 22. This step is referred to as the first step.

[0048] 3(B), an etching process is performed to provide a circuit intermediate body 20. As a result, a part of the substrate 5 is exposed, and an etched space 401 is provided. This step is referred to as the second step.

[0049] 3(C), the first etching resist 40 is removed, and the space 401 formed after etching is filled with the insulating resin 30. Then, the surface of the circuit intermediate body 20 is exposed, and the side surface 203 of the circuit intermediate body 20 and the surface of the base material 5 are covered with the insulating resin 30. This step is referred to as the third step. Although not shown, the third step may include a surface smoothing process (step) for making the surface of the circuit intermediate body 20 and the surface of the insulating resin 30 into one flat surface (the same plane) without any steps.

[0050] 4(A), a second etching resist 50 is provided across the surface of the circuit intermediate body 20 and the insulating resin 30 in the portion that will become the second circuit 22. This protects the end 201 and side surface 203 of the circuit intermediate body 20. Note that the end 202 of the circuit intermediate body 20, on which the second etching resist 50 is not provided, is protected by the insulating resin 30. This step is referred to as the fourth step.

[0051] As shown in Fig. 4(B), half etching is performed with the end 201 and side surface 203 of the circuit intermediate body 20 protected by the second etching resist 50 and the insulating resin 30, and with the side surface 203 of the circuit intermediate body 20 protected by the insulating resin 30. Then, a space 501 is provided, thereby completing the first circuit 21 and the second circuit 22. Note that etching of the end 202 from the side surface 203 is prevented, and the height of the end 201 is reduced, forming a top protrusion 212. This step is referred to as the fifth step.

[0052] 4(C), the second etching resist 50 is removed, and the space 501 is filled with the insulating resin 31. Then, the top portion 211 of the first circuit is filled. This step is called the sixth step. Although not shown, the sixth step may include a surface preparation process (step) for making the top portion 221 of the second circuit 22 (interlayer circuit), the surface of the insulating resin 30, and the surface of the insulating resin 31 into one flat surface (the same plane) without any steps.

[0053] Through the above steps, the circuit layer 4 is completed. Thereafter, the substrate 1A is subjected to necessary surface treatment such as solder resist, and the substrate 1A having the circuit layer 4 and the base material 5 is completed.

[0054] After the circuit layer 4, for example, a step of providing an electrolytic conductor by plating over the entire top portion 221 of the second circuit (interlayer circuit), the surface of the insulating resin 30, and the surface of the insulating resin 31 may be performed, and the necessary circuits may be formed using the electrolytic conductor. Specifically, as shown in Fig. 5(A), a substrate 5' may be formed including the circuit layer 4 and substrate 5 manufactured in the first to sixth steps, a new conductor 60 may be provided, and the first to sixth steps may be repeated to form a third circuit 21' (corresponding to the first circuit) and a fourth circuit 22' (corresponding to the second circuit 22) connected to the second circuit 22, thereby forming a substrate 1A in which a plurality of circuit layers 4 and circuit layers 4' are stacked. In this case, a connection surface 300 between the insulating resins, which has no connection surface in the thickness direction and extends in the planar direction, is formed between the insulating resins 30 and 30' or between the insulating resins 31 and 30'. Furthermore, a connection surface 60A between the conductors, which has no connection surface in the thickness direction and extends in the planar direction, is formed between the second circuit 22 and the third circuit 21'. The connection surface 300 between the insulating resins and the connection surface 60A between the conductors exist on the same plane without any steps. In a cross section in the plate thickness direction of a portion where the second circuit 22 and the third circuit 21' are adjacently overlapped, the width of the bottom of the third circuit 21' is preferably larger than the width of the top portion 221 of the second circuit 22. This can prevent the end of the top portion 221 of the second circuit 22 from being excessively etched.

[0055] 4(A) in the present embodiment, the case where the second etching resist 50 is provided across the surface of the circuit intermediate body 20 and the insulating resin 30 in the portion that will become the second circuit 22 has been exemplified, but as shown in FIG. 5(B), there is also a case where the second etching resist 50 is provided only on the surface of the circuit intermediate body 20 in the portion that will become the second circuit 22. Even in this case, since the side surface 203 of the circuit intermediate body 20 is covered with the insulating resin 30, it is possible to prevent etching from the side surface, and it is still possible to obtain the effect of suppressing excessive etching.

[0056] [Second embodiment] A second embodiment of the present invention will now be described with reference to FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. The present invention differs from the first embodiment in that a connection surface 23 between the conductors is provided between the first circuit 21 and the second circuit 22 of the circuit body 2B. Another difference from the first embodiment is that there is a connecting surface 301 between insulating resins 30B and 31B, which has no connecting surface in the thickness direction but has a connecting surface in the planar direction.

[0057] <Circuit body> The circuit body 2B has a connection surface 23 between the conductors between the first circuit 21 and the second circuit 22. The connection surface 23 between the conductors is a connection surface that does not extend in the thickness direction and extends in the planar direction. The circuit body 2B includes a first circuit 21 and a second circuit 22. The circuit body 2B is formed from a conductor, and is formed from a rolled conductor or an electrolytic conductor. The circuit body 2B may be either a circuit through which electricity flows and / or a circuit through which heat flows. <Insulator> The insulator 3B includes an insulating resin 30B and an insulating resin 31B. The insulating resin 30B and the insulating resin 31B may be made of the same material or different materials as long as they do not conduct electricity. The insulating resin 30B and the insulating resin 31B have a joint surface 301. The joint surface 301 between the insulating resins is a joint surface that does not extend in the thickness direction and extends in the planar direction. Furthermore, the connection surface 301 between the insulating resins and the connection surface 23 between the conductors are on the same plane without any steps.

[0058] In this embodiment, as shown in FIG. 7(B), the case where the width W2 of the top portion 211 is equal to the width W3 of the bottom portion 222 and the first circuit 21 and the second circuit 22 form a single trapezoid is illustrated. However, as shown in FIGS. 8(A) and (B), depending on the circuit design, the width W2 of the top portion 211 may be smaller than the width W3 of the bottom portion 222 (W2 < W3), or the width W2 of the top portion 211 may be larger than the width W3 of the bottom portion 222 (W2 > W3).

[0059] (Regarding the manufacturing method of the substrate) Referring to FIG. 9, the manufacturing method of the substrate 1 of the second embodiment will be described.

[0060] First, as shown in FIG. 9(A), a conductor 60 is provided on the entire surface of a base material 5. The conductor 60 corresponds to the first conductor and may be either a rolled conductor or a conductor formed by plating treatment. A first etching resist 40 that covers the surface of the conductor 60 is provided at a portion that will become the first circuit 21. This step is referred to as the seventh step.

[0061] As shown in FIG. 9(B), an etching process is performed to provide the first circuit 21. As a result, a part of the base material 5 is exposed, and a space 402 from which the conductor 60 has been removed is provided. This step is referred to as the eighth step.

[0062] As shown in FIG. 9(C), the first etching resist 40 is removed, and the insulating resin 30B is filled in the space 402 provided after etching. Then, the surface of the first circuit 21 is exposed, and the side surface 214 of the first circuit 21 and the surface of the base material 5 are covered with the insulating resin 30B. This step is referred to as the ninth step. Although not shown in the figure, the ninth step may include a planarization process (step) in which the surface of the first circuit 21 and the surface of the insulating resin 30B form a single flat surface (same plane) without a step. By this planarization process, the surface of the first circuit 21 and the surface of the insulating resin 30B become flat surfaces without a step.

[0063] As shown in Fig. 10(A), a plating process is performed to provide a conductor 61, which is an electrolytic conductor, across the surface of the first circuit 21 and the surface of the insulating resin 30B. The conductor 61 corresponds to the second conductor. This process results in a state where there is no connection surface in the thickness direction between the first circuit 21 and the conductor 61, but a connection surface extending in the planar direction. This process is referred to as the tenth process.

[0064] 10(B), a second etching resist 50 is provided on the portion that will become the second circuit 22. At this time, the second etching resist 50 is arranged so as to cover the end 217 of the first circuit 21 with the conductor 61 interposed therebetween. This step is referred to as an eleventh step.

[0065] As shown in FIG. 10(C), the etching process is performed in a state where the end 217 of the first circuit 21 is arranged so as to be covered with the second etching resist 50 with the conductor 61 interposed therebetween and the side surface 214 of the first circuit 21 is protected by the insulating resin 30B. Furthermore, the etching process is performed in a state where the top portion 211 of the first circuit 21 is positioned without being covered by the second etching resist 50 with the conductor 61 interposed therebetween and the side surface 214 of the first circuit 21 is protected by the insulating resin 30B. Then, the side surface 223 of the second circuit 22, the surface of the insulating resin 30B, and the surface (top portion 211) of the first circuit 21 are exposed, and the first circuit 21 and the second circuit 22 are provided. Furthermore, the top protrusion 212 of the first circuit 21 is formed, and the top protrusion 212 is positioned lower than the surface of the insulating resin 30B. Furthermore, a space 501 is provided where the conductor 61 has been removed by etching. Furthermore, a connection surface 23 between the conductors is present. This step is referred to as the twelfth step.

[0066] 11(A), insulating resin 31B is filled into space 501, thereby filling top portion 211 of first circuit 21 and side surface 223 of second circuit 22. This step also provides connection surface 301 between insulating resin 30B and insulating resin 31B, so that connection surface 301 between insulating resins and connection surface 23 between conductors are flush with each other. This step is referred to as the thirteenth step. Although not shown, the thirteenth step may include a surface preparation process (step) for making the top portion 221 of the second circuit 22 (interlayer circuit 22) and the surface of the insulating resin 31B into one flat surface (the same plane) without any steps.

[0067] Through the above steps, the circuit layer 4B is completed. Thereafter, the substrate 1B is subjected to necessary surface treatment such as solder resist, and the substrate 1B including the circuit layer 4B and the base material 5 is completed.

[0068] In this embodiment, insulating resin 30B is filled in after the first circuit 21 is formed. Then, by providing an electrolytic conductor and then providing a second circuit 22, the circuit width (W4) can be made smaller relative to the height (thickness) of the electrolytic conductor, making it easier to make the circuit thinner and increasing the degree of freedom in design.

[0069] After the circuit layer 4B, a process may be performed in which an electrolytic conductor is provided over the entire top portion 221 of the second circuit (interlayer circuit) and the surface of the insulating resin 31B by plating, and the necessary circuits may be formed using the electrolytic conductor. Specifically, as shown in Fig. 11(B), a substrate 5' may be formed by including the circuit layer 4B manufactured in the seventh to thirteenth steps of this embodiment and the substrate 5, and a new conductor 60 may be provided, and the seventh to thirteenth steps may be performed again to form a third circuit 21' (corresponding to the first circuit) and a fourth circuit 22' (corresponding to the second circuit 22) connected to the second circuit 22, thereby forming a substrate 1B in which a plurality of circuit layers 4B and circuit layers 4B' are stacked.

[0070] In this case, a connection surface 301A between the second insulating resins, which has no connection surface in the plate thickness direction and extends in the planar direction, is formed between insulating resin 31B and insulating resin 30B'. In other words, a connection surface 301A between the second insulating resins, which is different from connection surface 301 between the insulating resins, is formed. Furthermore, a connection surface 23A between conductors that has no connection surface in the plate thickness direction and extends in the planar direction is formed between second circuit 22 and third circuit 21'. In other words, a connection surface 23A between conductors other than connection surface 23 between conductors is formed. The connection surface 301A between the insulating resins and the connection surface 23A between the conductors are on the same plane without any steps. In a cross section in the plate thickness direction of a portion where the second circuit 22 and the third circuit 21' are adjacently overlapped, the width of the bottom of the third circuit 21' is preferably larger than the width of the top portion 221 of the second circuit 22. This can prevent the end of the top portion 221 of the second circuit 22 from being excessively etched.

[0071] 10(B), the present embodiment has been exemplified by providing the second etching resist 50 on the portion that will become the second circuit 22. However, as shown in FIG. 11(C), the second etching resist 50 may be provided so as to cover only the central portion of the first circuit 21 without covering the end portion 217 of the first circuit 21 with the conductor 61 interposed therebetween. Even in this case, the side surface 214 of the first circuit 21 is covered with the insulating resin 30B, so that etching from the side surface can be prevented, and the effect of suppressing excessive etching can still be obtained.

[0072] [Third embodiment] A third embodiment of the present invention will be described with reference to FIGS. The same components as those in the first and second embodiments are denoted by the same reference numerals, and the description thereof will be omitted. The present invention differs from the first and second embodiments in that a protective coating 7 is provided on the top portion 211 of the first circuit 21. (substrate) The substrate 1C of the present invention has a circuit layer 4C including a circuit body 2C, an insulator 3, and a protective coating . The substrate 1C of the present invention has a circuit layer 4C and a base material 5, which are stacked one on top of the other.

[0073] <Circuit body> The circuit body 2C includes a first circuit 21C and a second circuit 22C. The circuit body 2C is formed from a conductor, and is formed from a rolled conductor or an electrolytic conductor. The circuit body 2C may be either a circuit through which electricity flows and / or a circuit through which heat flows. The first circuit 21C is a planar circuit extending in the direction of the XY axis plane, and the second circuit 22C is an interlayer circuit extending in the direction of the thickness of the substrate on the Z axis. The circuit body 2C has a connection surface 23C between the conductors between the first circuit 21C and the second circuit 22C. The connection surface 23C between the conductors is a connection surface that does not extend in the thickness direction and extends in the planar direction.

[0074] <First Circuit> The planar circuit of the first circuit 21C has a top portion 211C and a top corner portion 216 of the planar circuit. The top portion 211C is a flat surface, and is formed so as to be flush with a connection surface 23C between conductors and a connection surface 301C between insulating resins, which will be described later. Top corners 216 are corners where insulating resin 30C and protective coating 7 come into contact, and are boundary portions positioned so as to surround center portion 25 of the planar circuit when viewed from the plane of the substrate (in the XY axis directions). Furthermore, the side surface 214C of the planar circuit that comes into contact with the insulating resin 30C forms a gently sloping surface that widens toward the bottom 215 of the first circuit 21C.

[0075] As shown in Figure 13(A), in the portion of the first circuit 21 where the first circuit 21C and the second circuit 22C are not overlapped, the cross section of the planar circuit when cut perpendicular to the direction extending in the planar direction of the planar circuit that is the first circuit 21C is trapezoidal. The width W1C of the bottom 215C of the first circuit 21C is larger than the width W2C of the top 211C of the first circuit 21C.

[0076] ≪Second Circuit≫ The interlayer circuit of the second circuit 22C has a top 221C of the interlayer circuit with a flat surface flush with the insulating resin 31C. Also, the bottom 222C of the interlayer circuit of the second circuit 22C corresponds to the portion connected to the top 211C of the first circuit 21C. The side surface 223C of the interlayer circuit in contact with the insulating resin 31C forms a gentle inclined surface that spreads toward the bottom 222C of the interlayer circuit. The structure of this inclined surface is a shape realized by using the method for manufacturing the circuit of the substrate of the present invention, and is the result of the side surface 223C of the second circuit 22 being left without being over-etched.

[0077] In the present invention, by etching the side surface of the circuit (second circuit 22) while protecting it with the insulating resin 31C, it is possible to suppress the circuit of the first circuit 21C from becoming too thin, making it easier to shape it to a circuit width close to the design value, and having the effect of suppressing the risk of disconnection of the circuit.

[0078] As shown in FIG. 12(C), the second circuit 22C has a trapezoidal cross-section of the interlayer circuit when cut orthogonally to the direction extending in the plane direction of the planar circuit, which is the first circuit, in the portion where the first circuit 21C and the second circuit 22C are adjacent and overlapped. The width W3C of the bottom 222C of the second circuit 22C is smaller than the width W4C of the top 221C of the second circuit 22C. In the present embodiment, as shown in FIGS. 13(A) and (B), in addition to the case where the width W2 of the top 211C is equal to the width W3 of the bottom 222C, although not shown, depending on the circuit design, there may also be cases where the width W2 of the top 211C is smaller than the width W3 of the bottom 222C (W2 < W3) or the width W2 of the top 211C is larger than the width W3 of the bottom 222C (W2 > W3).

[0079] 〈Insulator〉 The insulator 3C includes an insulating resin 30C and an insulating resin 31C. The insulating resin 30C and the insulating resin 31C may be made of the same material or different materials as long as they do not conduct electricity. Insulating resin 30C and insulating resin 31C have connecting surface 301C between the insulating resins, which is a connecting surface that does not extend in the thickness direction and extends in the planar direction. Furthermore, connection surface 301C between the insulating resins and connection surface 23C between the conductors are on the same plane and are arranged in a flat state without any steps.

[0080] <Insulating resin 30C> The insulating resin 30C is disposed so as to contact the side surface 214C of the first circuit 21C and the substrate 5. The insulating resin 30C is disposed so as to cover the side surface 214C of the first circuit 21C, and also serves to protect the side surface of the circuit from the etching solution during the manufacturing process of the circuit.

[0081] <Insulating resin 31C> Insulating resin 31C is arranged so as to be in contact with side surface 223C of second circuit 22C, the surface of protective coating 7, and the surface of substrate 5. Insulating resin 31C is filled into space 501 after etching in a state in which the side surface of first circuit 21, which will be described later, is covered with insulating resin 30C.

[0082] <Protective film> Protective coating 7 is disposed so as to cover a portion of the surface of first circuit 21C and the surface of insulating resin 30C. In other words, protective coating 7 is disposed so as to cover the portion that will become the planar circuit but not the portion that will form second circuit 22C. The protective coating 7 is used to protect the conductors of the top portion 221C and top corner portion 216 of the first circuit 21C from the etching solution during the etching process, and to not affect the formation of the electrolytic conductor 62 when the electrolytic conductor 62 that forms the base of the second circuit 22C is provided by the plating process. Specifically, a material having insulating properties can be used, for example, the same material as the insulating resin 30C and / or the insulating resin 31C can be used. Moreover, protective coating 7 has a connection surface with insulating resin 30C.

[0083] The protective coating 7 is preferably provided with a height (thickness) in the plate thickness direction that is lower than the second circuit 22C, and is preferably of the minimum height that can protect the first circuit 21C from the etching solution. By making the protective coating 7 low in height, when forming the electrolytic conductor 62 that is the basis of the second circuit 22C by plating, the step corresponding to the thickness of the protective coating 7 can be minimized, making it easier for the plating solution to come into contact with the electrolytic conductor 62, and making it easier to form an electrolytic conductor 62 in good condition.

[0084] The protective coating 7 may be disposed so as to cover the first circuit 21C and the insulating resin 30C without being disposed on the portion that will become the second circuit 22C, or may be disposed entirely and then removed by cutting from the portion that will become the second circuit 22C. The protective coating 7 is preferably disposed using a dispenser, inkjet printing, or screen printing. If the protective coating 7 is disposed entirely and then removed by cutting, there is a risk that the protective coating 7 may be removed so as to recess the surface of the first circuit 21 into the conductor, creating a step that may prevent the plating process from being performed in a satisfactory state. On the other hand, if the protective coating 7 is disposed using a dispenser, inkjet printing, or screen printing, it is preferable because it is disposed so as to cover a portion of the first circuit 21C and the insulating resin 30C, and is easily disposed so as not to cover the portion that will become the second circuit 22C.

[0085] Furthermore, a portion of the protective coating 7 preferably has an indented portion 71 formed so as to indent the interior of the second circuit 22C. By having the indented portion 71, the height in the plate thickness direction of the entire planar circuit of the first circuit 21C becomes constant. In other words, unlike the top portion 221 of the first embodiment, the etching process does not cause the first circuit 21C to curve inward, so the height of the planar circuit becomes constant throughout, making it easier to control the height of the planar circuit.

[0086] (Regarding substrate manufacturing methods) A method for manufacturing the substrate 1C of the third embodiment will be described with reference to FIG. 14(A), the same steps (seventh and eighth steps) as those of the second embodiment shown in FIGS. 9A and 9B are performed, and a first circuit 21C and an insulating resin 30C are provided on the surface of the substrate 5. This step is referred to as a fourteenth step.

[0087] Next, as shown in Fig. 14(B), a protective coating 7 is provided on the surface of the first circuit 21C. The protective coating 7 is provided across the surface of the first circuit 21C and the surface of the insulating resin 30C. This step is referred to as the fifteenth step.

[0088] As shown in Fig. 14(C), similar to Fig. 10(A) of the second embodiment, a conductor 61, which is a second conductor, is provided on the surface of the first circuit 21, the surface of the insulating resin 30C, and the surface of the protective coating 7. This step results in a state where there is no connection surface in the thickness direction between the first circuit 21 and the conductor 61, but a connection surface extending in the planar direction. This step is referred to as the sixteenth step.

[0089] Next, as shown in Fig. 15(A), similar to Fig. 10(B) of the second embodiment, a second etching resist 50 is provided on the surface of the second conductor. At this time, the second etching resist 50 is provided over the portion that will become the second circuit 22C, the insulating resin 30C, and the protective coating 7 with the second conductor 61 interposed therebetween. Furthermore, the second etching resist 50 is arranged so as to cover a portion of the upper part of the protective coating 7 with the second conductor 61 interposed therebetween. This step is referred to as the seventeenth step.

[0090] 10(C) of the second embodiment, an etching process is performed in a state in which the side and surface (top portion 221C) of the first circuit 21C are protected by the insulating resin 30C and the protective coating 7, and the side 214C of the first circuit 21C is protected by the insulating resin 30C. Then, the side 223C of the second circuit 22C, the surface of the insulating resin 30C, and the surface of the protective coating 7 are exposed, and the first circuit 21C and the second circuit 22C are formed. This step is referred to as the eighteenth step. In this case, the protective coating 7 protects the surface (edges and top portion 211) of the first circuit 21C, so that the first circuit 21C is not etched and the etching process can be performed while maintaining the height (thickness of the circuit) of the first circuit 21C throughout, which has the effect of improving the accuracy of the circuit height. Furthermore, by providing the second etching resist 50 so that the protective coating 7 penetrates into the second circuit 22C, excessive etching can be suppressed at the connection portion between the first circuit 21C and the second circuit 22C. Also, a space 501 is formed by removing the conductor 61 by etching. This results in a state where a connection surface 23C between the conductors that extends in the planar direction and has no connection surface in the plate thickness direction exists between the first circuit 21C and the second circuit 22C.

[0091] 15(C), similarly to FIG. 11(A) of the second embodiment, insulating resin 31C is filled into space 501, and protective coating 7 and side surface 223C of second circuit 22C are buried. This step is referred to as the nineteenth step. Furthermore, this process creates a connection surface 301 between the insulating resins 30C and 31C, so that the connection surface 301C between the insulating resins and the connection surface 23C between the conductors are on the same plane without any steps. Although not shown, the nineteenth step may include a process (step) of leveling the surface of the top portion 221C of the second circuit 22 (interlayer circuit 22) and the surface of the insulating resin 31C.

[0092] Through the above steps, the circuit layer 4C is completed. Thereafter, the substrate 1 is subjected to necessary surface treatment such as solder resist, and is completed as the substrate 1C.

[0093] In this embodiment, after the first circuit 21C is formed, the insulating resin 30C is filled in. Then, by providing an electrolytic conductor and then providing a second circuit 22C, the circuit width (W4) can be made smaller relative to the height (thickness) of the electrolytic conductor, which makes it easier to make the circuit thinner and increases the degree of freedom in design.

[0094] After the circuit layer 4C, for example, an electrolytic conductor may be provided by plating over the entire surface of the top portion 221C of the second circuit (interlayer circuit) and the surface of the insulating resin 31C to form the necessary circuits. Specifically, as shown in Fig. 16(A), a substrate 5' may be formed by including the circuit layer 4C and the substrate 5 manufactured in the fourteenth to nineteenth steps of this embodiment, and a new conductor 60 may be provided thereon. The fourteenth to nineteenth steps may be performed again to form a third circuit 21C' (corresponding to the first circuit) and a fourth circuit 22C' (corresponding to the second circuit 22) connected to the second circuit 22, thereby forming a substrate 1C in which a plurality of circuit layers 4C (4C') are stacked. In this case, a connection surface 301C1 between the second insulating resins, which has no connection surface in the plate thickness direction and extends in the planar direction, is formed between insulating resin 31C and insulating resin 30C'. In other words, a connection surface 301C1 between the second insulating resins, which is different from connection surface 301 between the insulating resins, is formed. Furthermore, a connection surface 23C1 between conductors that has no connection surface in the plate thickness direction and extends in the planar direction is formed between second circuit 22C and third circuit 21'C. In other words, a connection surface 23C1 between conductors other than connection surface 23C between conductors is formed. The connection surface 301C1 between the insulating resins and the connection surface 23C1 between the conductors are on the same plane without any steps. In a cross section of the portion where the second circuit 22C and the third circuit 21C' are adjacently superimposed, the width of the bottom of the third circuit 21C' is preferably larger than the width of the top portion 221C of the second circuit 22C, which can prevent the end of the top portion 221C of the second circuit 22C from being excessively etched.

[0095] In this embodiment, the fifteenth step in FIG. 14(B) illustrates a case where the protective coating 7 is not placed at the location where the second circuit 22C is to be formed using a dispenser, inkjet printing, or screen printing. However, instead of the fifteenth step, a twentieth step may be performed in which a protective coating 7 is applied to the entire surface of the first circuit 21C, as shown in Figure 16(B), and a twenty-first step may be performed in which the protective coating 7 in the portion that will become the second circuit 22C is removed by cutting to expose the surface of the first circuit 21C, as shown in Figure 16(C).

[0096] [Fourth embodiment] A fourth embodiment of the present invention will now be described with reference to FIG. The same components as those in the first to third embodiments are denoted by the same reference numerals, and the description thereof will be omitted. The substrate 1D of this embodiment differs from the other embodiments in that it uses a rolled conductor, includes a lower circuit 80 as a base material 5D, and is connected to the circuit body 2 of the first embodiment and is provided with a reinforcing structure 29. Furthermore, this embodiment is an embodiment in which the circuit body 2C of the third embodiment is connected to the circuit body 2 of the first embodiment.

[0097] (substrate) The substrate 1D of the present invention comprises a circuit body 2 of the first embodiment, an insulator 3, and a reinforcing structure 29 on a base material 5D including an underlying circuit 80. It further comprises a circuit layer 4C including a circuit body 2C of the third embodiment, an insulator 3, and a protective coating 7, which are laminated together. <Circuit body> The circuit body 2D of this embodiment includes the first circuit 21 and the second circuit 22 of the first embodiment. Note that parts with the same structure are given the same reference numerals and descriptions thereof will be omitted.

[0098] <Reinforcement structure> The reinforcing structure 29 is formed from the same conductor as the first circuit 21, and is formed from a rolled conductor that is a plate-shaped rolled plate. 17(B), the reinforcing structure 29 may be formed of a mesh-like or solid conductor (not shown), but a mesh-like structure is preferable because it can reduce the weight of the substrate 1D while suppressing warpage of the substrate compared to a solid structure. From the viewpoint of improving the heat dissipation effect, a solid structure is preferable to a mesh-like structure.

[0099] The reinforcing structure 29 is arranged to increase the rigidity of the substrate 1D. Another function is that by arranging the reinforcing structure 29 to surround the first circuits 21 in a connected state, heat from the first circuits 21 can be evenly absorbed from the surroundings via the insulating resin 30, suppressing thermal expansion of the first circuits 21 and circuits connected to the first circuits 21 and suppressing warping of the substrate 1D. The reinforcing structure 29 also serves to lower the temperature of electronic components connected to the first circuits 21.

[0100] 17(B), the reinforcing structure 29 is disposed in the same plane as the first circuit 21 and separated in the planar direction by the insulating resin 30. Also, as shown in FIG. 17(A), the insulating resin 31 and the insulating resin 35 of the base material 5D are disposed on the front and back surfaces of the reinforcing structure 29, and the reinforcing structure 29 is disposed so as not to be connected to other circuits. As shown in FIG. 22, by arranging a reinforcing structure 29 on the end face of the substrate 1D so as to surround the periphery of the substrate 1D and expose it, the heat dissipation effect can be further improved. <Base material> The base material 5D has the lower circuit 80 and insulating resin 35, and supports the first circuit 21 and the second circuit 22. The lower circuit 80 is connected to the bottom 215 of the planar circuit of the first circuit 21. There is no connecting surface between the lower circuit 80 and the first circuit 21 in the thickness direction or the planar direction, and the lower circuit 80 and the first circuit 21 are formed of an integral conductor from the same rolled plate as the first circuit 21.

[0101] (Regarding substrate manufacturing methods) A method for manufacturing the substrate 1D of the first embodiment will be described with reference to FIG. 19(A), a lower etching resist 81 is provided on the back surface of the plate-shaped rolled conductor 65 in a portion that will become the lower circuit 80. This step is referred to as the twenty-second step.

[0102] Next, the conductor 65 is half-etched to form the space 810 and the underlying circuit 80. This step is designated as the twenty-third step.

[0103] The space 810 is filled with insulating resin 35, and the lower etching resist 81 is removed. As a result, a substrate 5D is completed that includes the lower circuit 80 and insulating resin 35. This step is referred to as the twenty-fourth step. The substrate 5D corresponds to the substrate 5 in the first embodiment, and the upper surface side of the conductor 65 corresponds to the conductor 60 in the first embodiment.

[0104] Next, the first to sixth steps of the first embodiment are carried out to form the circuit layer 4 shown in FIG. 21(C). 20(A), in addition to the first step, a first etching resist 40 is provided on the portion that will become the reinforcing structure 29. This step is referred to as a twenty-fifth step.

[0105] 20(B), a second etching process is performed to form the circuit intermediate body 20 and the reinforcing structure intermediate body 28. This process is referred to as the twenty-sixth process.

[0106] 20(C), the third step is performed, resulting in a state after the third step, in which the surface of the reinforcing structural intermediate 28 is exposed and the side surfaces of the reinforcing structural intermediate 28 and the surface of the base material 5 are covered with insulating resin 30. This step is referred to as the twenty-seventh step.

[0107] 21(A), the fourth step is performed. At this time, the second etching resist 50 is placed without covering the surface of the reinforcement structure intermediate body 28. This step is referred to as the twenty-eighth step.

[0108] 21(B), the fifth step is performed, resulting in the state after the fifth step, and the upper part of the reinforcement structure intermediate 28 is removed to provide a space 501, thereby forming the reinforcement structure 29. This step is referred to as the twenty-ninth step.

[0109] 21(C), the sixth step is performed, resulting in the state after the sixth step, and the insulating resin 31 is filled into the space 501 above the reinforcement structure 29, thereby burying the reinforcement structure 29. This step is referred to as the thirtieth step.

[0110] Through the above steps, the circuit layer 4 including the reinforcing structure 29 is formed.

[0111] After the circuit layer 4, for example, a step of providing an electrolytic conductor by plating over the entire top portion 221 of the second circuit (interlayer circuit) and the surface of the insulating resin 31 may be performed, and the necessary circuits may be formed using the electrolytic conductor. Specifically, as shown in FIG. 21(C), the state including the circuit layer 4 manufactured in the 25th to 30th steps of this embodiment and the substrate 5D is referred to as substrate 5D'. In this case, the first circuit 21 corresponds to the first circuit of the rolled plate made of a rolled plate, and the second circuit 22 corresponds to the second circuit of the rolled plate made of a rolled plate. By providing a new conductor 60 on the surface of the base material 5D' and performing the fourteenth to nineteenth steps of the third embodiment, the substrate 1D shown in Figure 17(A) can be manufactured. In this case, the first circuit 21C connected to the second circuit of the rolled plate corresponds to the first circuit. The second circuit 22C corresponds to the second circuit.

[0112] Furthermore, when forming the first circuit 21C, the first circuit 21C1 may be arranged with an insulating resin 31 interposed therebetween so as to cover the upper part of the reinforcing structure 29, and when forming the second circuit 22C, the second circuit 22C1 connected to the first circuit 21C1 may be arranged with an insulating resin 31 interposed therebetween so as to cover the upper part of the reinforcing structure 29. It does not matter whether the first circuit 21C1 is connected to the first circuit 21C or not, and it does not matter whether the second circuit 22C1 is connected to the second circuit 22C or not. However, in particular, the reinforcing structure 29 can be placed with the insulating resin 31 interposed between the first circuit 21C and the second circuit 22C1. This increases the degree of freedom in circuit design, since there is no need to provide a through hole in the thickness direction of the reinforcing structure 29, compared to when a conventional through hole is used for the interlayer circuit. Furthermore, the volume of the conductor can be maintained large, which also has the effect of increasing the heat dissipation effect.

[0113] 22, the heat dissipation effect can be further improved by arranging and exposing the reinforcement structure 29 on the edge surface of the substrate 1D, but furthermore, when creating the first circuit 21C1 and the second circuit 22C, connecting structures 2921 and 2922 that connect to the reinforcement structure 29 may be provided on the same plane. The connecting structures 2921 and 2922 are made of conductors and are provided for the same purpose as the reinforcement structure 29. By providing the connecting structures 2921 and 2922, the heat dissipation effect is particularly improved because they are connected to the reinforcement structure 29. The connecting structure 2921 and the connecting structure 2922 may be disposed inside the substrate 1D, and the heat dissipation effect can be particularly improved when they are disposed on the end surface of the substrate 1D together with the reinforcing structure 29 as shown in Fig. 22. The reinforcing structure 29 may be disposed inside the substrate 1D, and the connecting structure 2921 and the connecting structure 2922 may be disposed on the end surface of the substrate 1D. The connecting structure 2921 and the connecting structure 2922 can be created by providing an etching resist on the parts that will become the connecting structure 2921 and the connecting structure 2922 when providing an etching resist for creating the first circuit 21C1 and the second circuit 22C. Furthermore, in the twenty-eighth step, the surface of the reinforcement structure intermediate 28 is covered with the etching resist 50, and then the twenty-ninth step is performed, whereby the reinforcement structure 29 can be produced without creating the space 501. In other words, the reinforcement structure 29 can be produced without the insulating resin 31 being interposed, and the reinforcement structure 29 can be connected to the connecting structure 2921 and the connecting structure 2922 without the insulating resin 31 being interposed.

[0114] In this embodiment, the case where the steps from the 25th step including the 1st step to the 30th step including the 6th step of the first embodiment are performed on the substrate 5D, and then the 25th step to the 30th step of the third embodiment are performed has been exemplified, but the 14th step to the 19th step of the second embodiment may be performed instead of the third embodiment. Also, the third embodiment and / or the second embodiment may be performed multiple times to form a multilayer substrate 1D.

[0115] In the present invention, a multilayer substrate can be formed by repeatedly stacking the first to third embodiments, and it may be either a case where the same embodiment is repeated for a substrate, or a case where multiple types of the first to third embodiments are combined and repeated multiple times. Specifically, an example is a case in which the state after the first embodiment is used as a substrate, a step of providing a first conductor on the surface of the substrate by plating, and then the second embodiment and / or the third embodiment are carried out.

[0116] In the present invention, the first circuit is a planar circuit and the second circuit is an interlayer circuit, but the first circuit may be an interlayer circuit. In other words, the present invention is also applicable to a case where the interlayer circuit of the first circuit and the interlayer circuit of the second circuit are adjacently superimposed.

[0117] The conductor in the present invention includes a rolled conductor in the form of a rolled plate and an electrolytic conductor obtained by plating. A rolled conductor is a conductor produced by inserting an ingot of raw conductor between two rotating rolls, and stretching the ingot while crushing it to a desired thickness. Specifically, this applies to rolled copper sheets or rolled aluminum sheets. Note that the present invention is not limited to rolled sheets, and rolled copper ingots or rolled aluminum ingots can also be used.

[0118] The electrolytic conductor is not particularly limited as long as it is a conductor produced by plating, but a specific example is copper plating.

[0119] A rolled conductor has a layered metal structure that extends in the direction of rolling (in the case of a plate-shaped conductor, in the plane (XY axis) direction of the substrate). In addition, heat treatment during the substrate production process results in crystal grains that are close to equiaxed. On the other hand, electrolytic conductors formed by plating are characterized by a columnar metal structure in the thickness direction (Z-axis direction). The rolled conductor and the electrolytic conductor have differences in these characteristics. Therefore, even though they are made of the same material, the rolled conductor has the effect of improving the rigidity of the substrate more than the electrolytic conductor due to these differences in characteristics. Therefore, a rolled conductor is preferably applied to the reinforcing structure 29 of the fourth embodiment of the present invention.

[0120] By mounting electronic components on the substrates 1A to 1D of the present invention, electronic devices can be provided that include the substrates 1A to 1D. Furthermore, with the substrate 1D of the present invention, a reinforcing structure made of a rolled plate is provided on the same plane as the first circuit 21, thereby making it possible to provide an electronic device with improved rigidity of the substrate. The conductors constituting the circuit of the substrate of the present invention are made of rolled conductors and / or conductors prepared by plating. The conductors are not particularly limited as long as they are made of a material that allows electricity to flow more easily than an insulator.

[0121] The electrolytic conductor is not particularly limited as long as it is a conductor produced by plating, but a specific example is copper plating.

[0122] In this specification, insulating resins 30, 30B and 30C correspond to the first insulating resin, insulating resins 31, 31B and 31C correspond to the second insulating resin, insulating resin 30' corresponds to the third insulating resin, and insulating resin 35 corresponds to the fourth insulating resin. [Industrial Applicability]

[0123] The electronic device of the present invention is an electronic device equipped with the substrate of the present invention, and its uses are not particularly limited, but examples include electronic devices for the space industry, automobiles, aircraft, unmanned aerial vehicles, mobile phones, smartphones, personal computers, LED modules, power semiconductor modules, etc. Since this electronic device uses a substrate with a controlled circuit width, it can be an electronic device that is less likely to suffer from connection defects. [Explanation of symbols]

[0124] 1A, 1B, 1C, 1D are substrates, 2, 2B, 2C, 2D are circuit bodies, 3, 3B, 3C are insulators, 4, 4B, 4C are circuit layers, 5, 5D are base materials, 7 is a protective coating, 20 is a circuit intermediate body, 21, 21C, 21C1 are a first circuit, 21' is a third circuit, 22, 22C, 22C1 are a second circuit, 22' is a fourth circuit, 23, 23A, 23C, 23C1 are connection surfaces, 25 is a central part, 28 is a reinforcing structure intermediate body, 29 is a reinforcing structure, 30, 30B, 30C are insulating resins, 31, 31B, 31C are insulating resins, 32 is a connection surface, 35 is an insulating resin, 40 is a first etching resist, 50 is a second etching resist, 60 is a conductor, 60A is a connection surface, 61 is a conductor, 62 is a second conductor, 65 is Conductor, 71 is the recessed portion, 80 is the lower circuit, 81 is the lower etching resist, 201 is the end, 202 is the end, 203 is the side, 211, 211C are the top, 212 is the top protrusion, 213 is the center, 214, 214C are the side, 215, 215C are the bottom, 216 is the top corner, 217 is the end, 221, 221C are the top, 222, 222C are Bottom, 223, 223C are side surfaces, 225 is a virtual line, 301 is a connection surface, 301A is a connection surface, 301C is a connection surface, 301C1 is a connection surface, 305 is a lateral protrusion, 401 is a space, 402 is a space, 501 is a space, 810 is a space, 910 is a substrate, 921 is a planar circuit, 924 is an end, 925 is a bottom, 926 is a bottom, 927 is an end, and 930 is an insulating resin.

Claims

1. a seventh step of providing a first etching resist covering a surface of the first conductor in a portion that will become a first circuit; an eighth step in which the first conductor is etched to provide a first circuit; a ninth step of filling a space formed after etching with a first insulating resin; a tenth step of providing a second conductor across a surface of the first circuit and a surface of the first insulating resin; an eleventh step of providing a second etching resist on the surface of the second conductor; a twelfth step in which a side surface of the first conductor is etched while being protected by the first insulating resin, to provide a second circuit connected to the first circuit; A method for manufacturing a substrate, comprising:

2. 2. The method for manufacturing a substrate according to claim 1, wherein the second etching resist in the eleventh step is provided across the upper surface of the first circuit and the upper surface of the first insulating resin, with the second conductor interposed therebetween.

3. a seventh step of providing a first etching resist covering a surface of the first conductor in a portion that will become a first circuit; an eighth step in which the first conductor is etched to provide a first circuit; a fourteenth step of filling a space formed after etching with a first insulating resin; a fifteenth step in which a protective coating is provided on a surface of the first circuit; a sixteenth step of providing a second conductor over a surface of the first circuit, a surface of the first insulating resin, and a surface of the protective coating; a seventeenth step of providing a second etching resist on the surface of the second conductor; an eighteenth step in which a side surface and a surface of the first conductor are etched while being protected by the first insulating resin and the protective coating, thereby providing a second circuit connected to the first circuit; A method for manufacturing a substrate, comprising:

4. 4. The method for manufacturing a substrate according to claim 3, wherein the second etching resist in the seventeenth step is provided across an upper surface of the protective coating and an upper surface of the first insulating resin, with the second conductor interposed therebetween.

5. A substrate having a first circuit, a second circuit, and an insulator, In a cross section of a portion where the first circuit and the second circuit are adjacently superimposed, a width of a bottom portion of the first circuit located on a central side in a thickness direction of the substrate is larger than a width of a top portion of the first circuit located on a surface side in the thickness direction of the substrate; the first circuit and the second circuit have a connection surface between conductors between a top portion of the first circuit and a bottom portion of the second circuit; A substrate characterized in that the connection surfaces between the conductors are arranged so that there are connection surfaces of conductors extending in a planar direction and there are no connection surfaces of conductors extending in a thickness direction of the board.

6. the insulator has a connection surface between an insulating resin of a first circuit that contacts a side surface of the first circuit and an insulating resin of a second circuit that contacts a side surface of the second circuit, The connection surfaces of the insulating resins are formed by connecting the insulating resins in a plane direction.

6. The substrate according to claim 5, wherein the connection surfaces between the conductors and the connection surfaces between the insulating resins are flush with each other without any steps.

7. 7. The substrate according to claim 5, wherein a protective coating is provided on the surface of the first circuit, and the protective coating has a height lower than that of the second circuit.

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