Quantum bit device and method of manufacturing the same

Abstract

In a quantum bit device having a coupling line for forming capacitive coupling between quantum bits, leakage of a control signal to the coupling line is suppressed. [Solution] The quantum bit device includes a first quantum bit substrate having a first quantum bit, a second quantum bit, and a ground electrode extending between the first quantum bit and the second quantum bit, and a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit.

Description

[Technical Field]

[0001] The disclosed technology relates to quantum bit devices and methods for manufacturing quantum bit devices. [Background technology]

[0002] The following technologies are known as technologies related to quantum bit devices. Patent Document 1 describes a quantum processor in which a plurality of qubits formed on the surface of a substrate are arranged in a pattern. Nearest-neighbor qubits in the pattern are connected, and the quantum processor includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits. The first and second qubits are separated by at least a third qubit in the pattern.

[0003] Patent document 2 describes a quantum computing device having a first chip having a plurality of qubits arranged on a first substrate, and a second chip having at least one conductive surface arranged on a second substrate facing the plurality of qubits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2023-505418 [Patent Document 2] Special Publication No. 2022-528739 Summary of the Invention [Problem to be solved by the invention]

[0005] A known quantum bit device uses transmons as quantum bits. Transmons are configured by connecting a superconducting Josephson element and a capacitor in parallel, and perform quantum operations using nonlinear energy. In multi-bit quantum bit devices, multiple quantum bits are interconnected via capacitors.

[0006] The quantum bit device may include a substrate such as a silicon substrate, a plurality of quantum bits provided on a first surface of the substrate, and a control port provided directly below each quantum bit on a second surface of the substrate to which a control signal for controlling the state of the quantum bit is input. The quantum bit substrate is provided with a coupling line for forming capacitive coupling between the quantum bits.

[0007] In a quantum bit device having the above configuration, when controlling the state of a quantum bit, a control signal is input to a control port provided directly below the quantum bit. The control signal input to the control port may propagate inside the substrate and be transmitted to other adjacent quantum bits via the coupling lines. In other words, with a quantum bit device having the above configuration, there is a risk of crosstalk occurring, in which the control signal leaks into the coupling lines and is transmitted to an unintended quantum bit.

[0008] The disclosed technology has been made in consideration of the above points, and aims to suppress leakage of control signals to coupling lines in a quantum bit device having coupling lines for forming capacitive coupling between quantum bits. [Means for solving the problem]

[0009] A quantum bit device according to the disclosed technology includes a first quantum bit substrate having a first quantum bit, a second quantum bit, and a ground electrode extending between the first quantum bit and the second quantum bit, and a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit. [Effects of the Invention]

[0010] According to the disclosed technique, in a quantum bit device having a coupling line for forming capacitive coupling between quantum bits, it is possible to suppress leakage of a control signal to the coupling line. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram schematically illustrating an example of the configuration of a quantum bit device according to an embodiment of the disclosed technique. [Figure 2] 1 is a plan view showing an example of a layout on a first surface of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 3] 10 is a plan view showing an example of a layout on a second surface of a quantum bit substrate according to an embodiment of the disclosed technique. FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line 4-4 in FIG. [Figure 5] FIG. 10 is an equivalent circuit diagram of a calculation block according to an embodiment of the disclosed technique. [Figure 6A] FIG. 1 is a plan view illustrating an example of a configuration of a capacitor according to an embodiment of the disclosed technique. [Figure 6B] 1 is a cross-sectional view showing an example of a configuration of a capacitor according to an embodiment of the disclosed technique. [Figure 7A] 1A to 1C are cross-sectional views showing an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technology. [Figure 7B] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 7C] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 7D] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 7E] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 7F] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 7G]10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 7H] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 8A] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 8B] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 8C] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 8D] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 8E] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 9A] 10A and 10B are diagrams illustrating an example of a process for combining a quantum bit substrate and a connection substrate. [Figure 9B] 10A and 10B are diagrams illustrating an example of a process for combining a quantum bit substrate and a connection substrate. [Figure 10] FIG. 1 is a diagram schematically illustrating an example of the configuration of a quantum bit device according to a comparative example. [Figure 11] FIG. 11 is a cross-sectional view taken along line 11-11 in FIG. [Figure 12] FIG. 1 is a cross-sectional view of a quantum bit device according to an embodiment of the disclosed technique. [Figure 13] FIG. 10 is a diagram schematically illustrating an example of the configuration of a quantum bit device according to another embodiment of the disclosed technique. [Figure 14] FIG. 10 is a plan view showing an example of a layout on one surface of a connection board according to another embodiment of the disclosed technology. [Figure 15] FIG. 10 is a plan view showing an example of a layout on the other surface of a connection board according to another embodiment of the disclosed technology. [Figure 16] FIG. 16 is a cross-sectional view taken along line 16-16 in FIG. [Figure 17]This shows a cross section taken along line 17-17 in FIG. [Figure 18] FIG. 10 is a diagram schematically illustrating an example of the configuration of a quantum bit device according to another embodiment of the disclosed technique. [Figure 19] FIG. 19 is a cross-sectional view taken along line 19-19 in FIG. [Figure 20] FIG. 10 is a diagram schematically illustrating an example of the configuration of a quantum bit device according to another embodiment of the disclosed technique. [Figure 21] 21 is a cross-sectional view taken along line 21-21 in FIG. 20. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant description will be omitted.

[0013] [First embodiment] FIG. 1 is a diagram schematically illustrating an example of the configuration of a quantum bit device 100 according to an embodiment of the disclosed technique. The quantum bit device 100 includes a quantum bit substrate 10 and a connection substrate 20. These substrates are stacked such that a surface S1 of the quantum bit substrate 10 and a surface S3 of the connection substrate 20 face each other. FIG. 2 is a plan view illustrating an example of a layout on the surface S1 of the quantum bit substrate 10, and FIG. 3 is a plan view illustrating an example of a layout on the surface S3 of the connection substrate 20 facing the surface S1 of the quantum bit substrate 10. FIG. 4 is a cross-sectional view of the quantum bit device 100, showing a cross section taken along line 4-4 in FIG. 1.

[0014] The quantum bit device 100 has four quantum bits 1 provided on a quantum bit substrate 10 as basic units 70. The four quantum bits 1 constituting one basic unit 70 are arranged at positions corresponding to the four vertices of a square, with a readout port 14 located at the center of the square. One readout port 14 is shared by the four quantum bits 1. A resonator 2 and a filter 3 are provided on each path from each of the four quantum bits 1 to the readout port 14. Each quantum bit 1 is connected to an adjacent quantum bit 1 via a coupling line 22 having a capacitor 23 provided on a connection substrate 20. This forms capacitive coupling between the adjacent quantum bits. Each quantum bit 1 creates a quantum entangled state with the adjacent quantum bit 1 to perform a quantum operation.

[0015] FIG. 5 is an equivalent circuit diagram of an operation block including one quantum bit 1, one resonator 2, and one filter 3. The quantum bit 1 is an element that forms a coherent two-level system using superconductivity and performs quantum operations using nonlinear energy. The quantum bit 1 has a transmon in which a Josephson junction 4 and a capacitor 5 are connected in parallel. The Josephson junction 4 has a pair of superconductor layers that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator layer with a thickness of about several nanometers sandwiched between the pair of superconductor layers. The superconductor layer may be, for example, aluminum, and the insulator layer may be, for example, aluminum oxide.

[0016] The resonator 2 is connected to the quantum bit 1 via a capacitor 17. The resonator 2 interacts with the quantum bit 1 to read out a response signal indicating the state of the quantum bit 1. The resonator 2 has a resonant circuit in which a superconducting inductor 6 and a capacitor 7 are connected in parallel. The filter 3 is connected to the resonator 2 via a capacitor 18. The filter 3 suppresses the signal at the frequency of the quantum bit 1 from relaxing to the readout port 14. Like the resonator 2, the filter 3 has a resonant circuit in which a superconducting inductor 8 and a capacitor 9 are connected in parallel.

[0017] A control port 12, a ground port 13, and a readout port 14 are connected to the operation block. A control signal for controlling the quantum bit 1 is input to the control port 12. The state of the quantum bit 1 is controlled by the control signal input to the control port 12. A response signal indicating the state of the quantum bit 1 is read out from the readout port 14. The ground port 13 is connected to an external ground potential. The ground potential of the ground port 13 is common to the ground of each part of the operation block.

[0018] The quantum bit substrate 10 has a substrate 11 made of, for example, silicon. A quantum bit 1, a resonator 2, and a filter 3 are provided on a surface S1 of the substrate 11. A readout port 14 has a through-electrode structure that penetrates the substrate 11. A response signal output via the resonator 2 and the filter 3 is transmitted to a surface S2 of the substrate 11 opposite to the surface S1 by the readout port 14 having the through-electrode structure.

[0019] A ground electrode 19 is provided on surface S1 of substrate 11 so as to cover almost the entire area except for the areas where quantum bits 1, resonator 2, filter 3, and readout port 14 are formed. In other words, ground electrode 19 extends between two adjacent quantum bits 1. A ground potential is supplied to ground electrode 19 from the outside via ground port 13. Control ports 12 are provided directly below each quantum bit 1 on surface S2 of substrate 11. A control signal input to control port 12 acts on quantum bits 1 via substrate 11. A ground electrode 19 is also provided on surface S2 of substrate 11.

[0020] Connection substrate 20 has a base material 21 made of, for example, silicon. A plurality of bond pads 24 are provided on a surface S3 of base material 21 facing quantum bit substrate 10. The bond pads 24 are arranged to correspond to each of the quantum bits 1 provided on quantum bit substrate 10. In other words, the bond pads 24 are arranged in a lattice pattern corresponding to the arrangement of the quantum bits 1 provided on quantum bit substrate 10. Each of the bond pads 24 is connected to a corresponding quantum bit 1 via a bump 30.

[0021] A coupled line 22 is provided on the surface S3 of the connection substrate 20. The coupled line 22 has a wiring 25 and a capacitor 23 provided midway along the wiring 25. A coupling pad 24 is connected to both ends of each of the multiple coupled lines 22. All of the coupling pads 24 are connected to any other adjacent coupling pad 24 via the coupling line 22. In this embodiment, not only are adjacent coupling pads connected to each other in the lattice direction, but also adjacent coupling pads in the diagonal direction are connected to each other via the coupling line 22 (see FIG. 3). A ground electrode 26 is provided on the surface S3 of the connection substrate 20 so as to cover almost the entire area except for the areas where the coupled lines 22 and the coupling pads 24 are formed.

[0022] One end of coupling line 22 is connected to quantum bit 1A via coupling pad 24A, and the other end of coupling line 22 is connected to quantum bit 1B adjacent to quantum bit 1A via coupling pad 24B (see FIG. 4). This forms capacitive coupling between adjacent quantum bits. All quantum bits 1 provided on quantum bit substrate 10 are connected to any other adjacent quantum bit 1 via coupling line 22 provided on connection substrate 20. In this embodiment, not only quantum bits adjacent to each other in the lattice direction but also quantum bits adjacent to each other in the diagonal direction are connected to each other via coupling line 22 (see FIG. 1). Ground electrode 19 provided on quantum bit substrate 10 is positioned so as to overlap coupling line 22 in a plan view.

[0023] Capacitor 23 is provided midway along wiring 25 that constitutes coupled line 22. Capacitor 23 may be a planar capacitor having a pair of comb-shaped conductors as electrodes formed on the surface of base material 21 of connection board 20, as shown in Fig. 6A. Capacitor 23 may also be a multilayer capacitor having an MIM (Metal / Insulator / Metal) structure formed on the surface of base material 21, as shown in Fig. 6B.

[0024] The following describes a method for manufacturing the quantum bit device 100. Figures 7A to 7H are cross-sectional views showing an example of a manufacturing process for the quantum bit substrate 10.

[0025] First, a substrate 11 of the quantum bit substrate 10 is prepared. A silicon substrate with a thickness of approximately 300 μm can be used as the substrate 11 (FIG. 7A). Next, a conductive film 41 with a thickness of approximately 100 nm is formed on both sides of the substrate 11 using, for example, sputtering, plasma CVD (Chemical Vapor Deposition), or ion plating. TiN, for example, can be used as the material for the conductive film 41 (FIG. 7B). Next, a resist mask (not shown) is formed on the surface of the conductive film 41, and the conductive film 41 is patterned by partially etching the conductive film 41 through the resist mask. This results in the formation of the resonator 2, the filter 3, the ground electrode 19, and so on (FIG. 7C).

[0026] Next, quantum bit 1 is formed on the surface of substrate 11 (FIG. 7D). The superconducting Josephson element constituting quantum bit 1 is formed, for example, by the following steps: forming an Al-containing lower electrode (not shown) on the surface of substrate 11 by vapor deposition; forming an ultrathin oxide film (not shown) with a thickness of approximately several nanometers on the surface of the lower electrode using O gas; and forming an Al-containing upper electrode (not shown) on the surface of the oxide film by vapor deposition. The lower electrode and upper electrode may be patterned by, for example, a lift-off method using a patterned resist mask (not shown). In this case, the resist mask may have an opening pattern in the shape of a cross including a first linear portion along a first direction and a second linear portion along a second direction perpendicular to the first direction. The lower electrode may be formed in the portion corresponding to the first linear portion by performing vapor deposition with the first direction tilted as the rotation axis. Subsequently, the upper electrode may be formed in the portion corresponding to the second linear portion by performing vapor deposition with the second direction tilted as the rotation axis. This method allows the lower electrode and upper electrode to be patterned using a single resist mask.

[0027] Next, a protective film 42 is formed to cover the surface of the quantum bit 1, for example, by CVD. The protective film 42 can be made of, for example, SiO2. The protective film 42 is then patterned using photolithography (FIG. 7E). Next, a hard mask (not shown) with an opening is formed where the readout port 14 will be formed. Using the hard mask, a through-hole 43 is formed in the substrate 11 at the position where the readout port 14 will be formed, for example, by Deep-RIE (Reactive Ion Etching) (FIG. 7F). Next, a conductive film is formed to cover the inner wall of the through-hole 43 and the periphery of the open end of the through-hole 43, for example, by vapor deposition. Aluminum, for example, can be used as the material for the conductive film. The conductive film is then patterned, for example, by lift-off. This forms the control port 12 and the readout port 14 (FIG. 7G). Next, the protective film 42 covering the quantum bit 1 is removed by etching, for example, using vapor hydrofluoric acid (FIG. 7H). Through the above steps, the quantum bit substrate 10 is completed.

[0028] 8A to 8E are cross-sectional views showing an example of a manufacturing process for the connection substrate 20. First, a base material 21 of the connection substrate 20 is prepared. As the base material 21, for example, a silicon substrate with a thickness of about 300 μm can be used (FIG. 8A).

[0029] Next, a conductive film 50 having a thickness of approximately 100 nm is formed on the surface of the substrate 21 using, for example, sputtering, plasma CVD, or ion plating. TiN, for example, can be used as the material for the conductive film 50 (FIG. 8B). Next, a resist mask (not shown) is formed on the surface of the conductive film 50, and the conductive film 50 is patterned by partially etching the conductive film 50 through the resist mask. This forms the coupled line 22 having the wiring 25 and the capacitor 23 (FIG. 8C).

[0030] Next, a patterned resist mask (not shown) is formed on the surface of the coupled line 22. Next, a conductive film such as an Al film is formed on the surface of the coupled line 22 via the resist mask by evaporation. Next, the conductive film on the resist mask is removed together with the resist mask, thereby patterning the conductive film. This forms bond pads 24 connected to one end and the other end of the coupled line 22 (FIG. 8D). Next, bumps 30 are formed on the surface of the bond pads 24. In, for example, can be used as the material for the bumps 30 (FIG. 8E). Through the above steps, the connection substrate 20 is completed.

[0031] 9A and 9B are diagrams showing an example of a process for combining a quantum bit substrate 10 and a connection substrate 20. The quantum bit substrate 10 and connection substrate 20 are arranged so that the surface S1 on which the quantum bit 1 is formed faces the surface S3 on which the coupling line 22 and the coupling pad 24 are formed of the connection substrate 20 (FIG. 9A). Next, each of the multiple coupling pads 24 provided on the connection substrate 20 is connected to the corresponding quantum bit 1 provided on the quantum bit substrate 10 via a bump 30 (FIG. 9B). This bonds the quantum bit substrate 10 and the connection substrate 20, forming capacitive coupling between adjacent quantum bits.

[0032] FIG. 10 is a schematic diagram illustrating an example of the configuration of a quantum bit device 100X according to a comparative example. FIG. 11 is a cross-sectional view taken along line 11-11 in FIG. 10 . The quantum bit device 100X according to the comparative example does not include the connection substrate 20 included in the quantum bit device 100 according to the embodiment of the disclosed technology. In the quantum bit device 100X according to the comparative example, the coupled line 22 is provided on the surface S1 of the quantum bit substrate 10X, and the control port 12 is provided directly below each quantum bit 1 on the surface S2 of the substrate 11. To control the state of a quantum bit 1, a control signal is input via a probe 60 that is brought into contact with the control port 12 provided directly below the quantum bit 1 of interest. The control signal acts on the quantum bit 1 of interest via the substrate 11. In the quantum bit device 100X according to the comparative example, the control signal input to the control port 12 propagates through the substrate 11 and leaks to the coupled line 22, potentially resulting in crosstalk being transmitted to an unintended quantum bit 1.

[0033] On the other hand, in the quantum bit device 100 according to the embodiment of the disclosed technique, the coupled line 22 is provided on a connection substrate 20 that is different from the quantum bit substrate 10, and the ground electrode 19 is disposed at a position that overlaps with the coupled line 22 in a plan view. That is, the ground electrode 19 is disposed on the propagation path of the control signal from the control port 12 to the coupled line 22 (see FIG. 12 ). As a result, the control signal propagating inside the substrate 11 is blocked by the ground electrode 19, making it possible to suppress leakage of the control signal to the coupled line 22.

[0034] Furthermore, in the quantum bit device 100 according to the embodiment of the disclosed technique, the coupling line 22 is provided on a connection substrate 20 that is different from the quantum bit substrate 10. This allows capacitive coupling to be formed not only between quantum bits adjacent to each other in the lattice direction, but also between quantum bits adjacent to each other in the diagonal direction. This increases the number of other quantum bits connected to one quantum bit compared to the quantum bit device 100X according to the comparative example. As a result, the number of two-qubit gates that can be formed increases, thereby enabling the quantum computing processing capability of the quantum bit device to be improved.

[0035] [Second embodiment] 13 is a diagram schematically illustrating an example of the configuration of a quantum bit device 100A according to a second embodiment of the disclosed technique. The quantum bit device 100A has a quantum bit substrate 10 and a connection substrate 20A. These substrates are stacked so that the surface S1 of the quantum bit substrate 10 and the surface S3 of the connection substrate 20 face each other. The quantum bit device 100A according to the second embodiment differs from the connection substrate 20 according to the first embodiment in the configuration of the connection substrate 20A. The connection substrate 20A has coupled lines on both sides.

[0036] Fig. 14 is a plan view showing an example of a layout of a surface S3 of the connecting substrate 20A opposite to surface S1 of the quantum bit substrate 10. Fig. 15 is a plan view showing an example of a layout of a surface S4 of the connecting substrate 20A opposite to surface S3. Fig. 16 is a cross-sectional view of the quantum bit device 100A taken along line 16-16 in Fig. 13. Fig. 17 is a cross-sectional view of the quantum bit device 100A taken along line 17-17 in Fig. 13.

[0037] On surface S3 of connection substrate 20A, coupled line 22A is provided, connecting quantum bits adjacent to each other in the lattice direction, and coupled line 22B is provided, connecting quantum bits adjacent to each other in the diagonal direction. On surface S4, coupled line 22C is provided, connecting quantum bits adjacent to each other in the diagonal direction. Coupled line 22B on surface S3 and coupled line 22C on surface S4 are arranged in directions that intersect with each other. Note that coupled lines 22A and 22B are an example of a "first coupled line" in the disclosed technology. Coupled line 22C is an example of a "second coupled line" in the disclosed technology.

[0038] 17, coupling line 22C provided on surface S4 of connection substrate 20A is connected to coupling pad 24 provided on surface S3 of connection substrate 20A via through electrode 37 that penetrates base material 21 of connection substrate 20A. Coupling pad 24 is connected to quantum bit 1 provided on quantum bit substrate 10 via bump 30. Ground electrode 26 is provided on surfaces S3 and S4 of connection substrate 20 so as to cover almost the entire area except for the areas where coupling lines 22A, 22B, and 22C, coupling pad 24, and through electrode 27 are formed.

[0039] The quantum bit device 100A according to the second embodiment of the disclosed technology, like the quantum bit device 100 according to the first embodiment described above, can suppress leakage of control signals to the coupled line 22. Furthermore, the capacitive coupling between quantum bits that is not formed by the coupled lines 22A and 23B provided on the surface S3 of the connecting substrate 20A is formed by the coupled line 22C provided on the surface S4 of the connecting substrate 20A. This further increases the number of other quantum bits connected to one quantum bit 1 compared to the quantum bit device 100 according to the first embodiment. As a result, the number of two-qubit gates that can be formed is further increased, making it possible to further improve the quantum computing processing capability of the quantum bit device.

[0040] [Third embodiment] Fig. 18 is a diagram schematically illustrating an example of the configuration of a quantum bit device 100B according to a third embodiment of the disclosed technique. Fig. 19 is a cross-sectional view of the quantum bit device 100B taken along line 19-19 in Fig. 18.

[0041] In the quantum bit devices according to the first and second embodiments, the capacitor 23 for forming capacitive coupling between quantum bits is provided midway along the wiring 25 constituting the coupled line 22. In the quantum bit device 100B according to the third embodiment, a capacitor for forming capacitive coupling between quantum bits is provided at the junction between the quantum bit 1 and the coupled line 22. That is, the coupled line 22 includes a wiring 25, a capacitor 23A provided between one end of the wiring 25 and the quantum bit 1A, and a capacitor 23B provided between the other end of the wiring 25 and the quantum bit 1B. Each of the capacitors 23A and 23B has an end of the wiring 25 as one electrode, a coupling pad 24 as the other electrode, and a dielectric 28 such as Al2O3 sandwiched between these electrodes. The coupling pad 24 is connected to the quantum bits 1A and 1B via bumps 30. The capacitor 23A is an example of a "first capacitor" in the technology disclosed herein. The capacitor 23B is an example of a "second capacitor" in the technology disclosed herein. Quantum bit 1A and quantum bit 1B are connected to each other via coupling line 22, which includes capacitor 23A, wiring 25, and capacitor 23B, thereby forming capacitive coupling between quantum bit 1A and quantum bit 1B.

[0042] According to the quantum bit device 100B according to the third embodiment of the disclosed technique, it is possible to suppress leakage of the control signal to the coupled line 22, similar to the quantum bit device 100 according to the first embodiment described above.

[0043] [Fourth embodiment] Fig. 20 is a diagram schematically illustrating an example of the configuration of a quantum bit device 100C according to a fourth embodiment of the disclosed technique. Fig. 21 is a cross-sectional view of the quantum bit device 100C, taken along line 21-21 in Fig. 20.

[0044] Quantum bit device 100C includes quantum bit substrates 10A and 10B, each having a plurality of quantum bits 1. Quantum bit substrates 10A and 10B are mounted on a connection substrate 20C. Connection substrate 20C includes coupling line 22D, which forms capacitive coupling between quantum bits provided on quantum bit substrate 10A, and coupling line 22E, which forms capacitive coupling between quantum bits provided on quantum bit substrate 10B. Connection substrate 20C also includes coupling line 22F, which forms capacitive coupling between quantum bits 1 provided on quantum bit substrate 10A and quantum bits 1 provided on quantum bit substrate 10B. Quantum bit substrate 10A is an example of a "first quantum bit substrate" in the disclosed technology. Quantum bit substrate 10B is an example of a "second quantum bit substrate" in the disclosed technology.

[0045] The quantum bit device 100C according to the fourth embodiment of the disclosed technology, like the quantum bit device 100 according to the first embodiment described above, can suppress leakage of control signals to the coupled line 22. Furthermore, since it has multiple quantum bit substrates, it can increase the number of bits compared to when it has only a single quantum bit substrate. Furthermore, since capacitive coupling is formed between quantum bits provided on different quantum bit substrates, it becomes possible to handle each quantum bit 1 without being aware of the boundaries between the quantum bit substrates.

[0046] The following additional notes are disclosed regarding the first to fourth embodiments described above. (Appendix 1) a first qubit substrate having a first qubit, a second qubit, and a ground electrode extending between the first qubit and the second qubit; a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit; qubit device including

[0047] (Appendix 2) the first quantum bit substrate and the connection substrate are arranged to overlap each other; The ground electrode is disposed at a position overlapping the first coupled line in a plan view. 10. The qubit device of claim 1.

[0048] (Appendix 3) the first quantum bit substrate has a control port to which a control signal for controlling the first quantum bit is input; The ground electrode is disposed on a propagation path of the control signal from the control port to the first coupled line. 10. The quantum bit device of claim 1 or 2.

[0049] (Appendix 4) the first quantum bit and the second quantum bit are provided on one surface of the first quantum bit substrate; The control port is provided on the other surface of the first quantum bit substrate. 4. The qubit device of claim 3.

[0050] (Appendix 5) One end of the first coupled line is connected to the first quantum bit via a first pad, and the other end of the first coupled line is connected to the second quantum bit via a second pad. 5. The quantum bit device of any one of claims 1 to 4.

[0051] (Appendix 6) The first coupled line is Wiring and a capacitor provided midway along the wiring; 6. The quantum bit device of any one of claims 1 to 5, comprising:

[0052] (Appendix 7) The first coupled line is Wiring and a first capacitor provided between one end of the wiring and the first quantum bit; a second capacitor provided between the other end of the wiring and the second quantum bit; 6. The quantum bit device of any one of claims 1 to 5, comprising:

[0053] (Appendix 8) the first coupled line is provided on one surface of the connection substrate, The connection substrate has a second coupling line provided on the other surface of the connection substrate, the second coupling line forming capacitive coupling between a quantum bit other than the second quantum bit and the first quantum bit. 8. The quantum bit device of any one of claims 1 to 7.

[0054] (Appendix 9) further comprising a second qubit substrate having a plurality of qubits; The connection substrate has a coupling line that forms capacitive coupling between a quantum bit provided on the first quantum bit substrate and a quantum bit provided on the second quantum bit substrate. 9. The quantum bit device of any one of Supplementary Notes 1 to 8.

[0055] (Appendix 10) forming a first qubit substrate having a first qubit, a second qubit, and a ground electrode extending between the first qubit and the second qubit; forming a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit; combining the first quantum bit substrate with the connection substrate; A method for manufacturing a quantum bit device, comprising:

[0056] (Appendix 11) the first quantum bit substrate and the connection substrate are arranged to overlap each other; The ground electrode is disposed at a position overlapping the first coupled line in a plan view. The manufacturing method described in Appendix 10.

[0057] (Appendix 12) the first quantum bit substrate has a control port to which a control signal for controlling the first quantum bit is input; The ground electrode is disposed on a propagation path of the control signal from the control port to the first coupled line. The method of manufacturing according to claim 10 or 11.

[0058] (Appendix 13) the first quantum bit and the second quantum bit are provided on one surface of the first quantum bit substrate; The control port is provided on the other surface of the first quantum bit substrate. The manufacturing method described in Appendix 12.

[0059] (Appendix 14) the first coupled line is provided on one surface of the connection substrate, The connection substrate has a second coupling line provided on the other surface of the connection substrate, the second coupling line forming capacitive coupling between a quantum bit other than the second quantum bit and the first quantum bit. 14. The method of any one of claims 10 to 13.

[0060] (Appendix 15) forming a second qubit substrate having a plurality of qubits; combining the second quantum bit substrate with the connecting substrate; Further comprising: The connection substrate has a coupling line that forms capacitive coupling between a quantum bit provided on the first quantum bit substrate and a quantum bit provided on the second quantum bit substrate. 15. The method of any one of claims 10 to 14. [Explanation of symbols]

[0061] 1, 1A, 1B qubits 10, 10A, 10B qubit boards 19 Ground electrode 20, 20A, 20C connection board 22, 22A, 22B, 22C, 22D, 22E, 22F coupled line 23, 23A, 23B capacitors 24, 24A, 24B Bonding Pads 25 Wiring 100, 100A, 100B, 100C Qubit Devices

Claims

1. a first qubit substrate having a first qubit, a second qubit, and a ground electrode extending between the first qubit and the second qubit; a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit; qubit device including

2. the first quantum bit substrate and the connection substrate are arranged to overlap each other; The ground electrode is disposed at a position overlapping the first coupled line in a plan view. The quantum bit device of claim 1 .

3. the first quantum bit substrate has a control port to which a control signal for controlling the first quantum bit is input; The ground electrode is disposed on a propagation path of the control signal from the control port to the first coupled line. The quantum bit device of claim 1 .

4. the first quantum bit and the second quantum bit are provided on one surface of the first quantum bit substrate; The control port is provided on the other surface of the first quantum bit substrate. The quantum bit device of claim 3 .

5. One end of the first coupled line is connected to the first quantum bit via a first pad, and the other end of the first coupled line is connected to the second quantum bit via a second pad. The quantum bit device of claim 1 .

6. The first coupled line is Wiring and a capacitor provided midway along the wiring; 10. The qubit device of claim 1, comprising:

7. The first coupled line is Wiring and a first capacitor provided between one end of the wiring and the first quantum bit; a second capacitor provided between the other end of the wiring and the second quantum bit; 10. The qubit device of claim 1, comprising:

8. the first coupled line is provided on one surface of the connection substrate, The connection substrate has a second coupling line provided on the other surface of the connection substrate, the second coupling line forming capacitive coupling between the first quantum bit and a quantum bit other than the second quantum bit. The quantum bit device of claim 1 .

9. further comprising a second qubit substrate having a plurality of qubits; The connection substrate has a coupling line that forms capacitive coupling between a quantum bit provided on the first quantum bit substrate and a quantum bit provided on the second quantum bit substrate. The quantum bit device of claim 1 .

10. forming a first qubit substrate having a first qubit, a second qubit, and a ground electrode extending between the first qubit and the second qubit; forming a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit; combining the first quantum bit substrate with the connection substrate; A method for manufacturing a quantum bit device, comprising:

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