Quantum bit device and method of manufacturing the same

Abstract

In a quantum bit device in which quantum bits provided on a plurality of quantum bit substrates are capacitively coupled to each other via a connection substrate, variations in coupling strength between the quantum bits are suppressed. [Solution] A quantum bit device includes a first quantum bit substrate having a first quantum bit and a first electrode, and a second quantum bit substrate having a second quantum bit and a second electrode. The quantum bit device includes a connection substrate having a third electrode and a fourth electrode, and disposed opposite the first quantum bit substrate and the second quantum bit substrate. The quantum bit device includes a first capacitor including the first electrode and the third electrode, a second capacitor including the second electrode and the fourth electrode, and a third capacitor. The first capacitor, the second capacitor, and the third capacitor are disposed in series between the first quantum bit and the second quantum bit. The capacitance of the first capacitor and the capacitance of the second capacitor are each greater than the capacitance of the third capacitor.

Description

[Technical Field]

[0001] The disclosed technology relates to quantum bit devices and methods for manufacturing quantum bit devices. [Background technology]

[0002] The following technologies are known as technologies related to quantum bit devices: Patent Document 1 describes a device having a structure in which a first quantum bit substrate and a second quantum bit substrate are flip-chip connected by solder bumps to a base substrate having superconducting wiring forming a closed loop.

[0003] Patent Document 2 discloses a configuration in which multiple quantum bit chips mounted on one carrier chip are connected by capacitive coupling, where terminals of the quantum bit chips are capacitively coupled to terminals provided on the opposing surface of the carrier chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] WO2018 / 212041 issue [Patent Document 2] Japanese Patent Application Publication No. 2023-69792 Summary of the Invention [Problem to be solved by the invention]

[0005] A quantum bit device is known to use a transmon as a quantum bit (Qubit). A transmon has a configuration in which a superconducting Josephson element and a capacitor are connected in parallel, and performs quantum operations using nonlinear energy. In a multi-bit quantum bit device, multiple quantum bits are connected to each other via a capacitor. To achieve even higher bit counts, a configuration in which the quantum bits provided on each of multiple quantum bit substrates are connected to each other via a capacitor can be considered. Specifically, multiple quantum bit substrates are mounted on a connection substrate, and the quantum bits provided on each quantum bit substrate are capacitively coupled to each other via wiring formed on the connection substrate. The capacitor between the quantum bits is formed by a parallel plate electrode type capacitor (hereinafter referred to as an inter-substrate capacitor) formed by opposing an electrode provided on the quantum bit substrate to an electrode provided on the connection substrate.

[0006] The capacitance C of a parallel plate capacitor is generally expressed by the following equation (1): In equation (1), ε is the dielectric constant of the dielectric, S is the electrode area, and d is the distance between the electrodes. C=ε·S / d (1)

[0007] In an inter-substrate capacitor, misalignment and differences in the way the bumps are crushed when the quantum bit substrate is mounted on the connecting substrate cause fluctuations in the electrode area S and inter-electrode distance d, resulting in fluctuations in capacitance C. Variations in capacitance C can cause fluctuations in the coupling strength between quantum bits, potentially destabilizing the characteristics of a two-qubit gate.

[0008] The disclosed technology has been developed in consideration of the above points, and aims to suppress variations in coupling strength between quantum bits in a quantum bit device in which quantum bits provided on each of multiple quantum bit substrates are capacitively coupled via a connecting substrate. [Means for solving the problem]

[0009] A quantum bit device according to the disclosed technology includes a first quantum bit substrate having a first quantum bit and a first electrode, and a second quantum bit substrate having a second quantum bit and a second electrode. The quantum bit device includes a connection substrate having a third electrode and a fourth electrode, and disposed opposite the first quantum bit substrate and the second quantum bit substrate. The quantum bit device includes a first capacitor including the first electrode and the third electrode, a second capacitor including the second electrode and the fourth electrode, and a third capacitor. The first capacitor, the second capacitor, and the third capacitor are disposed in series between the first quantum bit and the second quantum bit. The capacitance of the first capacitor and the capacitance of the second capacitor are each greater than the capacitance of the third capacitor. [Effects of the Invention]

[0010] According to the disclosed technology, in a quantum bit device in which quantum bits provided on each of a plurality of quantum bit substrates are capacitively coupled via a connection substrate, it is possible to suppress variations in coupling strength between the quantum bits. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view illustrating an example of a configuration of a quantum bit device according to an embodiment of the disclosed technique. [Figure 2] 1 is a plan view showing an example of the configuration of a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 3] FIG. 2 is an enlarged view of one of the basic units according to the embodiment of the disclosed technology. [Figure 4] FIG. 10 is an equivalent circuit diagram of a calculation block according to an embodiment of the disclosed technique. [Figure 5] 1 is a plan view showing the ends of a first quantum bit substrate and a second quantum bit substrate according to an embodiment of the disclosed technique. FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line 6-6 in FIG. 5. [Figure 7A]FIG. 1 is a plan view illustrating an example of a configuration of a capacitor according to an embodiment of the disclosed technique. [Figure 7B] 1 is a cross-sectional view showing an example of a configuration of a capacitor according to an embodiment of the disclosed technique. [Figure 8] 10 is a graph illustrating combined capacitance according to an embodiment of the disclosed technology. [Figure 9A] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9B] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9C] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9D] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9E] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9F] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9G] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 9H] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a first quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10A] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 10B] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 10C] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 11A] 10A and 10B are diagrams illustrating an example of a process for bonding a first quantum bit substrate and a second quantum bit substrate to a connection substrate according to an embodiment of the disclosed technique. [Figure 11B]10A and 10B are diagrams illustrating an example of a process for bonding a first quantum bit substrate and a second quantum bit substrate to a connection substrate according to an embodiment of the disclosed technique. [Figure 12] FIG. 10 is a cross-sectional view showing an example of the configuration of a quantum bit device according to another embodiment of the disclosed technique. [Figure 13] 10A and 10B are cross-sectional views showing an example of a method for closely adhering a first quantum bit substrate and a second quantum bit substrate to a connecting substrate according to an embodiment of the disclosed technique. [Figure 14] FIG. 10 is a cross-sectional view showing an example of the configuration of a quantum bit device according to another embodiment of the disclosed technique. [Figure 15] 10 is a plan view showing the ends of a first quantum bit substrate and a second quantum bit substrate according to another embodiment of the disclosed technique. FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line 16-16 in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant description will be omitted.

[0013] [First embodiment] 1 is a plan view showing an example of the configuration of a quantum bit device 100 according to an embodiment of the disclosed technique. The quantum bit device 100 has a first quantum bit substrate 10A, a second quantum bit substrate 10B, and a connection substrate 20. The first quantum bit substrate 10A and the second quantum bit substrate 10B are mounted on the connection substrate 20. The first quantum bit substrate 10A and the second quantum bit substrate 10B each have a plurality of quantum bits that are capacitively coupled to each other. Some of the quantum bits provided on the first quantum bit substrate 10A are capacitively coupled to some of the quantum bits provided on the second quantum bit substrate 10B via the connection substrate 20.

[0014] 2 is a plan view showing an example of the configuration of a first quantum bit substrate 10A. The first quantum bit substrate 10A has four quantum bits 1 as basic units 70. The first quantum bit substrate 10A has a plurality of basic units 70 arranged in a lattice pattern on the surface of a substrate 11 made of, for example, silicon.

[0015] FIG. 3 is an enlarged view of one of the basic units 70 shown in FIG. 2. The four quantum bits 1 that make up one basic unit 70 are arranged at positions corresponding to the four vertices of a square, with a readout port 14 located at the center of the square. One readout port 14 is shared by the four quantum bits 1. A resonator 2 and a filter 3 are provided on each path from each of the four quantum bits 1 to the readout port 14. Each quantum bit 1 is connected to an adjacent quantum bit 1 via a capacitor 15. As a result, each quantum bit 1 creates a quantum entangled state with the adjacent quantum bit 1 to perform a quantum operation.

[0016] FIG. 4 is an equivalent circuit diagram of an operation block including one quantum bit 1, one resonator 2, and one filter 3. The quantum bit 1 is an element that forms a coherent two-level system using superconductivity and performs quantum operations using nonlinear energy. The quantum bit 1 has a transmon in which a Josephson junction 4 and a capacitor 5 are connected in parallel. The Josephson junction 4 has a pair of superconductor layers that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator layer with a thickness of about several nanometers sandwiched between the pair of superconductor layers. The superconductor layer may be, for example, aluminum, and the insulator layer may be, for example, aluminum oxide.

[0017] The resonator 2 is connected to the quantum bit 1 via a capacitor 16. The resonator 2 interacts with the quantum bit 1 to read out a response signal indicating the state of the quantum bit 1. The resonator 2 has a resonant circuit in which a superconducting inductor 6 and a capacitor 7 are connected in parallel. The filter 3 is connected to the resonator 2 via a capacitor 17. The filter 3 suppresses the signal at the frequency of the quantum bit 1 from relaxing to the readout port 14. Like the resonator 2, the filter 3 has a resonant circuit in which a superconducting inductor 8 and a capacitor 9 are connected in parallel.

[0018] A control port 12, a ground port 13, and a readout port 14 are connected to the operation block. A control signal for controlling the quantum bit 1 is input to the control port 12. Note that the control port 12 and the ground port 13 are not shown in Figures 2 and 3. The state of the quantum bit 1 is controlled by the control signal input to the control port 12. A response signal indicating the state of the quantum bit 1 is read out from the readout port 14. The ground port 13 is connected to an external ground potential. The ground potential of the ground port 13 is common to the ground of each part of the operation block. The configuration of the second quantum bit substrate 10B is the same as that of the first quantum bit substrate 10A, so a description thereof will be omitted.

[0019] FIG. 5 is a plan view showing the ends of the first quantum bit substrate 10A and the second quantum bit substrate 10B, and FIG. 6 is a cross-sectional view taken along line 6-6 in FIG. 5. The first quantum bit substrate 10A and the second quantum bit substrate 10B each have a substrate 11 made of, for example, silicon. A control port 12 is provided on a first surface S1 of the substrate 11, and a quantum bit 1, a resonator 2, and a filter 3 are provided on a second surface S2 of the substrate 11. The quantum bit 1 is provided directly below the control port 12. A control signal input to the control port 12 acts on the quantum bit 1 via the substrate 11. The readout port 14 has a through-electrode structure that penetrates the substrate 11. A response signal output via the resonator 2 and the filter 3 is transmitted to the first surface S1 of the substrate 11 by the readout port 14 of the through-electrode structure.

[0020] First quantum bit substrate 10A has a first electrode 18A connected to quantum bit 1. Similarly, second quantum bit substrate 10B has a second electrode 18B connected to quantum bit 1. First quantum bit substrate 10A and second quantum bit substrate 10B are each connected to connection substrate 20 via bumps 40 and are juxtaposed on connection substrate 20. First quantum bit substrate 10A and second quantum bit substrate 10B are mounted on connection substrate 20 with second surfaces S2 on which quantum bit 1 is formed facing the surface of connection substrate 20. The surface of connection substrate 20 has a cavity 22 in a portion corresponding to quantum bit 1. This reduces the risk of unintended coupling with quantum bit 1.

[0021] The connection substrate 20 has a capacitor 30C at the boundary between the first quantum bit substrate 10A and the second quantum bit substrate 10B. The capacitor 30C may be a planar capacitor having a pair of comb-shaped conductors as electrodes formed on the surface of the substrate 21 of the connection substrate 20, as shown in FIG. 7A . Alternatively, the capacitor 30C may be a stacked capacitor having an MIM (Metal / Insulator / Metal) structure formed on the surface of the substrate 21, as shown in FIG. 7B . The connection substrate 20 has a third electrode 23A connected to one electrode of the capacitor 30C and a fourth electrode 23B connected to the other electrode of the capacitor 30C. The capacitor 30C is an example of a “third capacitor” in the technology disclosed herein.

[0022] First quantum bit substrate 10A is mounted on connection substrate 20 so that first electrode 18A and third electrode 23A face each other and a gap is formed between these electrodes. Similarly, second quantum bit substrate 10B is mounted on connection substrate 20 so that second electrode 18B and fourth electrode 23B face each other and a gap is formed between these electrodes.

[0023] By mounting first quantum bit substrate 10A and second quantum bit substrate 10B on connecting substrate 20, capacitive coupling is formed by series-connected capacitors 30A, 30B, and 30C between quantum bit 1A provided at an end of first quantum bit substrate 10A and quantum bit 1B provided at an end of second quantum bit substrate 10B. In other words, capacitors 30A, 30B, and 30C are provided in series between quantum bit 1A provided on first quantum bit substrate 10A and quantum bit 1B provided on second quantum bit substrate 10B.

[0024] Capacitor 30A includes a first electrode 18A provided on first quantum bit substrate 10A and a third electrode 23A provided on connection substrate 20. Capacitor 30A has a structure in which a gap is sandwiched between first electrode 18A and third electrode 23A. Capacitor 30A is an example of a "first capacitor" in the disclosed technology. Capacitor 30B includes a second electrode 18B provided on second quantum bit substrate 10B and a fourth electrode 23B provided on connection substrate 20. Capacitor 30B has a structure in which a gap is sandwiched between second electrode 18B and fourth electrode 23B. Capacitor 30B is an example of a "second capacitor" in the disclosed technology.

[0025] The combined capacitance C between the quantum bit 1A provided on the first quantum bit substrate 10A and the quantum bit 1B provided on the second quantum bit substrate 10B X is expressed by the following equation (2). In equation (2), C A is the capacitance of capacitor 30A, and C B is the capacitance of capacitor 30B, and C C is the capacitance of capacitor 30C. 1 / C X =1 / C A +1 / C B +1 / C C ···(2)

[0026] Since the capacitor 30C is formed in or on a single plane, it can be formed with high processing accuracy using existing microfabrication techniques such as photolithography and etching. Therefore, the electrode area S and the inter-electrode distance d of the capacitor 30C do not vary significantly. Therefore, the capacitance C of the capacitor 30C C On the other hand, the capacitor 30A is an inter-substrate capacitor formed between the first quantum bit substrate 10A and the connection substrate 20. Therefore, the electrode area S varies due to misalignment when the first quantum bit substrate 10A is mounted on the connection substrate 20, and the inter-electrode distance d varies due to differences in how the bumps 40 are crushed. A is the capacitance C C The same is true for capacitor 30B.

[0027] In the quantum bit device 100 according to this embodiment, the capacitance C A and the capacitance C of the capacitor 30B B are the capacitances C of the capacitor 30C, respectively. C That is, the capacitance C A , C B and C C The relationship is expressed by the following equation (3). C A ≒C B >>C C ···(3)

[0028] Capacitance C A , C B and C C The relationship between these two elements satisfies the above equation (3), and the combined capacitance C X Capacitance C at A , C B The effect of variations in capacitance C C When the capacitance C is fixed at 0.07 [fF], A , CB (C A =C B ) when the combined capacitance C X Graph showing capacitance C A , C B As the capacitance increases, the combined capacitance C X converges to 0.07 fF. This means that the capacitance C A , C B The capacitance C C The greater the deviation from X Capacitance C at A , C B This means that the effect of variations in capacitance C A , C B To virtually eliminate the effect of variations in capacitance C A , C B is the capacitance C C It is preferably 10 times or more, and more preferably 40 times or more.

[0029] The following describes a method for manufacturing the quantum bit device 100. Figures 9A to 9H are cross-sectional views showing an example of a manufacturing process for the first quantum bit substrate 10A. The manufacturing method for the second quantum bit substrate 10B is the same as that for the first quantum bit substrate 10A, and therefore will not be described again.

[0030] First, a substrate 11 of the first quantum bit substrate 10A is prepared. A silicon substrate with a thickness of approximately 300 μm can be used as the substrate 11 (FIG. 9A). Next, a conductive film 41 with a thickness of approximately 100 nm is formed on both sides of the substrate 11 using, for example, sputtering, plasma CVD (Chemical Vapor Deposition), or ion plating. TiN can be used as a material for the conductive film 41 (FIG. 9B). Next, a resist mask (not shown) is formed on the surface of the conductive film 41, and the conductive film 41 is patterned by partially etching the conductive film 41 through the resist mask. This results in the formation of the resonator 2, the filter 3, the first electrode 18A, and the like (FIG. 9C).

[0031] Next, quantum bit 1 is formed on the surface of substrate 11 (FIG. 9D). The superconducting Josephson element constituting quantum bit 1 is formed, for example, by the following steps: forming an Al-containing lower electrode (not shown) on the surface of substrate 11 by vapor deposition; forming an ultrathin oxide film (not shown) with a thickness of approximately several nanometers on the surface of the lower electrode using O2 gas; and forming an Al-containing upper electrode (not shown) on the surface of the oxide film by vapor deposition. The lower electrode and upper electrode may be patterned by, for example, a lift-off method using a patterned resist mask (not shown). In this case, the resist mask may have an opening pattern in the shape of a cross including a first linear portion along a first direction and a second linear portion along a second direction perpendicular to the first direction. The lower electrode may be formed in the portion corresponding to the first linear portion by performing vapor deposition while tilting the first direction as the rotation axis. Subsequently, the upper electrode may be formed in the portion corresponding to the second linear portion by performing vapor deposition while tilting the second direction as the rotation axis. The above method enables the lower electrode and upper electrode to be patterned using a single resist mask.

[0032] Next, a protective film 42 is formed to cover the surface of the quantum bit 1, for example, by CVD. The protective film 42 can be made of, for example, SiO2. The protective film 42 is then patterned using photolithography (FIG. 9E). Next, a hard mask (not shown) with an opening is formed where the readout port 14 will be formed. Using the hard mask, a through-hole 43 is formed in the substrate 11 at the position where the readout port 14 will be formed, for example, by Deep-RIE (Reactive Ion Etching) (FIG. 9F). Next, a conductive film is formed to cover the inner wall of the through-hole 43 and the periphery of the open end of the through-hole 43, for example, by vapor deposition. Aluminum, for example, can be used as the material for the conductive film. The conductive film is then patterned, for example, by lift-off. This forms the control port 12 and the readout port 14 (FIG. 9G). Next, the protective film 42 covering the quantum bit 1 is removed by etching, for example, using vapor hydrofluoric acid (FIG. 9H). Through the above steps, the first quantum bit substrate 10A is completed. The second quantum bit substrate 10B is manufactured in a similar process.

[0033] 10A to 10C are cross-sectional views showing an example of a manufacturing process for the connection substrate 20. First, a base material 21 of the connection substrate 20 is prepared. As the base material 21, for example, a silicon substrate with a thickness of about 300 μm can be used (FIG. 10A).

[0034] Next, a resist mask (not shown) is formed on the surface of the base material 21, and the surface of the base material 21 is partially etched through this resist mask to form cavities 22 at predetermined positions on the surface of the base material 21 (FIG. 10B). As an etching method, a deep-RIE method can be used.

[0035] Next, a resist mask (not shown) patterned to correspond to the patterns of the third electrode 23A, the fourth electrode 23B, and the capacitor 30C is formed on the surface of the base material 21. Next, a conductive film such as an Al film is formed on the surface of the base material 21 via the resist mask by vapor deposition. Next, the conductive film on the resist mask is removed together with the resist mask, thereby patterning the conductive film. As a result, the third electrode 23A, the fourth electrode 23B, and the capacitor 30C are formed on the surface of the base material 21 (FIG. 10C).

[0036] 11A and 11B are diagrams showing an example of a process for bonding the first quantum bit substrate 10A and the second quantum bit substrate 10B to the connection substrate 20. Bumps 40 are formed on the surfaces of the connection electrodes 19 formed on the second surfaces S2 of the first quantum bit substrate 10A and the second quantum bit substrate 10B. As a material for the bumps 40, for example, In can be used.

[0037] Next, connection electrodes 19 of first quantum bit substrate 10A and second quantum bit substrate 10B are bonded to connection electrodes 24 of connection substrate 20 via bumps 40. This bonds first quantum bit substrate 10A and second quantum bit substrate 10B to connection substrate 20. In this state, first electrode 18A and third electrode 23A face each other with a gap between them, and second electrode 18B and fourth electrode 23B face each other with a gap between them. Capacitor 30A is formed by first electrode 18A and third electrode 23A. Capacitor 30B is formed by second electrode 18B and fourth electrode 23B. Capacitance coupling is then formed between quantum bit 1A provided on first quantum bit substrate 10A and quantum bit 1B provided on second quantum bit substrate 10B by series-connected capacitors 30A, 30B, and 30C.

[0038] As described above, quantum bit device 100 according to an embodiment of the disclosed technique enables capacitive coupling to be formed between quantum bits provided on two different quantum bit substrates by capacitors 30A, 30B, and 30C connected in series. This increases the number of two-qubit gates that can be formed compared to when capacitive coupling between quantum bits is formed only within a single quantum bit substrate, thereby enabling improved quantum computing performance.

[0039] The capacitance C of the capacitors 30A and 30B formed between the first quantum bit substrate 10A and the second quantum bit substrate 10B and the connection substrate 20 A and C B However, the capacitance C A and C B is the capacitance C of the capacitor 30C, which has a relatively small variation. C is significantly larger than the combined capacitance C X Capacitance C at A , C B That is, according to the quantum bit device 100 according to the embodiment of the disclosed technique, it is possible to suppress variations in the coupling strength between quantum bits in a configuration in which quantum bits provided on each of a plurality of quantum bit substrates are capacitively coupled via a connection substrate.

[0040] In the above description, a quantum device having two quantum bit substrates has been exemplified, but the quantum device may have three or more quantum bits mounted on a connection substrate. Even in this case, in each pair of two adjacent quantum bit substrates, capacitive coupling is formed between the quantum bits by capacitors 30A, 30B, and 30C connected in series, and the capacitance of these capacitors is C A ≒C B >>C C It is configured to satisfy the following.

[0041] [Second embodiment] 12 is a cross-sectional view showing an example of the configuration of a quantum bit device 100A according to a second embodiment of the disclosed technique. The quantum bit device 100A has spacers 44 for forming gaps between the first quantum bit substrate 10A and the second quantum bit substrate 10B and the connecting substrate 20. The spacers 44 may be protruding structures formed at the contact portions with the quantum bit substrates, for example, by etching the base material 21 of the connecting substrate 20. The spacers 44 may also be made of a material other than the base material 21 (for example, a metal).

[0042] To bring the first quantum bit substrate 10A and the second quantum bit substrate 10B into close contact with the connecting substrate 20 via the spacers 44, for example, as shown in FIG. 13 , pressure may be applied via various probes used during operation of the quantum bit device 100A. The control probe 51 is a probe for inputting a control signal to the quantum bit 1 and is brought into contact with the control port 12. The readout probe 52 is a probe for reading out a response signal indicating the state of the quantum bit 1 and is brought into contact with the readout port 14. The ground probe 53 is a probe for applying a ground potential to the connecting substrate 20 and is brought into contact with the rear surface of the connecting substrate 20. A pressure is applied via the control probe 51 and the readout probe 52 to press the first quantum bit substrate 10A and the second quantum bit substrate 10B against the connecting substrate 20. The ground probe 53 applies a pressure to press the connecting substrate 20 against the first quantum bit substrate 10A and the second quantum bit substrate 10B. These probes have a plunger, a pipe, and a spring (none of which are shown), and are configured so that the pressing force is stabilized by the plunger connected to the spring stroking along the inner wall of the pipe.

[0043] Since the first quantum bit substrate 10A and the second quantum bit substrate 10B are not joined to the connecting substrate 20, if any of the quantum bit substrates deteriorates, is damaged, or breaks down, it is possible to easily replace that quantum bit substrate.

[0044] [Third embodiment] FIG. 14 is a cross-sectional view showing an example of the configuration of a quantum bit device 100B according to a third embodiment of the disclosed technology. In the quantum bit device 100B, the capacitors 30A and 30B each have an insulator 60. That is, the capacitor 30A has a structure in which the insulator 60 is sandwiched between the first electrode 18A and the third electrode 23A. The capacitor 30B has a structure in which the insulator 60 is sandwiched between the second electrode 18A and the fourth electrode 23B. The insulator 60 may be provided on the surface of the first electrode 18A and the surface of the second electrode 18B, respectively, or on the surface of the third electrode 23A and the surface of the fourth electrode 23B. Furthermore, the insulator 60 may be provided on the surface of each of the first to fourth electrodes.

[0045] Providing the insulator 60 between the electrodes of the capacitors 30A and 30B eliminates the need for spacers to form gaps between the first quantum bit substrate 10A and the second quantum bit substrate 10B and the connecting substrate 20. This simplifies the structure, making it possible to improve the yield of devices.

[0046] [Fourth embodiment] FIG. 15 is a plan view showing the ends of a first quantum bit substrate 10A and a second quantum bit substrate 10B according to a fourth embodiment of the disclosed technology, and FIG. 16 is a cross-sectional view taken along line 16-16 in FIG. 15. In the quantum bit devices 100, 100A, and 100B according to the first to third embodiments described above, the capacitor 30C, which has relatively small capacitance variation, is provided on the connection substrate 20. In contrast, the quantum bit device 100C according to the fourth embodiment has capacitors 30C1 and 30C2 corresponding to the capacitor 30C provided on the first quantum bit substrate 10A and the second quantum bit substrate 10B, respectively. The capacitors 30C1 and 30C2 may be planar capacitors having a pair of comb-shaped conductors as electrodes formed on the surface of the substrate 11 of each quantum bit substrate, or may be stacked capacitors having an MIM structure formed on the surface of the substrate 11.

[0047] Capacitor 30C1 has one electrode connected to quantum bit 1A and the other electrode connected to first electrode 18A. Capacitor 30C2 has one electrode connected to quantum bit 1B and the other electrode connected to second electrode 18B. By mounting first quantum bit substrate 10A and second quantum bit substrate 10B on connecting substrate 20, capacitive coupling is formed between quantum bit 1A and quantum bit 1B by capacitors 30C1, 30A, 30B, and 30C2 connected in series.

[0048] The combined capacitance C between qubit 1A and qubit 1B X is expressed by the following equation (4). In equation (4), C A is the capacitance of capacitor 30A, and C B is the capacitance of capacitor 30B, and C C1 is the capacitance of capacitor 30C1, and C C2 is the capacitance of capacitor 30C2. 1 / C X =1 / C A +1 / C B +1 / C C1 +1 / C C2 ···(4)

[0049] Since the capacitors 30C1 and 30C2 are formed in or on a single plane, they can be formed with high processing accuracy using existing microfabrication techniques such as photolithography and etching. Therefore, the electrode area S and the inter-electrode distance d of the capacitors 30C1 and 30C2 do not vary significantly. Therefore, the capacitance C of the capacitors 30C1 and 30C2 C1 and C C2 On the other hand, the capacitor 30A is an inter-substrate capacitor formed between the first quantum bit substrate 10A and the connection substrate 20. Therefore, the electrode area S varies due to misalignment when the first quantum bit substrate 10A is mounted on the connection substrate 20, and the inter-electrode distance d varies due to differences in how the bumps 40 are crushed. A is the capacitance CC1 and C C2 The same is true for capacitor 30B.

[0050] In the quantum bit device 100C according to this embodiment, the capacitance C A and the capacitance C of the capacitor 30B B are the capacitances C of the capacitors 30C1 and 30C2, respectively. C1 and C C2 That is, the capacitance C A , C B and C C1 and C C2 The relationship is expressed by the following equation (5). C A ≒C B >>C C1 ≒C C2 ···(5)

[0051] Capacitance C A , C B , C C1 and C C2 The relationship between these two elements satisfies the above equation (5), and the combined capacitance C X Capacitance C at A , C B This can reduce the influence of variations in the

[0052] According to the quantum bit device 100C of this embodiment, similar to the quantum bit devices of the first to third embodiments described above, it is possible to suppress variations in the coupling strength between quantum bits in a configuration in which quantum bits provided on each of a plurality of quantum bit substrates are capacitively coupled via a connecting substrate.

[0053] The following additional notes are disclosed regarding the first to fourth embodiments described above. (Appendix 1) a first qubit substrate having a first qubit and a first electrode; a second qubit substrate having a second qubit and a second electrode; a connection substrate having a third electrode and a fourth electrode and disposed opposite the first quantum bit substrate and the second quantum bit substrate; a first capacitor including the first electrode and the third electrode; a second capacitor including the second electrode and the fourth electrode; a third capacitor; and the first capacitor, the second capacitor, and the third capacitor are arranged in series between the first quantum bit and the second quantum bit; The capacitance of the first capacitor and the capacitance of the second capacitor are each greater than the capacitance of the third capacitor. qubit device.

[0054] (Appendix 2) The third capacitor is provided on the connection board. 10. The qubit device of claim 1.

[0055] (Appendix 3) The third capacitor is provided on at least one of the first quantum bit substrate and the second quantum bit substrate. 10. The qubit device of claim 1.

[0056] (Appendix 4) the first capacitor has a structure in which a gap formed between the first quantum bit substrate and the connection substrate is sandwiched between the first electrode and the third electrode; The second capacitor has a structure in which a gap formed between the second quantum bit substrate and the connection substrate is sandwiched between the second electrode and the fourth electrode. 4. The quantum bit device of any one of claims 1 to 3.

[0057] (Appendix 5) a spacer for forming the gap provided between the first quantum bit substrate and the second quantum bit substrate and the connecting substrate; 5. The qubit device of claim 4.

[0058] (Appendix 6) the first capacitor has a structure in which an insulator provided between the first quantum bit substrate and the connection substrate is sandwiched between the first electrode and the third electrode; The second capacitor has a structure in which an insulator provided between the second quantum bit substrate and the connection substrate is sandwiched between the second electrode and the fourth electrode. 4. The quantum bit device of any one of claims 1 to 3.

[0059] (Appendix 7) The third capacitor is a planar capacitor having a pair of electrodes formed in a single plane. 7. The quantum bit device of any one of claims 1 to 6.

[0060] (Appendix 8) The third capacitor has a MIM structure formed on a single plane. 7. The quantum bit device of any one of claims 1 to 6.

[0061] (Appendix 9) The capacitance of the first capacitor and the capacitance of the second capacitor are 10 times or more the capacitance of the third capacitor. 9. The quantum bit device of any one of Supplementary Notes 1 to 8.

[0062] (Appendix 10) The third capacitor is provided on the connection substrate at a position corresponding to the boundary between the first quantum bit substrate and the second quantum bit substrate. 1. The qubit device of claim 2.

[0063] (Appendix 11) one of the third capacitors is provided between the first quantum bit and the first electrode of the first quantum bit substrate; The other of the third capacitors is provided between the second quantum bit and the second electrode of the second quantum bit substrate. 4. The qubit device of claim 3.

[0064] (Appendix 12) forming a first qubit substrate having a first qubit and a first electrode; forming a second qubit substrate having a second qubit and a second electrode; forming a connection substrate having a third electrode and a fourth electrode; and arranging the first quantum bit substrate, the second quantum bit substrate, and the connecting substrate so that each of the first quantum bit substrate and the second quantum bit substrate faces the connecting substrate; a first capacitor including the first electrode and the third electrode and a second capacitor including the second electrode and the fourth electrode are formed, and the first capacitor, the second capacitor, and the third capacitor are provided in series between the first quantum bit and the second quantum bit; The capacitance of the first capacitor and the capacitance of the second capacitor are greater than the capacitance of the third capacitor. A method for manufacturing a quantum bit device.

[0065] (Appendix 13) The third capacitor is provided on the connection board. The manufacturing method described in Appendix 12.

[0066] (Appendix 14) The third capacitor is provided on at least one of the first quantum bit substrate and the second quantum bit substrate. The manufacturing method described in Appendix 12.

[0067] (Appendix 15) the first capacitor has a structure in which a gap formed between the first quantum bit substrate and the connection substrate is sandwiched between the first electrode and the third electrode; The second capacitor has a structure in which a gap formed between the second quantum bit substrate and the connection substrate is sandwiched between the second electrode and the fourth electrode. 15. The method of any one of claims 12 to 14.

[0068] (Appendix 16) a spacer for forming the gap provided between the first quantum bit substrate and the second quantum bit substrate and the connecting substrate; The manufacturing method described in Appendix 15.

[0069] (Appendix 17) the first capacitor has a structure in which an insulator provided between the first quantum bit substrate and the connection substrate is sandwiched between the first electrode and the third electrode; The second capacitor has a structure in which an insulator provided between the second quantum bit substrate and the connection substrate is sandwiched between the second electrode and the fourth electrode. 15. The method of any one of claims 12 to 14.

[0070] (Appendix 18) The third capacitor is a planar capacitor having a pair of electrodes formed in a single plane. 18. The method of any one of claims 12 to 17.

[0071] (Appendix 19) The third capacitor has a MIM structure formed on a single plane. 18. The method of any one of claims 12 to 17.

[0072] (Appendix 20) The capacitance of the first capacitor and the capacitance of the second capacitor are 10 times or more the capacitance of the third capacitor. 19. The method of any one of claims 12 to 19. [Explanation of symbols]

[0073] 1, 1A, 1B qubits 10A First Qubit Board 10B Second qubit substrate 18A 1st electrode 18B 2nd electrode 20 Connection board 23A 3rd electrode 23B 4th electrode 30A, 30B, 30C, 30C1, 30C2 capacitors 100, 100A, 100B, 100C Qubit Devices

Claims

1. a first qubit substrate having a first qubit and a first electrode; a second qubit substrate having a second qubit and a second electrode; a connection substrate having a third electrode and a fourth electrode and provided opposite the first quantum bit substrate and the second quantum bit substrate; a first capacitor including the first electrode and the third electrode; a second capacitor including the second electrode and the fourth electrode; a third capacitor; and and the first capacitor, the second capacitor, and the third capacitor are provided in series between the first quantum bit and the second quantum bit; The capacitance of the first capacitor and the capacitance of the second capacitor are each greater than the capacitance of the third capacitor. qubit device.

2. The third capacitor is provided on the connection board. The quantum bit device of claim 1 .

3. The third capacitor is provided on at least one of the first quantum bit substrate and the second quantum bit substrate. The quantum bit device of claim 1 .

4. the first capacitor has a structure in which a gap formed between the first quantum bit substrate and the connection substrate is sandwiched between the first electrode and the third electrode; The second capacitor has a structure in which a gap formed between the second quantum bit substrate and the connection substrate is sandwiched between the second electrode and the fourth electrode. The quantum bit device of claim 1 .

5. a spacer for forming a gap between the first quantum bit substrate and the second quantum bit substrate and the connecting substrate; The quantum bit device of claim 4 .

6. the first capacitor has a structure in which an insulator provided between the first quantum bit substrate and the connection substrate is sandwiched between the first electrode and the third electrode; The second capacitor has a structure in which an insulator provided between the second quantum bit substrate and the connection substrate is sandwiched between the second electrode and the fourth electrode. The quantum bit device of claim 1 .

7. The third capacitor is a planar capacitor having a pair of electrodes formed in a single plane. The quantum bit device of claim 1 .

8. The third capacitor has an MIM structure formed on a single plane. The quantum bit device of claim 1 .

9. The capacitance of the first capacitor and the capacitance of the second capacitor are 10 times or more the capacitance of the third capacitor. The quantum bit device of claim 1 .

10. forming a first qubit substrate having a first qubit and a first electrode; forming a second qubit substrate having a second qubit and a second electrode; forming a connection substrate having a third electrode and a fourth electrode; and arranging the first quantum bit substrate, the second quantum bit substrate, and the connecting substrate so that each of the first quantum bit substrate and the second quantum bit substrate faces the connecting substrate; a first capacitor including the first electrode and the third electrode and a second capacitor including the second electrode and the fourth electrode are formed, and the first capacitor, the second capacitor, and the third capacitor are provided in series between the first quantum bit and the second quantum bit; The capacitance of the first capacitor and the capacitance of the second capacitor are greater than the capacitance of the third capacitor. A method for manufacturing a quantum bit device.

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