Quantum bit device and method of manufacturing the same

Abstract

By adding technical innovations to the coupling lines formed between one quantum bit and multiple other adjacent quantum bits, the efficiency of extracting the electromagnetic field from the quantum bit can be improved while suppressing crosstalk. The quantum bit device includes a quantum bit substrate having a first quantum bit and a second quantum bit, a connection substrate disposed opposite the quantum bit substrate, and a coupling line including a first wiring and a second wiring that form a differential pair and form capacitive coupling between the first quantum bit and the second quantum bit, wherein at least one of the first wiring and the second wiring is disposed on the connection substrate.

Description

[Technical Field]

[0001] The disclosed technology relates to quantum bit devices and methods for manufacturing quantum bit devices. [Background technology]

[0002] The following technologies are known as technologies related to quantum bit devices. Patent Document 1 describes a device including a first quantum bit, a second quantum bit, a resonator that capacitively couples the first quantum bit to the second quantum bit, and a differential direct coupler that capacitively couples the first quantum bit to the second quantum bit. The differential direct coupler capacitively couples opposing pads of the first quantum bit and the second quantum bit.

[0003] Patent document 2 describes a quantum computer system having a plurality of quantum circuits arranged in a two-dimensional layout, and at least one internal quantum circuit of the plurality of quantum circuits includes a signal line extending outside the two-dimensional layout of the plurality of quantum circuits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2023-528762 [Patent Document 2] Special Publication No. 2021-504948 Summary of the Invention [Problem to be solved by the invention]

[0005] A quantum bit device is known to use a transmon as a quantum bit (Qubit). A transmon has a configuration in which a superconducting Josephson element and a capacitor are connected in parallel, and performs quantum operations using nonlinear energy. In a multi-bit quantum bit device, multiple quantum bits are connected to each other via coupling lines with capacitors.

[0006] One known quantum bit structure is a floating structure having a concentric pattern including a circular inner electrode and an annular outer electrode surrounding the inner electrode, as described in JP 2022-172189 A. This structure results in a relatively large capacitance of the quantum bit to ground, resulting in a relatively low efficiency of extracting the electromagnetic field from the quantum bit. Therefore, it is necessary to relatively increase the capacitance of the capacitors provided in the coupling lines for forming capacitive coupling between quantum bits. Increasing the capacitance between quantum bits increases the risk of crosstalk occurring between quantum bits.

[0007] The disclosed technology has been developed in consideration of the above points, and aims to improve the efficiency of electromagnetic field extraction from a quantum bit while suppressing crosstalk by adding technical ingenuity to the coupling lines formed between one quantum bit and multiple other quantum bits adjacent to it. [Means for solving the problem]

[0008] A quantum bit device according to the disclosed technique includes a quantum bit substrate having a first quantum bit and a second quantum bit, a connection substrate provided opposite the quantum bit substrate, and a coupling line including a first wiring and a second wiring that form a differential pair and form capacitive coupling between the first quantum bit and the second quantum bit, wherein at least one of the first wiring and the second wiring is provided on the connection substrate. [Effects of the Invention]

[0009] According to the disclosed technology, by applying technical innovations to the coupling lines formed between one quantum bit and multiple other quantum bits adjacent to it, it is possible to improve the efficiency of extracting the electromagnetic field from the quantum bit while suppressing crosstalk. [Brief explanation of the drawings]

[0010] [Figure 1]FIG. 1 is a diagram schematically illustrating an example of the configuration of a quantum bit device according to an embodiment of the disclosed technique. [Figure 2] FIG. 10 is a plan view showing an example of a layout on one surface of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 3] FIG. 10 is a plan view showing an example of a layout on a surface of a connection substrate facing a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 4] FIG. 1 is a cross-sectional view of a quantum bit device according to an embodiment of the disclosed technique. [Figure 5] FIG. 10 is an equivalent circuit diagram of a calculation block according to an embodiment of the disclosed technique. [Figure 6] FIG. 1 is a plan view showing an example of a quantum bit pattern according to an embodiment of the disclosed technique. [Figure 7] 1 is a cross-sectional view showing an example of the configuration of a Josephson element according to an embodiment of the disclosed technique. [Figure 8] 10 is a plan view showing an example of a layout of first wiring and second wiring according to an embodiment of the disclosed technique. FIG. [Figure 9] FIG. 9 is an equivalent circuit diagram corresponding to FIG. 8. [Figure 10A] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10B] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10C] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10D] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10E] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10F] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10G] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 10H] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process of a quantum bit substrate according to an embodiment of the disclosed technique. [Figure 11A] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 11B] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 11C] 10A to 10C are cross-sectional views showing an example of a manufacturing process of a connection board according to an embodiment of the disclosed technique. [Figure 12A] 10A to 10C are diagrams illustrating an example of a process for combining a quantum bit substrate and a connection substrate according to an embodiment of the disclosed technique. [Figure 12B] 10A to 10C are diagrams illustrating an example of a process for combining a quantum bit substrate and a connection substrate according to an embodiment of the disclosed technique. [Figure 13] FIG. 10 is a plan view showing an example of a layout in which both the first wiring and the second wiring are formed on a single plane. [Figure 14A] 10 is a graph showing the results of a simulation of loss when signal transmission is performed between quantum bits coupled by a coupled line formed of a single-phase wiring. [Figure 14B] 10 is a graph showing the results of a simulation of loss when signal transmission is performed between quantum bits coupled by a coupled line formed by differential wiring. [Figure 15] FIG. 10 is a cross-sectional view showing an example of the configuration of a quantum bit device according to another embodiment of the disclosed technique. [Figure 16] FIG. 10 is a plan view showing an example of a layout of first wirings and second wirings according to another embodiment of the disclosed technique. [Figure 17] FIG. 17 is an equivalent circuit diagram corresponding to FIG. 16. [Figure 18] FIG. 10 is a plan view showing an example of a layout of first wirings and second wirings according to another embodiment of the disclosed technique. [Figure 19] This shows the results of a simulation of loss when signal transmission is performed between quantum bits coupled by a coupled line configured with asymmetric differential wiring. [Figure 20A]FIG. 10 is a plan view showing an example of a layout of first wirings and second wirings according to another embodiment of the disclosed technique. [Figure 20B] FIG. 10 is a plan view showing an example of a layout of first wirings and second wirings according to another embodiment of the disclosed technique. [Figure 21] FIG. 10 is a plan view showing an example of a layout of first wirings and second wirings according to another embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant description will be omitted.

[0012] [First embodiment] FIG. 1 is a diagram schematically illustrating an example of the configuration of a quantum bit device 100 according to an embodiment of the disclosed technique. The quantum bit device 100 includes a quantum bit substrate 10 and a connection substrate 20. These substrates are stacked such that a surface S1 of the quantum bit substrate 10 and a surface S3 of the connection substrate 20 face each other. FIG. 2 is a plan view illustrating an example of a layout on the surface S1 of the quantum bit substrate 10, and FIG. 3 is a plan view illustrating an example of a layout on the surface S3 of the connection substrate 20. FIG. 4 is a cross-sectional view of the quantum bit device 100, showing a cross section taken along line 4-4 in FIG. 1.

[0013] The quantum bit device 100 has four quantum bits 1 provided on a quantum bit substrate 10 as basic units 70. The four quantum bits 1 constituting one basic unit 70 are arranged at positions corresponding to the four vertices of a square, and a readout port 14 is located at the center of the square. One readout port 14 is shared by the four quantum bits 1. A resonator 2 and a filter 3 are provided on each path from each of the four quantum bits 1 to the readout port 14. Each quantum bit 1 is connected to an adjacent quantum bit 1 via a coupled line 60. The coupled line 60 is configured to include two wires forming a differential pair. By connecting each quantum bit 1 to an adjacent quantum bit 1 via the coupled line 60, capacitive coupling is formed between the adjacent quantum bits. Each quantum bit 1 creates a quantum entangled state with the adjacent quantum bit 1 to perform a quantum operation.

[0014] Figure 5 is an equivalent circuit diagram of an operation block including one qubit 1, one resonator 2, and one filter 3. The qubit 1 is an element that forms a coherent two-level system using superconductivity and performs quantum operations using nonlinear energy. The qubit 1 has a transmon in which a Josephson element 4 and a capacitor 5 are connected in parallel.

[0015] The resonator 2 is connected to the quantum bit 1 via a capacitor 17. The resonator 2 interacts with the quantum bit 1 to read out a response signal indicating the state of the quantum bit 1. The resonator 2 has a resonant circuit in which a superconducting inductor 6 and a capacitor 7 are connected in parallel. The filter 3 is connected to the resonator 2 via a capacitor 18. The filter 3 suppresses the signal at the frequency of the quantum bit 1 from relaxing to the readout port 14. Like the resonator 2, the filter 3 has a resonant circuit in which a superconducting inductor 8 and a capacitor 9 are connected in parallel.

[0016] A control port 12, a ground port 13, and a readout port 14 are connected to the operation block. A control signal for controlling the quantum bit 1 is input to the control port 12. The state of the quantum bit 1 is controlled by the control signal input to the control port 12. A response signal indicating the state of the quantum bit 1 is read out from the readout port 14. The ground port 13 is connected to an external ground potential. The ground potential of the ground port 13 is common to the ground of each part of the operation block.

[0017] The quantum bit substrate 10 has a substrate 11 made of, for example, silicon. A quantum bit 1, a resonator 2, and a filter 3 are provided on a surface S1 of the substrate 11. A readout port 14 has a through-electrode structure that penetrates the substrate 11. A response signal output via the resonator 2 and the filter 3 is transmitted by the readout port 14 of the through-electrode structure to a surface S2 of the substrate 11 opposite to the surface S1. A control port 12 is provided directly below each quantum bit 1 on the surface S2 of the substrate 11. A control signal input to the control port 12 acts on the quantum bit 1 via the substrate 11.

[0018] A first wiring 61, which is one of a pair of differential wirings constituting a coupled line 60, is provided on surface S1 of substrate 11. First wiring 61 has a capacitor 63 along its path. All of the quantum bits arranged in a lattice pattern on quantum bit substrate 10 are connected to adjacent quantum bits 1 via first wiring 61.

[0019] 6 is a plan view showing an example of the pattern of a quantum bit 1. The quantum bit 1 includes a circular inner electrode 71 and an annular outer electrode 72 surrounding the inner electrode 71. In other words, the quantum bit 1 has a concentric pattern. The quantum bit 1 has a Josephson junction 4 provided between the inner electrode 71 and the outer electrode 72. The inner electrode 71 also functions as one electrode of a capacitor 5, and the outer electrode 72 also functions as the other electrode of the capacitor 5. A transmon is formed by the Josephson junction 4 and the capacitor 5 connected in parallel between the inner electrode 71 and the outer electrode 72.

[0020] FIG. 7 is a cross-sectional view showing an example of the configuration of a Josephson junction 4. The Josephson junction 4 has a pair of superconductors 73A and 73BB that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator 74 having a thickness of about several nanometers sandwiched between the superconductors 73A and 73B. The superconductors 73A and 73B may be made of aluminum, for example, and the insulator 74 may be made of aluminum oxide, for example. The superconductor 73A is connected to an outer electrode 72, and the superconductor 73B is connected to an inner electrode 71. A first wire 61 of a pair of differential wires constituting the coupled line 60 is connected to the outer electrode 72.

[0021] A surface S1 of the quantum bit substrate 10 is covered by a connection substrate 20. The connection substrate 20 has a base material 21 made of, for example, silicon. A surface S3 of the base material 21 facing the quantum bit substrate 10 is provided with a plurality of bond pads 22. The bond pads 22 are arranged in a lattice pattern corresponding to the arrangement of the quantum bits 1 provided on the quantum bit substrate 10. More specifically, the bond pads 22 are arranged at positions that overlap with the inner electrodes 71 of the quantum bits 1 in a plan view.

[0022] A second wiring 62, which is the other of a pair of differential wirings that make up the coupled line 60, is provided on surface S3 of the substrate 21. The second wiring 62 has a capacitor 64 along its path. All of the coupling pads 22 arranged in a grid pattern on the connection substrate 20 are connected to adjacent other coupling pads 22 via the second wiring 62. The second wiring 62 is arranged in the same arrangement as the first wiring 61 provided on the quantum bit substrate 10.

[0023] Each of the multiple bond pads 22 is connected to the inner electrode 71 of the corresponding quantum bit 1 via a bump 30. That is, the second wiring 62 is connected to the inner electrode 71 via the bond pad 22. All of the quantum bits 1 arranged in a lattice pattern on the quantum bit substrate 10 are connected to adjacent quantum bits 1 not only via the first wiring 61 but also via the second wiring 62.

[0024] The entire surface S4 of the connecting substrate 20 opposite to the surface S3 is covered with a conductive film 23. Electromagnetic waves emitted from the quantum bit 1 during operation of the quantum bit device 100 are blocked by the conductive film 23. A spacer 31 is provided between the quantum bit substrate 10 and the connecting substrate 20 to form a gap between these substrates. The spacer 31 may be formed by cutting the base material of the quantum bit substrate 10 or the connecting substrate 20, or may be formed from another material such as a metal.

[0025] FIG. 8 is a plan view showing an example of the layout of first wiring 61 and second wiring 62 constituting coupled line 60 that forms capacitive coupling between quantum bits 1A and 1B. FIG. 9 is an equivalent circuit diagram corresponding to FIG. 8. One end of first wiring 61 is connected to the outer electrode of quantum bit 1A, and the other end of first wiring 61 is connected to the outer electrode 72 of quantum bit 1B. One end of second wiring 62 is connected to the inner electrode 71 of quantum bit 1A via coupling pad 22A, and the other end of second wiring 62 is connected to the inner electrode 71 of quantum bit 1B via coupling pad 22B. Connecting first wiring 61 to outer electrode 72 and second wiring 62 to inner electrode 71 forms a differential pair. That is, differential signals having opposite phases are transmitted through first wiring 61 and second wiring 62. Capacitors 63 and 64 are provided along the respective paths of first wiring 61 and second wiring 62. Capacitors 63 and 64 may each be a planar capacitor having a pair of comb-shaped conductors as electrodes. Capacitors 63 and 64 may also be a stacked capacitor having an MIM (Metal / Insulator / Metal) structure. Capacitive coupling is formed between quantum bits 1A and 1B by coupled line 60 including first wiring 61 and second wiring 62 that form a differential pair.

[0026] The following describes a method for manufacturing the quantum bit device 100. Figures 10A to 10H are cross-sectional views showing an example of a manufacturing process for the quantum bit substrate 10.

[0027] First, a substrate 11 of the quantum bit substrate 10 is prepared. A silicon substrate with a thickness of approximately 300 μm can be used as the substrate 11 (FIG. 10A). Next, a conductive film 41 with a thickness of approximately 100 nm is formed on both sides of the substrate 11 using, for example, sputtering, plasma CVD (Chemical Vapor Deposition), or ion plating. TiN, for example, can be used as the material for the conductive film 41 (FIG. 10B). Next, a resist mask (not shown) is formed on the surface of the conductive film 41, and the conductive film 41 is patterned by partially etching the conductive film 41 through the resist mask. This results in the formation of the resonator 2, the filter 3, the first wiring 61, and so on (FIG. 10C). A capacitor 63 is formed along the path of the first wiring 61.

[0028] Next, quantum bit 1 is formed on the surface of substrate 11 (FIG. 10D). The superconducting Josephson element constituting quantum bit 1 is formed, for example, by the following steps: forming a superconducting film (not shown) of Al or the like that constitutes the lower electrode on the surface of substrate 11 by vapor deposition; forming an extremely thin oxide film (not shown) of about several nanometers thick on the surface of the lower electrode using O2 gas; and forming a superconducting film (not shown) of Al or the like that constitutes the upper electrode on the surface of the oxide film by vapor deposition. The lower electrode and the upper electrode may be patterned by, for example, a lift-off method using a patterned resist mask (not shown). In this case, the opening pattern of the resist mask may be a cross shape including a first linear portion along a first direction and a second linear portion along a second direction perpendicular to the first direction. Vapor deposition may be performed with the first direction tilted as the axis of rotation to form the lower electrode in the portion corresponding to the first linear portion. Subsequently, vapor deposition may be performed with the second direction tilted as the axis of rotation to form the upper electrode in the portion corresponding to the second linear portion. According to the above method, the lower electrode and the upper electrode can be patterned using a single resist mask.

[0029] Next, a protective film 42 is formed to cover the surface of the quantum bit 1, for example, by CVD. The protective film 42 can be made of, for example, SiO2. The protective film 42 is then patterned using photolithography (FIG. 10E). Next, a hard mask (not shown) with an opening is formed where the readout port 14 will be formed. Using the hard mask, a through-hole 43 is formed in the substrate 11 at the position where the readout port 14 will be formed, for example, by Deep-RIE (Reactive Ion Etching) (FIG. 10F). Next, a conductive film is formed to cover the inner wall of the through-hole 43 and the periphery of the open end of the through-hole 43, for example, by vapor deposition. Aluminum, for example, can be used as the material for the conductive film. The conductive film is then patterned, for example, by lift-off. This forms the control port 12 and the readout port 14 (FIG. 10G). The protective film 42 covering the quantum bit 1 is then removed by etching, for example, using vapor hydrofluoric acid (FIG. 10H).

[0030] 11A to 11C are cross-sectional views showing an example of a manufacturing process for connection substrate 20. First, a base material 21 of connection substrate 20 is prepared. As base material 21, for example, a silicon substrate with a thickness of about 300 μm can be used (FIG. 11A).

[0031] Next, a conductive film 23 with a thickness of approximately 100 nm is formed on both sides of the substrate 21 using, for example, sputtering, plasma CVD, or ion plating. TiN, for example, can be used as the material for the conductive film 23 (FIG. 11B). Next, a resist mask (not shown) is formed on the surface of the conductive film 23, and the conductive film 23 is patterned by partially etching the conductive film 23 through the resist mask. This results in the formation of the bond pad 22, the second wiring 62, and the like (FIG. 11C). A capacitor 64 is formed midway along the path of the second wiring 62.

[0032] 12A and 12B are diagrams showing an example of a process for combining a quantum bit substrate 10 and a connection substrate 20. Bumps 30 are formed on the surfaces of bond pads 22 formed on the connection substrate 20 (FIG. 12A). In, for example, can be used as the material for the bumps 30. The bumps 30 may also be formed on the surfaces of the inner electrodes 71 of the quantum bit 1. Next, spacers 31 are formed on the surface of the base material 11 of the quantum bit substrate 10 (FIG. 12A). The spacers 31 may be formed by cutting the base material 11, or may be formed from other materials such as metal. The spacers 31 may also be formed on the surface of the base material of the connection substrate 20. Next, the quantum bit substrate 10 and connection substrate 20 are arranged so that the surface S1 on which the quantum bit 1 and first wiring 61 are formed faces the surface S3 on which the second wiring 62 and bonding pads 22 are formed of the connection substrate 20 (FIG. 12A).

[0033] Next, each of the multiple coupling pads 22 provided on the connection substrate 20 is connected to the inner electrode 71 of the corresponding quantum bit 1 provided on the quantum bit substrate 10 via a bump 30 (FIG. 12B). This connects the quantum bit 1 provided on the quantum bit substrate 10 to the second wiring 62 provided on the connection substrate 20. A differential pair is formed by the first wiring 61 provided on the quantum bit substrate 10 and the second wiring 62 provided on the connection substrate 20. Capacitive coupling is formed between adjacent quantum bits by the coupling line 60 including the first wiring 61 and second wiring 62 that form the differential pair.

[0034] Here, the inventors considered that constructing the coupling line between quantum bits using differential wiring would be effective in improving the extraction efficiency of the electromagnetic field from the quantum bits. First, consider the case where both the first wiring 61 and the second wiring 62 forming a differential pair are formed on a single plane. The second wiring 62 connected to the inner electrode 71 of quantum bit 1A is extended to the outside of the outer electrode 72 toward the adjacent quantum bit 1B. When one quantum bit is coupled to only one other adjacent quantum bit, as shown in FIG. 13 , a cutout 73 is provided in the outer electrode 72 and the second wiring 62 is passed through the cutout 73, thereby enabling the second wiring 62 to be extended to the outside of the outer electrode 72. On the other hand, when attempting to couple one quantum bit to multiple other adjacent quantum bits (four in this embodiment), it is necessary to provide multiple cutouts in the outer electrode 72. If multiple cutouts are provided in the outer electrode 72, the outer electrode 72 will be divided, making it impossible to form the intended circuit. Therefore, multiple cutouts cannot be provided in the outer electrode 72. In this configuration in which multiple quantum bits with concentric circular patterns are arranged in a grid pattern on a substrate, it is difficult in terms of layout to configure the coupling lines formed between one quantum bit and multiple other quantum bits adjacent to it using differential wiring arranged in a single plane.

[0035] According to the quantum bit device 100 of the embodiment of the disclosed technique, the second wiring 62, which is one of the differential wirings constituting the coupled line 60, is provided on a connection substrate 20 separate from the quantum bit substrate 10. This makes it possible to extend the second wiring 62 to the outside of the outer electrode 72 without providing a missing portion in the outer electrode 72. Therefore, according to the quantum bit device 100 of the embodiment of the disclosed technique, it is possible to configure the coupled line formed between one quantum bit and other adjacent quantum bits using differential wiring.

[0036] Furthermore, by configuring the coupling lines between quantum bits using differential wiring, the efficiency of extracting the electromagnetic field from the quantum bits can be improved compared to when the coupling lines are configured using single-phase wiring. Figures 14A and 14B show simulation results of loss when signal transmission is performed between quantum bits. Figure 14A shows the case where the coupling lines between quantum bits are configured using single-phase wiring, and Figure 14B shows the case where the coupling lines between quantum bits are configured using differential wiring. The loss when the coupling lines between quantum bits are configured using single-phase wiring is approximately -100 dB. On the other hand, the loss when the coupling lines between quantum bits are configured using differential wiring is approximately -3 dB. Thus, by configuring the coupling lines between quantum bits using differential wiring, the efficiency of extracting the electromagnetic field from the quantum bits can be improved compared to when the coupling lines are configured using single-phase wiring, and the efficiency of signal transmission between quantum bits can be improved. The increased signal transmission efficiency between quantum bits allows the capacitance of the capacitors provided in the coupling lines to be reduced. This reduces the risk of crosstalk occurring between quantum bits. Furthermore, by configuring the coupling lines between quantum bits using differential wiring, it is possible to eliminate common-mode noise, thereby increasing resistance to noise originating from the ground. As described above, according to the disclosed technology, by applying technical ingenuity to the coupling lines formed between one quantum bit and multiple other quantum bits adjacent to it, it is possible to improve the efficiency of extracting the electromagnetic field from the quantum bit while suppressing crosstalk.

[0037] [Second embodiment] FIG. 15 is a cross-sectional view showing an example of the configuration of a quantum bit device 100A according to a second embodiment of the disclosed technology. FIG. 16 is a plan view showing an example of the layout of the first wiring 61 and the second wiring 62 according to the second embodiment. FIG. 17 is an equivalent circuit diagram corresponding to FIG. 16. In the quantum bit device 100 according to the first embodiment described above, the coupled-line 60 has capacitors 63 and 64 along the paths of the first wiring 61 and the second wiring 62. In the quantum bit device 100A according to the second embodiment, the coupled-line 60 has capacitors 63A and 63B at the connection between the first wiring 61 and the quantum bits 1A and 1B, respectively, and capacitors 64A and 64B at the connection between the second wiring 62 and the quantum bits 1A and 1B, respectively.

[0038] Bond pad 22A connected to one end of second wiring 62 is positioned so as to overlap inner electrode 71 of quantum bit 1A in a planar view, with a gap formed between bond pad 22A and inner electrode 71 of quantum bit 1A. This forms capacitor 64A, with bond pad 22A as one electrode and inner electrode 71 of quantum bit 1A as the other electrode. Similarly, bond pad 22B connected to the other end of second wiring 62 is positioned so as to overlap inner electrode 71 of quantum bit 1B in a planar view, with a gap formed between bond pad 22B and inner electrode 71 of quantum bit 1B. This forms capacitor 64B, with bond pad 22B as one electrode and inner electrode 71 of quantum bit 1B as the other electrode. One end of second wiring 62 is connected to inner electrode 71 of quantum bit 1A via capacitor 64A, and the other end is connected to inner electrode 71 of quantum bit 1B via capacitor 64B.

[0039] A gap is formed between arc-shaped pattern 65A connected to one end of first wiring 61 and outer electrode 72 of quantum bit 1A. This forms capacitor 63A, with arc-shaped pattern 65A as one electrode and outer electrode 72 of quantum bit 1A as the other electrode. Similarly, a gap is formed between arc-shaped pattern 65B connected to the other end of first wiring 61 and outer electrode 72 of quantum bit 1B. This forms capacitor 63B, with arc-shaped pattern 65B as one electrode and outer electrode 72 of quantum bit 1B as the other electrode. One end of first wiring 61 is connected to outer electrode 72 of quantum bit 1A via capacitor 63A, and the other end is connected to outer electrode 72 of quantum bit 1B via capacitor 63B.

[0040] According to the quantum bit device 100A of the second embodiment of the disclosed technology, as in the first embodiment, it is possible to configure the coupling line formed between one quantum bit and other adjacent quantum bits using differential wiring. It is also possible to improve the efficiency of extracting the electromagnetic field from the quantum bit 1. Furthermore, since the first wiring 61 and the second wiring 62 are coupled to the quantum bit 1 without contact, it is possible to suppress characteristic variations due to poor bump connections, etc.

[0041] In the above description, the case where both the first wiring 61 and the second wiring 62 are connected to the quantum bit via a capacitor has been exemplified, but one of the first wiring 61 and the second wiring 62 may be connected to the quantum bit via a capacitor. However, in order to increase the symmetry of the first wiring 61 and the second wiring 62, it is preferable that both the first wiring 61 and the second wiring 62 are connected to the quantum bit via a capacitor.

[0042] [Third embodiment] 18 is a plan view showing an example of the layout of the first wiring 61 and the second wiring 62 according to the third embodiment of the disclosed technology. In the first and second embodiments described above, the first wiring 61 has a pattern that extends in a straight line. In the third embodiment, the first wiring 61 has a meandering pattern.

[0043] The distance between outer electrode 72 of quantum bit 1A and outer electrode 72 of quantum bit 1B is shorter than the distance between inner electrode 71 of quantum bit 1A and inner electrode 71 of quantum bit 1B. Therefore, if first wiring 61 formed between outer electrode 72 of quantum bit 1A and outer electrode 72 of quantum bit 1B is patterned to extend in a straight line, the length of first wiring 61 will be shorter than the length of second wiring 62, and the symmetry of first wiring 61 and second wiring 62 forming a differential pair will be lost.

[0044] In the quantum bit device according to the third embodiment, the first wiring 61 has a meandering pattern, which makes it possible to align the wiring lengths of the first wiring 61 and the second wiring 62. This increases the symmetry of the first wiring 61 and the second wiring 62 that form a differential pair, making it possible to configure ideal differential wiring.

[0045] 19 shows the results of a simulation of loss when signal transmission is performed between quantum bits coupled by a coupled line configured with asymmetric differential wiring. In order to simulate a state in which the wiring lengths of first wiring 61 and second wiring 62 are asymmetric, an inductor component was inserted into one of the differential wirings. In this case, the loss was approximately -4 dB to -8 dB. On the other hand, when signal transmission is performed between quantum bits using a coupled line configured with symmetric differential wiring, the loss is approximately -3 dB (see FIG. 14B). In this way, by increasing the symmetry of the differential wiring, the efficiency of signal transmission between quantum bits can be further improved.

[0046] 18 illustrates the first wiring 61 having a crank-shaped meandering pattern, but the shape of the meandering pattern is not particularly limited, and the first wiring 61 may have, for example, an arc-shaped meandering pattern. Also, while Fig. 18 illustrates the case where the second wiring 62 has a pattern that extends in a straight line, both the first wiring 61 and the second wiring 62 may have meandering patterns. In this case, it is preferable to determine the shape of the meandering pattern of each wiring so that the wiring lengths of the first wiring 61 and the second wiring 62 are the same.

[0047] 20A, when the quantum bit substrate 10 has a plurality of vias 19 penetrating the substrate, the first wiring 61 may meander to avoid the vias 19. Alternatively, as shown in Fig. 20B, the vias 19 may be arranged to avoid the first wiring 61 having a meandering pattern. The vias 19 may serve, for example, to supply a ground potential from one surface of the quantum bit substrate 10 to the other surface.

[0048] [Fourth embodiment] 21 is a plan view showing an example of the layout of the first wiring 61 and the second wiring 62 according to the fourth embodiment of the disclosed technology. In the quantum bit devices according to the first to third embodiments described above, of the first wiring 61 and second wiring 62 that constitute a differential pair, only the second wiring 62 is provided on the connection substrate 20. In the quantum bit device according to the fourth embodiment, both the first wiring 61 and the second wiring 62 are provided on the connection substrate 20.

[0049] One end of second wiring 62 is connected to inner electrode 71 of quantum bit 1A via capacitor 64A, which has coupling pad 22A as one electrode and inner electrode 71 of quantum bit 1A as the other electrode. Similarly, the other end of second wiring 62 is connected to inner electrode 71 of quantum bit 1B via capacitor 64B, which has coupling pad 22B as one electrode and inner electrode 71 of quantum bit 1B as the other electrode. Coupling pads 22A and 22B each have substantially the same circular pattern as inner electrode 71, and are provided at positions that overlap inner electrodes 71 of the corresponding quantum bits in a plan view.

[0050] One end of first wiring 61 is connected to outer electrode 72 of quantum bit 1A via capacitor 66A, which has coupling pad 24A as one electrode and outer electrode 72 of quantum bit 1A as the other electrode. Similarly, the other end of first wiring 61 is connected to outer electrode 72 of quantum bit 1B via capacitor 66B, which has coupling pad 24B as one electrode and outer electrode 72 of quantum bit 1B as the other electrode. Coupling pads 24A and 24B each have an arc-shaped pattern corresponding to the annular pattern of outer electrode 72, and are provided at positions that overlap outer electrodes 72 of the corresponding quantum bits in a plan view.

[0051] The quantum bit device according to the fourth embodiment, like the first embodiment, allows the coupling lines that form capacitive coupling between adjacent quantum bits to be configured using differential wiring. This also improves the efficiency of extracting the electromagnetic field from the quantum bit 1. Furthermore, because both the first wiring 61 and the second wiring 62 are provided on the connection substrate 20, the symmetry of the first wiring 61 and the second wiring 62 that form the differential pair can be enhanced, enabling the configuration of ideal differential wiring. To further enhance the symmetry of the first wiring 61 and the second wiring 62, it is preferable that the capacitances of the capacitors 64A, 64B, 66A, and 66B be approximately the same. The capacitances of the capacitors 66A and 66B can be set by adjusting the area of ​​the overlapping portions of the coupling pads 24A and 24B and the outer electrode 72. The above areas can be set, for example, by adjusting the arc lengths of the coupling pads 24A and 24B.

[0052] The following additional notes are disclosed regarding the first to fourth embodiments described above. (Appendix 1) a qubit substrate having a first qubit and a second qubit; a connection substrate provided opposite the quantum bit substrate; a coupling line including a first wiring and a second wiring that form a differential pair, and that forms capacitive coupling between the first quantum bit and the second quantum bit; and At least one of the first wiring and the second wiring is provided on the connection substrate. qubit device.

[0053] (Appendix 2) Each of the first quantum bit and the second quantum bit is a Josephson element having a pair of superconductors joined by a Josephson junction; an inner electrode connected to one of the pair of superconductors; an annular outer electrode connected to the other of the pair of superconductors and surrounding the inner electrode; Including, the first wiring is connected to the outer electrode, The second wiring is connected to the inner electrode. 10. The qubit device of claim 1.

[0054] (Appendix 3) The second wiring is provided on the connection substrate. 1. The qubit device of claim 2.

[0055] (Appendix 4) Both the first wiring and the second wiring are provided on the connection substrate. 10. The qubit device of claim 1 or 2.

[0056] (Appendix 5) At least one of the first wiring and the second wiring is meandering. 5. The quantum bit device of any one of claims 1 to 4.

[0057] (Appendix 6) The first wiring and the second wiring have the same length. 6. The qubit device of claim 5.

[0058] (Appendix 7) the first wiring is connected to the first quantum bit via a capacitor; The second wiring is connected to the second quantum bit via a capacitor. 7. The quantum bit device of any one of claims 1 to 6.

[0059] (Appendix 8) The quantum bit substrate has three or more quantum bits including the first quantum bit and the second quantum bit. 8. The quantum bit device of any one of claims 1 to 7.

[0060] (Appendix 9) forming a qubit substrate having a first qubit and a second qubit; forming a connection substrate; positioning the quantum bit substrate and the connection substrate so that the quantum bit substrate and the connection substrate face each other; Including, a coupling line including a first wiring and a second wiring that form a differential pair, and that forms capacitive coupling between the first quantum bit and the second quantum bit, and at least one of the first wiring and the second wiring is provided on the connection substrate; A method for manufacturing a quantum bit device.

[0061] (Appendix 10) Each of the first quantum bit and the second quantum bit is a Josephson element having a pair of superconductors joined by a Josephson junction; an inner electrode connected to one of the pair of superconductors; an annular outer electrode connected to the other of the pair of superconductors and surrounding the inner electrode; Including, the first wiring is connected to the outer electrode, The second wiring is connected to the inner electrode. The manufacturing method described in Appendix 9.

[0062] (Appendix 11) The second wiring is provided on the connection substrate. The manufacturing method described in Appendix 9.

[0063] (Appendix 12) Both the first wiring and the second wiring are provided on the connection substrate. The method of manufacturing according to claim 9 or 10.

[0064] (Appendix 13) At least one of the first wiring and the second wiring is meandering. 13. The method of any one of claims 9 to 12.

[0065] (Appendix 14) The first wiring and the second wiring have the same length. The manufacturing method described in Appendix 13.

[0066] (Appendix 15) the first wiring is connected to the first quantum bit via a capacitor; The second wiring is connected to the second quantum bit via a capacitor. 15. The method of any one of claims 9 to 14.

[0067] (Appendix 16) The quantum bit substrate has three or more quantum bits including the first quantum bit and the second quantum bit. 16. The method of any one of claims 9 to 15. [Explanation of symbols]

[0068] 1, 1A, 1B qubits 4 Josephson element 10 qubit substrate 20 Connection board 60 Coupled Line 61 1st wiring 62 2nd wiring 71 Inner electrode 72 Outer electrode 73A, 73B Superconductors 100, 100A Qubit Device

Claims

1. a qubit substrate having a first qubit and a second qubit; a connection substrate provided opposite the quantum bit substrate; a coupling line including a first wiring and a second wiring that form a differential pair, and that forms capacitive coupling between the first quantum bit and the second quantum bit; and At least one of the first wiring and the second wiring is provided on the connection substrate. qubit device.

2. Each of the first quantum bit and the second quantum bit is a Josephson element having a pair of superconductors joined by a Josephson junction; an inner electrode connected to one of the pair of superconductors; an annular outer electrode connected to the other of the pair of superconductors and surrounding the inner electrode; Including, the first wiring is connected to the outer electrode, The second wiring is connected to the inner electrode. The quantum bit device of claim 1 .

3. The second wiring is provided on the connection substrate. The quantum bit device of claim 2 .

4. Both the first wiring and the second wiring are provided on the connection substrate. The quantum bit device of claim 1 or 2.

5. At least one of the first wiring and the second wiring is meandering. The quantum bit device of claim 1 .

6. The first wiring and the second wiring have the same length. The quantum bit device of claim 4 .

7. the first wiring is connected to the first quantum bit via a capacitor; The second wiring is connected to the second quantum bit via a capacitor. The quantum bit device of claim 1 .

8. forming a qubit substrate having a first qubit and a second qubit; forming a connection substrate; positioning the quantum bit substrate and the connection substrate so that the quantum bit substrate and the connection substrate face each other; Including, a coupling line including a first wiring and a second wiring that form a differential pair, and that forms capacitive coupling between the first quantum bit and the second quantum bit, and at least one of the first wiring and the second wiring is provided on the connection substrate; A method for manufacturing a quantum bit device.

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