Indication device

Abstract

A display device capable of suppressing a decrease in reliability is provided. [Solution] According to an embodiment, a display device comprises a substrate, a first inorganic insulating layer arranged above the substrate over a display area for displaying an image and a peripheral area surrounding the display area, pads arranged above the first inorganic insulating layer in the peripheral area, a dam arranged above the first inorganic insulating layer and surrounding the display area, and an organic insulating layer connected to the dam, formed continuously between the dam and the pad, and having a first opening overlapping the pad.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer as well as functional layers such as a hole transport layer and an electron transport layer. Technology to prevent a decrease in reliability is needed for such display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device comprises a substrate, a first inorganic insulating layer arranged above the substrate over a display area for displaying an image and a peripheral area surrounding the display area, pads arranged above the first inorganic insulating layer in the peripheral area, a dam arranged above the first inorganic insulating layer and surrounding the display area, and an organic insulating layer connected to the dam, formed continuously between the dam and the pad, and having a first opening overlapping the pad. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the configuration of the mounting area of ​​the display device shown in FIG. [Figure 5] FIG. 5 is a plan view showing an example of the configuration of the mounting area of ​​the display device shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the display device taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a display device according to a comparative example. [Figure 10] FIG. 10 is a schematic cross-sectional view of a display device according to the second embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of a display device according to the second embodiment. [Figure 12] FIG. 12 is a schematic plan view of a display device according to the third embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of the display device taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the display device taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a display device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described with reference to the drawings. The disclosure is merely an example, and any appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention.

[0008] In addition, in order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0010] In the following description, "overlapping" refers not only to a case where another element overlaps a target element from the third direction Z, but also to a case where another element overlaps a target element from the direction opposite to the third direction Z. Furthermore, "overlapping" refers not only to a case where the target elements come into contact with each other, but also to a state where the target elements are spaced apart from each other, or a state where another element is located between the target elements.

[0011] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes a substrate 10, a plurality of conductive pads PD, and a flexible substrate FPC connected to the pads PD. The substrate 10 has a circular main body 10a and an extension 10b extending from the main body 10a in the second direction Y. The extension 10b is formed in a trapezoidal shape whose width in the first direction X decreases with increasing distance from the main body 10a. The extension 10b has a substrate end 10c extending in the first direction X.

[0013] However, the shape of the substrate 10 in plan view may be other shapes such as a rectangle, a square, an ellipse, etc. The substrate 10 is formed of an insulating material such as glass or plastic.

[0014] The display device DSP further includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The display area DA overlaps the main body 10a in a planar view. In this embodiment, the shape of the display area DA in a planar view is circular. However, the shape of the display area DA in a planar view may be other shapes such as rectangular, square, or elliptical.

[0015] The peripheral area SA has a mounting area MA. The mounting area MA corresponds to the area overlapping the extension portion 10b in a plan view. A plurality of pads PD are provided in the mounting area MA. In the example shown in FIG. 1, the pads PD are arranged at intervals in the first direction X. The flexible substrate FPC is connected to the pads PD via an adhesive, which will be described later. In addition to the flexible substrate FPC, an IC chip or the like may also be mounted in the mounting area MA.

[0016] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. For example, the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. Note that the pixel PX may include four or more subpixels, including subpixels of other colors such as white, in addition to the above three subpixels.

[0017] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0018] In the pixel switch 2, the gate electrode is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the example shown in FIG. 1, the scanning line GL extends in a first direction X, and the signal line SL extends in a second direction Y. The signal line SL connects the pixel circuit 1 and the pad PD. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element DE. Note that the configuration of the pixel circuit 1 is not limited to the example shown in the figure.

[0019] The display device DSP further includes a dam ID surrounding the display area DA, and a dam OD surrounding the display area DA and the dam ID. The dam ID and the dam OD are each disposed in the peripheral area SA.

[0020] The dam ID has an arc portion IDa and a linear portion IDb extending in the first direction X. The dam OD has an arc portion ODa and a linear portion ODb extending in the first direction X. The centers of the arc portion IDa, the arc portion ODa, the display area DA, and the main body 10a are aligned with each other. However, the centers of the arc portion IDa, the arc portion ODa, the display area DA, and the main body 10a do not have to be aligned with each other.

[0021] The linear portions IDb and ODb are located between the display area DA and the pads PD. The number of dams provided in the display device DSP is not limited to two, i.e., the dam ID and the dam OD, but may be one or three or more.

[0022] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the first direction X. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the second direction Y.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example shown in FIG.

[0024] A rib layer 5 is disposed in the display area DA. In this embodiment, the rib layer 5 corresponds to the second inorganic insulating layer. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example shown in FIG. 2, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3.

[0025] That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio. Note that the sizes of the pixel apertures AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel apertures AP1, AP2, and AP3 may have the same size.

[0026] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0027] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0028] In the display area DA, partition walls 6 are arranged. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example shown in FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3, respectively.

[0029] From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a plan view and surround each of the display elements DE1, DE2, and DE3. The partition walls 6 surround pixel openings AP1, AP2, and AP3. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0030] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 (more specifically, the drain electrodes of the drive transistors 3 shown in FIG. 1) through contact holes (not shown). Each of the contact holes (not shown) overlaps the rib layer 5 and the partition wall 6.

[0031] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0032] The lower electrodes LE1, LE2, and LE3 are each disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are all covered with the rib layer 5.

[0033] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. In other words, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0034] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5. Furthermore, in the example shown in Figure 3, the upper part 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64. The second top layer 66 is disposed on the first top layer 65.

[0035] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0036] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0037] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0038] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3. That is, the sealing layers SE11, SE12, and SE13 are disposed above the upper electrodes UE1, UE2, and UE3 and the partition wall 6.

[0039] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0040] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0041] Furthermore, a resin layer RS1 is arranged to cover the sealing layers SE11, SE12, and SE13, a sealing layer SE2 is arranged to cover the resin layer RS1, and a resin layer RS2 is arranged to cover the sealing layer SE2. In this embodiment, the resin layer RS1 corresponds to the first resin layer, and the resin layer RS2 corresponds to the second resin layer. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously at least throughout the entire display area DA, and a portion of them extends into the peripheral area SA.

[0042] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). Color filters corresponding to the colors of the subpixels SP1, SP2, and SP3 may be disposed above the display elements DE1, DE2, and DE3, respectively.

[0043] The organic insulating layer 12 is made of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0044] In one example, the rib layer 5 is made of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are made of silicon nitride. The resin layers RS1 and RS2 are made of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0045] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent electrode made of an oxide conductive material such as ITO and a metal electrode made of a metal material such as silver. The upper electrodes UE1, UE2, and UE3 are made of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0046] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the third direction Z. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emitting layers.

[0047] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0048] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel current corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0049] The organic layers OR1, OR2, and OR3 emit light in response to the current that flows through them. Specifically, when a current flows between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a current flows between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a current flows between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0050] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0051] The bottom layer 63 and the shaft layer 64 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), and molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), and aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a multi-layer structure. The shaft layer 64 may also include a layer formed of an insulating material. Furthermore, the lower portion 61 may have a single-layer structure formed of a conductive material.

[0052] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. Examples of the metal material for the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide for the second top layer 66 include indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). The upper portion 62 may have a single-layer structure made of a specific material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0053] 4 and 5 are plan views showing an example of the configuration of the mounting area MA of the display device DSP shown in Fig. 1. Fig. 4 and 5 show the vicinity of the substrate edge 10c. A plurality of pads PD are aligned in the first direction X and extend in the second direction Y.

[0054] 4 and 5, a display area DA is formed in the upper part of the figure. In Fig. 4 and 5, the flexible substrate FPC shown in Fig. 1 is indicated by a dashed line. In Fig. 5, the rib layer 5 is omitted from the configuration example shown in Fig. 4. In Fig. 5, the organic insulating layer 12 is indicated by dots.

[0055] As shown in Figures 4 and 5, the rib layer 5 and the organic insulating layer 12 are arranged not only in the display area DA but also in the mounting area MA (peripheral area SA). As shown in Figure 4, the rib layer 5 is formed up to the substrate edge 10c. In contrast, as shown in Figure 5, the organic insulating layer 12 is not formed up to the substrate edge 10c. In other words, the peripheral area SA has an area A11 at the substrate edge 10c where the organic insulating layer 12 is not formed.

[0056] The organic insulating layer 12 has a plurality of protrusions 12P overlapping with the pads PD. The protrusions 12P are shaped to protrude toward the substrate edge 10c. As shown in FIG. 5, the organic insulating layer 12 has openings 121 (first openings) in the protrusions 12P overlapping with the pads PD.

[0057] 4, the rib layer 5 has openings 51 (second openings) overlapping with the pads PD. The openings 51 of the rib layer 5 overlap with the openings 121 of the organic insulating layer 12. In the example shown in FIG. 4, the openings 51 and the openings 121 overlap with one pad PD.

[0058] The openings 51 in the rib layer 5 and the openings 121 in the organic insulating layer 12 extend in a direction different from the direction in which the pads PD are arranged. The openings 51 and 121 extend, for example, in the second direction Y. Specifically, the openings 51 and 121 have a rectangular shape that is elongated in the second direction Y.

[0059] 4, the area of ​​opening 121 is larger than the area of ​​opening 51 in plan view. The edge of opening 121 is located outside the edge of opening 51. Therefore, organic insulating layer 12 is not exposed from opening 51.

[0060] 5, the organic insulating layer 12 further has slits 123. The slits 123 are formed between adjacent pads PD (protrusions 12P). The multiple slits 123 extend in the second direction Y and are aligned in the first direction X. The slits 123 open toward the substrate end 10c. In other words, the slits 123 are connected to the region A11 of the substrate end 10c.

[0061] 5, the organic insulating layer 12 further has slits 125 and 127 in the mounting area MA. A plurality of pads PD are located between the slits 125 and 127. The slits 125 and 127 are connected to the area A11 of the substrate end 10c. The rib layer 5 overlaps the slits 123, 125, and 127 and the area A11 in a plan view.

[0062] 5, the display device DSP further includes a plurality of metal layers M1, M2, M3, and M4. Each of the metal layers M1, M2, M3, and M4 extends in the second direction Y. Adjacent metal layers M1, M2, M3, and M4 are arranged at intervals in the first direction X. The pad PD is formed by the metal layers M3 and M4.

[0063] Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line VI-VI in Fig. 5. Fig. 7 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in Fig. 5.

[0064] As described above, the display device DSP includes the circuit layer 11. The circuit layer 11 is disposed above the substrate 10 across the display area DA and the peripheral area SA (mounting area MA). The circuit layer 11 has inorganic insulating layers 111, 112, and 113. In this embodiment, the inorganic insulating layer 113 corresponds to the first inorganic insulating layer. The above-described metal layers M1 and M2, together with the inorganic insulating layers 111, 112, and 113, form the circuit layer 11.

[0065] The inorganic insulating layer 111 is disposed on the substrate 10. The metal layer M1 is disposed on the inorganic insulating layer 111. The metal layer M1 is formed, for example, in the same layer as the scanning lines GL. The inorganic insulating layer 112 is disposed on the inorganic insulating layer 111 and the metal layer M1. As shown in FIG. 7, the inorganic insulating layer 112 has a contact hole CH1 that overlaps with the metal layer M1.

[0066] As shown in FIG. 7, the metal layer M2 is disposed on the inorganic insulating layer 112. The metal layer M2 is formed, for example, in the same layer as the signal lines SL. The metal layer M2 extends toward the display area DA. The metal layer M2 is electrically connected to the metal layer M1 via a contact hole CH1. The inorganic insulating layer 113 is disposed on the inorganic insulating layer 112 and the metal layer M2. The inorganic insulating layer 113 has a contact hole CH2 that overlaps the metal layer M2.

[0067] The metal layer M3 is located directly above the metal layer M1 in the peripheral area SA, and is disposed on the inorganic insulating layer 113. The metal layer M3 is electrically connected to the metal layer M2 via a contact hole CH2.

[0068] The organic insulating layer 12 is disposed on the inorganic insulating layer 113 and the metal layer M3. As shown in Figures 6 and 7, the organic insulating layer 12 covers the entire periphery of the metal layer M3.

[0069] The organic insulating layer 12 has a plurality of portions with different thicknesses. As shown in Fig. 7, the organic insulating layer 12 has a first portion P1 and a second portion P2 connected to the first portion P1. The opening 121 is included in the second portion P2.

[0070] The second portion P2 has a thickness smaller than that of the first portion P1. Here, the thickness of the first portion P1 corresponds to the distance from the upper surface of the inorganic insulating layer 113 along the third direction Z, and the thickness of the second portion P2 corresponds to the distance from the upper surface of the metal layer M3 along the third direction Z.

[0071] 7, a metal layer M2 is disposed below the first portion P1, and no metal layer M2 is disposed below the second portion P2. The first portion P1 and the second portion P2 form a step portion 12a in the organic insulating layer 12. For example, the portion of the organic insulating layer 12 that is closer to the pad PD than the step portion 12a corresponds to the second portion P2. The second portion P2 may have a thickness equivalent to that of the first portion P1.

[0072] The rib layer 5 is disposed on the organic insulating layer 12 and the inorganic insulating layer 113. In other words, the rib layer 5 covers the organic insulating layer 12 and the inorganic insulating layer 113. As shown in FIG. 6 , the inorganic insulating layer 113 is exposed from the organic insulating layer 12 between adjacent pads PD (at the slits 123).

[0073] Therefore, the rib layer 5 is in contact with the inorganic insulating layer 113 between adjacent pads PD. In other words, the inorganic insulating layer 113 is covered by the rib layer 5 at the slits 123. The metal layer M3 is exposed from the openings 121 of the organic insulating layer 12 and the openings 51 of the rib layer 5.

[0074] The metal layer M4 is disposed on the metal layer M3 and the rib layer 5. The pad PD is disposed above the inorganic insulating layer 113. The metal layer M4 is electrically connected to the metal layer M3 via the opening 121 in the organic insulating layer 12 and the opening 51 in the rib layer 5. The metal layer M4 overlaps the peripheral edge of the opening 51 in the rib layer 5.

[0075] The inorganic insulating layers 111, 112, and 113 are made of silicon oxide, silicon nitride, or silicon oxynitride. The metal layers M2, M3, and M4 are made of, for example, a plurality of layers.

[0076] In one example, the metal layers M2, M3, and M4 have two titanium layers made of a titanium-based material and an aluminum layer made of an aluminum-based material located between the two titanium layers. Note that at least one of the metal layers M2, M3, and M4 may be formed by disposing an aluminum layer between layers made of a molybdenum-based material.

[0077] FIG. 8 is a schematic cross-sectional view of the display device DSP taken along line VIII-VIII in FIG.

[0078] The circuit layer 11 further includes an organic insulating layer 114 formed of an organic insulating material. The organic insulating layer 114 is disposed on the inorganic insulating layer 113. The organic insulating layer 114 is covered with the organic insulating layer 12. In the example shown in FIG. 8, the organic insulating layer 114 is located inside the dam ID.

[0079] A sealing layer SE1x is disposed on the rib layer 5. The sealing layer SE1x is formed by the same process and from the same material as any one of the sealing layers SE11, SE12, and SE13 shown in FIG. 3. In this embodiment, the sealing layers SE11, SE12, SE13, and SE1x correspond to the first sealing layer, and the sealing layer SE2 corresponds to the second sealing layer. The resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in FIG. 3 are disposed above the sealing layer SE1x. The resin layer RS1 covers the sealing layer SE1x and the rib layer 5.

[0080] As described above, the display device DSP includes the dam ID and the dam OD. Both the dam ID and the dam OD protrude upward from the substrate 10. The dam ID and the dam OD are disposed on the inorganic insulating layer 113. The dam ID and the dam OD are covered with the rib layer 5.

[0081] The dam ID has the function of blocking the resin layer RS1. The dam ID has a protrusion ID1 and a protrusion ID2. The protrusion ID2 covers the protrusion ID1. In the example shown in FIG. 8, the end R1E of the resin layer RS1 is located to the side of the dam ID. However, the position of the end R1E is not limited to this example.

[0082] The dam OD has the function of blocking the resin layer RS2. The dam OD has a protrusion OD1 and a protrusion OD2. The protrusion OD2 covers the protrusion OD1. In the example shown in FIG. 8, the end R2E of the resin layer RS2 is located directly above the dam OD. That is, the resin layer RS2 covers a portion of the dam OD. However, the position of the end R2E is not limited to this example.

[0083] Focusing on the organic insulating layer 12, the first portion P1 of the organic insulating layer 12 is connected to the protrusion OD2. In other words, the organic insulating layer 12 is continuously formed between the dam OD and the pad PD. That is, the organic insulating layer 12 is not divided between the dam OD and the pad PD. In the example shown in FIG. 8, the region including the portion protruding in the third direction Z beyond the first portion P1 of the organic insulating layer 12 corresponds to the protrusion OD2 of the dam OD (straight portion ODb).

[0084] The protrusions ID1 and OD1 are formed, for example, from the same material and through the same manufacturing process as the organic insulating layer 114. The protrusions ID2 and OD2 are formed, for example, from the same material and through the same manufacturing process as the organic insulating layer 12. That is, in this embodiment, the dams ID and OD are formed from the same material as the organic insulating layers 114 and 12 and in the same layer as the organic insulating layers 114 and 12.

[0085] The rib layer 5 covers the organic insulating layer 12, the dam ID, and the dam OD. The sealing layer SE2 overlaps the dam ID (straight line portion IDb) and the dam OD (straight line portion ODb), respectively. In contrast, the sealing layer SE1x does not overlap the dam ID (straight line portion IDb) or the dam OD (straight line portion ODb), respectively.

[0086] The display device DSP further includes a polarizing plate 16 and protective members PO1 and PO2. The polarizing plate 16 is disposed above the sealing layer SE2. Specifically, the polarizing plate 16 is adhered to the resin layer RS2 by an adhesive AD1. The adhesive AD1 is formed of, for example, OCA (Optical Clear Adhesive).

[0087] 8, the end 16E of the polarizing plate 16 is located directly above the dam OD. That is, the dam OD overlaps the end 16E of the polarizing plate 16 in a planar view. However, the dam OD does not have to overlap the end 16E in a planar view.

[0088] The end S1E of the sealing layer SE1x is located inside the dam ID. The end S2E of the sealing layer SE2 is located outside the dam ID. In the example shown in FIG. 8, the end S2E of the sealing layer SE2 is located above the dam OD.

[0089] In the region outside the dam ID, the sealing layer SE2 is in contact with the rib layer 5. In other words, the sealing layer SE2 and the rib layer 5 are in contact between the display area DA and the dam OD. The resin layer RS1 is surrounded by the sealing layer SE1x, the rib layer 5, and the sealing layer SE2. This prevents moisture from penetrating into the resin layer RS1.

[0090] The flexible substrate FPC is adhered to the metal layer M4 by an adhesive AD2. In the example shown in FIG. 8, the adhesive AD2 covers not only the metal layer M4 but also a portion of the rib layer 5. The adhesive AD2 may be a conductive material such as an anisotropic conductive film. In addition, the end portion FPCE of the flexible substrate FPC overlaps the second portion P2 of the organic insulating layer 12. Here, the end portion includes the end portion and the area nearby.

[0091] The protective member PO1 is disposed between the polarizing plate 16 and the pad PD and above the rib layer 5. The protective member PO1 contacts the end 16E of the polarizing plate 16 and covers the end FPCE of the flexible substrate FPC. The protective member PO2 contacts the substrate 10, the circuit layer 11, the adhesive AD2, the flexible substrate FPC, etc.

[0092] The protective members PO1 and PO2 are formed of a resin material such as epoxy resin or acrylic resin. The protective member PO1 has a function of preventing moisture from penetrating into the mounting area MA, for example, between the end 16E of the polarizing plate 16 and the end FPCE of the flexible substrate FPC. The protective member PO2 has a function of preventing moisture from penetrating into the mounting area MA from the substrate end 10c of the substrate 10, for example.

[0093] 9 is a schematic cross-sectional view of a display device DSP10 according to a comparative example. The display device DSP10 according to the comparative example differs from the display device DSP according to this embodiment in that the organic insulating layer 12 has slits 200.

[0094] The slits 200 are located between the display area DA and the pads PD. The slits 200 are formed along the first direction X. As shown in FIG. 9 , the inorganic insulating layer 113 is exposed from the organic insulating layer 12 at the slits 200. The rib layer 5 covers the inorganic insulating layer 113 at the slits 200.

[0095] The organic insulating layer 12 has the slits 200, which causes a step portion 12b to be formed in the organic insulating layer 12. The size of the step portion 12b in the third direction Z is larger than the size of the step portion 12a (shown in FIG. 7) in the third direction Z.

[0096] Such step portion 12b may cause material forming the lower electrode to remain in the slit 200 (remaining portion LM shown in Figure 9), or stress may be concentrated in the rib layer 5 overlapping the step portion 12b, which may cause a crack to occur in the rib layer 5 (crack CR shown in Figure 9).

[0097] Such cracks CR can become paths for moisture to penetrate. The penetration of moisture from the remaining portions LM and cracks CR in the slits 200 can cause corrosion of the wiring (e.g., metal layers M2, M3, etc.). Such corrosion of the wiring leads to a decrease in the reliability of the display device DSP.

[0098] In this embodiment, the organic insulating layer 12 is not divided between the dam OD and the first portion P1. Specifically, the organic insulating layer 12 is continuously formed between the dam OD and the pad PD.

[0099] In other words, the organic insulating layer 12 according to this embodiment is flatter in the first portion P1 than the organic insulating layer 12 of the display device DSP10 according to the comparative example, and does not have a step portion 12b. This makes it possible to suppress the occurrence of the remaining portion LM (shown in FIG. 9) and to suppress the occurrence of cracks by making it difficult for stress to concentrate on the rib layer 5. As a result, the wiring is less susceptible to corrosion, and a decrease in the reliability of the display device DSP can be suppressed.

[0100] Furthermore, in this embodiment, the rib layer 5 made of an inorganic insulating material is in contact with and firmly adheres to the inorganic insulating layer 113 via the slits 123. This improves the adhesion between the rib layer 5 and the base layer, making it possible to prevent the rib layer 5 from peeling off.

[0101] Furthermore, in this embodiment, the organic insulating layer 12 has a first portion P1 and a second portion P2 having a thickness smaller than that of the first portion P1. The flexible substrate FPC is disposed above the second portion P2.

[0102] This makes it possible to reduce the step between the flexible substrate FPC and the first portion P1 of the organic insulating layer 12 when the flexible substrate FPC is disposed. Also, in the region where the flexible substrate FPC does not overlap, the thickness can be increased by the first portion P1, so that the elements below the organic insulating layer 12 can be sufficiently protected.

[0103] As described above, the configuration of this embodiment can provide a display device DSP that can suppress a decrease in reliability. In addition, this embodiment can provide various other advantageous effects.

[0104] Next, other embodiments will be described. In the other embodiments described below, the same components as those in the first embodiment described above will be assigned the same reference numerals as those in the first embodiment, and detailed descriptions thereof may be omitted or simplified.

[0105] [Second embodiment] 10 and 11 are schematic cross-sectional views of the display device DSP according to this embodiment. Fig. 11 shows an enlarged view of the pad PD and its vicinity in Fig. 10. In Fig. 11, some elements such as the flexible substrate FPC, adhesive AD2, and protective members PO1 and PO2 are omitted.

[0106] 10 and 11, the sealing layer SE2 in this embodiment extends further toward the pad PD than in the first embodiment. Specifically, the end S2E of the sealing layer SE2 is located closer to the pad PD than the end 16E of the polarizing plate 16.

[0107] 11, the sealing layer SE2 extends to a position where it overlaps the step portion 12a of the organic insulating layer 12. From another perspective, the sealing layer SE2 overlaps the first portion P1 of the organic insulating layer 12. From yet another perspective, the sealing layer SE2 overlaps a portion of the metal layer M3.

[0108] 10, the adhesive AD2 covers not only the metal layer M4 but also the rib layer 5 and part of the sealing layer SE2. The protective member PO1 overlaps the end S2E of the sealing layer SE2 and is in contact with the upper surface S2U of the sealing layer SE2. In the mounting area MA, the sealing layer SE2 is located between the rib layer 5 and the protective member PO1.

[0109] This embodiment can also achieve the same effects as the first embodiment. In this embodiment, the end S2E of the sealing layer SE2 is located closer to the pad PD than the end 16E of the polarizing plate 16. As a result, even if a crack occurs in the rib layer 5, the rib layer 5 is covered with the sealing layer SE2, making it difficult for moisture to penetrate into the mounting area MA, and reducing reliability.

[0110] [Third embodiment] Fig. 12 is a schematic plan view of the display device DSP according to this embodiment. Fig. 13 is a schematic cross-sectional view of the display device DSP taken along line XIII-XIII in Fig. 12. Fig. 14 is a schematic cross-sectional view of the display device DSP taken along line XIV-XIV in Fig. 12. This embodiment differs from the second embodiment in that it further includes an inorganic insulating layer IL. In Fig. 12, the organic insulating layer 12 is indicated by dots, and the inorganic insulating layer IL is indicated by diagonal lines.

[0111] 12, multiple inorganic insulating layers IL are arranged in the peripheral area SA. Focusing on the peripheral area SA, the multiple inorganic insulating layers IL are formed so as to cover the multiple protrusions 12P, respectively. The width of the inorganic insulating layers IL in the first direction X is larger than the width of the protrusions 12P in the first direction X.

[0112] The inorganic insulating layers IL have openings ILA (third openings) that overlap with the pads PD. The openings ILA overlap with the openings 121 of the organic insulating layer 12 and the openings 51 of the rib layer 5. The openings 51 have, for example, the same size as the openings ILA in a plan view.

[0113] The inorganic insulating layers IL adjacent to each other in the first direction X are spaced apart between the adjacent pads PD. In other words, a slit ILS is formed between the adjacent inorganic insulating layers IL.

[0114] 13 and 14, the inorganic insulating layer IL is disposed on the inorganic insulating layer 113, the metal layer M3, and the organic insulating layer 12. The inorganic insulating layer IL covers the organic insulating layer 12. Note that a portion of the organic insulating layer 12 is exposed from the inorganic insulating layer IL.

[0115] The peripheral edge of the organic insulating layer 12 is not exposed from the inorganic insulating layer IL at the protruding portion 12P. From another perspective, the inorganic insulating layer IL is in contact with the metal layer M3 in the opening 121 and in contact with the inorganic insulating layer 113 outside the opening 121 (for example, between adjacent pads PD), as shown in FIG.

[0116] The slits ILS of the inorganic insulating layer IL overlap the slits 123 of the organic insulating layer 12. The width of the slits ILS in the first direction X is, for example, smaller than the width of the slits 123 in the first direction X. As shown in FIG. 13 , the inorganic insulating layer 113 is exposed from the inorganic insulating layer IL between adjacent pads PD (slits ILS).

[0117] The rib layer 5 is disposed on the organic insulating layer 12 and the inorganic insulating layer 113, IL. In other words, the inorganic insulating layer IL is disposed between the organic insulating layer 12 and the rib layer 5. The rib layer 5 has, for example, a thickness greater than that of the inorganic insulating layer IL.

[0118] The rib layer 5 is in contact with the inorganic insulating layer 113 between adjacent pads PD. In other words, the inorganic insulating layer 113 is covered with the rib layer 5 at the slits ILS.

[0119] The metal layer M3 is exposed from the opening 121 in the organic insulating layer 12, the opening ILA in the inorganic insulating layer IL, and the opening 51 in the rib layer 5. The metal layer M4 is electrically connected to the metal layer M3 via the opening 121 in the organic insulating layer 12, the opening 51 in the rib layer 5, and the opening ILA in the inorganic insulating layer IL.

[0120] Fig. 15 is a schematic cross-sectional view of the display device DSP according to this embodiment. Focusing on the display area DA, as shown in Fig. 15, inorganic insulating layers IL1, IL2, and IL3 are disposed on the organic insulating layer 12. The inorganic insulating layer IL is formed, for example, from the same material and by the same manufacturing process as the inorganic insulating layers IL1, IL2, and IL3 in the display area DA.

[0121] The lower electrodes LE1, LE2, and LE3 are disposed on the inorganic insulating layers IL1, IL2, and IL3, respectively. That is, the inorganic insulating layers IL1, IL2, and IL3 are disposed between the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3 in the display area DA.

[0122] The inorganic insulating layers IL1, IL2, IL3, and IL are formed of, for example, a different inorganic insulating material from that of the rib layer 5. In this embodiment, the inorganic insulating layers IL1, IL2, IL3, and IL correspond to a third inorganic insulating layer. In one example, the inorganic insulating layers IL1, IL2, IL3, and IL are formed of silicon nitride, and the rib layer 5 is formed of silicon oxynitride.

[0123] This embodiment can also achieve the same effects as the second embodiment. In this embodiment, the organic insulating layer 12 is covered with the inorganic insulating layer IL, which can prevent the organic insulating layer 12 from being scraped off during the manufacturing process. In other words, the aluminum layer is less likely to be exposed from the sidewall of the metal layer M3.

[0124] This makes it possible to suppress deposition of silver near the metal layer M3 in the process of forming the lower electrodes LE1, LE2, and LE3, and to suppress the occurrence of poor electrical contact between the metal layer M3 and the metal layer M4. As a result, with this embodiment, it is possible to further suppress deterioration in the reliability of the display device DSP.

[0125] In this embodiment, an example has been disclosed in which the inorganic insulating layers IL adjacent to each other in the first direction X are spaced apart, but the adjacent inorganic insulating layers IL do not have to be spaced apart. In this case, the rib layer 5 made of an inorganic insulating material contacts the inorganic insulating layer IL between the adjacent pads PD.

[0126] All display devices that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices described above as embodiments of the present invention are within the scope of the present invention as long as they incorporate the gist of the present invention. Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also considered to be within the scope of the present invention. For example, displays in which a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions, to the above-described embodiments are also within the scope of the present invention as long as they incorporate the gist of the present invention.

[0127] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0128] 5...rib layer, 6...partition wall, 10...substrate, 11...circuit layer, 12...organic insulating layer, 51...opening, 61...lower part, 62...upper part, 111, 112, 113...inorganic insulating layer, 114...organic insulating layer, 123...slit, AP1, AP2, AP3...pixel opening, DA...display area, DE1, DE2, DE3...display element, DSP...display device, FPC...flexible substrate, ID...dam, IL, IL1, IL2, IL3...inorganic insulating layer, ILA...opening, LE1, LE2, LE3...lower electrode, M1, M2, M3, M4...metal layer, MA...mounting area, OD...dam, OR1, OR2, OR3...organic layer, P1...first part, P2...second part, PD...pad, PO1, PO2...protective material, RS1, RS2...resin layer, SA...peripheral area, SE1x, SE2, SE11, SE12, SE13...sealing layer, UE1, UE2, UE3...upper electrode.

Claims

1. A substrate; a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area surrounding the display area; a pad disposed above the first inorganic insulating layer in the peripheral region; a dam disposed above the first inorganic insulating layer and surrounding the display area; an organic insulating layer connected to the dam, continuously formed between the dam and the pad, and having a first opening overlapping the pad; Display device.

2. a second inorganic insulating layer covering the organic insulating layer and the dam and having a second opening overlapping the first opening; The display device according to claim 1 .

3. a lower electrode disposed above the organic insulating layer in the display area; the second inorganic insulating layer has a pixel opening overlapping the lower electrode in the display region; The display device according to claim 2 .

4. an organic layer that covers the lower electrode through the pixel opening and emits light in response to a current flowing therethrough; an upper electrode covering the organic layer; The display device according to claim 3 .

5. a partition wall surrounding the pixel opening in the display region; the partition wall includes a lower portion disposed above the second inorganic insulating layer and an upper portion having an end portion protruding from a side surface of the lower portion. The display device according to claim 4 .

6. a first sealing layer formed of an inorganic material and disposed above the upper electrode and the partition wall in the display region; a first resin layer covering the first sealing layer; a second sealing layer covering the first resin layer and made of an inorganic material; the second sealing layer is in contact with the second inorganic insulating layer between the dam and the display area; The display device according to claim 5 .

7. Further, a second resin layer covering the second sealing layer is provided. an end of the second resin layer is located above the dam; The display device according to claim 6.

8. further comprising a polarizing plate disposed above the second sealing layer; an end of the second sealing layer is located closer to the pad than an end of the polarizing plate; The display device according to claim 7 .

9. a polarizing plate disposed above the second sealing layer; a protective member in contact with an end of the polarizing plate and disposed above the second inorganic insulating layer, The display device according to claim 7 .

10. Further comprising a flexible substrate connected to the pad; The protective member covers an end portion of the flexible substrate. The display device according to claim 9 .

11. an end of the second sealing layer is located closer to the pad than an end of the polarizing plate; The display device according to claim 10.

12. The protective member overlaps the end portion of the second sealing layer. The display device according to claim 11.

13. Further comprising a flexible substrate connected to the pad; the organic insulating layer has a first portion connected to the dam and a second portion connected to the first portion and including the first opening; the second portion has a thickness less than that of the first portion; the flexible substrate overlaps the second portion; The display device according to claim 1 .

14. the organic insulating layer has slits formed between adjacent pads; The display device according to claim 2 .

15. the second inorganic insulating layer is in contact with the first inorganic insulating layer between adjacent pads; The display device according to claim 14.

16. Further comprising a third inorganic insulating layer; The third inorganic insulating layer is In the display area, the organic insulating layer is disposed between the organic insulating layer and the lower electrode, a third opening covering the organic insulating layer and overlapping the first opening in the peripheral region; The display device according to claim 3 .

17. the third inorganic insulating layer is in contact with the first inorganic insulating layer between adjacent pads; The display device according to claim 16.

18. the third inorganic insulating layer is formed of an inorganic insulating material different from that of the second inorganic insulating layer; The display device according to claim 16.

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