Liquid crystal display device

Abstract

In liquid crystal displays, the decrease in storage capacity due to higher resolution leads to a greater impact from parasitic capacitance and other factors. [Solution] This liquid crystal display device comprises a liquid crystal layer, pixel electrodes and common electrodes located below the liquid crystal layer and forming liquid crystal capacitance, an organic layer formed below the pixel electrodes and common electrodes, and relay electrodes formed below the organic layer and electrically connected to the pixel electrodes. The device comprises a capacitor electrode formed below the organic layer, which forms the relay electrode and the holding capacitance.

Description

Technical Field

[0001] The present disclosure relates to a liquid crystal display device.

Background Art

[0002] Patent Document 1 discloses a method for increasing the holding capacitance of a liquid crystal display device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When increasing the holding capacitance by a conventional method, there is a problem that the yield during manufacturing decreases.

Means for Solving the Problems

[0005] A liquid crystal display device according to an aspect of the present disclosure includes a liquid crystal layer, a pixel electrode and a common electrode that are located below the liquid crystal layer and form a liquid crystal capacitance, an organic layer formed below the pixel electrode and the common electrode, a relay electrode formed below the organic layer and electrically connected to the pixel electrode, and a capacitance electrode formed below the organic layer and forming a holding capacitance with the relay electrode.

Effects of the Invention

[0006] In a liquid crystal display device, it is possible to increase the holding capacitance while ensuring the yield during manufacturing.

Brief Description of the Drawings

[0007] [Figure 1] It is a plan view showing a configuration example of a liquid crystal display device according to this embodiment. [Figure 2]This is a cross-sectional view showing an example of the configuration of the display unit and non-display unit, including the cross-section aa in Figure 1. [Figure 3] This is a circuit diagram showing an example of the subpixel configuration of this liquid crystal display device. [Figure 4] This is a plan view that is an enlarged portion of Figure 1. [Figure 5] This is a plan view showing an example configuration of a liquid crystal display device. [Figure 6] This is a cross-sectional view showing an example of the configuration of a liquid crystal display device. [Figure 7] This is a cross-sectional view showing an example of the configuration of a liquid crystal display device. [Figure 8] This is a plan view showing an example configuration of a liquid crystal display device. [Figure 9] This is a plan view showing an example configuration of a liquid crystal display device. [Figure 10] This is a plan view showing example patterns of capacitive electrodes and intermediate electrodes. [Figure 11] This is a plan view showing example patterns of capacitive electrodes and intermediate electrodes. [Figure 12] This is a plan view showing example patterns of capacitive electrodes and intermediate electrodes. [Figure 13] This is a plan view showing example patterns of capacitive electrodes and intermediate electrodes. [Figure 14] This is a plan view showing example patterns of capacitive electrodes and intermediate electrodes. [Modes for carrying out the invention]

[0008] Figure 1 is a plan view showing an example configuration of a liquid crystal display device according to this embodiment. Figure 2 is a cross-sectional view showing an example configuration of a display unit and a non-display unit, including the cross-section aa in Figure 1. Figure 3 is a circuit diagram showing an example configuration of subpixels of this liquid crystal display device. Figure 4 is a plan view enlarged from a part of Figure 1. As shown in Figures 1 to 4, the liquid crystal display device 10 according to this embodiment comprises a liquid crystal layer 30, a pixel electrode PD and a common electrode CD located below the liquid crystal layer 30 and forming a liquid crystal capacitance LC, an organic layer YL formed below the pixel electrode PD and the common electrode CD, a relay electrode TD formed below the organic layer YL and electrically connected to the pixel electrode PD, and a capacitive electrode JD formed below the organic layer YL and forming a holding capacitance JC with the relay electrode TD.

[0009] Thus, by forming a capacitive electrode JD below the organic layer YL and adding a retaining capacity JC (lower layer retaining capacity), the overall retaining capacity can be increased while ensuring the yield during manufacturing. A retaining capacity PC (upper layer retaining capacity) may be formed in the area where the pixel electrode PD and the common electrode CD overlap via an insulating film 27 (for example, an inorganic insulating film). Note that "formed in the lower layer" means a state in which it is formed in a process earlier than the one being compared.

[0010] In the display section DA of the liquid crystal display device 10, the following layers are stacked in this order: light-shielding layer UA, insulating films 11 and 13 (e.g., inorganic insulating films), first scan line GA, insulating film 15 (e.g., inorganic insulating film), semiconductor layer (e.g., oxide semiconductor layer) SL, insulating film 17 (e.g., inorganic insulating film), second scan line GB, insulating film 19 (e.g., inorganic insulating film), source electrode SE, insulating film 21 (e.g., inorganic insulating film), capacitive electrode JD, insulating film 23 (e.g., inorganic insulating film), relay electrode TD, organic layer YL (including color filter CF and organic insulating film 24 on color filter CF), auxiliary electrode SD, insulating film 26 (e.g., planarization film), pixel electrode PD, insulating film 27 (e.g., inorganic insulating film), common electrode CD, light-shielding layer UB, and insulating film 29 (e.g., inorganic insulating film). The liquid crystal layer 30 is arranged on the insulating film 29 via an alignment film.

[0011] The first scanning line GA, the insulating film 15 (e.g., an inorganic insulating film), the semiconductor layer SL, the insulating film 17, and the second scanning line GB form the transistor TR. The source region of the semiconductor layer SL is connected to the source electrode SE through a contact hole HA penetrating the insulating film 19, and the source electrode SE is connected to the data line DL. A part of the data line DL may be the source electrode SE. The drain region of the semiconductor layer SL is connected to the relay electrode TD through a contact hole HB penetrating the insulating films 19, 21, and 23. The semiconductor layer SL may be an oxide semiconductor (e.g., indium gallium zinc oxide). The light-shielding layer UA may overlap with a photo spacer (not shown) in the liquid crystal layer 30 in plan view. The light-shielding layer UA may overlap with the semiconductor layer SL (e.g., an oxide semiconductor) in plan view.

[0012] The relay electrode TD is connected to the auxiliary electrode SD through a contact hole HD penetrating the organic layer YL (color filter CF, planarization film 24), and a part of the auxiliary electrode SD contacts the pixel electrode PD, so that the relay electrode TD and the pixel electrode PD are electrically connected. The electric field (horizontal electric field) from the pixel electrode PD reaches the common electrode CD through the opening KC of the common electrode CD and the liquid crystal layer 30, thereby controlling the transmittance of the liquid layer layer 30 (the vicinity of the opening KC).

[0013] For the capacitive electrode JD, the relay electrode TD, and the common electrode CD, a light-transmissive conductive film (e.g., indium tin oxide, indium zinc oxide, etc.) can be used, but it is not limited thereto. It may be a light-transmissive ultra-thin film (e.g., about 3.0 nm to 20 nm) such as silver, aluminum, magnesium silver alloy, etc.

[0014] Regarding an electrode film on a base (e.g., an organic layer) with large irregularities, there is a situation where it is difficult to perform high-precision patterning due to phenomena such as the resist becoming thick in the recessed parts while becoming thin in the parts other than the recessed parts. In this embodiment, by providing the capacitive electrode JD on the lower layer side of the organic layer YL with a large thickness, the capacitive electrode JD can be patterned accurately and stably. That is, according to this embodiment, defects such as leakage caused by film residue in the capacitive electrode formation process or disconnection due to film breakage in the capacitive electrode formation process are unlikely to occur. As a result, while maintaining a high yield, the charge holding capacity can be increased and the display quality can be improved.

[0015] The capacitive electrode JD in this embodiment is located above the first and second scanning lines GA and GB and the data line DL (source electrode SE), and below the relay electrode TD. For this reason, the parasitic capacitance between the relay electrode TD and the data line DL and the parasitic capacitance between the relay electrode TD and the scanning lines GA and GB are reduced, and the display quality can be further improved.

[0016] For the insulating films 11, 13, 15, 17, 19, 21, 23, 27, and 29, an inorganic insulating film (such as a silicon oxide film or a silicon nitride film) with a film thickness of about 0.05 μm to 0.5 μm can be used. The film thicknesses of the color filter CF, the organic insulating film 24, and the planarization layer 26 may each be about 1.0 μm to 3.0 μm. The organic layer YL may be thicker than each of the insulating films 11, 13, 15, 17, 19, 21, 23, 27, and 29. For the organic insulating film 24 and the planarization layer 26, polyimide or the like can be used.

[0017] As shown in FIGS. 1 to 4, the organic layer YL may include the color filter CF and may also include the organic insulating film 24 formed above the color filter CF. A common potential Vcom may be supplied to the common electrode CD and the capacitive electrode JD. The common potential Vcom may be a DC voltage.

[0018] The liquid crystal display device 10 includes data lines DL formed in a layer below the capacitive electrode JD, and a portion of the capacitive electrode JD may overlap with the data lines DL in a plan view. The capacitive electrode JD may be formed in a layer below the relay electrode TD, and an insulating film 23 (for example, an inorganic insulating film) may be formed between the capacitive electrode JD and the relay electrode TD. The thickness of the insulating film 23 may be 1 / 2, 1 / 3, or 1 / 5 of the thickness of the organic layer YL.

[0019] The liquid crystal display device 10 may include an auxiliary electrode SD formed above the organic layer YL and in contact with the pixel electrode PD, and a contact hole HD that penetrates the organic layer YL and electrically connects the auxiliary electrode SD and the relay electrode TD. An aperture KC may be formed on the common electrode CD, which overlaps the pixel electrode PD and the color filter CF in a plan view. A light-shielding layer UB may be formed on the common electrode CD, which surrounds the aperture KC of the common electrode in a plan view. The light-shielding layer UB may be a color mixing suppression layer.

[0020] The liquid crystal display device 10 includes a planarization film 26 that fills the contact holes HD, and the pixel electrodes PD may rest on the planarization film 26. In a planar view, the pixel electrodes PD and the common electrode CD overlap, and a retaining capacitance (upper layer retaining capacitance PC) may be formed between the pixel electrodes PD and the common electrode CD. The liquid crystal layer 30 is in a transverse electric field mode, and the common electrode CD may be formed above the pixel electrodes PD.

[0021] The liquid crystal display device 10 may include a transistor TR connected to a relay electrode TD and formed below the capacitive electrode JD. The first and second scan lines GA·GB may function as gate electrodes of the transistor TR, and the data line DL may be connected to the pixel electrode PD via the transistor TR, as well as the relay electrode TD and the contact hole HD.

[0022] Figure 5 is a plan view showing an example configuration of a liquid crystal display device. As shown in Figures 2 and 5, the liquid crystal display device 10 comprises a display unit DA and a non-display unit NA, and the non-display unit NA may include a power supply wiring PL to which a common potential Vcom is supplied. A capacitive electrode JD is formed across the display unit DA and the non-display unit NA and may be electrically connected to the power supply wiring PL in the non-display unit NA. The display unit DA includes a plurality of pixels PX, and the pixel density of the display unit DA may be 1000 ppi or more, or 1500 ppi or more. The liquid crystal display device 10 may also be a head-mounted display (body-worn display) with a pixel density of 1000 ppi or more.

[0023] The non-display section NA includes a first electrode D1 formed in the same layer as the relay electrode TD, and the capacitive electrode JD and power supply wiring PL may be electrically connected via the first electrode D1. The power supply wiring PL may be formed in the same layer as the data line DL (source electrode SE). The power supply wiring PL may be formed to follow the edge of the display section DA in a plan view.

[0024] The non-display area NA includes a second electrode D2 formed in the same layer as the auxiliary electrode SD and a third electrode D3 formed in the same layer as the pixel electrode PD, and the common electrode CD may be connected to the power supply wiring PL via the first to third electrodes D1 to D3.

[0025] That is, the power supply wiring PL may be connected to the first electrode D1 via a contact hole HC that penetrates the insulating film 21 and 23, and the first electrode D1 may be connected to the capacitive electrode JD via a contact hole HE that penetrates the insulating film 23, and also to the second electrode D2 via a contact hole HF that penetrates the organic insulating film 24. The second electrode D2 and the third electrode D3 may be in contact, and the third electrode D3 and the common electrode CD may be in contact.

[0026] Figs. 6 and 7 are cross-sectional views showing a configuration example of a liquid crystal display device. As shown in Fig. 2 and Figs. 6 and 7, the liquid crystal display device 10 may include a pixel circuit board 2 having a pixel electrode PD, a common electrode CD, an organic layer YL, a relay electrode TD, and a capacitive electrode JD, a counter substrate 4 facing the pixel circuit board 2 through a liquid crystal layer 30, and a light-emitting device 5 that irradiates light to the liquid crystal layer 30 through the pixel circuit board 2 or the counter substrate 4. The light-emitting device 5 may be provided on the pixel circuit board 2 side as shown in Fig. 6, or may be provided on the counter substrate 4 side as shown in Fig. 7. The color filter CF may be formed on the pixel circuit board 2 (Fig. 2), or may be formed on the counter substrate 4.

[0027] Figs. 8 and 9 are plan views showing a configuration example of a liquid crystal display device. As shown in Figs. 8 and 9, a plurality of data lines DL may be arranged in the display portion DA, and data signals of opposite polarities may be supplied to adjacent data lines DL. It is desirable that the difference between the capacitive electrode overlap ratio Ra (the ratio of the total area of the capacitive electrode overlap portion DZ to the upper surface area of the data line DL) for one of the adjacent data lines DL and the capacitive electrode overlap ratio Rb for the other is small. For example, 0.9 < Rb / Ra < 1.1 may be satisfied. A part of the capacitive electrode JD may be aligned with a part of the data line DL (Fig. 9).

[0028] As shown in Fig. 1 and Figs. 8 and 9, the capacitive electrode JD may be a mesh-like conductive pattern. A bent-shaped opening KJ may be formed in the capacitive electrode JD. The opening KJ of the capacitive electrode JD may be a shape that bends at a plurality of locations (for example, two locations). The capacitive electrode JD, which is a conductive pattern, includes a plurality of openings KJ, and the plurality of openings KJ may be arranged in a staggered manner in a second direction X2 orthogonal to the arrangement direction (first direction X1: horizontal direction in the figure) of the data lines DL. The opening KJ may be a polygonal shape that does not include an interior angle of less than 80 degrees. The opening KC of the common electrode CD may be an extended shape that extends in a direction oblique to the second direction X2. In a plan view, the contact hole HB may overlap the opening KJ (opening of the capacitive electrode) and the opening KC (opening of the common electrode).

[0029] Figures 10 to 14 are plan views showing examples of capacitive electrode and intermediate electrode patterns. The patterns of the capacitive electrode JD and intermediate electrode TD are not limited to those shown in Figure 1, etc. They can also be configured as shown in Figures 10 to 14. The capacitive electrode patterns in Figures 10 and 11 have advantages such as reduced parasitic capacitance between data lines and scan lines and the capacitive electrode JD, and ease of patterning. The capacitive electrode patterns in Figures 12 to 14 have the advantage of increasing the retained capacitance between the intermediate electrode TD and the capacitive electrode JD, as well as reducing parasitic capacitance between data lines DL and the capacitive electrode JD while equalizing the capacitive load of each data line DL.

[0030] The embodiments described above are for illustrative and explanatory purposes only, and not for limitation. It will be apparent to those skilled in the art that many variations are possible based on these examples and descriptions. The gist of this embodiment is summarized below, where "as described above" includes the configurations disclosed in Figures 1 to 14.

[0031] 〔summary〕 The liquid crystal layer, Located below the liquid crystal layer, the pixel electrodes and common electrodes form the liquid crystal capacitance, An organic layer formed below the pixel electrode and common electrode, A relay electrode is formed below the organic layer and is electrically connected to the pixel electrode, A liquid crystal display device comprising a capacitor electrode formed below the organic layer and comprising the relay electrode and the retaining capacitance.

[0032] The aforementioned liquid crystal display device includes a color filter as described above.

[0033] The liquid crystal display device described above, wherein the organic layer includes an organic insulating film formed above the color filter.

[0034] The liquid crystal display device described above, wherein a common potential is supplied to the common electrode and the capacitive electrode.

[0035] The capacitive electrode is formed in a lower layer than the relay electrode, as described above for the liquid crystal display device.

[0036] The liquid crystal display device described above, comprising an inorganic insulating film formed between the capacitive electrode and the relay electrode.

[0037] The capacitive electrode is a mesh-like conductive pattern, as described above for the liquid crystal display device.

[0038] The liquid crystal display device described above, wherein a bent-shaped opening is formed in the capacitive electrode.

[0039] The liquid crystal display device described above, wherein the opening of the capacitive electrode is bent at multiple points.

[0040] The common electrode and capacitive electrode are light-transmitting, as described above, in the liquid crystal display device.

[0041] Including data lines formed in a layer below the capacitive electrode, The liquid crystal display device described above, wherein a portion of the capacitive electrode overlaps with the data line in a plan view.

[0042] An auxiliary electrode formed above the aforementioned organic layer and in contact with the pixel electrode, The liquid crystal display device described above, comprising a contact hole that penetrates the organic layer and electrically connects the auxiliary electrode and the relay electrode.

[0043] It comprises a display unit and a non-display unit, The non-display section includes power supply wiring to which a common potential is supplied. The capacitive electrode is formed across the display section and the non-display section, and is electrically connected to the power supply wiring in the non-display section, as described above for the liquid crystal display device.

[0044] The non-display portion includes a first electrode formed in the same layer as the relay electrode, The liquid crystal display device described above, wherein the capacitive electrode and the power supply wiring are electrically connected via the first electrode.

[0045] The non-display portion includes a second electrode formed in the same layer as the auxiliary electrode and a third electrode formed in the same layer as the pixel electrode. The liquid crystal display device described above, wherein the common electrode is connected to the power supply wiring via the first to third electrodes.

[0046] The liquid crystal display device described above, wherein an aperture is formed in the common electrode that overlaps with the pixel electrode and the color filter in a plan view.

[0047] The liquid crystal display device described above, wherein a light-shielding layer is formed on the common electrode, surrounding the opening of the common electrode in a plan view.

[0048] The facility includes a planarizing film that fills the aforementioned contact hole, The above-described liquid crystal display device wherein the pixel electrodes are mounted on the planarization film.

[0049] The liquid crystal display device described above, wherein the pixel electrode and the common electrode overlap in a plan view, and a holding capacitance is formed between the pixel electrode and the common electrode.

[0050] The aforementioned liquid crystal layer is in transverse electric field mode, The liquid crystal display device described above, wherein the common electrode is formed in a layer above the pixel electrode.

[0051] The liquid crystal display device described above, comprising a transistor connected to the relay electrode and formed in a lower layer than the capacitive electrode.

[0052] A pixel circuit board having the pixel electrode, the common electrode, the organic layer, the relay electrode, and the capacitive electrode, A counter substrate facing the pixel circuit board via the liquid crystal layer, The liquid crystal display device described above, comprising a light-emitting device that irradiates the liquid crystal layer with light via the pixel circuit board or the opposing substrate.

[0053] The aforementioned liquid crystal display device having a pixel density of 1000 ppi or more.

[0054] A pixel circuit board for a liquid crystal display device, Pixel electrodes and common electrodes capable of forming liquid crystal capacitance, An organic layer formed below the pixel electrode and common electrode, A relay electrode is formed below the organic layer and is electrically connected to the pixel electrode, A pixel circuit board comprising a layer formed below the organic layer and comprising the relay electrode and a capacitive electrode that forms a holding capacitance. [Explanation of symbols]

[0055] 2 Pixel Circuit Board 4 Opposite substrate 5. Light-emitting device 10 LCD display device 24 Organic insulating film 26 Planarization film 30 liquid crystal layers YL organic layer DA display section NA Hidden part CD Common Electrode JD capacitive electrode TD relay electrode PD pixel electrode SD auxiliary electrode CF Color Filter D1-D3: Electrodes 1-3

Claims

1. The liquid crystal layer, Located below the liquid crystal layer, the pixel electrodes and common electrodes form the liquid crystal capacitance, An organic layer formed below the pixel electrode and common electrode, A relay electrode is formed below the organic layer and is electrically connected to the pixel electrode, A liquid crystal display device comprising a capacitor electrode formed below the organic layer and comprising the relay electrode and the retaining capacitance.

2. The liquid crystal display device according to claim 1, wherein the organic layer includes a color filter.

3. The liquid crystal display device according to claim 2, wherein the organic layer includes an organic insulating film formed above the color filter.

4. The liquid crystal display device according to claim 1, wherein a common potential is supplied to the common electrode and the capacitive electrode.

5. The liquid crystal display device according to claim 1, wherein the capacitive electrode is formed in a lower layer than the relay electrode.

6. The liquid crystal display device according to claim 1, comprising an inorganic insulating film formed between the capacitive electrode and the intermediate electrode.

7. The liquid crystal display device according to claim 1, wherein the capacitive electrode is a mesh-like conductive pattern.

8. The liquid crystal display device according to claim 1, wherein a bent-shaped opening is formed in the capacitive electrode.

9. The liquid crystal display device according to claim 8, wherein the opening of the capacitive electrode has a shape that is bent at multiple locations.

10. The liquid crystal display device according to claim 1, wherein the common electrode and the capacitive electrode are light-transmitting.

11. Including data lines formed in a layer below the capacitive electrode, The liquid crystal display device according to claim 1, wherein a portion of the capacitive electrode overlaps with the data line in a plan view.

12. An auxiliary electrode formed above the aforementioned organic layer and in contact with the pixel electrode, The liquid crystal display device according to claim 1, further comprising a contact hole that penetrates the organic layer and electrically connects the auxiliary electrode and the relay electrode.

13. It comprises a display unit and a non-display unit, The non-display section includes power supply wiring to which a common potential is supplied. The liquid crystal display device according to claim 12, wherein the capacitive electrode is formed across the display unit and the non-display unit, and is electrically connected to the power supply wiring in the non-display unit.

14. The non-display portion includes a first electrode formed in the same layer as the relay electrode, The liquid crystal display device according to claim 13, wherein the capacitive electrode and the power supply wiring are electrically connected via the first electrode.

15. The non-display portion includes a second electrode formed in the same layer as the auxiliary electrode and a third electrode formed in the same layer as the pixel electrode. The liquid crystal display device according to claim 14, wherein the common electrode is connected to the power supply wiring via the first to third electrodes.

16. The liquid crystal display device according to claim 2, wherein an aperture is formed in the common electrode that overlaps with the pixel electrode and the color filter in a plan view.

17. The liquid crystal display device according to claim 16, wherein a light-shielding layer is formed on the common electrode, surrounding the opening of the common electrode in a plan view.

18. The facility includes a planarizing film that fills the aforementioned contact hole, The liquid crystal display device according to claim 12, wherein the pixel electrode is mounted on the planarization film.

19. A liquid crystal display device according to any one of claims 1 to 18, wherein the pixel electrode and the common electrode overlap in a plan view, and a holding capacitance is formed between the pixel electrode and the common electrode.

20. The aforementioned liquid crystal layer is in transverse electric field mode, The liquid crystal display device according to any one of claims 1 to 18, wherein the common electrode is formed in a layer above the pixel electrode.

21. A liquid crystal display device according to any one of claims 1 to 18, comprising a transistor connected to the relay electrode and formed in a lower layer than the capacitive electrode.

22. A pixel circuit board having the pixel electrode, the common electrode, the organic layer, the relay electrode, and the capacitive electrode, A counter substrate facing the pixel circuit board via the liquid crystal layer, A liquid crystal display device according to any one of claims 1 to 18, comprising a light-emitting device that irradiates the liquid crystal layer with light via the pixel circuit board or the opposing substrate.

23. A liquid crystal display device according to any one of claims 1 to 18, wherein the pixel density is 1000 ppi or more.

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