Power supply unit and memory system

Abstract

It compensates for the supply of power voltage. [Solution] According to the embodiment, the power supply device has a plurality of channels CH that output voltage, and includes a PMIC (Power Management Integrated Circuit 31) capable of notifying the outside of output abnormalities of the plurality of channels, and a plurality of voltage output terminals TO. The plurality of voltage output terminals include a first voltage output terminal TO_1 connected to the first channel CH1 of the plurality of channels. When the PMIC detects an output abnormality of the first channel, it stops the output of a first voltage V1 from the first channel to the first voltage output terminal, electrically connects a second channel CH(n+1) different from the first channel of the plurality of channels to the first voltage output terminal, and is configured to output a second voltage V1 from the second channel to the first voltage output terminal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a power supply device and a memory system.

Background Art

[0002] A power supply device and a memory system including a PMIC (Power Management Integrated Circuit) are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, a power supply device capable of compensating for the supply of a power supply voltage is provided.

Means for Solving the Problems

[0005] The power supply device according to the embodiment includes a Power Management Integrated Circuit (PMIC) that has multiple channels for outputting voltage and can notify the outside of output abnormalities in the multiple channels, and multiple voltage output terminals. The multiple voltage output terminals include a first voltage output terminal connected to the first channel among the multiple channels. When the PMIC detects an output abnormality in the first channel, it is configured to stop outputting a first voltage from the first channel to the first voltage output terminal, electrically connect the first voltage output terminal to a second channel different from the first channel among the multiple channels, and output a second voltage from the second channel to the first voltage output terminal. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a data processing device including a memory system according to the first embodiment. [Figure 2] A block diagram showing an example of the configuration of the non-volatile memory in the memory system according to the first embodiment. [Figure 3] Circuit diagram showing an example of the circuit configuration of a memory cell array in the memory system according to the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of a power supply device according to the first embodiment. [Figure 5] This figure shows a specific example of a power supply unit in a state where the PMIC according to the first embodiment has detected an output abnormality. [Figure 6] A circuit diagram showing an example of the circuit configuration of a power supply device according to the second embodiment. [Figure 7] This figure shows a specific example of a power supply unit in a state where the PMIC according to the second embodiment has detected an output abnormality. [Figure 8] A circuit diagram showing an example of the circuit configuration of a power supply device according to the third embodiment. [Figure 9] This figure shows a specific example of a power supply unit in a state where the PMIC according to the third embodiment has detected an output abnormality. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be given a common reference numeral. When multiple components having a common reference numeral need to be distinguished, a subscript will be added to the common reference numeral to distinguish them. When there is no particular need to distinguish between multiple components, only the common reference numeral will be assigned to those components, and no subscript will be added. Here, the subscript is not limited to subscripts or superscripts, but also includes, for example, lowercase alphabet letters added to the end of the reference numeral, and indices indicating arrangement.

[0008] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0009] 1. First Embodiment A power supply unit according to the first embodiment will be described below. In this description, a power supply unit mounted on a memory system will be used as an example. Note that this power supply unit can also be applied to other semiconductor devices besides memory systems.

[0010] 1.1 Configuration 1.1.1 Data Processing Unit Configuration First, with reference to Figure 1, an example of the configuration of a data processing device including a memory system will be described. Figure 1 is a block diagram showing an example of the configuration of a data processing device 1 including a memory system 3.

[0011] As shown in Figure 1, the data processing device 1 includes a host 2 and a memory system 3. The data processing device 1 may include multiple hosts 2 or multiple memory systems 3. When the data processing device 1 includes multiple hosts 2 and multiple memory systems 3, multiple memory systems 3 may be connected to one host 2. Alternatively, multiple hosts 2 may be connected to one memory system 3.

[0012] Host 2 is an information processing device (computing device) that accesses the memory system 3. Host 2 controls the memory system 3. More specifically, for example, Host 2 requests (commands) a write operation or a read operation of data (hereinafter referred to as "user data") to the memory system 3. Host 2 transmits and receives data and various signals to and from the memory system 3 via the host bus HB. In addition, Host 2 supplies a power voltage to the power supply device 30 of the memory system 3.

[0013] The memory system 3 is, for example, an SSD (Solid State Drive). The memory system 3 is connected to Host 2 via the host bus HB. The type of the host bus HB depends on the application applied to the memory system 3. When the memory system 3 is an SSD, the host bus HB complies with, for example, the PCIe (registered trademark) (Peripheral Component Interconnect Express) standard. The memory system 3 executes processing based on a request signal received from Host 2 or a spontaneous processing request.

[0014] 1.1.2 Configuration of Memory System Continuing, referring to FIG. 1, an example of the configuration of the memory system 3 will be described.

[0015] The memory system 3 includes a non-volatile memory 10, a memory controller 20, and a power supply device 30.

[0016] The non-volatile memory 10 is a non-volatile storage medium (semiconductor storage device). The non-volatile memory 10 may include a plurality of memory chips. Hereinafter, the case where the non-volatile memory 10 is a NAND type flash memory will be described. Note that the non-volatile memory 10 may be a non-volatile storage medium other than the NAND type flash memory. The non-volatile memory 10 is connected to the memory controller 20 via the NAND bus NB. The non-volatile memory 10 stores the data received from the memory controller 20 in a non-volatile manner.

[0017] The memory controller 20 is, for example, a SoC (System on a Chip). Based on requests (commands) from the host 2, the memory controller 20 commands the non-volatile memory 10 to perform read operations, write operations, erase operations, and the like. Further, the memory controller 20 manages the memory areas of the non-volatile memory 10.

[0018] The power supply device 30 steps down the power supply voltage supplied from the host 2 and supplies the non-volatile memory 10 and the memory controller 20 with a power supply voltage of a desired voltage. In the example shown in FIG. 1, the power supply device 30 generates voltages V1, V2, … Vn (n is an integer of 2 or more). For example, the power supply device 30 supplies the voltages V1 and V2 to the non-volatile memory 10 and supplies the voltage Vn to the memory controller 20. Further, the power supply device 30 transmits a signal ALT notifying the memory controller 20 of an abnormality in the output voltage.

[0019] Next, an example of the internal configuration of the memory controller 20 will be described.

[0020] The memory controller 20 includes a host interface circuit (host I / F) 21, a CPU (Central Processing Unit) 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory) 24, a buffer memory 25, an ECC (Error Check and Correction) circuit 26, and a memory interface circuit (memory I / F) 27. These circuits are interconnected via an internal bus. Note that each function of the host interface circuit 21, the ECC circuit 26, and the memory interface circuit 27 may be realized by a dedicated circuit or may be realized by the CPU 22 executing firmware.

[0021] The host interface circuit 21 is an interface circuit connected to the host 2 via the host bus HB. The host interface circuit 21 controls communication between the host 2 and the memory controller 20. The host interface circuit 21 transmits requests and user data received from the host 2 to the CPU 22 and the buffer memory 25, respectively. The host interface circuit 21 also transmits user data in the buffer memory 25 to the host 2 based on control by the CPU 22.

[0022] The CPU 22 is a processor. The CPU 22 controls the overall operation of the memory controller 20. For example, the CPU 22 commands write, read, and erase operations to the non-volatile memory 10 based on requests from the host 2. The CPU 22 also manages the memory space of the non-volatile memory 10. Furthermore, the CPU 22 controls the power supply 30 by sending control signals CNT to the power supply 30.

[0023] ROM23 is non-volatile memory. For example, ROM23 is EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory). ROM23 is a non-temporary storage medium that stores firmware and programs. For example, CPU22 loads firmware from ROM23 into RAM24 and executes it.

[0024] RAM24 is volatile memory. RAM24 is either DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc. RAM24 is used as the CPU22's workspace. RAM24 also stores firmware for managing the non-volatile memory 10, various management tables, etc.

[0025] The buffer memory 25 is a volatile semiconductor memory. The buffer memory 25 is DRAM or SRAM, etc. The buffer memory 25 temporarily stores user data, written data, and read data, etc.

[0026] The ECC circuit 26 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. Encoding is the operation of generating a codeword based on data. For example, the ECC circuit 26 generates an error correction code (hereinafter also referred to as "parity") based on user data. Then, the ECC circuit 26 adds parity to the user data to generate a codeword, i.e., write data. Decoding is the operation of correcting errors in data. The ECC circuit 26 decodes the data read from the non-volatile memory 10.

[0027] The memory interface circuit 27 controls communication between the memory controller 20 and the non-volatile memory 10. The memory interface circuit 27 is connected to the non-volatile memory 10 via the NAND bus NB. Based on the control of the CPU 22, the memory interface circuit 27 sends and receives data, commands, addresses, and various control signals to and from the non-volatile memory 10. More specifically, during a write operation, for example, the memory interface circuit 27 sends the write data, address, write command, and various control signals from the buffer memory 25 to the non-volatile memory 10. Similarly, during a read operation, for example, the memory interface circuit 27 sends the address, read command, and various control signals to the non-volatile memory 10. The memory interface circuit 27 also sends the data read from the non-volatile memory 10 to the buffer memory 25.

[0028] 1.1.3 Configuration of Non-Volatile Memory Next, with reference to Figure 2, an example of the overall configuration of the non-volatile memory 10 will be described. Figure 2 is a block diagram showing an example of the configuration of the non-volatile memory 10.

[0029] As shown in Figure 2, the non-volatile memory 10 includes a sequencer 11, a voltage generation circuit 12, a low decoder 13, a sense amplifier 14, and a memory cell array 15.

[0030] The sequencer 11 controls the overall operation of the non-volatile memory 10. The sequencer 11 controls the voltage generation circuit 12, the low decoder 13, and the sense amplifier 14, etc. The sequencer 11 performs write operations, read operations, erase operations, etc.

[0031] The voltage generation circuit 12 is supplied with power voltage from the power supply unit 30. Based on the control of the sequencer 11, the voltage generation circuit 12 generates voltages used for writing, reading, and erasing operations and supplies them to the row decoder 13, sense amplifier 14, etc.

[0032] The row decoder 13 decodes, for example, the address (row address) received from the memory controller 20. Based on the decoding result, the row decoder 13 selects one of the block BLKs and supplies voltage to the selected block BLK.

[0033] During read operations, the sense amplifier 14 senses data read from any string unit SU of any block BLK. During write operations, the sense amplifier 14 supplies a voltage to the memory cell array 15 corresponding to the data to be written.

[0034] The memory cell array 15 is a collection of multiple memory cell transistors (hereinafter also referred to as "memory cells") arranged in a two-dimensional or three-dimensional matrix. The memory cell array 15 contains multiple blocks BLK. In the example shown in Figure 2, the memory cell array 15 contains four blocks BLK0 to BLK3. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased all at once. In other words, a block BLK is a data erasure unit. Each block BLK contains multiple string units SU. In the example shown in Figure 2, each block BLK contains four string units SU0 to SU3. A string unit SU is a collection of multiple NAND strings in which multiple memory cell transistors are connected in series. The number of blocks BLK in the memory cell array 15, the number of string units SU within each block BLK, and the number of NAND strings NS within each string unit SU are arbitrary.

[0035] 1.1.4 Circuit configuration of memory cell array Next, the circuit configuration of the memory cell array 15 will be described with reference to Figure 3. Figure 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array 15. The example shown in Figure 3 shows one block BLK, but the configuration of the other block BLKs is the same.

[0036] As shown in Figure 3, each block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes multiple NAND strings NS. Each of the multiple NAND strings NS within a string unit SU is connected to one of the bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MC (MC0 to MC7), as well as selection transistors ST1 and ST2. The number of memory cell transistors MC within a NAND string NS is not limited to eight. Also, the number of selection transistors ST1 and ST2 within a NAND string NS may be one or more each.

[0037] A memory cell transistor (MC) is a memory element that stores data non-volatilely. The memory cell transistor (MC) includes a control gate and a charge storage layer. The memory cell transistor (MC) may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type, using an insulator in the charge storage layer, or it may be of the FG (Floating Gate) type, using a conductor in the charge storage layer.

[0038] The selection transistors ST1 and ST2 are switching elements. They are used to select the string unit SU during various operations.

[0039] The current paths of the selection transistor ST2, memory cell transistors MC0~MC7, and selection transistor ST1 within the NAND string NS are connected in series. The drain of selection transistor ST1 is connected to the bit line BL. The source of selection transistor ST2 is connected to the source line SL.

[0040] The control gates of memory cell transistors MC0 to MC7 in the same block BLK are connected in common to word lines WL0 to WL7, respectively. More specifically, for example, each of string units SU0 to SU3 contains multiple memory cell transistors MC0. The control gates of the multiple memory cell transistors MC0 contained in string units SU0 to SU3 are connected in common to a single word line WL0. That is, the control gates of the multiple memory cell transistors MC0 in block BLK are connected in common to a single word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0041] The gates of multiple selection transistors ST1 within each string unit SU are connected in common to a single selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 within string unit SU0 are connected in common to selection gate line SGD0. The gates of multiple selection transistors ST1 within string unit SU1 are connected in common to selection gate line SGD1. The gates of multiple selection transistors ST1 within string unit SU2 are connected in common to selection gate line SGD2. The gates of multiple selection transistors ST1 within string unit SU3 are connected in common to selection gate line SGD3.

[0042] The gates of multiple selection transistors ST2 within block BLK are connected in common to the selection gate line SGS.

[0043] Word lines WL0 to WL7, selection gate lines SGD0 to SGD3, and selection gate line SGS are connected to the row decoder 13, respectively.

[0044] The bit line BL is connected in common to one NAND string NS of each of the multiple string units SU in each block BLK. Each bit line BL is connected to the sense amplifier 14.

[0045] Source lines SL are shared, for example, between multiple block lines BLK.

[0046] A collection of multiple memory cell transistors MC connected to a common word line WL within a single string unit SU is denoted, for example, as a "cell unit CU". In other words, a cell unit CU is a collection of multiple memory cell transistors MC that are selected collectively during a write or read operation. A page is a unit of data that is written (or read) to a cell unit CU in a batch. For example, if a memory cell transistor MC stores 1 bit of data, the storage capacity of the cell unit CU is 1 page. That is, the cell unit CU stores 1 page of data. A cell unit CU may have a storage capacity of 2 pages or more, depending on the number of bits of data stored by the memory cell transistor MC.

[0047] 1.1.4 Power supply unit configuration Next, an example of the configuration of the power supply unit 30 will be described with reference to Figure 4. Figure 4 is a circuit diagram showing an example of the circuit configuration of the power supply unit 30.

[0048] As shown in Figure 4, the power supply unit 30 includes a PMIC (Power Management Integrated Circuit) 31, multiple load switches LSW, multiple inductor elements 32, multiple capacitor elements 33, and multiple voltage output terminals TO. In the example shown in Figure 4, the power supply unit 30 includes n load switches LSW1 to LSWn, n+1 inductor elements 32_1 to 32_(n+1), n+1 capacitor elements 33_1 to 33_(n+1), and n voltage output terminals TO_1 to TO_n.

[0049] For example, the non-volatile memory 10, memory controller 20, PMIC 31, load switch LSW, inductor element 32, and capacitor element 33 are each individually mounted on the printed circuit board.

[0050] The PMIC31 is an IC chip that manages the power supply voltage. In this embodiment, the PMIC31 manages the power supply voltage output to the non-volatile memory 10 and the memory controller 20.

[0051] The PMIC31 has multiple channels CH for stepping down the input voltage received from the host 2 to a desired voltage value and outputting it. The PMIC31 includes a buck converter (DC-DC converter) or a constant voltage circuit (e.g., LDO: Low Dropout) corresponding to each channel CH (not shown). In this embodiment, the number of channels CH of the PMIC31 is greater than the number of voltage output terminals TO of the power supply 30. The surplus channels CH are used to compensate for the output voltage. Hereinafter, the surplus channels CH will also be referred to as "redundant channels".

[0052] More specifically, in the example shown in Figure 4, the power supply unit 30 outputs voltages V1 to Vn from n voltage output terminals TO_1 to TO_n. In contrast, the PMIC 31 has n+1 channels CH. Note that the PMIC 31 may have more than n+1 channels CH.

[0053] n channels CH1 to CHn are connected to n voltage output terminals TO_1 to TO_n of the power supply unit 30, respectively. The n voltage output terminals TO_1 to TO_n are connected to either the non-volatile memory 10 or the memory controller 20. That is, the n channels CH1 to CHn are connected to either the non-volatile memory 10 or the memory controller 20. For example, channel CH1 is connected to the non-volatile memory 10 via voltage output terminal TO_1. PMIC 31 supplies voltage V1 to the non-volatile memory 10 via channel CH1. Channel CH2 is connected to the non-volatile memory 10 via voltage output terminal TO_2. PMIC 31 supplies voltage V2 to the non-volatile memory 10 via channel CH2. Channel CHn is connected to the memory controller 20 via voltage output terminal TO. PMIC 31 supplies voltage Vn to the memory controller 20 via channel CHn.

[0054] Channel CH(n+1) is a surplus channel CH used for output voltage compensation. That is, the PMIC31 in this embodiment has a redundant section including a redundant channel CH(n+1). The redundant channel CH(n+1) is connected to the voltage output terminals TO_1 to TO_n, respectively, via load switches LSW1 to LSWn.

[0055] If PMIC31 detects an abnormal voltage (output anomaly) in any of channels CH1 to CHn, it stops outputting the voltage from that channel CH. Then, PMIC31 uses the redundant channel CH(n+1) to output the corresponding voltage in place of the channel CH from which the anomaly was detected.

[0056] The PMIC31 has a GPIO (General Purpose Input Output) signal output function. For example, the PMIC31 outputs control signals CS1 to CSn for controlling load switches LSW1 to LSWn. For example, when load switch LSW is turned ON, the control signal CS changes from a Low ("L") level to a High ("H") level.

[0057] Furthermore, the PMIC 31 has a function to notify an external party of an output abnormality. The PMIC 31, i.e., the power supply 30, sends a signal ALT to the memory controller 20, for example, to notify it of an output abnormality. For example, if an abnormality is detected, the ALT signal is changed from the "L" level to the "H" level. For example, the memory controller 20 notifies the user of the data processing device 1 via the host 2 that an abnormality has occurred in the power supply 30. For example, the user can back up the data stored in the non-volatile memory 10, thereby avoiding a situation where the data stored in the non-volatile memory 10 becomes unreadable due to a failure of the power supply 30.

[0058] A load switch LSW is a circuit that electrically connects a redundant channel CH(n+1) and a voltage output terminal TO based on a control signal CS. In this embodiment, one terminal of each of the n load switches LSW1 to LSWn is connected to the redundant channel CH(n+1). The other terminals of the n load switches LSW1 to LSWn are connected to the n channels CH1 to CHn, respectively. For example, each load switch LSW is turned ON when a "H" level control signal CS is input. More specifically, for example, load switch LSW1 is turned ON when a "H" level control signal CS1 is input, and electrically connects the redundant channel CH(n+1) and the voltage output terminal TO_1. Similarly, load switch LSW2 is turned ON when a "H" level control signal CS2 is input, and electrically connects the redundant channel CH(n+1) and the voltage output terminal TO_2. The load switch LSWn is turned ON when a high-level control signal CSn is input, electrically connecting the redundant channel CH(n+1) and the voltage output terminal TO_n.

[0059] The inductor element 32 and the capacitor element 33 are used as filters to smooth the voltage output from the corresponding channel CH. One pair of inductor elements 32 and capacitor elements 33 are connected to one channel CH. More specifically, one end of inductor element 32_1 is connected to channel CH1, and the other end is connected to one electrode of the capacitor element 33 and to the voltage output terminal TO_1. The other electrode of the capacitor element 33 is grounded (connected to the ground voltage wiring). Similarly, inductor element 32_2 and capacitor element 33_2 are connected between channel CH2 and the voltage output terminal TO_2. Inductor element 32_n and capacitor element 33_n are connected between channel CHn and the voltage output terminal TO_n. Inductor element 32_(n+1) and capacitor element 33_(n+1) are connected to the redundant channel CH(n+1).

[0060] 1.2 Specific examples of when the PMIC detects an output abnormality Next, with reference to Figure 5, a specific example of when the PMIC 31 detects an output abnormality will be described. Figure 5 is a diagram showing a specific example of the power supply unit 30 in a state where the PMIC 31 has detected an output abnormality.

[0061] As shown in Figure 5, for example, if an abnormality is detected in the output voltage of channel CH1, the PMIC31 stops outputting voltage V1 from channel CH1.

[0062] In this state, PMIC31 sets the control signal CS1 to a "H" level, for example, to turn on the load switch LSW1. PMIC31 also sets the other control signals CS2 to CSn to a "L" level, turning off the load switches LSW2 to LSWn. This electrically connects the redundant channel CH(n+1) to the voltage output terminal TO_1. PMIC31 then supplies voltage V1 from the redundant channel CH(n+1) to the voltage output terminal TO_1.

[0063] Furthermore, the PMIC31 notifies the memory controller 20 that an abnormality has occurred by setting the ALT signal to the "H" level.

[0064] 1.3 Effects according to this embodiment The effects of this embodiment make it possible to provide a power supply device that can compensate for the supply of power voltage. These effects will now be explained.

[0065] For example, if an output abnormality occurs in any channel CH of the PMIC, it will not only turn off the affected channel CH to protect the connected circuit, but will also turn off other channels CH. For example, if an output abnormality occurs due to a persistent failure of the PMIC, the abnormality will not be resolved even if the power is turned on and off again. In such a case, the memory system 3 will not operate because it will not be supplied with power voltage. Consequently, the host will not be able to access the data in the non-volatile memory 10. For example, the chip size of the PMIC is relatively small. For this reason, PMICs are often mounted using wafer-level CSPs (Chip Size Packages). For example, in order to maintain mechanical strength, the PMIC is fixed with underfill, making it difficult to replace.

[0066] In contrast, in the configuration according to this embodiment, the PMIC 31 has a surplus channel CH (redundant channel CH) for power supply voltage compensation. When an output abnormality is detected, the PMIC 31 can stop the output of the power supply voltage from the channel CH where the output abnormality was detected. The PMIC 31 can control the load switch LSW to electrically connect the redundant channel CH to the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred. That is, the PMIC 31 can supply voltage from the redundant channel CH to the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred. As a result, the power supply unit 30 can output the power supply voltage as in a normal state, even when an output abnormality occurs in the PMIC 31. In other words, the power supply unit 30 can compensate for the supply of power supply voltage. The memory system 3 can operate normally even if an abnormality occurs in the power supply unit 30 because the power supply voltage is supplied from the power supply unit 30. That is, the host 2 can access the data in the non-volatile memory 10. Therefore, the reliability of the memory system 3 can be improved.

[0067] Furthermore, in the configuration according to this embodiment, the PMIC 31, i.e., the power supply unit 30, can notify the memory controller 20 of the abnormality if an output abnormality occurs. For example, by notifying the user of the abnormality and prompting them to back up their data, a situation in which the data in the non-volatile memory 10 becomes inaccessible can be avoided. Thus, the reliability of the data can be improved.

[0068] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a configuration of the power supply unit 30 that differs from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0069] 2.1 Power supply unit configuration First, an example of the configuration of the power supply unit 30 will be described with reference to Figure 6. Figure 6 is a circuit diagram showing an example of the circuit configuration of the power supply unit 30.

[0070] As shown in Figure 6, the power supply unit 30 includes a PMIC 31, a plurality of load switches LSW, a plurality of inductor elements 32, a plurality of capacitor elements 33, and a plurality of voltage output terminals TO. In the example shown in Figure 6, the power supply unit 30 includes n inductor elements 32_1 to 32_n, n capacitor elements 33_1 to 33_n, and n voltage output terminals TO_1 to TO_n. The connections of the n inductor elements 32_1 to 32_n and the n capacitor elements 33_1 to 33_n are the same as in the first embodiment.

[0071] The number of channels CH in the PMIC 31 of this embodiment is the same as the number of voltage output terminals TO of the power supply unit 30. That is, there are no redundant channels CH. Multiple channels CH can be connected in common via a load switch LSW. That is, multiple voltage output terminals TO can be connected to one channel CH. For example, if an output abnormality occurs, the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred is electrically connected to another channel CH via the load switch LSW. For example, a channel CH capable of supplying a voltage within the operating guarantee range of the external circuit (non-volatile memory 10 or memory controller 20) to which the voltage output terminal TO is connected is selected for connection to the voltage output terminal TO via the load switch LSW. That is, the voltage value of the output voltage of a channel CH connected to the voltage output terminal TO via the load switch LSW may be within the voltage guarantee range of the voltage output from that voltage output terminal TO.

[0072] More specifically, in the example shown in Figure 6, the power supply unit 30 outputs voltages V1 to Vn from n voltage output terminals TO_1 to TO_n. In contrast, the PMIC 31 has n channels CH1 to CHn. In this embodiment, the n channels CH1 to CHn are connected to the n voltage output terminals TO_1 to TO_n of the power supply unit 30, respectively. Furthermore, each channel CH is configured to be further connected to one or more voltage output terminals TO via one or more load switches LSW. In the example shown in Figure 6, one end of the load switch LSW1 is connected to channel CH1 and voltage output terminal TO_1, and the other end is connected to channel CH2 and voltage output terminal TO_2. As a result, channel CH1 is configured to be connectable to voltage output terminal TO_2 via load switch LSW1. In other words, channel CH2 is configured to be connectable to voltage output terminal TO_1 via load switch LSW1. For example, the guaranteed voltage range of voltage V1 output from channel CH1 and the guaranteed voltage range of voltage V2 output from channel CH2 overlap in at least part. For example, let the lower limit of voltage V1 be V1L and the upper limit of voltage V1 be V1H. When channel CH2 is connected to voltage output terminal TO_1 via load switch LSW1, it is preferable that the output voltage V2 of channel CH2 and its lower limit V1L and upper limit V1H satisfy the relationship V1L ≤ V2 ≤ V1H. Also, for example, let the lower limit of voltage V2 be V2L and its upper limit V2H. When channel CH1 is connected to voltage output terminal TO_2 via load switch LSW1, it is preferable that the output voltage V1 of channel CH1 and its lower limit V2L and upper limit V2H satisfy the relationship V2L ≤ V1 ≤ V2H.

[0073] Furthermore, channel CH2 and voltage output terminal TO_2 are connected to one end of load switch LSW2, and channel CHn and voltage output terminal TO_n are connected to the other end. This configures channel CH2 to be connectable to voltage output terminal TO_n via load switch LSW2. In other words, channel CHn is configured to be connectable to voltage output terminal TO_2 via load switch LSW2. The voltage guarantee range of voltage V2 output from channel CH2 and the voltage guarantee range of voltage Vn output from channel CHn overlap at least partially.

[0074] If the PMIC31 detects an abnormal voltage (output abnormality) output from any of channels CH1 to CHn, it stops the voltage output from that channel CH. Then, the PMIC31 uses another channel CH connected via the load switch LSW to output a voltage to the corresponding voltage output terminal TO.

[0075] 2.2 Specific Examples of When the PMIC Detects an Output Anomaly Next, with reference to Figure 7, a specific example of when the PMIC 31 detects an output abnormality will be described. Figure 7 is a diagram showing a specific example of the power supply unit 30 when the PMIC 31 has detected an output abnormality.

[0076] As shown in Figure 7, for example, if an abnormality is detected in the output voltage of channel CH1, the PMIC31 stops outputting voltage V1 from channel CH1.

[0077] In this state, the PMIC31 sets the control signal CS1 to a "H" level, for example, to turn on the load switch LSW1. The PMIC31 also sets another control signal CS2 to a "L" level, to turn off the load switch LSW2. This electrically connects channel CH2 and voltage output terminal TO_1. The PMIC31 supplies voltage V2 from channel CH2 to voltage output terminals TO_1 and TO_2. If voltage V2 is within the operating range of the circuit to which voltage output terminal TO_1 is connected, the connected circuit (non-volatile memory 10) can operate.

[0078] Furthermore, the PMIC31 notifies the memory controller 20 that an abnormality has occurred by setting the ALT signal to the "H" level.

[0079] 2.3 Effects according to this embodiment In the configuration according to this embodiment, the power supply unit 30 can connect multiple voltage output terminals TO to one channel CH of the PMIC 31 via the load switch LSW. If an output abnormality is detected, the PMIC 31 can stop outputting the power supply voltage from the channel CH where the output abnormality was detected. The PMIC 31 can control the load switch LSW to electrically connect the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred to another channel CH. That is, the PMIC 31 can supply voltage from another channel CH to the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred via the load switch LSW. As a result, even if an output abnormality occurs in the PMIC 31, the power supply unit 30 can output power supply voltage from the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred. In other words, the power supply unit 30 can compensate for the supply of power supply voltage. If the voltage value of the power supply voltage output from the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred is within the operating range of the connected circuit, the memory system 3 can operate normally even if a malfunction occurs in the power supply unit 30. That is, the host 2 can access the data in the non-volatile memory 10. Therefore, the reliability of memory system 3 can be improved.

[0080] Furthermore, in the configuration according to this embodiment, similar to the first embodiment, the PMIC 31 can notify the memory controller 20 of the abnormality if an output abnormality occurs. For example, by notifying the user of the abnormality and prompting them to back up their data, a situation in which the data in the non-volatile memory 10 becomes inaccessible can be avoided. Thus, the reliability of the data can be improved.

[0081] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, the configuration of the power supply unit 30 will be described, which differs from that of the first and second embodiments. The following description will focus on the differences from the first and second embodiments.

[0082] 3.1 Power supply unit configuration First, an example of the configuration of the power supply unit 30 will be described with reference to Figure 8. Figure 8 is a circuit diagram showing an example of the configuration of the power supply unit 30.

[0083] As shown in Figure 8, the power supply unit 30 includes a PMIC 31, a plurality of inductor elements 32, a plurality of capacitor elements 33, a plurality of diodes 34, and a plurality of voltage output terminals TO. In the example shown in Figure 8, the power supply unit 30 includes n inductor elements 32_1 to 32_n, n capacitor elements 33_1 to 33_n, and n voltage output terminals TO_1 to TO_n. The connections of the n inductor elements 32_1 to 32_n and the n capacitor elements 33_1 to 33_n are the same as in the first and second embodiments.

[0084] This embodiment is a configuration in which the load switch LSW of the second embodiment is replaced with a diode 34. The diode 34 is connected in a reverse bias between the channel CH with a high output voltage and its corresponding voltage output terminal TO, and the channel CH with a low output voltage and its corresponding voltage output terminal TO. In other words, the channel CH with a high output voltage and its corresponding voltage output terminal TO are connected to the cathode side of the diode 34, and the channel CH with a low output voltage and its corresponding voltage output terminal TO are connected to the anode side. This prevents the voltage of the channel CH with a high output voltage from being applied to the channel CH with a low output voltage under normal conditions.

[0085] The number of channels CH in the PMIC of this embodiment is the same as the number of voltage output terminals TO of the power supply unit 30, as in the second embodiment. No redundant channels CH are provided. Two or more voltage output terminals TO can be connected to one channel CH via one or more diodes 34. For example, if an output abnormality occurs, the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred is electrically connected to another channel CH via the diode 34. For example, the channel CH connected to the voltage output terminal TO via the diode 34 is selected to have a lower output voltage than the channel CH connected to the voltage output terminal TO without the diode 34, and to be able to supply a voltage within the operating range of the external circuit. That is, the voltage value obtained by subtracting the voltage drop due to the diode 34 from the output voltage of the channel CH connected to the voltage output terminal TO via the diode 34 may be included in the voltage guarantee range of the voltage output from the voltage output terminal TO.

[0086] More specifically, in the example shown in Figure 8, the power supply unit 30 outputs voltages V1 to Vn from n voltage output terminals TO_1 to TO_n. In contrast, the PMIC 31 has n channels CH1 to CHn. In this embodiment, the n channels CH1 to CHn are connected to the n voltage output terminals TO_1 to TO_n of the power supply unit 30, respectively. Each channel CH is also connected to the voltage output terminal TO corresponding to a channel CH with a lower output voltage than the channel CH, via a diode 34 connected in reverse bias. In the example shown in Figure 8, the output voltage V1 of channel CH1 and the output voltage V2 of channel CH2 are V1 > V2. In this case, channel CH1 and voltage output terminal TO_1 are connected to the cathode of diode 34_1, and channel CH2 and voltage output terminal TO_2 are connected to the anode of diode 34_1. Therefore, channel CH1 is connected to channel CH2 and voltage output terminal TO_2 via diode 34_1 connected in reverse bias. For example, when channel CH1 is off, the PMIC 31 can supply voltage from channel CH2 to voltage output terminal TO_1 via diode 34_1. For example, let VL be the lower limit of the operating guaranteed voltage of the external circuit (non-volatile memory 10) to which voltage output terminal TO_1 is connected, and VH be the upper limit. Let VD be the voltage drop across diode 34. Preferably, the output voltage V2 of channel CH2, the voltage drop VD, the lower limit VL, and the upper limit VH are in the relationship VL ≤ (V2 - VD) ≤ VH.

[0087] The output voltage V2 of channel CH2 and the output voltage Vn of channel CHn are in the relationship V2 > Vn. In this case, channel CH2 and the voltage output terminal TO_2 are connected to the cathode of diode 34_2, and channel CHn and the voltage output terminal TO_n are connected to the anode of diode 34_2. Therefore, channel CH2 is connected to channel CHn and the voltage output terminal TO_n via diode 34_2 which is connected in reverse bias. For example, when channel CH2 is off, PMIC31 can supply voltage from channel CHn to the voltage output terminal TO_2 via diode 34_2.

[0088] In this embodiment, the PMIC31 eliminates the control signal CS described using the first and second embodiments.

[0089] 3.2 Specific Examples of When the PMIC Detects an Output Anomaly Next, with reference to Figure 9, a specific example of when the PMIC 31 detects an output abnormality will be described. Figure 9 is a diagram showing a specific example of the power supply unit 30 when the PMIC 31 has detected an output abnormality.

[0090] As shown in Figure 9, for example, if an abnormality is detected in the output voltage of channel CH1, the PMIC31 stops outputting voltage V1 from channel CH1. As a result, the voltage output terminal TO_1 is supplied with voltage V2' (=V2-VD), which is the output voltage V2 of channel CH2 minus the voltage drop across diode 34_1.

[0091] The PMIC31 notifies the memory controller 20 that an abnormality has occurred by setting the ALT signal to the "H" level.

[0092] 3.3 Effects according to this embodiment In the configuration according to this embodiment, the power supply unit 30 can connect multiple voltage output terminals TO to one channel CH of the PMIC 31 via the diode 34. When an output abnormality is detected, the PMIC 31 can stop the output from the channel CH where the output abnormality was detected. As a result, the PMIC 31 can supply a voltage to the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred, via the diode 34, that is the power supply voltage of the other channel CH minus the voltage drop due to the diode 34. In other words, the power supply unit 30 can compensate for the supply of power supply voltage. If the voltage value output from the voltage output terminal TO corresponding to the channel CH where the output abnormality occurred falls within the operating range of the connected circuit, the memory system 3 can operate normally even if a malfunction occurs in the power supply unit 30. In other words, the host 2 can access the data in the non-volatile memory 10. Thus, the reliability of the memory system 3 can be improved.

[0093] Furthermore, in the configuration according to this embodiment, similar to the first and second embodiments, the PMIC 31 can notify the memory controller 20 of the abnormality if an output abnormality occurs. For example, by notifying the user of the abnormality and prompting them to back up their data, a situation in which the data in the non-volatile memory 10 becomes inaccessible can be avoided. Thus, the reliability of the data can be improved.

[0094] 4. Variations, etc. The power supply device according to the above embodiment includes a Power Management Integrated Circuit (PMIC) (31) (31) (31) which has multiple channels (CH) that output voltage and can notify the outside of output abnormalities of the multiple channels, and multiple voltage output terminals (TO). The multiple voltage output terminals include a first voltage output terminal (TO_1) connected to a first channel (CH1) among the multiple channels. When the PMIC detects an output abnormality of the first channel, it stops outputting a first voltage (V1) from the first channel to the first voltage output terminal, electrically connects a second channel (CH(n+1)) different from the first channel among the multiple channels to the first voltage output terminal, and is configured to output a second voltage (V1) from the second channel to the first voltage output terminal.

[0095] With the configuration according to the above embodiment, reliability can be improved.

[0096] Furthermore, various modifications are applicable, not limited to the embodiments described above.

[0097] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0098] 1...Data processing unit, 2...Host, 3...Memory system, 10...Non-volatile memory, 11...Programmable logic controller, 12...Voltage generation circuit, 13...Raw decoder, 14...Sense amplifier, 15...Memory cell array, 20...Memory controller, 21...Host interface circuit, 22...CPU, 23...ROM, 24...RAM, 25...Buffer memory, 26...ECC circuit, 27...Memory interface circuit, 30...Power supply unit, 31...PMIC, 32...Inductor element, 33...Capacitor Sita element, 34…diode, BL, BL0~BLm…bit line, BLK, BLK0~BLK3…block, CH, CH1~CHn…channel, CS, CS1~CSn…control signal, LSW, LSW1~LSWn…load switch, MC, MC0~MC7…memory cell transistor, SGD, SGD0~SGD3…selection gate line, SL…source line, ST1, ST2…selection transistor, SU, SU0~SU3…string unit, WL, WL0~WL7…word line

Claims

1. A Power Management Integrated Circuit (PMIC) having multiple channels for outputting voltage and capable of notifying externally of output abnormalities in the multiple channels, Multiple voltage output terminals and Equipped with, The plurality of voltage output terminals include a first voltage output terminal connected to the first channel among the plurality of channels, The PMIC is configured to, when it detects an output abnormality in the first channel, stop outputting the first voltage from the first channel to the first voltage output terminal, electrically connect the first voltage output terminal to a second channel different from the first channel among the plurality of channels, and output a second voltage from the second channel to the first voltage output terminal. power supply.

2. The PMIC further comprises a plurality of load switches controlled by the PMIC, The first terminal of each of the aforementioned load switches is connected to the second channel. The second terminal of each of the plurality of load switches is connected to each of the plurality of voltage output terminals. The power supply device according to claim 1.

3. The first voltage and the second voltage have the same voltage value. The power supply device according to claim 1.

4. When the PMIC detects an output abnormality of the first channel, it turns on the first load switch, whose second terminal is connected to the first voltage output terminal, among the plurality of load switches. The power supply device according to claim 2.

5. The number of the aforementioned multiple channels is greater than the number of the aforementioned multiple voltage output terminals. The power supply device according to claim 1.

6. The number of the aforementioned load switches is the same as the number of the aforementioned voltage output terminals. The power supply device according to claim 2.

7. An inductor element having its first end connected to the first channel and its second end connected to the first voltage output terminal, A capacitor element in which the first electrode is connected to the second terminal and the first voltage output terminal of the inductor element, and the second electrode is grounded. It also has, The power supply device according to claim 1.

8. A first load switch, the first end of which is connected to the second channel and the second end of which is connected to the first voltage output terminal, A second load switch whose first end is connected to a third channel different from the first and second channels among the plurality of channels, and whose second end is connected to a second voltage output terminal connected to the second channel among the plurality of voltage output terminals, It further includes, The PMIC controls the first load switch and the second load switch. The power supply device according to claim 1.

9. The voltage value of the second voltage is greater than or equal to the lower limit and less than or equal to the upper limit of the first voltage. The power supply device according to claim 8.

10. When the PMIC detects an output abnormality of the first channel, it turns on the first load switch and turns off the second load switch. The power supply device according to claim 8.

11. The number of the aforementioned multiple channels is the same as the number of the aforementioned multiple voltage output terminals. The power supply device according to claim 7.

12. A first diode whose anode is connected to the second channel and whose cathode is connected to the first voltage output terminal, The anode is connected to a third channel, which is different from the first and second channels among the plurality of channels, and the cathode is connected to a second voltage output terminal, which is connected to the second channel among the plurality of voltage output terminals, and This also includes, The power supply device according to claim 1.

13. The first output voltage value of the first channel is higher than the second output voltage value of the second channel. The second output voltage value of the second channel is higher than the third output voltage value of the third channel. The power supply device according to claim 12.

14. The number of the aforementioned multiple channels is the same as the number of the aforementioned multiple voltage output terminals. The power supply device according to claim 12.

15. A power supply device according to any one of claims 1 to 14, A non-volatile memory supplied with voltage from the aforementioned power supply device, A memory controller that receives voltage from the aforementioned power supply and controls the non-volatile memory, Equipped with, Memory system.

16. The aforementioned non-volatile memory is a NAND flash memory. The memory system according to claim 15.

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