Semiconductor equipment

Abstract

This invention enables area reduction in semiconductor devices with small-capacity memory. [Solution] The latch circuit LT comprises a first inverter circuit and a second inverter circuit. Furthermore, the latch circuit LT comprises a pMOS transistor MP3 and an nMOS transistor MN3 connected between the first inverter circuit and the power supply voltage node. The write port circuit WTC consists of a transfer gate made up of a pMOS transistor MP4 and an nMOS transistor MN4, and transfers the write data to the inverting storage node SNb. The read port circuit RDC consists of a transfer gate made up of a pMOS transistor MP5 and an nMOS transistor MN5, and transfers the read data from the non-inverting storage node SNt.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having memory. [Background technology]

[0002] Non-patent document 1 describes an SRAM macro comprising a memory cell consisting of 12 transistors. The memory cell consists of a write port circuit, a latch circuit, and a read port circuit. The write port circuit consists of a transfer gate consisting of 2 transistors. The latch circuit consists of 6 transistors including 2 cross-coupled CMOS inverter circuits. The read port circuit consists of a driver circuit consisting of 4 transistors.

[0003] Non-patent document 2 describes an SRAM macro comprising a memory cell consisting of 16 transistors. The memory cell consists of a write port circuit, a latch circuit, and a read port circuit. The write port circuit consists of a driver circuit consisting of 4 transistors. The latch circuit consists of 8 transistors, including two cross-coupled CMOS inverter circuits, and also supports bit write mask operation. The read port circuit consists of a driver circuit consisting of 4 transistors. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] M. Sinangil, et al., “A 290mV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7nm FinFET Technology”, VLSI 2018 [Non-Patent Document 2] H.Fujiwara, et al., “A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell-Based Two-Port Register File with a 16T Bitcell with_No Half-Selection Issue ”, ISSCC 2021 [Overview of the project] [Problems that the invention aims to solve]

[0005] In recent years, semiconductor devices that handle various AI (Artificial Intelligence) processing, such as image recognition, have become widespread. Such semiconductor devices require the temporary storage of processing data at various points distributed within the device. Therefore, high-speed, relatively small-capacity memory is necessary. Flip-flops and SRAM (Static Random Access Memory) are known examples of such memory.

[0006] In the case of a single-port SRAM, for example, the memory cell can be composed of six transistors. However, SRAM requires peripheral circuits including various circuits such as decoders, sense amplifiers, write assist circuits, and read assist circuits. Therefore, in SRAM, the area per bit increases as the capacity decreases, meaning that the area efficiency decreases. On the other hand, a flip-flop only requires a decoder as peripheral circuitry. However, a flip-flop is composed of two D latches, each consisting of about 20 transistors. Therefore, flip-flops have a large area per bit and are only practically applicable when the capacity is sufficiently small.

[0007] Therefore, from the perspective of improving area efficiency, there is a need for a memory that complements the gap between SRAM and flip-flops. Specifically, there is a need for a memory suitable for holding approximately 16 to 64 128-bit data points. One such memory is the D-latch macro. A D-latch macro can be composed of a memory cell consisting of 16 transistors, in other words, a latch cell, as shown in Non-Patent Document 2. However, if we consider a case where many small-capacity D-latch macros are arranged in a semiconductor device, for example, it is desirable to further reduce the area of ​​the latch cell.

[0008] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a write port circuit, a latch circuit, a read port circuit, and first and second storage nodes for storing complementary data. The latch circuit includes a first pMOS transistor and a first nMOS transistor that constitute a first inverter circuit with the second / first storage nodes as input / output. The latch circuit also includes a second pMOS transistor and a second nMOS transistor that constitute a second inverter circuit with the first / second storage nodes as input / output. Furthermore, the latch circuit includes a third pMOS transistor and a third nMOS transistor connected between the first inverter circuit and a power supply voltage node. The write port circuit consists of a transfer gate made up of a fourth pMOS transistor and a fourth nMOS transistor, and transfers write data to the first storage node. The read port circuit consists of a transfer gate made up of a fifth pMOS transistor and a fifth nMOS transistor, and transfers read data from the second storage node. [Effects of the Invention]

[0010] According to the above-described embodiment, in a semiconductor device having a small-capacity memory, area reduction can be achieved.

Brief Description of the Drawings

[0011] [Figure 1] FIG. 1 is a schematic diagram showing a configuration example of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing a configuration example of a main part of a peripheral circuit in the memory shown in FIG. 1. [Figure 3] FIG. 3 is a circuit diagram showing a configuration example of a latch cell in FIG. 1. [Figure 4A] FIG. 4A is a timing chart showing an example of a write operation by the latch cell shown in FIG. 3. [Figure 4B] FIG. 4B is a schematic diagram for supplementarily explaining the operation shown in FIG. 4A. [Figure 5A] FIG. 5A is a timing chart showing an example of a read operation by the latch cell shown in FIG. 3. [Figure 5B] FIG. 5B is a schematic diagram for supplementarily explaining the operation shown in FIG. 5A. [Figure 6A] FIG. 6A is a timing chart showing an example of a bit write mask operation by the latch cell shown in FIG. 3. [Figure 6B] FIG. 6B is a schematic diagram for supplementarily explaining the operation shown in FIG. 6A. [Figure 7A] FIG. 7A is a schematic diagram showing an example of a design specification of the latch cell shown in FIG. 3. [Figure 7B] FIG. 7B is a schematic diagram showing an example of a further design specification in the latch cell shown in FIG. 3. [Figure 8] FIG. 8 is a diagram showing an example of a detailed design specification of the latch cell shown in FIGS. 3, 7A, and 7B in a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a perspective view showing a structural example of each MOS transistor constituting the latch cell in a semiconductor device according to the second embodiment. [Figure 10] Figure 10 is a schematic diagram showing an example of the latch cell layout configuration shown in Figures 3 and 8. [Figure 11] Figure 11 is a schematic diagram showing a different layout configuration example of the latch cell shown in Figures 3 and 8, compared to Figure 10. [Figure 12] Figure 12 shows an example of detailed design specifications for the latch cell shown in Figures 3, 7A, and 7B in a semiconductor device according to the third embodiment. [Figure 13] Figure 13 is a schematic diagram showing an example of the latch cell layout configuration shown in Figures 3 and 12. [Figure 14] Figure 14 is a schematic diagram showing a different layout configuration example for the latch cell shown in Figures 3 and 12 compared to the case in Figure 13. [Figure 15] Figure 15 is a perspective view showing an example of the structure of each MOS transistor constituting a latch cell in a semiconductor device according to the fourth embodiment. [Figure 16] Figure 16 is a schematic diagram showing an example of the latch cell layout configuration shown in Figures 3 and 12 in a semiconductor device according to the fourth embodiment. [Figure 17] Figure 17 is a schematic diagram showing a different layout configuration example for the latch cell in the semiconductor device according to the fourth embodiment, compared to the case in Figure 16, as shown in Figures 3 and 12. [Figure 18] Figure 18 is a circuit diagram showing an example of a latch cell configuration for comparison purposes. [Figure 19] Figure 19 is a schematic diagram showing an example of the latch cell layout configuration shown in Figure 18. [Modes for carrying out the invention]

[0012] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. However, unless otherwise specified, they are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements (including number, numerical value, quantity, range, etc.), the number is not limited to that specific number unless otherwise specified or when it is clearly limited in principle. In other words, the number of elements may be greater than or less than a specific number.

[0013] Furthermore, in the embodiments, the constituent elements (including element steps) are not necessarily essential unless specifically stated or considered fundamentally essential. Similarly, when referring to the shape, positional relationship, etc., of constituent elements, it includes those that substantially approximate or resemble their shape, etc., unless specifically stated or considered fundamentally not essential. The same applies to the numerical values ​​and ranges mentioned above.

[0014] Furthermore, in this embodiment, a MOSFET (MOS Field Effect Transistor) is referred to as a MOS transistor. A p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively. In this embodiment, for the sake of simplicity, the explanation will be given using a MOS transistor that uses an oxide film as the gate insulating film. However, the gate insulating film is not necessarily limited to an oxide film.

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings used to illustrate the embodiments, the same reference numerals are generally used for identical components, and repeated descriptions of such components will be omitted.

[0016] (First Embodiment) <Overview of Semiconductor Devices> Figure 1 is a schematic diagram showing an example configuration of a semiconductor device according to the first embodiment. Figure 2 is a schematic diagram showing an example configuration of the main peripheral circuit in the memory MEM shown in Figure 1. The semiconductor device according to the first embodiment includes at least a memory MEM as shown in Figure 1. The memory MEM is, for example, a D latch macro composed of hard macros. The semiconductor device includes, for example, various logic circuits that are responsible for various AI processing. In this case, the semiconductor device may have memory MEMs as shown in Figure 1 distributed and mounted in various locations within the device in order to temporarily store the processing data of the various logic circuits.

[0017] The memory MEM shown in Figure 1 comprises a latch cell array LCARY, a memory control circuit CTRL, a word driver circuit WD, and a data input / output circuit IOC. The memory control circuit CTRL, the word driver circuit WD, and the data input / output circuit IOC are peripheral circuits of the latch cell array LCARY. The latch cell array LCARY comprises "N (=n+1)*M (=m+1)" latch cells LC[0,0]-LC[n,m] arranged in a matrix. In this specification, multiple latch cells LC[0,0]-LC[n,m] are collectively referred to as latch cells LC.

[0018] The memory control circuit CTRL controls the entire memory MEM. As shown in Figure 2, the memory control circuit CTRL mainly comprises a clock generation circuit CKG and an address decoder ADEC. The clock generation circuit CKG receives inputs from outside the memory MEM, such as a clock signal CLK, a chip enable signal CEN, and a write enable signal WEN. Based on these input signals, the clock generation circuit CKG outputs a write decode instruction signal DECW or a read decode instruction signal DECR to the address decoder ADEC. The clock generation circuit CKG also outputs a write enable signal WTEN or a read enable signal RDEN to the data input / output circuit IOC based on these input signals.

[0019] The address decoder ADEC receives an address signal ADR from outside the memory MEM. In response to the write decode instruction signal DECW, the address decoder ADEC activates one write word line WWLN[k] based on the address signal ADR. This write word line WWLN[k] is one of the N write word lines WWLN[n:0] shown in Figure 1. Similarly, in response to the read decode instruction signal DECR, the address decoder ADEC activates one read word line RWLN[k] based on the address signal ADR. This read word line RWLN[k] is one of the N read word lines RWLN[n:0] shown in Figure 1.

[0020] The word driver circuit WD drives 2 × N read selection lines RCP[n:0] and RCPN[n:0], which are complementary signal lines, as shown in Figure 1. The N read selection lines RCP[n:0] are the non-inverting signal lines. In this specification, these N read selection lines RCP[n:0] are collectively referred to as the non-inverting read selection lines RCP, or simply as read selection lines RCP. On the other hand, the remaining N read selection lines RCPN[n:0] are the inverting signal lines. In this specification, these N read selection lines RCPN[n:0] are collectively referred to as the inverting read selection lines RCPN, or simply as read selection lines RCPN.

[0021] Furthermore, the word driver circuit WD drives 2 × N write selection lines WCP[n:0] and WCPN[n:0], which are complementary signal lines. The N write selection lines WCP[n:0] are non-inverting signal lines. In this specification, these N write selection lines WCP[n:0] are collectively referred to as non-inverting write selection lines WCP, or simply write selection lines WCP. On the other hand, the remaining N write selection lines WCPN[n:0] are inverting signal lines. In this specification, these N write selection lines WCPN[n:0] are collectively referred to as inverting write selection lines WCPN, or simply write selection lines WCPN.

[0022] As shown in Figure 2, the word driver circuit WD receives the signal from each read word line RWLN[k] and drives each inverted read selection line RCPN[k]. The word driver circuit WD also drives each non-inverted read selection line RCP[k] by inverting the signal from each read word line RWLN[k]. Similarly, the word driver circuit WD receives the signal from each write word line WWLN[k] and drives each inverted write selection line WCPN[k]. The word driver circuit WD also drives each non-inverted write selection line WCP[k] by inverting the signal from each write word line WWLN[k].

[0023] The data input / output circuit (IOC) controls the input and output of data to and from the memory (MEM) and its external environment. Specifically, the data input / output circuit (IOC) primarily comprises a write latch circuit (DLT) and a write driver (WDV) as its write circuit. The data input / output circuit (IOC) also primarily comprises a read switch (RSW) and a read latch circuit (QLT) as its read circuit.

[0024] First, during a write operation, the data input / output circuit IOC receives M-bit input data D[m:0] from outside the memory MEM, as shown in Figure 1. The write latch circuit DLT latches the M-bit input data D[m:0] as write data in accordance with the write enable signal WTEN. The write driver WDV transfers the latched M-bit write data to the latch cell array LCARY via M inverted write bit lines WBLN[m:0].

[0025] The M bits of write data transferred from the write driver WDV are written to M latch cells LC connected to the activated write selection line WCP. In this specification, the inverted write bit lines WBLN[m:0] of these M lines are collectively referred to as the inverted write bit lines WBLN, or simply the write bit lines WBLN.

[0026] On the other hand, during a read operation, the data input / output circuit IOC receives the read data from M latch cells LC via M non-inverting read bit lines RBL[m:0]. These M latch cells LC are cells connected to the activated read selection line RCP. In this specification, these M non-inverting read bit lines RBL[m:0] are collectively referred to as non-inverting read bit lines RBL, or simply read bit lines RBL.

[0027] The read latch circuit QLT receives and latches read data from M latch cells LC via switch RSW in response to the read enable signal RDEN. In other words, unlike typical SRAMs, the read latch circuit QLT receives and latches read data without going through a sense amplifier. The read latch circuit QLT then outputs the M-bit read data to the outside as the M-bit output data Q[m:0].

[0028] Furthermore, as shown in Figure 1, the data input / output circuit IOC also receives an M-bit bit write mask signal BWM[m:0] from outside the memory MEM. The bit write mask signal BWM[m:0] is used to mask some bits of the M-bit input data D[m:0] during the write operation. This eliminates the need for, for example, read-modify-write operations.

[0029] During bit write mask operation, the write driver WDV shown in Figure 2 outputs a high impedance to the write bit line WBLN[k] of the bit to be masked. As a result, the latch cell LC connected to the write bit line WBLN[k] can maintain the data it currently stores regardless of the write operation.

[0030] Furthermore, during bit write mask operation, the data input / output circuit IOC drives the M inverting bit write mask selection lines BWB[m:0] and the M non-inverting bit write mask selection lines BW[m:0]. As will be described in detail later, by driving these selection lines, the latch cell LC can more reliably maintain the data it is currently storing. In this specification, the M inverting bit write mask selection lines BWB[m:0] are collectively referred to as the inverting bit write mask selection line BWB, or simply the bit write mask selection line BWB. Similarly, the M non-inverting bit write mask selection lines BW[m:0] are collectively referred to as the non-inverting bit write mask selection line BW, or simply the bit write mask selection line BW.

[0031] In Figure 1, the value of M (=m+1), which represents the bit width, is, for example, 128, 256, 512, or 1024. The value of N (=n+1), which represents the word line count, is, for example, 16, 32, or 64. Generally, within this range of memory capacity, the D-latch macro can be advantageous compared to flip-flops and SRAM in terms of area efficiency. The D-latch macro can also be described as a macro whose area ratio between the data storage area and the peripheral circuit area is intermediate between that of flip-flops and SRAM.

[0032] For example, SRAM may include a number of sense amplifiers and various assist circuits within its data input / output circuit (IOC) corresponding to the bit width. Therefore, as the bit width increases, the area ratio of the data input / output circuit (IOC) increases. On the other hand, D-latch macros do not require such sense amplifiers or assist circuits. Consequently, the area ratio of the data input / output circuit (IOC) does not increase significantly even as the bit width increases. As a result, D-latch macros can improve area efficiency even with larger bit widths.

[0033] In Figure 1, the memory MEM is shown as an example of a single-port memory. However, the memory MEM may be a dual-port memory capable of independently performing read and write operations. In this case, the memory MEM receives read address signals and write address signals from an external source. Accordingly, the read selection line RCP and the write selection line WCP may be activated simultaneously.

[0034] <Configuration of a latch cell (embodiment)> Figure 3 is a circuit diagram showing an example configuration of the latch cell LC in Figure 1. The latch cell LC shown in Figure 3 comprises a write port circuit WTC, a latch circuit LT, and a read port circuit RDC. The latch cell LC also includes an inverting storage node (first storage node) SNb and a non-inverting storage node (second storage node) SNt that store complementary data.

[0035] The latch circuit LT comprises four nMOS transistors MN1-MN3, MN6 and four pMOS transistors MP1-MP3, MP6. The pMOS transistor (first pMOS transistor) MP1 and the nMOS transistor (first nMOS transistor) MN1 constitute a first inverter circuit. This first inverter circuit performs signal inversion using the non-inverting memory node SNt and the inverting memory node SNb as input and output.

[0036] The pMOS transistor (second pMOS transistor) MP2 and the nMOS transistor (second nMOS transistor) MN2 constitute a second inverter circuit. This second inverter circuit performs signal inversion using the inverting memory node SNb and the non-inverting memory node SNt as input and output.

[0037] The pMOS transistor (third pMOS transistor) MP3 is connected between the first inverter circuit and the high-potential power supply voltage node Nvd. The nMOS transistor (third nMOS transistor) MN3 is connected between the first inverter circuit and the low-potential power supply voltage node Nvs. The high-potential power supply voltage node Nvd is supplied with the high-potential power supply voltage VDD. The low-potential power supply voltage node Nvs is supplied with the low-potential power supply voltage VSS.

[0038] Furthermore, the pMOS transistor (the sixth pMOS transistor) MP6 is connected in parallel with the pMOS transistor MP3. The nMOS transistor (the sixth nMOS transistor) MN6 is connected in parallel with the nMOS transistor MN3. As will be explained in detail later, the pMOS transistor MP6 and the nMOS transistor MN6 are provided to implement the bit write mask function. Therefore, the pMOS transistor MP6 and the nMOS transistor MN6 can be omitted if the bit write mask function is not required.

[0039] The write port circuit WTC consists of a pMOS transistor (the fourth pMOS transistor) MP4 and an nMOS transistor (the fourth nMOS transistor) MN4. The pMOS transistor MP4 and nMOS transistor MN4 form a transfer gate and transfer the write data to the inverting storage node SNb. On the other hand, the read port circuit RDC consists of a pMOS transistor (the fifth pMOS transistor) MP5 and an nMOS transistor (the fifth nMOS transistor) MN5. The pMOS transistor MP4 and nMOS transistor MN4 form a transfer gate and transfer the read data from the non-inverting storage node SNt.

[0040] Here, the latch cell LC shown in Figure 3 is connected, more specifically, to eight signal lines (WCP, WCPN, RCP, RCPN, BW, BWB, WBLN, RBL) as described in Figures 1 and 2. The non-inverting write selection line WCP and the inverting write selection line WCPN are activated during write operations. The non-inverting read selection line RCP and the inverting read selection line RCPN are activated during read operations. The read bit line RBL transfers the read data from the latch cell LC. The write bit line WBLN transfers the write data to the latch cell LC.

[0041] The non-inverting bit write mask selection line BW and the inverting bit write mask selection line BWB are activated when bit write mask operations are performed. In other words, these bit write mask signal lines are activated when a high-impedance write operation is performed on any of the multiple latch cells LC. In other words, these signal lines are activated to maintain data stored in any of the multiple latch cells regardless of the write operation.

[0042] The nMOS transistor (first nMOS transistor) MN1 is connected between the inverting memory node SNb and the intermediate node (first intermediate node) ND1. The gate of nMOS transistor MN1 is connected to the non-inverting memory node SNt. The nMOS transistor (second nMOS transistor) MN2 is connected between the non-inverting memory node SNt and the low-potential power supply node Nvs. The gate of nMOS transistor MN2 is connected to the inverting memory node SNb.

[0043] The nMOS transistor (third nMOS transistor) MN3 is connected between the intermediate node ND1 and the low-potential power supply voltage node Nvs. The gate of nMOS transistor MN3 is connected to the inverting write selection line WCPN. The nMOS transistor (fourth nMOS transistor) MN4 is connected between the write bit line WBLN and the inverting storage node SNb. The gate of nMOS transistor MN4 is connected to the non-inverting write selection line WCP.

[0044] The nMOS transistor (the fifth nMOS transistor) MN5 is connected between the read bit line RBL and the non-inverting memory node SNt. The gate of nMOS transistor MN5 is connected to the non-inverting read selection line RCP. The nMOS transistor (the sixth nMOS transistor) MN6 is connected between the intermediate node ND1 and the low-potential power supply voltage node Nvs. The gate of nMOS transistor MN6 is connected to the non-inverting bit write mask selection line BW.

[0045] The first pMOS transistor MP1 is connected between the inverting memory node SNb and the intermediate node (second intermediate node) ND2. The gate of pMOS transistor MP1 is connected to the non-inverting memory node SNt. The second pMOS transistor MP2 is connected between the non-inverting memory node SNt and the high-potential power supply node Nvd. The gate of pMOS transistor MP2 is connected to the inverting memory node SNb.

[0046] The third pMOS transistor MP3 is connected between the intermediate node ND2 and the high-potential power supply node Nvd. The gate of pMOS transistor MP3 is connected to the non-inverting write selection line WCP. The fourth pMOS transistor MP4 is connected between the write bit line WBLN and the inverting memory node SNb. The gate of pMOS transistor MP4 is connected to the inverting write selection line WCPN.

[0047] The pMOS transistor (the fifth pMOS transistor) MP5 is connected between the read bit line RBL and the non-inverting memory node SNt. The gate of pMOS transistor MP5 is connected to the inverting read selection line RCPN. The pMOS transistor (the sixth pMOS transistor) MP6 is connected between the intermediate node ND2 and the high-potential power supply voltage node Nvd. The gate of pMOS transistor MP6 is connected to the inverting bit write mask selection line BWB.

[0048] <Operation of the latch cell (embodiment)> [Writing operation] Figure 4A is a timing chart showing an example of a write operation using the latch cell LC shown in Figure 3. Figure 4B is a schematic diagram to supplement the operation shown in Figure 4A. Figure 4B shows the state of each signal line in the latch cell LC and the on / off state of each transistor during the write period. In Figure 4A, the write period Twt is the period from time t1 to time t2, which is one period of the clock signal CLK. During the write period Twt, the read selection line RCP is inactive, in this case at the "L" level. Therefore, the pMOS transistor MP5 and the nMOS transistor MN5 are in the off state.

[0049] Meanwhile, the write selection line WCP transitions from an inactive state to an active state, specifically from the "L" level to the "H" level. Consequently, pMOS transistor MP4 and nMOS transistor MN4 switch from the off state to the on state. Also, pMOS transistor MP3 and nMOS transistor MN3 switch from the on state to the off state. Since no bit write mask operation is performed here, the bit write mask selection line BW transitions from an active state to an inactive state, specifically from the "H" level to the "L" level. Consequently, pMOS transistor MP6 and nMOS transistor MN6 switch from the on state to the off state.

[0050] In this state, let's consider a case where the inverted memory node SNb is rewritten from the "H" level to the "L" level. The write bit line, specifically the inverted write bit line WBLN, is at the "L" level at time t1. The ON state pMOS transistor MP4 and nMOS transistor MN4 transfer this "L" level to the "H" level memory node SNb.

[0051] In this process, the write bit line WBLN is driven by the write driver WDV shown in Figure 2. Meanwhile, the power supply voltage VDD to the pMOS transistor MP1 is cut off. As a result, the inverting memory node SNb can be rewritten to the "L" level. Furthermore, by inputting this "L" level to the pMOS transistor MP2, the non-inverting memory node SNt can be rewritten from the "L" level to the "H" level.

[0052] Subsequently, the write selection line WCP transitions from the active state to the inactive state. The bit write mask selection line BW transitions from the inactive state to the active state. Consequently, the pMOS transistor MP4 and the nMOS transistor MN4 switch from the on state to the off state. The two pMOS transistors MP3 and MP6 and the two nMOS transistors MN3 and MN6 switch from the off state to the on state. This completes the write operation.

[0053] [Read operation] Figure 5A is a timing chart showing an example of the read operation using the latch cell LC shown in Figure 3. Figure 5B is a schematic diagram to supplement the operation shown in Figure 5A. Figure 5B shows the state of each signal line in the latch cell LC and the on / off state of each transistor during the read period. In Figure 5A, the read period Trd is the period from time t3 to time t4, which is one period of the clock signal CLK.

[0054] During the read period Trd, the write selection line WCP is inactive, in this case at the "L" level. Therefore, pMOS transistor MP4 and nMOS transistor MN4 are in the off state. pMOS transistor MP3 and nMOS transistor MN3 are in the on state. Also, the bit write mask selection line BW is active, in this case at the "H" level. Therefore, pMOS transistor MP6 and nMOS transistor MN6 are in the on state. On the other hand, the read selection line RCP transitions from inactive to active, in this case from the "L" level to the "H" level. Consequently, pMOS transistor MP5 and nMOS transistor MN5 switch from the off state to the on state.

[0055] In this state, consider the case where we read out the non-inverting memory node SNt, which is storing an "H" level. The voltage level of the read bit line RBL is undefined at time t3. The ON state pMOS transistor MP5 and nMOS transistor MN5 connect the non-inverting memory node SNt to the read bit line RBL, which has an undefined voltage level. In this case, if the read bit line RBL is at an "L" level, the voltage level of the non-inverting memory node SNt may decrease from the "H" level. Accordingly, the voltage level of the inverting memory node SNb may also increase from the "L" level.

[0056] As will be described in detail later, in this embodiment, even when the voltage level of each memory node may change, the voltage level of the read bit line RBL can be correctly determined. As a result, the voltage level of the read bit line RBL becomes "H" level. Subsequently, the read selection line RCP transitions from the active state to the inactive state. Accordingly, the pMOS transistor MP5 and the nMOS transistor MN5 switch from the on state to the off state. With this, the read operation is completed.

[0057] [Bitlight mask operation] Figure 6A is a timing chart showing an example of bit write mask operation using the latch cell LC shown in Figure 3. Figure 6B is a schematic diagram to supplement the operation shown in Figure 6A. Figure 6B shows the state of each signal line in the latch cell LC and the on / off state of each transistor during the bit write mask period. In Figure 6A, the period from time t5 to time t6, which is one period of the clock signal CLK, is the bit write mask period Tbwm.

[0058] The state of the bit write mask selection line BW differs between the bit write mask period Tbwm and the write period Twt shown in Figure 4A. Specifically, during the bit write mask period Tbwm, the bit write mask selection line BW is in the active state, in this case at the "H" level. Consequently, the pMOS transistor MP6 and the nMOS transistor MN6 are in the ON state. As a result, the inverting memory node SNb is driven by either the high-potential power supply voltage VDD or the low-potential power supply voltage VSS, unlike in the case of Figure 4A.

[0059] In this state, let's assume, for example, that the inverting memory node SNb is storing an "L" level. As described in Figures 1 and 2, the write bit line WBLN is high impedance during the bit write mask period Tbwm. That is, the voltage level of the write bit line WBLN is undefined. The ON state pMOS transistor MP4 and nMOS transistor MN4 connect the write bit line WBLN, which has an undefined voltage level, to the inverting memory node SNb.

[0060] In this case, if the write bit line WBLN is at the "H" level, the voltage level of the inverting memory node SNb may rise from the "L" level. Accordingly, the voltage level of the non-inverting memory node SNt may also fall from the "H" level. As will be described in detail later, in this embodiment, even if the voltage level of each memory node changes in this way, the voltage level of each memory node can be correctly maintained. As a result, the inverting memory node SNb can maintain the "L" level regardless of the write operation.

[0061] <Regarding the difference from a latch cell (comparative example)> Figure 18 is a circuit diagram showing an example configuration of a comparative latch cell LCx. The comparative latch cell LCx differs from the configuration example shown in Figure 3 in the configuration of the write port circuit WTC and the read port circuit RDC. In Figure 18, the write port circuit WTC consists of a driver circuit consisting of two pMOS transistors MP7 and MP8 and two nMOS transistors MN7 and MN8. The read port circuit RDC consists of a driver circuit consisting of a pMOS transistor MP9 and an nMOS transistor MN9, and a transfer gate. The transfer gate consists of a pMOS transistor MP5 and an nMOS transistor MN5, as in the case of Figure 3.

[0062] As shown above, the comparative latch cell LCx consists of a total of 16 transistors. On the other hand, the latch cell LC shown in Figure 3 consists of a total of 12 transistors, or 10 transistors if the bit write mask function is not required. As a result, area reduction can be achieved in semiconductor devices with small capacity memory. More specifically, area reduction of the semiconductor device can be achieved by using the D latch macro itself. In addition, by reducing the number of transistors in the latch cell LC, the area of ​​the D latch macro itself can be reduced, further reducing the area of ​​the semiconductor device. In particular, even when D latch macros are distributed throughout the semiconductor device, the increase in area can be suppressed.

[0063] However, as shown in Figure 3, if the write port circuit WTC and the read port circuit RDC are each composed solely of transfer gates, the stability of the latch cell LC may be reduced. In other words, because the latch circuit LT is connected to the write bit line WBLN and the read bit line RBL only through transfer gates, the latch circuit LT may not be able to store the correct data. In the configuration example shown in Figure 18, this concern does not arise because a driver circuit is provided.

[0064] There are three possible cases in which the correct data cannot be stored. The first case is data corruption during read operations, as shown in Figures 5A and 5B. Specifically, "L" / "H" level data stored in the non-inverting storage node SNt may be corrupted by "H" / "H" level data pre-held in the read bit line RBL. The second case is data corruption during bit write mask operations, as shown in Figures 6A and 6B. Specifically, "L" / "H" level data stored in the inverting storage node SNb may be corrupted by "H" / "H" level data pre-held in the write bit line WBLN.

[0065] A third case involves inter-port interference during read / write operations when the latch cell LC allows dual-port operation. Specifically, when dual-port operation is allowed, the write transfer gate and the read transfer gate may be on for the same period. In this case, during a write operation, the write operation may be hindered depending on the data on the read bit line RBL. Similarly, during a read operation, the read operation may be hindered depending on the data on the write bit line WBLN.

[0066] As a specific example, assume that two memory nodes SNb / SNt store the "L" level / "H" level. Further, assume that the read bit line RBL holds the "H" level in advance. In this case, the memory node SNb on the inversion side tends to maintain the "L" level. In such a state, when rewriting the memory node SNb on the inversion side from the "L" level to the "H" level, there is a possibility that the rewrite operation fails.

[0067] <Design specifications of the latch cell (Embodiment)> FIG. 7A is a schematic diagram showing an example of the design specifications of the latch cell LC shown in FIG. 3. In FIG. 7A, let the on-current value flowing through the pMOS transistor MP4 be "I" A1 ". Let the on-current value flowing in series through the nMOS transistor MN1 and the nMOS transistor MN3 be "I" B1 ". Also, let the on-current value flowing through the nMOS transistor MN5 be "I" C1 ". Let the on-current value flowing through the pMOS transistor MP2 be "I" D1 ". Further, let the on-current value flowing through the nMOS transistor MN6 be "I" E1 ".

[0068] Here, assume that the memory node SNb on the inversion side and the memory node SNt on the non-inversion side store the "L" level and the "H" level, respectively. Assume that the write bit line WBLN holds the "H" level in advance. Assume that the read bit line RBL holds the "L" level in advance.

[0069] In this case, the stability of the latch cell LC decreases when "I" A1 > I B1 ", or when "I" C1 > I D1 ", or when "I" A1 > I E1This is the case where the stability of the latch cell LC may decrease, for example, during read operations or bit write mask operations. In this case, the write transfer gate primarily operates the pMOS transistor MP4 to charge the inverting memory node SNb, and the read transfer gate primarily operates the nMOS transistor MN5 to discharge the non-inverting memory node SNt.

[0070] Therefore, in this embodiment, as shown in Figure 7A, the latch cell LC is “I A1 B1 It is configured to satisfy the relationship of ". Also, the latch cell LC is "I C1 D1 It is configured to satisfy the relationship of ". Furthermore, the latch cell LC is "I A1 E1 The system is configured to satisfy the following relationship: This enhances the stability of the latch cell LC, i.e., the data retention capacity of the two memory nodes SNt and SNb.

[0071] In detail, for example, in Figures 5A and 6A, the voltage drop that may occur at the non-inverting storage node SNt can be suppressed. Furthermore, the voltage rise that may occur at the inverting storage node SNb can be suppressed. During the write operation, as mentioned above, the drive operation is performed by the write driver WDV shown in Figure 2. Therefore, even if the relationship described above is satisfied, the data can be written correctly, or in other words, rewritten.

[0072] Figure 7B is a schematic diagram showing an example of further design specifications for the latch cell LC shown in Figure 3. In Figure 7B, the on-current value flowing through the nMOS transistor MN4 is set to “I A2 The on-current flowing in series between pMOS transistor MP3 and pMOS transistor MP1 is set to “I B2 " and the on-current value flowing through the pMOS transistor MP5 is set to "I C2 Let's set the on-current value flowing through the nMOS transistor MN2 to "I​​​D2 Furthermore, the on-current value flowing through the pMOS transistor MP6 is set to "I E2 "Let's assume that."

[0073] Here, we assume that the inverting memory node SNb and the non-inverting memory node SNt store "H" level and "L" level, respectively. We assume that the write bit line WBLN initially holds an "L" level. We assume that the read bit line RBL initially holds an "H" level.

[0074] In this case, the stability of the latch cell LC decreases because “I A2 >I B2 In cases where it becomes " or "I C2 >I D2 In cases where it becomes "I A2 >I E2 This is the case where the stability of the latch cell LC may decrease, for example, during read operations or bit write mask operations. In this case, the write transfer gate mainly operates the nMOS transistor MN4 to discharge the inverting memory node SNb, and the read transfer gate mainly operates the pMOS transistor MP5 to charge the non-inverting memory node SNt.

[0075] Therefore, in this embodiment, as shown in Figure 7B, the latch cell LC is “I A2 B2 It is configured to satisfy the relationship of ". Also, the latch cell LC is "I C2 D2 It is configured to satisfy the relationship of ". Furthermore, the latch cell LC is "I A2 E2 The system is configured to satisfy the following relationship: This enhances the stability of the latch cell LC, i.e., the data retention capacity of the two memory nodes SNt and SNb.

[0076] ​​​The on-current value of each MOS transistor, as described above, is determined by the drain current Id in the saturation region of the MOS transistor, as shown in equation (1). In equation (1), "μ" is the electron or hole mobility, "Cx" is the gate capacitance per unit area, "Vgs" is the gate-source voltage, "Vth" is the threshold voltage, "W" is the gate width, and "L" is the gate length. Id = (1 / 2) * μ * Cx * (W / L) * (Vgs-Vth) 2 …(1)

[0077] <Main effects of the first embodiment> In the first embodiment described above, each latch cell constituting the D latch macro is composed of 10 or 12 MOS transistors. This enables area reduction in semiconductor devices with small memory capacity. Furthermore, in the first embodiment, the relationship between the on-current value of the MOS transistor constituting the transfer gate and the on-current value of the MOS transistor constituting the latch circuit is appropriately determined. This enhances the stability of the latch cells.

[0078] (Second Embodiment) <Design specifications for latch cells> Figure 8 shows an example of detailed design specifications for the latch cell LC shown in Figures 3, 7A, and 7B in the semiconductor device according to the second embodiment. Figures 7A and 7B show the design specifications for the current relationship in the latch cell LC. In the second embodiment, this current relationship is realized by setting the threshold voltage Vth based on equation (1) described above. In Figure 8, |VthP*| represents the threshold voltage Vth set for the pMOS transistor MP* in Figures 7A and 7B. Similarly, |VthN*| represents the threshold voltage Vth set for the nMOS transistor MN* in Figures 7A and 7B.

[0079] In Figure 8, the relative magnitudes of the threshold voltages Vth are determined by four conditions [A1], [A2], [A3], and [A4]. Under condition [A1], the threshold voltage |VthP4| of pMOS transistor MP4 is higher than the threshold voltages |VthN1| and |VthN3| of the two nMOS transistors MN1 and MN3. Furthermore, the threshold voltage |VthP4| of pMOS transistor MP4 is higher than the threshold voltage |VthN6| of nMOS transistor MN6.

[0080] Under condition [A3], the threshold voltage |VthN4| of the nMOS transistor MN4 is higher than the threshold voltages |VthP1| and |VthP3| of the two pMOS transistors MP1 and MP3. Furthermore, the threshold voltage |VthN4| of the nMOS transistor MN4 is higher than the threshold voltage |VthP6| of the pMOS transistor MP6.

[0081] Under condition [A2], the threshold voltage |VthN5| of the nMOS transistor MN5 is higher than the threshold voltage |VthP2| of the pMOS transistor MP2. Under condition [A4], the threshold voltage |VthP5| of the pMOS transistor MP5 is higher than the threshold voltage |VthN2| of the nMOS transistor MN2.

[0082] <Latch cell layout> Figure 9 is a perspective view showing an example of the structure of each MOS transistor constituting a latch cell in a semiconductor device according to the second embodiment. Figure 9 shows a planar type MOS transistor. Here, the plane direction of the semiconductor substrate SUB is defined as the X-axis direction and the Y-axis direction, and the direction perpendicular to these plane directions is defined as the Z-axis direction. A diffusion layer DF extending in the Y-axis direction is formed on the semiconductor substrate SUB. Insulating layers ISL are formed on both sides of the diffusion layer DF in the X-axis direction.

[0083] Furthermore, in the Z-axis direction, a gate layer GT is formed above the diffusion layer DF. The gate layer GT is made of a material such as polysilicon and is stretched in the X-axis direction. The region of the diffusion layer DF that intersects with the gate layer GT becomes the channel region CH. Above the channel region CH, a gate layer GT is formed via a gate insulating film (not shown). Also, in the Y-axis direction, the diffusion layers DF located on both sides of the channel region CH are the source diffusion layer SC and the drain diffusion layer DR, respectively.

[0084] In a pMOS transistor, the source diffusion layer SC and drain diffusion layer DR contain p-type impurities, while the channel region CH contains n-type impurities. In an nMOS transistor, the source diffusion layer SC and drain diffusion layer DR contain n-type impurities, while the channel region CH contains p-type impurities. The gate length L is determined by the length in the Y-axis direction of the channel region CH, and therefore by the thickness of the gate layer GT. The gate width W is determined by the width in the X-axis direction of the channel region CH.

[0085] Figure 10 is a schematic diagram showing an example layout configuration of the latch cell LC shown in Figures 3 and 8. In Figure 10, one transistor region AR-L and two transistor regions AR-H1 and AR-H2 are provided in the Y-axis direction. The transistor region (first transistor region) AR-L is a region for realizing a relatively low threshold voltage Vth. On the other hand, the two transistor regions (second and third transistor regions) AR-H1 and AR-H2 are regions for realizing a relatively high threshold voltage Vth.

[0086] Within the transistor regions AR-L, AR-H1, and AR-H2, two diffusion layers DFp and DFn, extending in the Y-axis direction, are formed aligned in the X-axis direction. Diffusion layer DFp is a diffusion layer for pMOS transistors, and diffusion layer DFn is a diffusion layer for nMOS transistors. In addition, multiple gate layers GT, extending in the X-axis direction, are formed aligned in the Y-axis direction. Furthermore, the impurity concentration in the channel region CH differs between the transistor region AR-L for low threshold voltages and the two transistor regions AR-H1 and AR-H2 for high threshold voltages.

[0087] Here, five gate layers GT1a, GT1b, GT2, GT3, and GT6 are provided within the transistor region AR-L. Of these, two gate layers GT3 and GT6 are provided individually for two diffusion layers DFp and DFn. As a result, four pMOS transistors and four nMOS transistors are formed within the transistor region AR-L. That is, the latch circuit LT shown in Figure 3 is formed within the transistor region AR-L.

[0088] In detail, for example, one of the two gate layers GT1a and GT1b forms the pMOS transistor MP1 and the nMOS transistor MN1. The other of the two gate layers GT1a and GT1b is a dummy gate layer that may arise due to the allocation of the diffusion layer. Furthermore, the gate layer GT2 forms the pMOS transistor MP2 and the nMOS transistor MN2. Similarly, the gate layer GT3 forms the pMOS transistor MP3 and the nMOS transistor MN3. The gate layer GT6 forms the pMOS transistor MP6 and the nMOS transistor MN6.

[0089] On the other hand, one gate layer GT4 is provided within the transistor region AR-H1. More specifically, the gate layer GT4 is provided individually for the two diffusion layers DFp and DFn. As a result, a pMOS transistor MP4 and an nMOS transistor MN4 are formed within the transistor region AR-H1. In other words, the write port circuit WTC shown in Figure 3 is formed within the transistor region AR-H1.

[0090] Furthermore, one gate layer GT5 is provided within the transistor region AR-H2. Specifically, the gate layer GT5 is provided individually for the two diffusion layers DFp and DFn. As a result, a pMOS transistor MP5 and an nMOS transistor MN5 are formed within the transistor region AR-H2. In other words, the readout port circuit RDC shown in Figure 3 is formed within the transistor region AR-H2.

[0091] Thus, in Figure 10, the latch circuit LT is positioned between the write port circuit WTC and the read port circuit RDC in the Y-axis direction (first direction). This suppresses interference between, for example, the write bit line WBLN connected to the write port circuit WTC and the read bit line RBL connected to the read port circuit RDC. Furthermore, it makes it easier to secure layout space for each circuit that constitutes the data input / output circuit IOC shown in Figure 2.

[0092] In Figure 10, two dummy gate layers GTd1 and GTd2 are provided at the boundary between transistor region AR-L and transistor region AR-H1 to secure separation space. Similarly, two dummy gate layers GTd3 and GTd4 are provided at the boundary between transistor region AR-L and transistor region AR-H2 to secure separation space.

[0093] Depending on the manufacturing process applied, such separation spaces may be necessary to separate regions with different threshold voltages Vth. For example, in Figure 10, the diffusion layer DFp within transistor region AR-H1 is separated from the diffusion layer DFp within the adjacent transistor region AR-L. Note that the layout configuration example shown in Figure 10 is applicable not only to planar MOS transistors like those shown in Figure 9, but also to FinFETs, which will be discussed later.

[0094] Figure 11 is a schematic diagram showing a different layout configuration example of the latch cell LC shown in Figures 3 and 8 compared to Figure 10. The latch cell LC shown in Figure 11 has a different number of dummy gate layers compared to Figure 10. Specifically, one dummy gate layer GTd1 is provided at the boundary between transistor region AR-L and transistor region AR-H1. Similarly, one dummy gate layer GTd4 is provided at the boundary between transistor region AR-L and transistor region AR-H2.

[0095] Depending on the manufacturing process applied, inserting a single dummy gate layer in this way can separate regions with different threshold voltages Vth. When a layout configuration example like the one shown in Figure 11 can be applied, the latch cell LC can be further reduced in area compared to the case in Figure 10.

[0096] <Regarding the difference from a latch cell (comparative example)> Figure 19 is a schematic diagram showing an example layout configuration of the latch cell LCx shown in Figure 18. In Figure 19, two transistor regions AR-H and AR-L are formed. Transistor region AR-H is a region for achieving a relatively high threshold voltage. Transistor region AR-L is a region for achieving a relatively low threshold voltage. And, contrary to the case in Figure 11, the latch circuit LT in Figure 18 is formed in transistor region AR-H. On the other hand, the write port circuit WTC and the read port circuit RDC in Figure 18 are formed in transistor region AR-L.

[0097] In Figure 19, the latch cell LCx requires a total of 10 gate layers GT, including one dummy gate layer GTd. On the other hand, the latch cell LC shown in Figure 11 only needs a total of 9 gate layers GT, including two dummy gate layers GTd1 and GTd4. Thus, even with the addition of two dummy gate layers in Figure 11, the latch cell LC can be made more compact compared to the case in Figure 19.

[0098] <Main effects of the second embodiment> As described above, the method according to the second embodiment can be used to obtain the same effects as those described in the first embodiment. Furthermore, in the method according to the second embodiment, the stability of the latch cell can be improved by appropriately setting the threshold voltage Vth. The method according to the second embodiment is particularly useful as a method for saving space when there are layout rules with relatively little flexibility regarding line width, pitch, etc.

[0099] (Third embodiment) <Design specifications for latch cells> Figure 12 shows an example of detailed design specifications for the latch cell LC shown in Figures 3, 7A, and 7B in the semiconductor device according to the third embodiment. In the second embodiment, the current relationship shown in Figures 7A and 7B was realized by setting the threshold voltage Vth. In the third embodiment, this current relationship is realized by setting the "gate width W / gate length L" based on the equation (1) described above. In Figure 12, (W / L) P* This represents the (W / L) set for the pMOS transistor MP* in Figures 7A and 7B. Similarly, (W / L) N* This represents the (W / L) value set for the nMOS transistor MN* in Figures 7A and 7B.

[0100] In Figure 12, the relative magnitudes of (W / L) are determined by four conditions [B1], [B2], [B3], and [B4]. Under condition [B1], the (W / L) of pMOS transistor MP4 is smaller than the (W / L) of the two nMOS transistors MN1 and MN3. Furthermore, the (W / L) of pMOS transistor MP4 is smaller than the (W / L) of nMOS transistor MN6.

[0101] Under condition [B3], the (W / L) of nMOS transistor MN4 is smaller than the (W / L) of the two pMOS transistors MP1 and MP3. Furthermore, the (W / L) of nMOS transistor MN4 is smaller than the (W / L) of pMOS transistor MP6.

[0102] Under condition [B2], the (W / L) of the nMOS transistor MN5 is smaller than the (W / L) of the pMOS transistor MP2. Under condition [B4], the (W / L) of the pMOS transistor MP5 is smaller than the (W / L) of the nMOS transistor MN2.

[0103] <Latch cell layout> Figure 13 is a schematic diagram showing an example layout configuration of the latch cell LC shown in Figures 3 and 12. In Figure 13, each MOS transistor is arranged in the same way as in Figure 11. That is, in the Y-axis direction, the write port circuit WTC and the read port circuit RDC are arranged on both sides of the latch circuit LT, respectively. However, Figure 13 differs from Figure 11 in the following three points. The first difference is that the threshold voltage Vth of each nMOS transistor is the same. The threshold voltage Vth of each pMOS transistor is also the same.

[0104] The second difference is that, here, instead of two, one dummy gate layer GTd5 is provided. The dummy gate layer GTd5 is provided between the pMOS transistor MP4 and the nMOS transistor MN4, and between the pMOS transistor MP3 and the nMOS transistor MN3. Unlike in Figure 11, this dummy gate layer GTd5 may arise due to the allocation of the diffusion layer, rather than to separate the transistor regions.

[0105] Furthermore, as a third difference, each of the two diffusion layers DFp and DFn has two different sizes in the X-axis direction. As a result, the four nMOS transistors MN1-MN3 and MN6 that constitute the latch circuit LT have the same gate width (first gate width) W1. On the other hand, the two nMOS transistors MN4 and MN5 that constitute the write port circuit WTC and the read port circuit RDC have the same gate width (second gate width) W2. The gate width W2 is smaller than the gate width W1.

[0106] Similarly, the four pMOS transistors MP1-MP3 and MP6 that constitute the latch circuit LT have the same gate width (third gate width) W3. On the other hand, the two pMOS transistors MP4 and MP5 that constitute the write port circuit WTC and the read port circuit RDC have the same gate width (fourth gate width) W4. The gate width W4 is smaller than the gate width W3.

[0107] Note that the gate length L of each pMOS transistor and each nMOS transistor is the same. On the other hand, for example, the gate width W1 of an nMOS transistor and the gate width W3 of a pMOS transistor may be equivalent depending on the manufacturing process. That is, for example, if the difference between the electron mobility and the hole mobility shown in equation (1) can be ignored to some extent, the gate widths W1 and W3 may be equivalent. Also, the gate widths W2 and W4 may be equivalent.

[0108] On the other hand, if the difference between electron mobility and hole mobility cannot be ignored, for example, the gate width W3 of a pMOS transistor may be larger than the gate width W1 of an nMOS transistor. Even in this case, in order to realize the current relationship shown in Figure 12, the diffusion layer DFn is configured to have two gate widths W1 and W2. The diffusion layer DFp is also configured to have two gate widths W3 and W4.

[0109] Figure 14 is a schematic diagram showing a different layout configuration for the latch cell LC shown in Figures 3 and 12 compared to Figure 13. In Figure 14, each MOS transistor is arranged in the same way as in Figure 13. That is, in the Y-axis direction, the write port circuit WTC and the read port circuit RDC are arranged on both sides of the latch circuit LT, respectively. However, Figure 14 differs from Figure 13 in the following two points. The first difference is that each pMOS transistor has the same gate width W. Each nMOS transistor also has the same gate width W.

[0110] The second difference is that the gate layer GT has two different sizes in the Y-axis direction. As a result, the four nMOS transistors MN1-MN3 and MN6 that make up the latch circuit LT have the same gate length (first gate length) L1. The four pMOS transistors MP1-MP3 and MP6 that make up the latch circuit LT also have the same gate length L1. On the other hand, the two nMOS transistors MN4 and MN5 that make up the write port circuit WTC and the read port circuit RDC have the same gate length (second gate length) L2. The two pMOS transistors MP4 and MP5 that make up the latch circuit LT also have the same gate length L2. And the gate length L2 is larger than the gate length L1.

[0111] <Main effects of the third embodiment> As described above, the same effects as those described in the first embodiment can be obtained by using the method according to the third embodiment. Furthermore, in the method according to the third embodiment, the stability of the latch cell can be improved by appropriately setting the "gate width W / gate length L". For example, when using a manufacturing process in which it is difficult to apply the second embodiment, that is, when it is difficult to set multiple threshold voltages Vth, the method according to the third embodiment may be used. In addition, each method shown in Figures 13 and 14 can be appropriately selected, for example, depending on the manufacturing process to which it is applied. Furthermore, each method can be appropriately selected according to the required performance of the latch cell LC, for example, target values ​​such as area, speed, and leakage current.

[0112] (Fourth embodiment) <Latch cell layout> Figure 15 is a perspective view showing an example of the structure of each MOS transistor constituting a latch cell in a semiconductor device according to the fourth embodiment. Unlike the planar MOS transistor shown in Figure 9, Figure 15 shows a FinFET. In a FinFET, the diffusion layer DF is formed by multiple fins, in this example, three fins. The multiple fins are formed aligned in the X-axis direction and extended in the Y-axis direction. The gate layer GT is formed to cover three of the four surfaces that form the surface of each fin, via a gate insulating film (not shown).

[0113] The region of the diffusion layer DF covered by the gate layer GT is the channel region CH. Furthermore, the diffusion layers DF located on either side of the channel region CH in the Y-axis direction are the source diffusion layer SC and the drain diffusion layer DR, respectively. Using such a FinFET increases the contact area between the gate layer GT and the channel region CH. Therefore, transistor performance can be improved, for example, by reducing leakage current. Also, in a FinFET, the gate width W is determined by the number of fins.

[0114] Figure 16 is a schematic diagram showing an example of the layout configuration of the latch cell LC shown in Figures 3 and 12 in the semiconductor device according to the fourth embodiment. In the fourth embodiment, as in the third embodiment, the current relationship shown in Figure 3 is realized by setting the "gate width W / gate length L". However, in the fourth embodiment, unlike in the third embodiment, each MOS transistor is composed of a FinFET as shown in Figure 15.

[0115] In Figure 16, each MOS transistor is arranged in the same way as in Figure 13. That is, in the Y-axis direction, the write port circuit WTC and the read port circuit RDC are arranged on either side of the latch circuit LT. Also, each of the two diffusion layers DFp and DFn has two different sizes in the X-axis direction, and consequently, two different gate widths W. However, Figure 16 differs from Figure 13 in the following two points.

[0116] The first difference is that the gate width W shown in Figure 13 is realized by the number of fins. That is, the four nMOS transistors MN1-MN3 and MN6 each have the same number of fins (first number of fins) FN1, in this case 3. The remaining two nMOS transistors MN4 and MN5 also have the same number of fins (second number of fins) FN2, in this case 2. And the number of fins FN2 is less than the number of fins FN1.

[0117] Similarly, the four pMOS transistors MP1-MP3 and MP6 each have the same number of fins (the third fin number) FN3, in this case three. The remaining two pMOS transistors MP4 and MP5 also have the same number of fins (the fourth fin number) FN4, in this case two. The number of fins FN4 is less than the number of fins FN3. Note that the gate length L of each MOS transistor may be the same.

[0118] Here, as in the case of Figure 13, depending on the manufacturing process, the number of fins FN1 and FN3 may be the same. Similarly, the number of fins FN2 and FN4 may also be the same. In particular, when using a FinFET, the difference in electron and hole mobility can sometimes be ignored compared to when using a planar MOS transistor.

[0119] The second difference is the formation of dummy gate layers to switch the number of fins. Specifically, two dummy gate layers GTd1 and GTd2 are formed between the write port circuit WTC and the latch circuit LT. Similarly, two dummy gate layers GTd3 and GTd4 are formed between the read port circuit RDC and the latch circuit LT.

[0120] Figure 17 is a schematic diagram showing a different layout configuration example for the latch cell LC shown in Figures 3 and 12 in the semiconductor device according to the fourth embodiment, compared to the case in Figure 16. Figure 17 shows a layout that is almost the same as that in Figure 16. However, Figure 17 differs from Figure 16 in the following three points. The first difference is that the number of fins, and therefore the gate width W, of each MOS transistor is the same, in this case, 3.

[0121] The second difference is that, as in Figure 14, each MOS transistor has two different gate lengths L. That is, the four nMOS transistors MN1-MN3, MN6 and the four pMOS transistors MP1-MP3, MP6 have the same gate length L1. The remaining two nMOS transistors MN4, MN5 and the two pMOS transistors MP4, MP5 also have the same gate length L2. And gate length L2 is larger than gate length L1.

[0122] A third difference is that in the write port circuit (WTC), the dummy gate layer GTd1 is formed with a gate length of L2, while the dummy gate layer GTd2 is formed with a gate length of L1. Similarly, in the read port circuit (RDC), the dummy gate layer GTd4 is formed with a gate length of L2, while the dummy gate layer GTd3 is formed with a gate length of L1.

[0123] <Main effects of the fourth embodiment> As described above, the method according to the fourth embodiment can be used to obtain the same effects as those described in the first and third embodiments. Furthermore, in the method according to the fourth embodiment, for example, the stability of the latch cell can be improved by appropriately setting the number of fins. In addition, by using FinFETs, the performance of each transistor can be improved, and for example, the power consumption of the semiconductor device can be reduced.

[0124] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0125] AR-H1, AR-H2, AR-L Transistor Regions BW Non-inverted bit write mask selection line BWB Inverted BitWrite Mask Selection Line LC latch cell MN1-MN6 nMOS transistors MP1-MP6 pMOS transistors ND1, ND2 intermediate nodes QLT read latch circuit RBL Read Bit Line RCP non-inverted readout selection line RCPN inverted readout selection line SNb inverted memory node SNt non-inverted memory node WBLN write bit line WCP non-inverted side write selection line WCPN Inverted side write selection line

Claims

1. The non-inverted write selection line and the inverted write selection line are activated during the write operation, The non-inverted read selection line and the inverted read selection line are activated during the read operation, A plurality of latch cells connected to the non-inverting write selection line and the inverting write selection line, and the non-inverting read selection line and the inverting read selection line, Multiple read bit lines for transferring read data from the multiple latch cells, Multiple write bit lines for transferring write data to the multiple latch cells, It has, Each of the aforementioned plurality of latch cells is A first storage node and a second storage node that store complementary data, A first nMOS transistor is connected between the first memory node and the first intermediate node, and its gate is connected to the second memory node. A second nMOS transistor is connected between the second memory node and the low-potential power supply voltage node, and its gate is connected to the first memory node. A third nMOS transistor is connected between the first intermediate node and the low-potential power supply voltage node, and its gate is connected to the inverting write selection line, A fourth nMOS transistor is connected between one of the plurality of write bit lines and the first storage node, and its gate is connected to the non-inverting write selection line. A fifth nMOS transistor is connected between one of the plurality of read bit lines and the second storage node, and its gate is connected to the non-inverting read selection line. A first pMOS transistor is connected between the first memory node and the second intermediate node, and its gate is connected to the second memory node. A second pMOS transistor is connected between the second memory node and the high-potential power supply voltage node, and its gate is connected to the first memory node. A third pMOS transistor is connected between the second intermediate node and the high-potential power supply voltage node, and its gate is connected to the non-inverting write selection line, A fourth pMOS transistor is connected between one of the plurality of write bit lines and the first storage node, and its gate is connected to the inverting write selection line. A fifth pMOS transistor is connected between one of the plurality of read bit lines and the second storage node, and its gate is connected to the inverting read selection line. Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, The ON current value flowing through the fourth pMOS transistor is set to "I Ａ１ ", the ON current value flowing through the first nMOS transistor and the third nMOS transistor is "I Ｂ１ If we do this, then "I Ａ１ <I Ｂ１ It is configured to satisfy the relationship of ", The ON current value flowing through the fifth nMOS transistor is set to "I Ｃ１ ", the ON current value flowing through the second pMOS transistor is "I Ｄ１ If we do this, then "I Ｃ１ <I Ｄ１ It is configured to satisfy the relationship of ", The on-current value flowing through the fourth nMOS transistor is "I Ａ２ ", and when the on-current values flowing through the third pMOS transistor and the first pMOS transistor are "I Ｂ２ ", it is configured to satisfy the relationship of "I Ａ２ < I Ｂ２ ", The ON current value flowing through the fifth pMOS transistor is set to "I Ｃ２ ", the ON current value flowing through the second nMOS transistor is "I Ｄ２ If we do this, then "I Ｃ２ <I Ｄ２ It is structured to satisfy the relationship of Semiconductor equipment.

3. In the semiconductor device described in claim 2, The threshold voltage of the fourth pMOS transistor is higher than the threshold voltages of the first nMOS transistor and the third nMOS transistor. The threshold voltage of the fifth nMOS transistor is higher than the threshold voltage of the second pMOS transistor. The threshold voltage of the fourth nMOS transistor is higher than the threshold voltages of the first pMOS transistor and the third pMOS transistor. The threshold voltage of the fifth pMOS transistor is higher than the threshold voltage of the second nMOS transistor. Semiconductor equipment.

4. In the semiconductor device described in claim 3, A first transistor region, which is a region for achieving a relatively low threshold voltage, This region is for achieving a relatively high threshold voltage, and in the first direction, it comprises a second transistor region and a third transistor region arranged on both sides of the first transistor region, Equipped with, The first transistor region has a first nMOS transistor, a second nMOS transistor, a third nMOS transistor, a first pMOS transistor, a second pMOS transistor, and a third pMOS transistor formed therein. The second transistor region has the fourth nMOS transistor and the fourth pMOS transistor formed therein. The third transistor region has the fifth nMOS transistor and the fifth pMOS transistor formed therein. Semiconductor equipment.

5. In the semiconductor device described in claim 2, The gate width / gate length of the fourth pMOS transistor is smaller than that of the first nMOS transistor and the third nMOS transistor. The gate width / gate length of the fifth nMOS transistor is smaller than that of the second pMOS transistor. The gate width / gate length of the fourth nMOS transistor is smaller than that of the first pMOS transistor and the third pMOS transistor. The gate width / gate length of the fifth pMOS transistor is smaller than that of the second nMOS transistor. Semiconductor equipment.

6. In the semiconductor device described in claim 2, The first nMOS transistor, the second nMOS transistor, and the third nMOS transistor are positioned in the first direction between the fourth nMOS transistor and the fifth nMOS transistor. The first pMOS transistor, the second pMOS transistor, and the third pMOS transistor are positioned in the first direction between the fourth pMOS transistor and the fifth pMOS transistor. Semiconductor equipment.

7. In the semiconductor device described in claim 6, Each MOS transistor has the same gate length. The first nMOS transistor, the second nMOS transistor, and the third nMOS transistor each have a first gate width of the same size. The fourth nMOS transistor and the fifth nMOS transistor have the same second gate width. The second gate width is smaller than the first gate width. The first pMOS transistor, the second pMOS transistor, and the third pMOS transistor each have a third gate width of the same size. The fourth pMOS transistor and the fifth pMOS transistor have the same fourth gate width. The fourth gate width is smaller than the third gate width. Semiconductor equipment.

8. In the semiconductor device described in claim 6, Each pMOS transistor has the same gate width. Each nMOS transistor has the same gate width. The first nMOS transistor, the second nMOS transistor, the third nMOS transistor, the first pMOS transistor, the second pMOS transistor, and the third pMOS transistor all have the same first gate length. The fourth nMOS transistor, the fifth nMOS transistor, the fourth pMOS transistor, and the fifth pMOS transistor each have a second gate length of the same size. The second gate length is greater than the first gate length. Semiconductor equipment.

9. In the semiconductor device described in claim 6, Each MOS transistor is composed of a FinFET. The first nMOS transistor, the second nMOS transistor, and the third nMOS transistor each have the same number of first Fin numbers. The fourth nMOS transistor and the fifth nMOS transistor have the same number of second Fin numbers. The second Fin number is less than the first Fin number. The first pMOS transistor, the second pMOS transistor, and the third pMOS transistor each have the same number of third Fin values. The fourth pMOS transistor and the fifth pMOS transistor have the same number of fourth Fin values. The fourth Fin number is less than the third Fin number. Semiconductor equipment.

10. In the semiconductor device described in claim 9, The first Fin number and the third Fin number are the same number. The second Fin number and the fourth Fin number are the same number. Semiconductor equipment.

11. In the semiconductor device described in claim 1, Furthermore, it includes a plurality of non-inverting bit write mask selection lines and a plurality of inverting bit write mask selection lines that are activated when a high-impedance write operation is performed on any of the plurality of latch cells, Each of the aforementioned plurality of latch cells further, A sixth nMOS transistor is connected between the first intermediate node and the low-potential power supply voltage node, and its gate is connected to one of the plurality of non-inverting bit write mask selection lines, A sixth pMOS transistor is connected between the second intermediate node and the high-potential power supply voltage node, and its gate is connected to one of the plurality of inverting bit write mask selection lines, Equipped with, Semiconductor equipment.

12. In the semiconductor device according to claim 11, The ON current value flowing through the fourth pMOS transistor is set to "I Ａ１ ", the ON current value flowing through the first nMOS transistor and the third nMOS transistor is "I Ｂ１ If we do this, then "I Ａ１ <I Ｂ１ It is configured to satisfy the relationship of ", The ON current value flowing through the fifth nMOS transistor is set to "I Ｃ１ ", the ON current value flowing through the second pMOS transistor is "I Ｄ１ If we do this, then "I Ｃ１ <I Ｄ１ It is configured to satisfy the relationship of ", The ON current value flowing through the fourth nMOS transistor is set to "I Ａ２ ", the ON current value flowing through the third pMOS transistor and the first pMOS transistor is "I Ｂ２ If we do this, then "I Ａ２ <I Ｂ２ It is configured to satisfy the relationship of ", The ON current value flowing through the fifth pMOS transistor is set to "I Ｃ２ ", the ON current value flowing through the second nMOS transistor is "I Ｄ２ If we do this, then "I Ｃ２ <I Ｄ２ It is configured to satisfy the relationship of ", The ON current value flowing through the sixth nMOS transistor is set to "I Ｅ１ If we do this, then "I Ａ１ <I Ｅ１ It is configured to satisfy the relationship of ", The ON current value flowing through the sixth pMOS transistor is set to "I Ｅ２ If we do this, then "I Ａ２ <I Ｅ２ It is structured to satisfy the relationship of Semiconductor equipment.

13. In the semiconductor device described in claim 1, Furthermore, the system includes a read latch circuit that inputs and latches the read data transferred to the plurality of read bit lines without going through a sense amplifier. Semiconductor equipment.

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