Semiconductor equipment

Abstract

Transistors with excellent electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) We will provide Zista. [Solution] The transistor comprises an oxide semiconductor layer having a channel formation region, first, second It has a gate electrode, a source electrode, and a drain electrode. The first and second gate electrodes are acid An oxide semiconductor layer is sandwiched in between. The oxide semiconductor layer is the source electrode, the drain electrode It has a pair of sides that are in contact with the pole, and without the source electrode and drain electrode in between, the first It has a region enclosed by a second electrode.

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and their driving methods, or their manufacturing methods.

[0002] In this specification, a semiconductor device refers to a circuit including semiconductor elements (such as transistors and diodes), and a device having the same circuit. Further, it refers to all devices that can function by utilizing semiconductor characteristics . For example, integrated circuits, chips equipped with integrated circuits, display devices, light-emitting devices , lighting devices, and electronic devices may have a semiconductor device.

Background Art

[0003] Transistors are widely used in various electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductors applicable to transitors, but oxide semiconductors are attracting attention as other materials . For example, a transistor using an amorphous oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) is disclosed in Patent Document 1

[0004] .

[0005] In addition, techniques for improving the carrier mobility by forming an oxide semiconductor layer into a laminated structure are disclosed in Patent Document 2 and Patent Document 3 .

[0006] In addition, as one means for miniaturizing and narrowing the border of an active matrix type display device, a pixel It is known that the driver circuit and the part are fabricated on the same substrate. Pixel circuit of a display device This is fabricated using either an n-channel or p-channel transistor. This is possible. Therefore, by reducing the number of manufacturing steps and lowering manufacturing costs, the bezel width can be reduced. To fabricate a narrow display device, single-conductivity transistors are used instead of CMOS circuits. It is preferable to design the driver accordingly.

[0007] The main circuit in the driver circuit of a display device is a shift register. For example, see Patent Document 4. In the case of 5, a shift register composed of transistors using an oxide semiconductor layer is opened. It is shown. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Patent Document 2] Japanese Patent Publication No. 2011-138934 [Patent Document 3] Japanese Patent Publication No. 2011-124360 [Patent Document 4] Japanese Patent Publication No. 2011-090761 [Patent Document 5] Japanese Patent Publication No. 2011-209714 [Overview of the project] [Problems that the invention aims to solve]

[0009] The objective of one embodiment of the present invention is to provide a semiconductor device capable of controlling the threshold voltage. Or, semiconductors with excellent electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) The objective is to provide a conductive device.

[0010] One object of this invention is to improve the reliability of a semiconductor device composed of unipolar transistors. To do so, or to increase its driving frequency. Or, one embodiment of the present invention The challenge is to provide a novel semiconductor device.

[0011] Furthermore, the description of multiple problems does not preclude the existence of each other. The form does not need to solve all of these problems. Also, if there are other problems not listed, the specification These issues will become clear from the drawings, claims, etc., and these issues will also be addressed in this invention. This could become a challenge for one aspect of the Ming Dynasty. [Means for solving the problem]

[0012] One embodiment of the present invention is an oxide semiconductor layer having a channel-forming region and first and second gate electricity It has an electrode, first and second insulating layers, a source electrode, and a drain electrode, and the first gate electrode The electrode faces the oxide semiconductor layer via the first insulating layer, and the second gate electrode faces the second insulating layer Facing the oxide semiconductor layer via an intervening element, and provided in the first and second insulating layers, at least one The first opening is in contact with the first gate electrode, and the oxide semiconductor layer is the source electrode, The region surrounded by the first and second sides in contact with the drain electrode and the first and second gate electrodes. It is a transistor having [a certain characteristic].

[0013] One embodiment of the present invention is an oxide semiconductor layer having a channel-forming region and first and second channels It has a drain electrode, first and second insulating layers, a source electrode, and a drain electrode, and the first The first gate electrode and the second gate electrode are provided with an oxide semiconductor layer in between, and the first gate electrode is Distributed below the oxide semiconductor layer via an insulating layer 1, the first gate electrode, the first insulating The layer, oxide semiconductor layer, source electrode, and drain electrode are covered by a second insulating layer. The second gate electrode is located in at least one first opening provided in the first and second insulating layers. The oxide semiconductor layer is in contact with the first gate electrode, and is in contact with the source electrode and drain electrode. The oxide semiconductor layer has first and second sides, and sandwiches the source electrode and the drain electrode. A semiconductor transistor having a region surrounded by a first and second electrode. It is a body device. [Effects of the Invention]

[0014] One embodiment of the present invention provides a semiconductor device capable of controlling a threshold voltage. However, semiconductor devices with excellent electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) To provide, or a highly reliable semiconductor device; To provide, or an oxide To provide a semiconductor device in which a driver circuit and a pixel are fabricated on the same substrate from a semiconductor film. This becomes possible. Alternatively, one embodiment of the present invention makes it possible to provide a novel semiconductor device. It will become.

[0015] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0016] [Figure 1]A diagram showing an example of a transistor configuration. A: Circuit symbol. B: Plan view. C: Cross-sectional view of the same diagram B, cut along the cutting line A1-A2. D: Cross-sectional view of the same diagram B, cut along the cutting line B1-B2. [Figure 2] A diagram showing an example of a transistor configuration. A: Circuit symbol. B: Plan view. C: Cross-sectional view of the same diagram B, cut along the cutting line A1-A2. D: Cross-sectional view of the same diagram B, cut along the cutting line B1-B2. [Figure 3] A diagram showing an example of a transistor configuration. A: Circuit symbol. B: Plan view. C: Cross-sectional view of the same diagram B, cut along the cutting line A1-A2. D: Cross-sectional view of the same diagram B, cut along the cutting line B1-B2. [Figure 4] AC: A cross-sectional view showing an example of a transistor fabrication method. [Figure 5] AC: A cross-sectional view showing an example of a transistor fabrication method. [Figure 6] A, B: Cross-sectional diagrams showing an example of a transistor fabrication method. [Figure 7] A, B: Cross-sectional diagrams showing an example of a transistor fabrication method. [Figure 8] Circuit symbol diagram for an inverter circuit. [Figure 9] A: Circuit diagram showing an example of an inverter circuit configuration. B: Truth table for an inverter circuit. [Figure 10] A and B: Circuit diagrams showing an example of an inverter circuit configuration. [Figure 11] A: Circuit symbol diagram of a clocked inverter circuit. B, C: Circuit diagrams showing an example of the configuration of a clocked inverter circuit. [Figure 12] A: Circuit symbol diagram of a latch circuit. B: Circuit diagram showing an example of a latch circuit configuration. [Figure 13] A circuit diagram showing an example of a shift register configuration. [Figure 14] A block diagram showing an example of the configuration of an active-matrix display device. [Figure 15] AC: A plan view showing an example of the display panel configuration. [Figure 16] An exploded perspective view showing an example of the configuration of an active-matrix display device. [Figure 17]A and B: Circuit diagrams showing an example of pixel configuration. [Figure 18] A plan view showing an example of the pixel configuration. [Figure 19] A cross-sectional view showing an example of the pixel configuration. [Figure 20] AF: A diagram showing an example of the configuration of electronic equipment. [Figure 21] AF: A diagram illustrating an example of RFID tag usage. [Figure 22] A, B: Nanobeam electron diffraction patterns of oxide semiconductor films. [Figure 23] A, B: Diagrams showing examples of transmission electron diffraction measurement devices. [Figure 24] A graph showing an example of structural analysis using transmission electron diffraction measurement. [Modes for carrying out the invention]

[0017] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The present invention is not limited to the following description, and its form may not depart from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, The present invention is not limited to the embodiments described below.

[0018] Furthermore, although several embodiments of the present invention are shown below, these embodiments can be combined as appropriate. It goes without saying that this is possible. Also, within one embodiment, there are several configuration examples. Even when such configurations are shown, it is possible to combine the examples of each configuration as appropriate.

[0019] Furthermore, in the drawings used to describe embodiments of the invention, the same part or similar function may be shown. Parts that share the same component are denoted by the same symbol, and explanations of their repetitions may be omitted.

[0020] A transistor is an element that has three terminals called the gate, source, and drain. Yes. The two terminals that function as source or drain are the channel type of the transistor. Depending on the voltage applied to each terminal, one terminal becomes the source and the other becomes the drain. Generally, in an n-channel transistor, the terminal to which a low voltage is applied is called the source. The terminal to which a high voltage is applied is called the drain. Conversely, in a p-channel transistor... In this system, the terminal to which a low voltage is applied is called the drain, and the terminal to which a high voltage is applied is called the source. It is called [this]. Below, in order to facilitate understanding of the circuit configuration and operation, we will use two transistors. In some cases, the explanation is limited to one terminal as the source and the other as the drain. Of course, the drive Depending on the method, the relative magnitudes of the voltages applied to each terminal of the transistor change, and the source and The drains may be swapped.

[0021] Furthermore, the transistor has a second gate for applying voltage to the back channel. In some cases, a gate may be provided. In that case, to distinguish between the two gates, we will refer to the gate and the normal call gate. We'll call the terminal that's exposed the "front gate," and the other one the "back gate."

[0022] (Embodiment 1) In this embodiment, a transistor will be described as an example of a semiconductor device. Here, The front gate is located on the substrate side of the semiconductor layer where the channel is formed, and the bottom gate is located on the substrate side. Let's explain the T-type transistor.

[0023] <Configuration Example 1: FET-1> Figure 1A shows the circuit symbol for a transistor in Configuration Example 1. The transistor is a front gate. It has two gates, a front gate and a back gate, with the back gate being connected to the front gate. They are connected. Here, the transistor represented by the circuit symbol in Figure 1A is called FET-1. Bu.

[0024] Note that the circuit symbol in Figure 1A is such that the transistor (FET-1) has a width in the channel length direction. The back gate is longer than the front gate, and the back gate is formed in the semiconductor layer. This indicates that the device structure overlaps with the drain region. Figures 1B-1D illustrate the device structure of FET-1.

[0025] Figures 1B-1D show an example of the device structure of FET-1. Figure 1B shows the transistor This is a top view. Figure 1C is a cross-sectional view taken along the cutting line A1-A2 in Figure 1B, and Figure 1D is a cross-sectional view taken along the cutting line A1-A2 in Figure 1B. This is a cross-sectional view taken along the break B1-B2. Figure 1C also shows the transistor in the channel width direction. This is a cross-sectional view, and Figure 1D is also a cross-sectional view of the transistor in the channel length direction.

[0026] The transistor 11 is formed on the substrate 100, and consists of an insulating layer 101, an insulating layer 102, and a flow Socket gate electrode 121, oxide semiconductor (OS) layer 130, source electrode 140S, drain It has an electrode 140D and a back gate electrode 150. In the channel width direction, the insulating layer 10 Openings 172 and 173 are formed in 1 and 102. Openings 172 and 173 are used to control odor The back gate electrode 150 is in contact with the front gate electrode 121, and the back gate electrode Pole 150 is connected to the front gate electrode 121.

[0027] The insulating layer 101 constitutes a gate insulating layer for the front gate electrode 121, and the insulating layer 10 2 constitutes the gate insulating layer for the back gate electrode 150.

[0028] A transistor in which the channel formation region is made of Si (hereinafter referred to as a Si transistor) is S By adding impurities to the i-layer, the resistance of the Si layer is partially reduced, thereby lowering the source region. , forming a drain region. In contrast, the channel formation region is made of an oxide semiconductor. A transistor (hereinafter referred to as an OS transistor) has a source electrode or a drive in an oxide semiconductor layer. By directly joining the rain electrodes, a device with the electrical characteristics of a transistor can be created. It can be obtained.

[0029] Therefore, in transistor 11, the source electrode 140S and the drain electrode 140D are Each is provided in contact with the OS layer 130. In transistor 11, the channel length is shortened. Therefore, in the OS layer 130, the source electrode 140S and the drain electrode 140D are in contact. The region exists on the top surface as well, but is mainly present on its sides. The region in contact with the - electrode 140S and drain electrode 140D is due to a common conductive film. By etching 141 and 142), the source electrode 140S and the drain electrode 140D are produced. This is because it forms these particles, suppressing variations in size and resulting in a good yield. This is because, on the side surface of the OS layer 130, the source electrode 140S and the drain electrode This is to maximize the area in contact with the pole 140D.

[0030] Here, the length L1 of the OS layer 130 shown in Figure 1D is defined as the channel length of the transistor 11. The channel length L1 is determined by the source electrode 140S and drain electrode on the upper surface of the OS layer 130. This corresponds to the distance between 140D. Also, length L2 is the channel length of OS layer 130. Therefore, the region in contact with the source electrode 140S and the drain electrode 140D is the OS layer. By being located on the 130 side, the channel length L1 is shortened while L2 is also shortened as much as possible. This allows us to bring it closer to L1, and as a result, the on-current characteristics of transistor 11 can be improved. This allows for improved frequency response while maintaining the necessary bandwidth.

[0031] The channel length L1 should be 0.5 μm or more. L1 is preferably 0.5 μm to 2 μm. The thickness is μm, and more preferably 0.5 μm to 1 μm. Also, the thickness of the OS layer 130. The wavelength should be 150 nm or greater; for example, it can be 150 nm to 1.5 μm. A thickness of 250 nm to 1.5 μm is more preferable. The detailed configuration of the OS layer 130 will be described later. However, if the OS layer 130 consists of two metal oxide films 131 and 132, the first metal oxide film The thickness of the material film 131 should be 100 nm or more, for example, 100 nm to 1000 nm. m is sufficient, and 200 nm to 1000 nm is preferred. Also, the second layer is a metal oxide film. The thickness of 132 should be 50 nm or more, between 50 nm and 500 nm, or 10 It should be between 0nm and 300nm.

[0032] The OS layer 130 is provided sandwiched between the front gate electrode 121 and the back gate electrode 150. The channel length and channel width are greater for the back gate electrode 150. The OS layer 130 is longer than the S layer 130, and the entire OS layer 130 is back gate electrode via the insulating layer 102. It is covered with 150. In the planar layout of Figure 1B, the OS layer 130 is a back gate. It is located inside electrode 150.

[0033] In the channel width direction, openings 172 and 173 are formed in the insulating layers 101 and 102. At openings 172 and 173, the back gate electrode 150 is connected to the front gate electrode 12 It is in contact with 1 and connected to the front gate electrode 121. This connection structure is a battery This means not only making the gate electrode 150 the same potential as the front gate electrode 121, but also This contributes to improving the electrical characteristics of transistor 11.

[0034] As shown in Figure 1C, the OS layer 130 is connected to the source electrode 140S and the drain electrode 140D Without going through, the area surrounded by the front gate electrode 121 and the back gate electrode 150 It has a region. With this device structure, the front gate electrode 121 and the back The electric field of the gate electrode 150 can electrically surround the OS layer 130. As in example 11, the OS layer where the channel is formed is the electric field of the gate electrode (121, 150) A transistor device structure that is electrically surrounded by is called surrounded This can be called a channel (s-channel) structure.

[0035] Since transistor 11 has an s-channel structure, the front gate electrode 121 Therefore, the electric field for inducing the channel can be effectively applied to the OS layer 130, The current drive capability of the inverter 11 is improved, and high on-current characteristics are obtained. Because this can be increased, it becomes possible to miniaturize transistor 11.

[0036] Furthermore, transistor 11 is surrounded by a front gate electrode 121 and a back gate electrode 150. Therefore, the mechanical strength of transistor 11 can be increased.

[0037] In Figure 1C, the direction perpendicular to the plane of the paper is the direction of current flow. Therefore, the front gate To more effectively apply the electric field of electrode 121 to the OS layer 130, openings 172 and 173 The channel length Wc1 is preferably longer than the length L2 of the OS layer 130. As a result, the portions present in the openings 172 and 173 of the back gate electrode 150, To efficiently apply the electric field to the entire surface of the OS layer 130 in the channel width direction. It is possible.

[0038] The following describes the films and other components that make up the transistor 11.

[0039] (substrate) There are no particular restrictions on the material of the circuit board 100. The circuit board 100 is used for the operation of the transistor 11. If it is a support substrate used during manufacturing, it can withstand at least the heat treatment during the transistor 11 formation process. It needs to have a certain degree of heat resistance. For example, glass substrate, ceramic substrate, quartz substrate A plate, sapphire substrate, etc., may be used as the substrate 100. Alternatively, silicon or silicon carbide may be used. Single-crystal semiconductor substrates made from materials such as crystalline materials, polycrystalline semiconductor substrates, silicon germanium, etc. It is also possible to apply compound semiconductor substrates, SOI substrates, etc., on these substrates. A backplane substrate on which devices such as transistors and capacitors are fabricated is called substrate 1. It is possible to set it to 00.

[0040] Furthermore, if the substrate 100 is a substrate that is not a support substrate when the transistor 11 is manufactured... In this case, the heat resistance of the substrate 100 does not need to be high, and rigidity is not particularly required. Therefore, in addition to the substrates mentioned above, flexible substrates such as resin substrates may also be used. In this case, When fabricating the lunger 11, a release layer (tungsten oxide) is applied to the support substrate during fabrication. A portion of the transistor 11 or This process involves fabricating everything. Then, the support substrate, including the release layer, is separated, and the substrate is insulated with a resin material. The substrate 100 can be fixed to the edge layer.

[0041] (Front gate electrode, back gate electrode) The front gate electrode 121 and the back gate electrode 150 have a single-layer structure and a stacked structure of two or more layers. It can be formed from a conductor. This conductor can be a metal, an alloy, or a metallic compound (for example) Examples include metal oxides, metal nitrides, silicides, and phosphorus-containing silicon. These conductors containing metals may also be conductors to which other elements or compounds have been added.

[0042] Metals used in conductive materials include aluminum, chromium, copper, tantalum, titanium, and molybdenum. Examples include den, tungsten, manganese, and zirconium.

[0043] Examples of metal oxides include indium oxide, indium-sulfide (ITO), and indium oxide (ITO). Examples include tungsten oxide and silicon oxide. It may also be added. Metal oxides can be used as conductors with light-transmitting properties.

[0044] For example, if the front gate electrode 121 and the back gate electrode 150 are made into a two-layer structure, A film in which an aluminum film is laminated on a tan film, a film in which a titanium film is laminated on a titanium nitride film, nitriding A film in which a tungsten film is laminated on a titanium film, a tantalum nitride film, or a tungsten nitride film This can be achieved by forming a film with a tungsten film laminated on top, or a film with a copper film laminated on top of a titanium film. Furthermore, if a three-layer structure is used, for example, the layers would be stacked in the order of titanium film, aluminum film, and titanium film. It should be formed with the prepared membrane.

[0045] Here, the front gate electrode 121 is formed of a single layer of conductor. For example, Freon The gate electrode 121 can be formed from a tungsten film of 80 nm to 200 nm. Furthermore, the back gate electrode 150 is formed of a single layer of conductor. For example, thickness 80n It can be formed from m-200nm In-Sn oxide (ITO).

[0046] (Source electrode, drain electrode) The source electrode 140S and drain electrode 140D are also simple, similar to the front gate electrode 121. It can be formed from a conductor with a layered structure or a laminated structure of two or more layers. This conductor can be a metal. and alloys, metal compounds (e.g., metal oxides, metal nitrides, silicides, etc.), including phosphorus. Silicon is one example. Other elements or compounds are added to these metal-containing conductors. A conductor is also acceptable.

[0047] Metals used in conductive materials include aluminum, chromium, copper, silver, tantalum, titanium, and chromium. Examples include ribdenum, tungsten, manganese, and zirconium.

[0048] When the source electrode 140S and drain electrode 140D have a two-layer structure, the second layer is made thicker, Formed from low-resistance metals such as aluminum and copper, the first layer is in direct contact with the OS layer 130. The conductor that functions as a barrier layer for the second conductor, or the properties of the OS layer 130 It is preferable to form it with a conductor that does not degrade. Also, the front gate electrode 121, the battery The same applies when the gate electrode 150 is formed from a three-layer conductive material, the first and third layers The eyes are preferably formed of a conductor that functions as a barrier layer against the second layer of conductors. .

[0049] When the source electrode 140S and drain electrode 140D have a two-layer structure, aluminum is placed on the titanium film. A film with a layered aluminum film, a film with a copper film layered on a tungsten film, and a film with an aluminum film on a tungsten film. A film made by laminating aluminum films, a film made by laminating copper films on a copper-magnesium-aluminum alloy film. Alternatively, a film in which a copper film is laminated on a titanium film can be used. Also, in the case of a three-layer structure, the first layer The third layer is formed by a film made of titanium, titanium nitride, molybdenum, or molybdenum nitride. Therefore, the second layer should be a low-resistance film made of aluminum and copper.

[0050] (Insulating layer) The insulating layers 101 and 102 can be formed as a single insulating film or as two or more insulating films. Yes, it can. Examples of such insulating films include aluminum oxide, magnesium oxide, and silicon oxide. Silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, germanium oxide M, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafny oxide Examples include films made of luminous material, tantalum oxide, Ga-Zn oxide, etc.

[0051] Hafnium silicate (HfSiO x ), nitrogen-containing hafnium silicate (HfSi x O y N z ), nitrogen-containing hafnium aluminate (HfAl x O y N z ), hafnium oxide, By using high-k materials such as yttrium oxide, the back gate and front gate leakage of the transistor 11 can be reduced. These insulating films can be formed by using sputtering method, CVD method, MBE method, ALD method or PLD method.

[0052] In addition, in this specification, the oxynitride refers to a compound having a higher oxygen content than nitrogen , and the nitride oxide refers to a compound having a higher nitrogen content than oxygen.

[0053] When the insulating layer 101 has a multilayer structure, the insulating film in contact with the OS layer 130 is preferably an insulator containing oxygen (such as oxide, oxynitride, etc.). Here, the insulating layer 101 has a two-layer structure of an insulating film 111 and an insulating film 112. The insulating film 111 is a silicon nitride film, and the insulating film 112 is a silicon oxynitride film.

[0054] When the insulating layer 102 has a multilayer structure, the insulating film in contact with the OS layer 130 is preferably an insulator containing oxygen (such as oxide, oxynitride, etc.). Further, the insulating layer 102 preferably has an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition desorbs a part of oxygen by heating. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition means that in thermal desorption spectrometry (TDS) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 atoms / cm or more, preferably 18 or 3.0×10 3 atoms / cm or more. The above-mentioned T 20 3 DS (Thermal Desorption Spectrometry) analysis. Note that the above T ​The surface temperature of the film during DS analysis is between 100°C and 700°C, or below 100°C. A temperature range of 500°C or less is preferred.

[0055] Here, the insulating layer 102 has a laminated structure of insulating films 113-115, and insulating film 113, 1 14 is a silicon oxidizride film, and the insulating film 115 is a silicon nitride film.

[0056] The thickness of the insulating film 114 is 30 nm to 500 nm, preferably 50 nm to 400 nm. This is sufficient. Also, as the insulating film 114, instead of the silicon oxidiznitride film, a silicon oxide film These may be formed.

[0057] The second insulating film layer 114 is formed as an oxide insulating film that supplies oxygen to the OS layer 130. The insulating film contains more oxygen than satisfies the stoichiometric composition. The insulating film 114 is It is preferable that there are few defects. Typically, g = The spin density calculated from the signal appearing around 2.001 is 1.5 × 10⁻⁶. 18 SPI ns / cm 3 Less than, and even 1 x 10 18 spins / cm 3 The following is preferable: A typical example of an electron spin with a g-value of 2.001 originates from silicon dangling bonds. It is.

[0058] The insulating film 113 serves as a pathway for oxygen released from the insulating film 114 to move to the OS layer 130. Therefore, it is preferable to form it with an insulating film that is permeable to oxygen and contains oxygen. Furthermore, the insulating film 113 acts as a barrier layer for the OS layer 130 during the formation of insulating films 114 and 115. It works even if you do that.

[0059] Furthermore, in the insulating film 113, all the oxygen that enters the insulating film 113 from the outside is transferred to the outside. When movement occurs, or when some of the oxygen that enters the insulating film 113 from the outside remains in the insulating film 113 In this case, or when oxygen enters the insulating film 113 from the outside, the insulating film 113 contains Oxygen moves to the outside of the insulating film 113, causing oxygen migration within the insulating film 113. In some cases, it may be the case.

[0060] Since the insulating film 113 is in contact with the OS layer 130, it has fewer defects than the insulating film 114. This is preferable. The insulating film 113 is calculated from the ESR signal near g=2.001. The spin density is 3 × 10 17 spins / cm 3 The following silicon oxide films or nitrided oxide films A silicon film is preferred. Also, g is near 1.93 (for example, 1.89 to 1.9). The spin density calculated from the ESR signal in 6) is 1 × 10⁻⁶ 17 spins / cm 3 below Furthermore, it is preferable that the level be below the detection limit.

[0061] The thickness of the insulating film 113 is 5 nm to 150 nm, preferably 5 nm to 50 nm. be.

[0062] The uppermost layer of the insulating layer 102 is formed of an insulating film 115 that has a hydrogen and oxygen blocking effect. It is preferable to do so. Furthermore, it is preferable to include oxygen, hydrogen, water, alkali metals, and alkaline earth It is preferable that the insulating film has a blocking effect, such as a metal-like material. To prevent the intrusion of impurities such as hydrogen into layer 130 and to allow oxygen to be released from the OS layer 130. This can be prevented. Here, a silicon nitride film is formed as the insulating film 115.

[0063] The thickness of the insulating film 115 is 50 nm to 300 nm, preferably 100 nm to 200 nm. This is how it should be done. As insulating film 115, silicon nitride, silicon nitride oxide, aluminum nitride Aluminum nitride, aluminum oxide, aluminum oxide, gallium oxide, Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, nitrogen oxide A film made of hafnium oxide, etc., can be formed.

[0064] (Oxide semiconductor (OS) layer) The OS layer 130 has a single-layer or multi-layer structure made of metal oxide. A semiconductor film (oxide semiconductor film) made of a metal oxide in which a nel-forming region is provided is provided with at least one It is sufficient to have a layer. As metal oxides constituting the OS layer 130, indium oxide, oxide Tin, zinc oxide, in-Zn oxide, sn-Zn oxide, al-Zn oxide, Zn-Mg Oxides, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn acid In-Al-Zn oxide (also written as IGZO), In-Sn-Zn oxide, S n-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf -Zn oxide, In-Zr-Zn oxide, In-Ti-Zn oxide, In-Sc-Zn acid In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In -Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu- Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In -Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In- Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide In-Sn-Hf-Zn oxide and In-Hf-Al-Zn oxide can be used. ru.

[0065] The oxide semiconductor that forms the channel formation region of the OS layer 130 is at least indium (In) Alternatively, those containing zinc (Zn) are preferred. Such oxide semiconductors include In-G α-Zn oxide and In-Sn-Zn oxide are typical examples. Furthermore, oxide semiconductors are used in electrical... It may also contain elements that act as stabilizers to reduce variations in its properties. Examples of such elements include Ga, Sn, Hf, Al, and Zr.

[0066] Here, In-Ga-Zn oxide refers to an oxide having In, Ga, and Zn as its main components. This means that the ratio of In, Ga, and Zn is not specified. Also, gold other than In, Ga, and Zn is not specified. It may contain group elements.

[0067] When an oxide semiconductor film contains a large amount of hydrogen, the hydrogen combines with the oxide semiconductor. Some of these become donors, generating electrons, which act as carriers. This causes OS transitions. The threshold voltage of the station shifts in the negative direction.

[0068] The OS layer 130 (at least the region where channels are formed) produces hydrogen along with oxygen deficiency. It is preferable that it be reduced as much as possible. Specifically, in the OS layer 130, secondary ionic Secondary Ion Mass Spectrometer (SIMS) The hydrogen concentration obtained by (y) is 2 × 10 20 atoms / cm 3 The following is preferably 5× 1019 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 below , comfortable 5×10 18 atoms / cm 3 More preferably 1 × 10 18 a toms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 Below, further better Mashiku is 1 x 10 16 atoms / cm 3 The following applies:

[0069] In the OS layer 130, if silicon or carbon, which are among the Group 14 elements, is included, the OS layer At layer 130, oxygen deficiency increases, leading to reduced resistance. Therefore, at OS layer 130... The concentrations of silicon and carbon (concentrations obtained by SIMS) are 2 × 10 18 atom / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0070] In the OS layer 130, alkali metals or alkaline earth metals obtained by SIMS The concentration is 1 × 10 18 atoms / cm 3 The following is preferably 2 × 10 16 ate / c m 3 The following applies: Alkali metals and alkaline earth metals, when combined with oxide semiconductors, This can generate a rear current, which can increase the transistor's off-current. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the OS layer 130. It's nice.

[0071] Furthermore, if nitrogen is present in the oxide semiconductor, electrons, which act as carriers, are generated, increasing the carrier density. This increases, making it easier to lower resistance. Therefore, the nitrogen concentration in the OS layer 130 is reduced as much as possible. Preferably, for example, the nitrogen concentration obtained by SIMS is 5 × 10 18 at oms / cm 3 The following is preferable:

[0072] Furthermore, the channel formation region of the OS layer 130 is CAAC-OS (C Axis Alig Composed of (ned Crystalline Oxide Semiconductor) It is preferable that CAAC-OS has a polycrystalline structure, a microcrystalline structure, or This is because it is an oxide semiconductor with the lowest defect level density compared to amorphous structures. The crystal structure of the metal oxide constituting the S layer 130 will be described in Embodiment 4. .

[0073] The metal oxide constituting the OS layer 130 has a microcrystalline structure, a polycrystalline structure, CAAC-OS, and is single-layered. The OS layer 130 may have two or more crystalline structures. Two or more of the following regions: the region of polycrystalline structure, the region of CAAC-OS, and the region of single crystal structure. The above region may be present. Also, the OS layer 130 may have, for example, a microcrystalline structure region, multi-layered The product of two or more regions from among the crystal structure region, the CAAC-OS region, and the single crystal structure region. It may have a layered structure.

[0074] The OS layer 130 is a single layer of metal oxide or a film structure consisting of two or more layers of metal oxide films stacked together. This can be done. When the OS layer 130 has a stacked structure, each layer of the OS layer 130 is composed of The metal oxide film preferably contains at least one identical metal. For example, In-M- When formed with a multilayer film of Zn oxide (where M is Ga, Y, Zr, La, Ce, or Nd) The atomic ratios of In, M, and Zn in each layer can be set appropriately. Alternatively, the multilayer film can be... With In as the common metal element, In-M-Zn oxide film, In-M oxide film, In-Zn acid The ionized film may be combined as appropriate.

[0075] For example, if the metal oxide film 131 is an In-Ga-Zn oxide film, then the metal oxide film 132 is , an In-Ga-Zn oxide film containing more Ga than metal oxide film 131, or In-G A suitable oxide film would be α.

[0076] Here, the OS layer 130 has a two-layer structure consisting of a metal oxide film 131 and a metal oxide film 132. The metal oxide film 131 on the front gate electrode 121 side has a channel formation region. It is an oxide semiconductor film. The metal oxide film 132 is located at the source electrode 140S and the drain electrode In the process of forming electrode 140D, the process of depositing conductive films (141, 142) and conductive films (14 1, 142) Burr to suppress damage to the metal oxide film 131 during the etching process It is preferable to have it function as a layer, and to form a film that is denser than the metal oxide film 131. This is preferable.

[0077] The presence of the metal oxide film 132 creates a boundary between the insulating layer 102 (gate insulating layer) and the OS layer 130. The channel-forming region (metal oxide film 131) can be separated from the surface. Even if trap levels are formed on the surface, the charge flowing through the channel is trapped in the trap levels. This makes it more difficult. Therefore, the on-current of transistor 11 can be increased, and the field effect This can increase fruit mobility.

[0078] Furthermore, as described above, in transistor 11, a channel is formed in the metal oxide film 131. Therefore, the source electrode 140S and the drain electrode 140D are on the side of the metal oxide film 131. It is sufficient that it is at least in contact with the metal oxide film 132, so the source region and drain The region does not need to exist. Therefore, the metal oxide film 132 is not an oxide semiconductor. The film may also have high resistance. The metal oxide film 132 is connected to the source electrode 140S, and the drain The contact resistance with electrode 140D is very high, even if it is composed of an insulator with infinite resistance. Therefore, the range of films that can be used as the metal oxide film 132 increases.

[0079] Therefore, it is possible to form a thick metal oxide film 132. The film 132 is made to function as a protective film for the metal oxide film (oxide semiconductor film) 131. Therefore, the diffusion of copper into the OS layer 130 (metal oxide film 131) is possible. This can be prevented by 132, so-called channel etch type bottom gate transient In transistor 11, which is a starter, the source electrode 140S and drain electrode 140D are extended This makes it easier to use copper materials that are prone to scattering.

[0080] In the OS layer 130, the thickness of the metal oxide film 131 should be 100 nm or more, for example For example, a wavelength of 100 nm to 1000 nm is acceptable, with 200 nm to 1000 nm being preferred. Furthermore, the thickness of the metal oxide film 132 should be 50 nm or more, for example, 50 nm or A value of 500 nm is acceptable, but 100 nm to 300 nm is preferred.

[0081] For example, metal oxide film 131 and metal oxide film 132 can be subjected to In-G sputtering. When forming with an α-Zn oxide film, the sputtering target of the metal oxide film 131 is used. And, In-Ga- is formed when the atomic ratio of In:Ga:Zn is 1:1:1 or 1:3:2. A Zn oxide target can be used, and the sputtering target of the metal oxide film 132 As a set, the In:Ga:Zn (atomic ratio) is 1:3:2, or 1:3:4, or A 1:3:6 In-Ga-Zn oxide target can be used. This allows for the use of gold As the group oxide film 132, a Ga-rich In-Ga-Zn oxide film is used, which is richer in Ga than the metal oxide film 131. It can form a physical film.

[0082] For example, as a metal oxide film 131, an In-Ga-Zn oxide film is formed by sputtering. The metal oxide film 132 is formed using an In-Ga oxide film by sputtering. In addition, as a sputtering target for the metal oxide film 131, In:Ga:Zn (number of atoms) An In-Ga-Zn oxide target with a ratio of 1:1:1 or 1:3:2 is used. It is possible to use In:Ga(atomic) as a sputtering target for the metal oxide film 132. An In-Ga oxide target with a numerical ratio of 7:93 can be used. This allows for the use of such a target. The metal oxide film 132 is formed as an In-Ga oxide film that is richer in Ga than in In. This can be achieved. Such a Ga-rich In-Ga oxide film is suitable as a Cu diffusion prevention film. It is a membrane.

[0083] <Configuration Example 2: FET-2> The transistor in Configuration Example 2 is a modified version of the transistor in Configuration Example 1, and is a back gate. The front gate can be independently input with either a voltage or a signal. Figure 2A shows configuration example 2. This is the circuit symbol for the transistor. The transistor has a front gate and a back gate. It has two gates, and the back gate is not connected to the front gate. Here, the transistor represented by the circuit symbol in Figure 2A is referred to as FET-2.

[0084] Figures 2B-2D show an example of the device structure of FET-2. Figure 2B shows the transistor This is a top view. Figure 2C is a cross-sectional view taken along the cutting line A1-A2 in Figure 2B, and Figure 2D is a cross-sectional view taken along the cutting line A1-A2 in Figure 2B. This is a cross-sectional view taken along the break B1-B2. Figure 2C also shows the transistor in the channel width direction. This is a cross-sectional view, and Figure 2D is also a cross-sectional view of the transistor in the channel length direction.

[0085] The transistor 12 is formed on the substrate 100, and consists of an insulating layer 101, an insulating layer 102, and a flow Socket electrode 121, OS layer 130, source electrode 140S, drain electrode 140D, It has a gate electrode 151, an electrode 152, and an electrode 153. In the channel width direction In the insulating layers 101 and 102, openings 172 and 173 are formed. In 173, electrodes 152 and 153 are in contact with the front gate electrode 121. In the transistor 12, the back gate electrode 151 is connected to the front gate electrode 121. not present.

[0086] Transistor 12 has three electrodes (151) that connect the back gate electrode 150 of transistor 11. It has a device structure divided into -153). Transistor 12 also has a device structure divided into transistor 11 and Similarly, it is an s-channel transistor, and similarly its frequency characteristics and on-current characteristics The quality has improved.

[0087] In transistor 12, as shown in Figure 2C, the OS layer 130 is located at the source electrode 140S And without going through the drain electrode 140D, the front gate electrode 121 and the back gate electrode It has a region surrounded by electrode 151, electrode 152, and electrode 153. By connecting electrode 121 and electrodes 152 and 153 as shown in the figure, These electrodes can surround the bottom surface, two opposing sides, and top surface of the OS layer 130. Furthermore, the electric field of the front gate electrode 121 makes it possible to electrically surround the OS layer 130. Electrodes 152 and 153 form part of the front gate, as shown in Figure 2C. Since it faces the side of the OS layer 130, it can be called a side gate electrode.

[0088] Furthermore, the back gate electrode 150 of transistor 11 has a pair of side gate electrodes. This can be called a back gate electrode (Figure 1C).

[0089] As shown in Figure 2C, electrodes 152 and 153 are connected to the OS layer 130 via the insulating layer 102. It has a region facing the upper surface. That is, in the channel width direction, electrodes 152, 153 The widths SGov2 and SGov3 of the region facing the top surface of the OS layer 130 have values ​​greater than 0. Tsu.

[0090] The back gate electrode 151 receives different potentials or signals from the front gate electrode 121. Therefore, depending on the input signal and input potential of the back gate electrode 151, transistor 1 The threshold voltage of 2 (hereinafter sometimes referred to as Vth or threshold) is set in the positive voltage direction. Alternatively, it can be shifted in the negative voltage direction. This controls the Vth of transistor 12. As a result, during operation, the transistor 12 is configured to either enhance or deplete. It is possible to change it as needed.

[0091] <Configuration Example 3: FET-3> The transistor in Configuration Example 3 is a modified version of the transistor in Configuration Example 2, and is a back gate. This is a transistor that does not have [a certain component]. Figure 3A shows the circuit diagram of the transistor according to Configuration Example 3. This is the number. Here, the transistor represented by the circuit symbol in Figure 3A is called FET-3.

[0092] Figures 3B-3D show an example of the device structure of FET-3. Figure 3B shows the transistor This is a top view. Figure 3C is a cross-sectional view taken along the cutting line A1-A2 in Figure 3B, and Figure 3D is a cross-sectional view taken along the cutting line A1-A2 in Figure 3B. This is a cross-sectional view taken along the break B1-B2. Figure 3C also shows the transistor in the channel width direction. This is a cross-sectional view, and Figure 3D is also a cross-sectional view of the transistor in the channel length direction.

[0093] The transistor 13 is formed on the substrate 100, and consists of an insulating layer 101, an insulating layer 102, and a flow End electrode 121, OS layer 130, source electrode 140S, drain electrode 140D, It has pole 152 and electrode 153. In the channel width direction, insulating layers 101, 102 The openings 172 and 173 are formed. In the openings 172 and 173, the electrode 15 2. Electrode 153 is in contact with the front gate electrode 121.

[0094] Transistor 13 is in phase with transistor 12, which does not have a back gate electrode 151. In transistor 13, as shown in Figure 3C, the OS layer 130 is the source electrode. Without going through 140S and the drain electrode 140D, the front gate electrode 121 and the electric The region surrounded by the conductive film composed of pole 152 and electrode 153 (bottom surface, opposing 2 It has two sides and a top surface. Therefore, transistor 13 also has transistors 11 and 1 Similar to point 2, due to its s-channel structure, the frequency characteristics and on-current characteristics are It will improve.

[0095] As shown in Figure 3C, electrodes 152 and 153 are connected to the OS layer via the insulating layer 102. 130 has a region facing the upper surface. The circuit symbol in Figure 3A shows that FET-3 is of this size. This indicates that it has gate electrodes (151, 152).

[0096] <Variation> The following describes some variations of the transistor.

[0097] In transistor 11, either the opening 172 or the opening 173 is formed, back The gate electrode 150 may be connected to the front gate electrode 121. In the converters 12 and 13, the device that forms either electrode 152 or electrode 153 It can be a structural type.

[0098] Transistors 11-13 have either a side gate electrode or a back gate electrode, or It is an S-Channel transistor having both, but the side gate electrode and The device structure can be such that neither a back gate electrode nor a gate electrode is provided. The transistor does not have an S-Channel structure, but like transistor 11, it has an OS layer. The device structure is such that the source electrode 140S and the drain electrode 140D are in contact on the side of 130. Therefore, while shortening the channel length L1, we also shorten L2 as much as possible (bringing it closer to L1). This allows us to improve frequency characteristics while ensuring on-current characteristics. can.

[0099] <<Unipolar Transistor Circuit>> The transistor (FET-1-FET-3) has a channel formation region made of oxide semiconductor. Therefore, it is an n-channel transistor. Below is an example of a circuit configuration using unipolar transistors. As shown, FET-1-3 is used as the transistor in the circuit.

[0100] <Inverter Circuit> From unipolar transistors, for example, basic logic circuits (buffer circuits, inverter circuits, etc.) It can be used to construct locked inverter circuits, NAND gates, NOR gates, etc. This section will explain inverter circuits. Figure 8 shows the circuit symbol for an inverter circuit.

[0101] The inverter circuits shown in Figures 9A, 10A, and 10B (INV-1, INV-2, INV- 3) Each has a transistor M1 and a transistor M2 connected in series. Transistor M1 has the device structure of FET-1, and transistor M2 has the device structure of FET-2. It has the following device structure. Thus, the on-current characteristics and frequency characteristics are improved. By using transistors (FET-1, FET-2), power consumption is reduced and the operating frequency is lowered. This makes it possible to provide inverter circuits with a high number of units.

[0102] In the following explanation, the inverter circuit (INV-1) will be abbreviated as INV-1. This can sometimes happen. The same applies to other circuits, components, voltages, signals, etc.

[0103] (INV-1) Figure 9A is the circuit diagram of INV-1, and Figure 9B is its truth table. Note that Figure 9B is a diagram of INV-1. Instead of a potential value, it is expressed using a potential level, where "H" represents a high potential. It has a magnitude that turns on transistor M1. Also, "L" is a low-level potential. This represents a potential magnitude that turns transistor M1 off.

[0104] INV-1 has an input terminal (IN) and an output terminal (OUT), and the power supply voltage is VDD. VSS is supplied. VDD is the high supply voltage and is input to the drain of transistor M2. VSS is a low supply voltage and is input to the source of transistor M1.

[0105] Transistor M1 has its back gate connected to the front gate, and the front gate is connected to the end The drain is connected to the input (IN) terminal and the drain is connected to the output (OUT) terminal. Transistor M 2. The front gate and source are connected, and the source is connected to the terminal (OUT), and the back Signal φ1 is input to the gate.

[0106] Signal φ1 may be a signal with a fluctuating potential level, or it may be a signal with a constant potential level. For example, as shown in Figure 9B, the signal φ1 has a potential that corresponds to the signal input from terminal (IN). The signal can be made to have a fluctuating level. When the terminal (IN) becomes high level, The potential of signal φ1 becomes VH1, and when terminal (IN) goes low, the potential of signal φ1 becomes Make it VL1.

[0107] In this case, for example, when transistor M1 is ON, the current flowing through transistor M2 By reducing the current, when transistor M1 is in the off state, the current flowing through transistor M2 is increased. A signal φ1 that causes [a certain effect] may be supplied to the transistor M2. VH1 is set to a potential such that a voltage higher than the source (a positive bias voltage) is applied to the back gate of the transistor M2. This allows the threshold voltage of the transistor M2 to be lowered compared to the case where no voltage is applied to the back gate. On the other hand, VL1 is set to a potential such that a voltage lower than the source (a negative bias voltage) is applied to the back gate of the transistor M2. This allows the threshold voltage of the transistor M2 to be increased compared to the case where no voltage is applied to the back gate. When the transistor M1 is in the on state, the discharge of the node NA occurs slowly, and when the transistor M1 is in the off state, the charging of the node NA occurs rapidly. Therefore, it is possible to obtain an INV-1 that operates at high speed with low power consumption.

[0108]

[0109] (INV-2) The inverter circuit (INV-2) in FIG. 10A is a modified example of INV-1 and has a circuit configuration in which the back gate of the transistor M2 is connected to the drain.

[0110] In INV-2, since VDD is applied to the back gate of the transistor M2, a positive bias voltage is applied to the back gate of the transistor M2.

[0111] (INV-3) The inverter circuit (INV-3) in FIG. 10B is a modified example of INV-2 and corresponds to a circuit in which the connection between the front gate and the back gate of the transistor M2 is swapped. The transistor M2 has its front gate connected to the drain and its back gate connected to the source. ​​​​​​​​​​​​

[0112] In this embodiment, the inverter circuit is configured with FET-1 and FET-2, but other embodiments may also exist. It is possible to use the transistors in the example configuration. For example, INV-1-INV-3 Alternatively, transistor M1 may be constructed using FET-3. It can be composed of transistors that do not have a back gate electrode and a side gate electrode. It is possible.

[0113] <Clocked Inverter Circuit> This explains a clocked inverter (CINV) circuit composed of unipolar transistors. do.

[0114] Figure 11A shows the circuit symbol for a clocked inverter circuit. Figures 11B and 11C show the clocked inverter circuit. An example of a bucked inverter circuit configuration is shown.

[0115] The clock inverter circuits (CINV-1, CINV-2) shown in Figures 11B and 11C are: Each has three transistors M11, M12, and M13 connected in series. Transistors M11 and M12 have the device structure of FET-1, and transistor M13 is F It has the ET-2 device structure. Thus, the on-current characteristics and frequency characteristics are improved. By using the transistors (FET-1, FET-2), power consumption is reduced. This makes it possible to provide a clocked inverter circuit with a high operating frequency.

[0116] (CINV-1) As shown in Figure 11B, CINV-1 is connected to transistor M1 and V of INV-1 (Figure 9A). This corresponds to a circuit in which transistor M11 is connected between the SS input terminals. Transistor M11 A clock signal (CLK1) is input to the front gate, and the back gate is connected to the front gate. Transistor M12 has its front gate connected to a terminal (IN) and its back gate, and its drain connected to the terminal (OUT). Transistor M13 has its front gate connected to the source, the source connected to the terminal (OUT), and a clock signal (CLK2) input to the back gate.

[0117] When CLK1 is at a high level, CINV-1 functions as an inverter circuit, and when CLK1 is at a low level, the terminal (OUT) is in a high-impedance state. CLK2 is used as a signal for controlling the Vth of transistor M13, and transistor M13 can be switched between an enhancement mode and a depletion mode by CLK2.

[0118] For example, the same signal as CLK1 can be input as CLK2. In this case, when CLK1 is at a high level, M11 is turned on, and the Vth of M13 is shifted to the negative voltage side. When CLK1 is at a low level, M11 is turned off, and the Vth of M13 is shifted to the positive voltage side.

[0119] (CINV-2) As shown in FIG. 11C, CINV-2 corresponds to a circuit in which the connections of the front gate and the back gate of M13 in CINV-1 are interchanged, and operates in the same manner as CINV-1.

[0120] <Latch Circuit> As an example of a sequential circuit, a configuration example of a latch circuit is shown. FIG. 12A is a block diagram showing an example of the configuration of the latch circuit, and FIG. 12B is the circuit diagram thereof.

[0121] The latch circuit (LAT) 200 is connected to the clocked inverter circuits 201, 202, and It has a inverter circuit 203. The inverter circuit 203 and the clocked inverter circuit 202 This forms a loop circuit consisting of two inverters. The input terminals of this loop circuit are It is connected to input terminal (D) via clocked inverter circuit 201.

[0122] Here, INV-1-INV-3 is used in the inverter circuit 203, and a clocked inverter... By using CINV-1 and CINV-2 in transistor circuits 201 and 202, a unipolar transistor can be used. A fast-rising latch circuit can be obtained using a sta-based design.

[0123] Clock signals CLK1 and CLK3 are signals that are inverted in phase from each other. CLK2 controls the Vth of transistor M13 in the clocked inverter circuit 201. This is a signal, and CLK4 is the V of transistor M13 in the clocked inverter circuit 202. This is a signal that controls th.

[0124] <Shift register> As an example of a sequential circuit, a shift register configuration example is shown. As shown in Figure 13, multiple LAs By connecting T in series, a shift register 210 can be configured. In register 210, the clock signal CLK and the clock signal CLKB are in opposite phases to each other. These are signals that are in a reciprocal relationship. The output terminal of the LAT is connected to the input terminal of the next stage LAT. The input terminal D of the first stage LAT receives the start pulse signal SP. The rising edge of the lock signal CLK or CLKB triggers the input to the first stage LAT. The pulse signals are sequentially transferred to the next stage LAT, and the signal SROUT1- is output from the output terminal. It will be extracted as SROUT4.

[0125] For example, the shift register 210 is a gate driver for an active-matrix display device. It can be used in circuits and source driver circuits. In Embodiment 3, Act This section describes a video-matrix type display device.

[0126] (Embodiment 2) This embodiment describes the method for manufacturing a transistor according to Embodiment 1. Now, let's explain how to manufacture transistor 11 (FET-1) as an example.

[0127] Figures 4A-7B are cross-sectional views showing an example of a method for fabricating transistor 11. In the plane, the left side shows a cross-sectional view in the channel length direction (B1-B2), and the right side shows a cross-sectional view in the channel width direction. A cross-sectional view in the direction (A1-A2) is shown.

[0128] The films that make up the transistor 11 (insulating film, semiconductor film, oxide semiconductor film, metal oxide film, conductive film) Electrode films, etc., are produced by sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. It can be formed using the Plasma Deposition (PLD) method, or by coating or printing methods. This is possible. Film deposition methods include sputtering and plasma chemical vapor deposition (PE). CVD is the most common method, but thermal CVD can also be used. An example of thermal CVD is MOCVD. (Organometallic deposition) or ALD (atomic layer deposition) methods may also be used.

[0129] Thermal CVD is a method in which the chamber is subjected to atmospheric pressure or reduced pressure, and the raw material gas and oxidizer are simultaneously processed. The film is formed by sending the material into a chamber, reacting it near or on the substrate, and depositing it onto the substrate. Thus, since thermal CVD is a film deposition method that does not generate plasma, It has the advantage of not generating defects through damage.

[0130] Furthermore, the ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber, and sequentially supplying the raw material gases for the reaction. Next, the gas is introduced into the chamber, and the film deposition process is carried out by repeating this gas introduction sequence. For example, Switching between each switching valve (also called a high-speed valve) allows for the use of two or more raw materials. The gases are supplied to the chamber in sequence, and the first raw material gas and the other gases are supplied in order to prevent the mixing of multiple raw material gases. Simultaneously or afterward, an inert gas (such as argon or nitrogen) is introduced to the second raw material. Introducing the gas. Note that if an inert gas is introduced simultaneously, the inert gas will be used as a carrier gas. Furthermore, an inert gas may be introduced simultaneously when introducing the second raw material gas. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the second A raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate to form a first single atomic layer. The first single layer forms a film and reacts with a second source gas introduced later, forming a second single layer on top of the first single layer. A thin film is formed by stacking layers.

[0131] By controlling the gas introduction sequence and repeating this process multiple times until the desired thickness is achieved, the step-level coverage can be improved. A thin film with excellent properties can be formed. The thickness of the thin film depends on the number of times the gas introduction sequence is repeated. Because it can be adjusted, precise film thickness control is possible, and miniature transistors can be created. This is suitable for manufacturing. Below, with reference to the drawing, an example of how to manufacture transistor 11 is shown. explain.

[0132] Here, a glass substrate is used as the substrate 100. First, as shown in Figure 4A, the substrate 10 A conductive film 120 constituting the front gate electrode 121 is formed on the 0. Here, conductive A tungsten film with a thickness of 100 nm is formed as film 120 by sputtering.

[0133] Furthermore, tungsten films can be deposited using a film deposition apparatus that utilizes ALD. In this process, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film. Subsequently, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. SiH4 gas may be used instead of 2H6 gas.

[0134] A photolithography process using a first photoresist mask is performed on the conductive film 120. A resist mask RM1 (not shown) is formed. Using the resist mask RM1, tungsten The film is etched to form the front gate electrode 121 (Figure 4B). After this, Remove the GIST mask RM1.

[0135] In the etching process of the transistor 11 manufacturing process, wet etching and dry etching are performed. Etching, or both, is performed.

[0136] The front gate electrode 121 is formed by electrolytic plating, printing, inkjet, or other methods. It is also possible.

[0137] Next, as shown in Figure 4C, an insulating layer 101 is formed covering the front gate electrode 121. The insulating layer 101 can be formed by sputtering, CVD, vapor deposition, etc. Here, a silicon nitride film with a thickness of 400 nm is formed as insulating film 111 by the PECVD method. This completes the process, and a silicon oxidizride film with a thickness of 50 nm is formed as the insulating film 112.

[0138] Alternatively, the film constituting the insulating layer 101 may be formed by thermal CVD. For example, hafniac oxide When forming a film, a liquid containing a solvent and a hafnium precursor compound (hafnium alcohol) is used. A hydroxide solution, typically tetrakisdimethylamide hafnium (TDMAH), is vaporized. Two types of gases are used: a raw material gas and ozone (O3) as an oxidizing agent. The chemical formula for dimethylamide hafnium is Hf[N(CH3)2]4. Examples of liquid materials include tetrakis(ethylmethylamide)hafnium.

[0139] For example, when forming an aluminum oxide film, the solvent and an aluminum precursor compound are included. The process uses two types of gases: a raw material gas obtained by vaporizing a liquid (such as TMA) and H2O as an oxidizing agent. It is present. The chemical formula for trimethylaluminum is Al(CH3)3. Also, other materials... The liquid components include tris(dimethylamide)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) There is.

[0140] For example, when forming a silicon oxide film, hexachlorodisilane is adsorbed onto the film-forming surface. This removes chlorine contained in the adsorbed material and provides radicals of oxidizing gases (O2, nitrous oxide). It is supplied and reacted with the adsorbed material.

[0141] Next, as shown in Figure 5A, the metal oxide film 13 constituting the OS layer 130 is placed on the insulating layer 101. 1. Form a 132-layer film.

[0142] Metal oxide films 131 and 132 can be formed using a film deposition apparatus that utilizes ALD. For example, when forming an In-Ga-Zn oxide film, In(CH3)3 gas and O3 gas are used. InO2 layers are formed by sequentially introducing gas, and then Ga(CH3)3 gas and O3 gas are introduced. A GaO layer is formed by simultaneously introducing Zn(CH3)2 and O3 gas, and then Zn(CH3)2 and O3 gas are introduced simultaneously. It is introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. By mixing these gases, InGaO2 layers, InZnO2 layers, GaInO layers, ZnInO layers, Ga A mixed compound layer, such as a ZnO layer, may be formed. Alternatively, an inert gas such as Ar may be used instead of O3 gas. While it is possible to use H2O gas bubbled with gas, it is better to use O3 gas which does not contain H. It is preferable. Alternatively, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Alternatively, Zn(CH3)2 gas may be used.

[0143] When forming metal oxide films 131 and 132 by sputtering, plasma is generated. For this purpose, an RF power supply, AC power supply, DC power supply, etc., can be used as appropriate. Cut.

[0144] Sputtering gases include noble gases (typically argon), oxygen, and mixtures of noble gases and oxygen. Use as appropriate. In the case of a mixture of noble gas and oxygen, the gas ratio of oxygen to noble gas It is preferable to increase the target of the metal oxide films 131 and 132 to be formed. You can select the appropriate one according to the composition.

[0145] To obtain an oxide semiconductor film that is of high purity intrinsic or substantially high purity intrinsic, a chamber In addition to evacuating the inside to a high vacuum, it is also necessary to purify the sputtering gas. The oxygen gas or argon gas used has a dew point of -40°C or lower, preferably -80°C or lower. A gas that has been purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using this method, the absorption of moisture and other substances into the metal oxide films 131 and 132 is prevented as much as possible. It is possible.

[0146] Here, we use an In-Ga-Zn oxide target (In:Ga:Zn=3:1:2). By sputtering, a metal oxide film 131 with a thickness of 300 nm was produced using the In-Ga-Z method. An n oxide film is formed. The metal oxide film 131 is formed as an oxide semiconductor film. By sputtering using an In-Ga oxide target (In:Ga=7:93) Then, an In-Ga oxide film with a thickness of 50 nm is formed as the metal oxide film 132. The material film 132 is formed as an oxide semiconductor film or as an insulating film.

[0147] Next, a photolithograph using a second photoresist mask is applied to the metal oxide film 132. After forming a resist mask RM2 (not shown) by the following process, the resist mask RM2 Using this method, the stacked film of metal oxide film 131 and metal oxide film 132 is made into an element by wet etching. Separation is performed to form the OS layer 130. After this, the resist mask RM2 is removed (Figure 5B). ).

[0148] For example, after the formation of the OS layer 130, the temperature should be 150°C or higher but below the substrate strain point, preferably 200°C or higher. Heat treatment may be performed at a temperature of 450°C or lower, more preferably between 300°C and 450°C. The heat treatment is one of the processes for increasing the purity of oxide semiconductors, and the hydrogen contained in the OS layer 130 This can reduce water and other substances.

[0149] A laminated film consisting of conductive films 141 and 142 is formed by covering the OS layer 130 and the insulating layer 101. (Figure 5C). Here, a tungsten film with a thickness of 50 nm is made by sputtering. 141), and a copper film (142) with a thickness of 300 nm are formed.

[0150] Alternatively, the conductive film 141 may be formed by the ALD method. In this case, the OS layer 130 is plasma The conductive film 141 can be formed without causing damage.

[0151] Furthermore, the front gate electrode 121 (including the electrode formed in the same layer) and the source electrode Connect electrode 140S and drain electrode 140D (including electrodes formed in the same layer). In this case, before forming the conductive films 141 and 142, an opening for this connection is formed in the insulating layer 101. In this case, the photolithography process using the third photoresist mask is performed to remove the resist. A resist mask RM3 is formed on the insulating layer 101 and the OS layer 130, and the resist mask RM3 is used The etching process creates an opening in the insulating layer 101. The resist mask RM3 is then removed. After that, conductive films 141 and 142 are formed.

[0152] Next, a photolithography process using a fourth photoresist mask is performed on the conductive film 142. This forms a resist mask RM4 (not shown). Using the resist mask RM4, the product The layer films (141, 142) are etched, and the source electrode 140S and drain electrode 140D are used. It forms (Figure 6A).

[0153] For example, etching of the copper film (142) is performed by the wet etching method, and the tungsten film When etching (141) is performed using a dry etching method with SF6, the surface of the copper film A fluoride is formed. The copper from the copper film diffuses into the OS layer 130 due to the fluoride. This is suppressed. Also, the metal oxide film 132 of the OS layer 130 is relative to the metal oxide film 131. It functions as an etching protective film, and also diffuses from conductive films 141 and 142 to metals. It functions as a barrier layer. Therefore, it prevents degradation of the electrical characteristics of transistor 11 and reduces reliability. It can hold down the lower part.

[0154] After removing the resist mask RM4, the insulating layer 101, OS layer 130, and source electrode 140S are installed. Then, an insulating layer 102 is formed covering the drain electrode 140D (Figure 6B).

[0155] Here, insulating film 113 and insulating film 114 are deposited in succession. Continuous deposition refers to the first layer of film. This is a film deposition method in which, after forming the first layer, the second and subsequent layers of film are formed without exposing the processed substrate to the atmosphere. By performing continuous film deposition, the concentration of impurities originating from atmospheric components at the interface of the multilayer film can be reduced. ru.

[0156] Insulating film 113 and insulating film 114 are a silicon oxide nitride film with a thickness of 50 nm and a silicon nitride film with a thickness of 400 nm. A silicon oxidizride film of thickness m is formed. In a PECVD apparatus, by changing the film deposition conditions... This forms a two-layer silicon oxide nitride film. The raw material gas for the silicon oxide nitride film is silicon It is preferable to use a depositing gas containing silicon and an oxidizing gas. Typical examples of gases include silanes, disilanes, trisilanes, and silane fluorides. Oxidizing properties Examples of gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0157] When using a PECVD apparatus, the insulating film 113 can be deposited under the following conditions: The gases are silane and nitrous oxide, with a flow rate of 30 sccm for silane and nitrous oxide. The nitrogen dioxide concentration is 4000 sccm. The pressure in the processing chamber is 200 Pa, and the substrate temperature is 22 The temperature is 0°C. In the PECVD apparatus, a high-frequency power supply of 27.12 MHz is used, and 150 A high-frequency power of W is supplied to the parallel plate electrodes. Under these conditions, oxygen permeates the oxidative nitride iontochemistry. A reconstituted film can be formed.

[0158] Furthermore, the insulating film 114 is formed in the same processing chamber without opening it to the atmosphere. This can be carried out under the following conditions: The source gas is the same as that used in insulating film 113. The flow rate is . The run pressure is 200 sccm, and the nitrous oxide pressure is 4000 sccm. The pressure in the treatment chamber is The pressure is 200 Pa, and the substrate temperature is 220°C. In the PECVD apparatus, 27.12 M A high-frequency power supply of Hz is used to supply 1500W of high-frequency power to the parallel plate electrodes.

[0159] The PECVD apparatus shown as an example here has an electrode area of ​​6000 cm². 2 This is a parallel plate type PEC. This is a VD (Vacuum Deposition) device. The power supplied during the deposition of the insulating film 114 is measured as power per unit area (power density). Converted to degrees, this is 0.25 W / cm². 2 That is the case.

[0160] The deposition of insulating film 113 using a PECVD apparatus involves setting the substrate temperature to between 280°C and 400°C, and applying pressure. The force is 20 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 250 Pa or less. It is preferable to carry out the procedure under the condition that high-frequency power is supplied to electrodes installed in the processing chamber. By appropriately selecting the listed raw material gases, a silicon oxide film can also be formed under these conditions. It is possible.

[0161] By forming the insulating film 113 under these conditions, an oxygen-permeable silicon oxidnitride film is formed. Alternatively, a silicon oxide film can be formed. Furthermore, the substrate temperature can be set to 280°C or higher and 400°C. The following strengthens the bond between silicon and oxygen. As a result, oxygen permeates, and the structure becomes denser. A dense and hard silicon oxidnitride film or silicon oxide film can be formed. Typically, the etching rate when using 0.5 wt% hydrofluoric acid at 25°C is 1 A silicon oxidiznitride film or silicon oxide film with a flow rate of 0 nm / min or less, preferably 8 nm / min or less. It is possible to form this.

[0162] Furthermore, since the insulating film 113 is formed while heating, the OS layer 130 contains hydrogen, water, etc. In this case, hydrogen, water, etc. contained in the OS layer 130 can be removed during the process. The hydrogen contained in the OS layer 130 combines with oxygen radicals generated in the plasma to form water. Because the substrate is heated, water generated by the bonding of oxygen and hydrogen is released into the OS layer 13. It desorbs from 0. That is, by forming the insulating film 113 by the PECVD method, the OS layer 130 The amount of water and hydrogen contained can be reduced.

[0163] Furthermore, since the OS layer 130 is heated during the deposition of the insulating film 113, the OS layer 130 is exposed. The heating time in this state is short, and the desorption of oxygen from the OS layer 130 due to heat treatment is suppressed. It is controlled. By setting the pressure in the processing chamber to between 100 Pa and 250 Pa, the insulating film 113 Since the water content can be reduced, variations in the electrical characteristics of transistor 11 can be reduced, and This allows for the suppression of fluctuations in the threshold voltage.

[0164] It is preferable to minimize damage to the OS layer 130 during the deposition of the insulating film 113. When the insulating film 114 is formed under conditions that reduce defects, the oxygen in the insulating film 114 The amount of desorption is easily reduced. Therefore, the oxygen supplied from the insulating film 114 is used to desorb the OS layer 130. This is because it can be difficult to sufficiently reduce defects. Therefore, the pressure in the processing chamber By setting the pressure to 100 Pa or more and 250 Pa or less, the OS layer 130 during the deposition of the insulating film 113 is formed. It is possible to reduce the damage.

[0165] Furthermore, by increasing the amount of oxidizing gas relative to the silicon-containing sedimentary gas to more than 100 times, It is possible to reduce the hydrogen content contained in the edge film 113. As a result, the OS layer 130 This reduces the amount of hydrogen mixed in, thus suppressing the negative shift in the transistor's threshold voltage. It can be controlled.

[0166] When using a PECVD apparatus, the insulating film 114 can be deposited under the following conditions: Substrate The temperature is between 180°C and 280°C, more preferably between 200°C and 240°C. The pressure inside the processing chamber is 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 2 It is 00 Pa or less. The high-frequency power supplied to the electrodes of the PECVD apparatus is 0.17 W / cm². 2 More than 0.5W / cm 2 More preferably, 0.25 W / cm² 2 More than 0.35W / c m 2 The following applies:

[0167] By supplying high-frequency power of the above power density in a reaction chamber at the above pressure, in the plasma As the decomposition efficiency of the raw material gas increases, oxygen radicals increase, and oxidation of the raw material gas progresses, insulation The oxygen content in film 114 becomes higher than the stoichiometric ratio. On the other hand, the substrate temperature is the above temperature In films formed at a certain temperature, the bonding force between silicon and oxygen is weak, so in subsequent heat treatment processes... Some of the oxygen in the membrane is removed. As a result, there is more oxygen than is needed to satisfy the stoichiometric composition. It can form a silicon oxidogenic nitride film in which some of the oxygen is removed by heating.

[0168] An insulating film 113 is provided on the OS layer 130. Therefore, in the process of forming the insulating film 114 In this configuration, the insulating film 113 becomes a protective film for the OS layer 130. Therefore, damage to the OS layer 130 The insulating film 114 can be formed using high-frequency power with high power density while reducing the load. can.

[0169] After forming insulating films 113 and 114, a heat treatment is performed. This heat treatment causes insulating film 11 A portion of the oxygen contained in 4 is moved to the OS layer 130, and the amount of oxygen deficiency contained in the OS layer 130 This can be further reduced. After heat treatment, an insulating film 115 is formed.

[0170] The insulating film 113 and insulating film 114 contain water, hydrogen, etc., and the device blocks water, hydrogen, etc. When forming an insulating film 115 that has insulating properties, if heat treatment is performed after the formation of the insulating film 115, Water, hydrogen, etc. contained in the edge film 113 and insulating film 114 move to the OS layer 130, and the OS layer 13 A defect occurs at 0. By performing heat treatment before the formation of the insulating film 115, the insulating film 113 Furthermore, the amount of water and hydrogen contained in the insulating film 114 can be effectively reduced.

[0171] By forming the insulating film 114 on the insulating film 113 while heating, oxygen is introduced into the OS layer 130. This heating method allows for movement and reduction of oxygen deficiencies in the OS layer 130. There are cases where processing is not necessary.

[0172] The temperature for this heat treatment is typically between 150°C and 400°C, preferably below 300°C. The temperature should be 400°C or lower, preferably 320°C to 370°C. The heat treatment should be performed using nitrogen and oxygen. Ultra-dry air (water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppm or less) The procedure should be carried out in an atmosphere of air (at ppb or less) or a noble gas (argon, helium, etc.). Furthermore, it is preferable that the above nitrogen, oxygen, ultra-dry air, or noble gases do not contain hydrogen, water, etc. For this heat treatment, an electric furnace, RTA device, etc., can be used. This allows for heat treatment at a temperature above the strain point of the substrate, albeit for a short period of time. Therefore, the heat treatment time can be shortened.

[0173] Here, a heat treatment is performed at 350°C for 1 hour in a nitrogen and oxygen atmosphere. After that, the insulating film is... Forms 115.

[0174] When forming insulating film 115 by PECVD, the substrate temperature should be between 300°C and 400°C. Preferably, the temperature should be between 320°C and 370°C, as this allows for the formation of a dense film. .

[0175] When forming a silicon nitride film as insulating film 115 by the PECVD method, the silicon is included. Sedimentary gases, nitrogen, and ammonia are preferably used as raw material gases. Compared to nitrogen, By using a small amount of ammonia, the ammonia dissociates in the plasma, generating reactive species. The active species is involved in the bonding of silicon and hydrogen in the silicon-containing sedimentary gas, and The triple bond of nitrogen is broken. As a result, the bonding between silicon and nitrogen is promoted, and silicon and It is possible to form a dense silicon nitride film with fewer hydrogen bonds and fewer defects. On the other hand, if the amount of ammonia relative to nitrogen is high, the sedimentary gas containing silicon and the decomposition of nitrogen occur. The process did not proceed, and silicon and hydrogen bonds remained, resulting in increased defects and a rough silicon nitride. A film is formed. For these reasons, nitrogen is used in relation to ammonia in the source gas. It is preferable that the flow rate ratio be 5 to 50, or 10 to 50.

[0176] Here, as the insulating film 115, silane, nitrogen, and ammonia are used in a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed from the raw material gas A. The flow rate is 50 s for silane. The nitrogen content is 5000 sccm and the ammonia content is 100 sccm. With a pressure of 100 Pa and a substrate temperature of 350°C, a 27.12 MHz high-frequency power supply was used. A high-frequency power of 000W is supplied to the parallel plate electrodes. The PECVD apparatus has an electrode area of ​​6000 cm 2 This is a parallel plate type PECVD apparatus, and the supplied power is used to measure power per unit area. Converted to (power density), it is 1.7 × 10⁻⁶ -1 W / cm 2 That is the case.

[0177] Through the above steps, insulating film 113, insulating film 114, and insulating film 115 can be formed. Cut.

[0178] A heat treatment may be performed after the formation of the insulating film 115. The temperature of the heat treatment is typically: 150°C to 400°C, preferably 300°C to 400°C, preferably 320°C The temperature shall be 370°C or lower. When performing this heat treatment, the water between insulating film 113 and insulating film 114 Because the amount of ions and water is reduced, the occurrence of defects in the OS layer 130 as described above is suppressed. It is.

[0179] Next, a photolithography process using a fifth photoresist mask is performed on the insulating layer 102. A resist mask RM5 (not shown) is then formed. Using the resist mask RM5, The edge layer 102 and the insulating layer 101 are etched to form openings 172 and 173. (Figure 7A).

[0180] After removing the resist mask RM5, a conductive film is formed on the insulating layer 102. The resist mask R is created by a photolithography process using a sixth photoresist mask. Form M6 (not shown). Etch the conductive film using the resist mask RM6. The back gate electrode 150 is formed. After this, the resist mask is removed.

[0181] Through the above process, the transistor 11 is formed using the first to sixth photoresist masks. It can be manufactured (Figure 7B). Other transistors according to Embodiment 1 can also be manufactured. It can be manufactured in the same way as the Ta11.

[0182] As described above, in this embodiment, in the process of manufacturing the OS transistor, channel type A process to form a film that supplies oxygen to the OS layer in order to reduce defects in the OS layer, including the formation region. The process includes supplying oxygen from the film to the OS layer, thus providing a highly reliable OS transition. It is possible to create a T.

[0183] (Embodiment 3) In this embodiment, an OS transistor according to Embodiment 1 is used as an example of a semiconductor device. This section describes an active-matrix display device.

[0184] <Example of display device configuration> An active-matrix display device is a semiconductor display device that includes a display panel, controller, power supply circuit, etc. It is a conductive device. Figure 14 shows the configuration of an active-matrix liquid crystal display (LCD). This is a block diagram showing an example. Figures 15A, 15B, and 15C show the components of the LCD. An example of the configuration of a liquid crystal panel (LC panel) is shown.

[0185] As shown in Figure 14, the display device 400 is connected to the controller 401 and the power management unit (PMU). 402, Power supply circuit 403, Pixel section 411, Gate driver circuit 412, Source driver circuit It has road 413.

[0186] The controller 401 controls the display device 400. The controller 401 also controls video Signals and synchronization signals for controlling screen refresh are input. For example, there are horizontal synchronization signals, vertical synchronization signals, and reference clock signals, and these signals Then, control signals for the driver circuits (412, 413) are generated. Also, controller 401 This controls the PMU402. Based on control signals from the controller 401 or an external source... Then, the PMU402 controls the power supply circuit 403.

[0187] The pixel section 411 consists of multiple pixels 421 arranged in an array, multiple gate lines 422, and It has multiple source lines 423. Pixels 421 in the same row are connected to gate lines 422 in each row. And, pixels 421 in the same column are connected to source lines 423 in each column. Pixel 421 is It has a transistor that controls the conduction with source line 423. The gate of this transistor is It is connected to gate line 422, and its on / off state is controlled by the signal input to the gate line. ru.

[0188] Source line 423 is connected to source driver circuit 413. 3 generates a data signal from the video signal input from the controller 401 and outputs to the source line It has the function of outputting to 423. The gate driver circuit 412 is connected to the controller 401. It has the function of outputting a gate signal to the gate line 422 according to the input control signal. The gate signal is a signal for selecting pixel 421 to input the data signal. Gate line 42 2 is connected to the gate driver circuit 412.

[0189] When the pixel section 411 is configured with OS transistors, both driver circuits (412, 413) In addition, the shift register 210 (Figure 13) is made of a unipolar transistor as shown in Embodiment 1. By using this method, the pixel unit 411 and the driver circuits (412, 413) can be integrated onto the same substrate. It is possible.

[0190] <Example of display panel configuration> Figure 15A shows that the pixel unit 411 and the driver circuits (412, 413) are integrated on the same substrate. An example of the configuration of a display panel with a structure is shown. The display panel 471 consists of circuit board 501 and circuit board 502. The substrate 501 has a pixel section 411 and driver circuits (412, 413), and Terminal section 415 is fabricated. In the example in Figure 15A, there are two gate driver circuits 412. It is divided and formed into gate driver circuit 412R and gate driver circuit 412L. Yes, they are.

[0191] The terminal section 415 connects the pixel section 411 and the driver circuits (412, 413) to an external circuit. Multiple terminals for connection are formed. Terminal section 415 is connected to FPC416. It is (FPC; Flexible printed circuit). Here, Devices in which the FPC416 is not connected to terminal 415 are also included in the display panel. It shall be considered as such.

[0192] The sealing member 503 maintained a gap (cell gap) between substrate 501 and substrate 502. In this state, they are facing each other. For example, in the case of a liquid crystal display panel (LCD panel), the circuit board A liquid crystal layer is sealed between 501 and substrate 502. The sealing member 503 seals the substrate 5 A liquid crystal layer is sealed between 01 and substrate 502. Also, as shown in Figure 15A, dry By providing the sealing member 503 so as to overlap with the circuit (412, 413), the display panel The frame that does not contribute to the display of Nell 471 can be narrowed.

[0193] In the display panel 471, for example, the pixel section 411 is configured with a circuit made of OS transistors. In this case, the driver circuit (412, 413) is also composed of a circuit made of OS transistors. These driver circuits (412, 413) are connected to FET-1-FET-3 (Figures 1-3). By using this, it is possible to create a circuit with a high drive frequency and low power consumption.

[0194] Since the display panel 471 has circuits (411-413) formed on the substrate 501, Since the number of components such as IC chips installed in the section can be reduced, costs can be lowered. Furthermore, if the circuit is not integrated on the same substrate as the pixel section 411, it becomes necessary to extend the wiring. The number of connections between wires increases. If a driver circuit is provided on the same board 501, the number of connections between wires increases. This can reduce the number of connections between components, leading to improved reliability or yield. .

[0195] Furthermore, some or all of the source driver circuit 413 is a CMOS circuit using Si transistors. It is also possible to configure it with a circuit. In this case, a part of the source driver circuit 413 is used. The IC chip can be integrated into the circuit board 501, and this IC chip can then be mounted onto the circuit board 501.

[0196] A display panel of such an example configuration is shown in Figures 15B and 15C. In 472, TCP418 is an IC chip that forms part of the source driver circuit 413. This is implemented (TCP; Tape Carrier Package). Figure 15C shows The display panel 473 shows the source driver circuit 413 on the TCP 418 IC chip. All circuits are integrated. Note that the TCP418 has an FP connected to the IC chip. C is not shown in the diagram. In this case, the circuit board 501 has a terminal section 41 connected to TCP 418. 7 is being manufactured. The source line of the pixel unit 411 is connected to TCP 418 at terminal 417. Multiple terminals are formed for this purpose. Note that TCP418 is not installed. This configuration is also considered one example of the display panel configuration of this embodiment.

[0197] Furthermore, some of the circuits of the source driver circuit 413 are used in the pixel section 411 and the gate driver circuit 4 If it can be fabricated with transistors of the same conductivity type as 12, the circuit can be integrated onto substrate 501. Furthermore, other circuits may be incorporated into the IC chip.

[0198] The method of mounting the IC chip is not particularly limited. The bare chip can be directly attached to the substrate 501. The COG (Chip on Glass) method is also acceptable. Alternatively, instead of TCP, The IC chip is incorporated into SOF (System on Film), and the SOF is placed on substrate 501 It can be attached to this.

[0199] <Structure of display device> As an example of a display device 400, the structure of the display device will be described with reference to Figure 16. Figure 16 is an exploded perspective view of the display device.

[0200] As shown in Figure 16, the display device 400 is located between the upper cover 481 and the lower cover 482. , Touch panel unit 484 connected to FPC483, and a table connected to FPC485 Display panel 471, backlight unit 487, frame 489, printed circuit board 490, It has a battery 491. Note that the backlight unit 487, battery 491, The touch panel unit 484 may not be provided in some cases. For example, the display device 400 However, in the case of reflective liquid crystal displays or electroluminescent (EL) displays, the backlight The 487th unit is an unnecessary part.

[0201] The upper cover 481 and the lower cover 482 are the touch panel unit 484 and the display panel. The shape and dimensions can be appropriately modified to match the size of 471.

[0202] The touch panel unit 484 displays a resistive or capacitive touch panel. It can be used superimposed on the panel 471. Also, the opposing substrate (sealing substrate) of the display panel 471. It is also possible to incorporate touch panel functionality into the board. Alternatively, a display panel It is also possible to equip each of the 471 pixels with a light sensor to create an optical touch panel. Alternatively, an electrode for a touch sensor is provided within each pixel of the display panel 471, and a capacitive type touch panel It is also possible to use "ru".

[0203] The backlight unit 487 has a light source 488. It may also be provided at the end of T487 and configured to use a light-diffusing plate.

[0204] Frame 489 provides protection for the display panel 471, as well as through the operation of the printed circuit board 490. It functions as an electromagnetic shield to block the generated electromagnetic waves. Also, frame 48 9 may also function as a heat sink.

[0205] The printed circuit board 490 contains a power supply circuit and signal processing for outputting video signals and clock signals. It has a power supply circuit. The power supply that provides power to the power supply circuit can be an external commercial power supply. Alternatively, the power source may be a separately provided battery 491. The battery 491 is a commercial battery. This can be omitted when using a power supply.

[0206] Furthermore, the display device 400 is equipped with additional components such as polarizing plates, phase difference plates, and prism sheets. It is also acceptable to use the display panel 471 shown in Figure 15A in the example in Figure 16. Display panels with other structures (for example, display panels 472 and 473) may also be used.

[0207] <Pixels of a liquid crystal display (LCD)> FIG. 17A is a circuit diagram showing an example of the configuration of pixels of an LCD. Pixel 430 has a transistor 431, a liquid crystal element 432, and a capacitive element 433.

[0208] The liquid crystal element 432 has two electrodes and a liquid crystal layer sandwiched between the two electrodes. One of the electrodes is composed of a pixel electrode formed on a substrate 501, and the pixel electrode is connected to the transistor 43 1. Also, a voltage VLC is input to the other electrode of the liquid crystal element 432. The transistor 431 functions as a switch for controlling the conduction state between the liquid crystal element 432 (pixel electrode) and the source line 423, and its gate is connected to the gate line 422. Here, the transistor 431 applies FET-1 (FIG. 1). The capacitive element 433 has the function of a holding capacitor for holding the voltage between the two electrodes of the liquid crystal element 432. When the transistor 431 is in the on state, the liquid crystal element 432

[0209] and the capacitive element 433 are discharged or charged according to the potential of the source line 423. Due to the voltage held by the liquid crystal element 432 and the capacitive element 433, the alignment state of the liquid crystal layer changes, and the transmittance of the liquid crystal element 432 changes .

[0210] Note that by changing the circuit configuration of the pixel, a display device other than an LCD can be obtained. For example, when making an electronic paper, in FIG. 17A, instead of the liquid crystal element 432, a display element for controlling gradation by an electrophoretic method or the like may be provided.

[0211] <Pixels of an EL display device> Also, when the display device 400 is an EL display device, the pixel 440 in FIG. 17B may be provided in the pixel portion 411 Pixel 440 has a transistor 441, a transistor 442, an EL element 4​​ It has transistors 43 and a capacitive element 444. Here, transistors 441 and 442 are the same It is a conductive transistor.

[0212] Transistor 441 is a switch transistor that controls the conduction between pixel 440 and source line 423. It is a transistor. Also, transistor 442 is a transistor called a drive transistor. It is a FET-1 device and has the same device structure.

[0213] The EL element 443 consists of two electrodes (anode and cathode) and an organic element sandwiched between the two electrodes. This is a light-emitting element having a light-emitting layer containing a compound. One electrode is subjected to a constant potential input. It is connected to wiring 425. The light-emitting layer contains at least a light-emitting substance. Light-emitting substance Examples include organic EL materials and inorganic EL materials. Furthermore, the light emission of the light-emitting layer is singlet light. Emission (fluorescence) when returning from an excited state to the ground state, when returning from a triplet excited state to the ground state It emits light (phosphorescence).

[0214] The EL element 443 is capable of changing its light emission intensity by the current flowing between its two electrodes. This is an element. Here, the current flowing through transistor 442 determines the light emission of the EL element 443. The intensity is adjusted. In other words, the voltage at the gate of transistor 442 controls the EL element 443 The light intensity is adjusted.

[0215] A capacitive element 444 is connected between the gate of transistor 442 and wiring 425. The element 444 functions as a holding capacitor that maintains the gate voltage of transistor 442. When transistor 441 is turned on, the source signal input to source line 423 A current of a magnitude corresponding to the potential flows through transistor 441. This current causes the transistor The gate of the STA442 is charged or discharged, and its potential is adjusted.

[0216] Note that the pixel circuit configuration is not limited to the example in Figure 17. For example, the pixel shown in Figure 17 may have a switch Switches, resistors, capacitives, sensors, transistors, or logic circuits may be added.

[0217] For example, in this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having sub-elements and light-emitting elements, can use various forms, or various It may have elements. Examples of display elements, display devices, light-emitting elements, or light-emitting devices include EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL) Elements (inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) ), transistor (a transistor that emits light in response to current), electron emission element, liquid crystal element, electric Ink cartridges, electrophoretic elements, grating light bulbs (GLVs), plasma displays PDP (Photographic Display Panel), MEMS (Micro-Electro-Mechanical Systems), Digital Ma Micromirror device (DMD), DMS (Digital Microshutter), MIR ASOL (registered trademark), IMOD (Interference Modulation) element, E Lectrowetting elements, piezoelectric ceramic displays, carbon nanotubes, etc. Display media whose contrast, brightness, reflectivity, transmittance, etc., change due to electromagnetic interference. Some have bodies. An example of a display device using EL elements is an EL display. There are such devices. An example of a display device using an electron-emitting element is a field emission device. Surface-to-Eye Display (FED) or Surface-to-Eye Display (SED: Surface-to-Eye Display) Examples include (e.g., an Electron-emitter Display). An example of a display device using liquid crystal elements is a liquid crystal display (transmissive liquid crystal display). Semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection Examples include liquid crystal displays. An example of a display device using electronic ink or electrophoretic elements. Examples include electronic paper.

[0218] <Device structure of pixels in a display device> The following describes the device configuration of pixels in an active-matrix display device with reference to Figures 18 and 19. Let's explain the structure. Here, as an example, we will explain the device structure of the pixel section 411. Here, the structure of the pixel section 411 will be explained using pixel 430 in Figure 17A as an example.

[0219] Figure 18 is a top view of the pixel section 411 (pixel 430), and shows a planar laser such as transistor 431. This corresponds to the out. Also, Figure 19 is a cross-sectional view taken along the cutting line B3-B4 in Figure 18. It also corresponds to a cross-sectional view of the display panel 471.

[0220] Pixel 430 has circuits (411, 412, 413) formed from an oxide semiconductor film. It includes a backplane and a color filter substrate. The backplane's support substrate is a substrate The support substrate for the color filter substrate is substrate 502. Substrates 501, 502 A substrate that transmits visible light is used, for example, a glass substrate or a flexible substrate made of resin. This is used. When using a flexible substrate, after forming the backplane, it is used during fabrication. After separating the support substrate, the flexible substrate can be fixed in place.

[0221] Figure 18 shows the planar layout of pixels 430 on the backplane side. The lane is an OS using the first to sixth photoresist masks described in Embodiment 2. It is manufactured using the same process as transistor manufacturing. Therefore, backplane fabrication The method will be based on Embodiment 2. Together with the pixel portion 411, an oxide is applied to the substrate 501. A driver circuit (412, 413) is formed using a monocrystalline semiconductor film.

[0222] The sealing member 503 (Figure 15A) seals the liquid crystal layer 520 between the substrate 501 and the substrate 502. It is stopped. On the substrate 502, there is a shielding film 541 that has the function of blocking visible light, and a specific wave A colored layer 542 that transmits a wide range of visible light is provided. Shielding film 541 and colored layer 5 A resin film 543 is provided on 42, and an electrode 652 is provided on the resin film 543. Electrode 652 is called the common electrode and constitutes the electrode of the liquid crystal element 432. An orientation film 532 is formed covering 52.

[0223] The pixel section 411 has wiring (GL) 621, wiring (SL) 645, electrode (ME) 646, and It has a gate electrode (BG) 650 and an oxide semiconductor layer (OS) 630. This constitutes transistor 431. Wiring (GL) 621 is opposite gate wire 422. This includes the region that will become the front gate electrode of transistor 431. Wiring (SL) 645 This corresponds to source line 423 and includes the region that becomes the source electrode of transistor 431. Electrode ( ME)646 constitutes the drain electrode of transistor 431. Note that Figure 19 shows The cross-sectional structure of the lunger 431 in the channel length direction is shown.

[0224] A metal oxide layer (OC) 635 and a pixel electrode (PIX) 651 are formed in the pixel portion 411. The metal oxide layer 635 and the pixel electrode 651 constitute a pair of electrodes of the capacitive element 433. It accomplishes. Also, the pixel electrode 651 constitutes the electrode of the liquid crystal element 432. The liquid crystal layer 520 is sandwiched between them. The region where pixel electrode 651 and electrode 652 face each other functions as a liquid crystal element 432 (Figure 19).

[0225] As shown in Figure 19, an insulating layer 601 is formed covering the wiring 621, and on the insulating layer 601, An oxide semiconductor layer 630 and a metal oxide layer 635 are formed. The insulating layer 601 is an insulating layer It consists of a laminated film of an edge film 611 and an insulating film 612. Oxide semiconductor layer 630 and metal oxide layer 6 35 consists of a multilayer film of metal oxide film 631 and metal oxide film 632. Oxide semiconductor layer 63 At 0, the metal oxide film 631 is an oxide semiconductor film in which a channel is formed. A wiring (SL) 645 is in contact with one of a pair of opposing sides of the semiconductor layer 630, and on the other side... Electrode (ME) 646 is in contact.

[0226] The oxide semiconductor layer 630, the metal oxide layer 635, the wiring 645, and the electrode 646 are covered by an insulating layer. An edge layer 602 is formed. The back gate electrode 650 and the pixel electrode are placed on the insulating layer 602. Electrode 651 is formed. It covers and aligns the back gate electrode 650 and the pixel electrode 651. A film 531 is formed.

[0227] The insulating layer 602 has a laminated structure consisting of insulating films 613-615. An aperture 671 is formed that reaches the electrode 646, and in the aperture 671, the electrode 646 and the pixel Electrode 651 is in contact. Also, the insulating layer 602 and insulating layer 601 reach the wiring 621. An opening 672 (Figure 18) is formed, and the back gate electrode 650 is located in the opening 672. It is in contact with wiring 621. Note that, as shown in Figure 1A, the back gate electrode 650 and wiring 621 Two openings may be provided to connect them.

[0228] The opening 673 is formed in the laminated film of insulating film 613 and insulating film 614 within the insulating layer 602. In the aperture 673, the metal oxide layer 635 and the pixel electrode 65 are separated by the insulating film 615. The region where 1 is facing functions as a capacitive element 433. In this case, insulating films 613, 61 After continuously depositing film 4, an opening 673 is formed. Then, an insulating film 615 made of nitride insulator is formed. Formed. The metal oxide layer 635 can be used as an electrode for the capacitive element 433 because For example, when forming the opening 673, or when forming the insulating film (nitride insulating film) 615, metal acid Oxygen vacancies are formed in the oxide layer 635, and hydrogen that has diffused from the insulating film 615 into the oxygen vacancies. This is thought to be because donors are generated by bonding to the loss. Specifically, the metal oxide layer 6 The resistivity of 35 is typically 1 × 10⁻⁶. -3 Ωcm or more, 1 × 10 4 Less than Ωcm, even better Alternatively, the resistivity is 1 × 10⁻⁶ -3 Ωcm or more, 1 × 10 -1 It should be less than Ωcm.

[0229] The metal oxide layer 635 preferably has a higher hydrogen concentration than the oxide semiconductor layer 630. In oxide layer 635, the hydrogen concentration obtained by SIMS is 8 × 10⁻⁶. 19 atoms / cm 3 Preferably 1 × 10 20 atoms / cm 3The above is a comfortable 5x1 0 20 atoms / cm 3 That concludes the explanation. In the oxide semiconductor layer 630, SIMS is performed The hydrogen concentration obtained is 5 × 10 19 atoms / cm 3 Less than 5 × 10 18 a toms / cm 3 Less than 1 × 10 18 atoms / cm 3 The following are more preferable is 5 x 10 17 atoms / cm 3 More preferably 1 × 10 16 ate / c m 3 The following applies:

[0230] Note that in Figures 18 and 19, it is driven in TN (Twisted Nematic) mode. The pixel configuration example shown is not limited to this. Witching mode, STN (Super Twisted Nematic) mode Code, VA (Vertical Alignment) mode, MVA (Multi-d Main Vertical Alignment mode, IPS (In-Plane) e Switching) mode, OCB (Optically Compensated d Birefringence) mode, Blue phase mode, TBA (Transverse) (se Bend Alignment) mode, VA-IPS mode, ECB (Elec (Trially Controlled Birefringence) Mode, FL C (Ferroelectric Liquid Crystal) mode, AFLC ( AntiFerroelectric Liquid Crystal) mode, PDL C (Polymer Dispersed Liquid Crystal) mode, P NLC (Polymer Network Liquid Crystal) mode, Modes such as Host Mode and ASV (Advanced Super View) It is also possible to use pixels with a structure driven by a code.

[0231] Furthermore, the liquid crystal layer 520 is divided into, for example, thermotropic liquid crystal or lyotropic liquid crystal. Similar liquid crystal materials can be used. Alternatively, the liquid crystal layer 520 may contain, for example, Nematics. Liquid crystals are classified into crystalline liquid crystals, smetic liquid crystals, cholesteric liquid crystals, or discotic liquid crystals. A liquid crystal material can be used. Alternatively, the liquid crystal layer 520 may be, for example, a ferroelectric liquid crystal. Alternatively, a liquid crystal material classified as an antiferroelectric liquid crystal can be used. For example, 20 includes main-chain polymer liquid crystals, side-chain polymer liquid crystals, or composite polymer liquid crystals. Any liquid crystal material classified as polymer liquid crystal or low-molecular-weight liquid crystal can be used. For the liquid crystal layer 520, for example, a liquid crystal material classified as polymer dispersed liquid crystal (PDLC) is used. It is possible to be there.

[0232] Furthermore, if an alignment layer is not used, a liquid crystal exhibiting a blue phase may be used in the liquid crystal layer 520. One phase is one of the liquid crystal phases, and when cholesteric liquid crystal is heated, the cholesteric phase This is a phase that appears just before the transition to the isotropic phase. The blue phase only appears within a narrow temperature range. Therefore, chiral agents and UV-curing resins are added to improve the temperature range. A liquid crystal composition containing a chiral agent has a short response time of 1 msec or less and is optically isotropic. Therefore, alignment processing is unnecessary, and it is preferable because it has low dependence on the viewing angle.

[0233] Furthermore, here we have a liquid crystal display device that uses a color filter to display color images. While this is an example, the method of color display is not limited to this. For example, emitting light of different hues The configuration may include sequentially lighting up multiple light sources to display a color image. .

[0234] (Embodiment 4) In this embodiment, the oxide semiconductor film and the like that constitute the OS layer of the OS transistor will be described. do.

[0235] <Structure of oxide semiconductor film> The following describes the structure of the OS layer of an OS transistor. In this context, "parallel" refers to a state where two straight lines are positioned at an angle of -10° or more and 10° or less. It refers to the state. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "approximately parallel" means two This refers to a state where straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" This refers to a state where two straight lines are positioned at an angle of 80° to 100°. Therefore, This also includes cases where the angle is between 85° and 95°. Furthermore, "approximately perpendicular" means that two lines are at an angle of 60° or less. This refers to a state where objects are positioned at an angle of 120° or less upwards.

[0236] The OS layer can be formed from a single-crystal oxide semiconductor film or a non-single-crystal oxide semiconductor film. Crystalline oxide semiconductor films include amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and polycrystalline oxide films. Semiconductor film, CAAC-OS (C Axis Aligned Crystalline This refers to oxide semiconductor films, etc.

[0237] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is disordered and has no crystal component. The entire film is completely amorphous and has no crystal part even in a minute region. A typical example is an oxide semiconductor film.

[0238] A microcrystalline oxide semiconductor film contains, for example, microcrystals (also called nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a higher degree of order than the amorphous oxide semiconductor film. For this reason, the microcrystalline oxide semiconductor film is characterized by having a lower density of defect energy levels than the amorphous oxide semiconductor film.

[0239] A CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts. s

[0240] <CAAC-OS film> s By observing a composite analysis image (also called a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of crystal parts can be confirmed. On the other hand, a clear boundary between crystal parts, that is, a grain boundary (also called a grain boundary), cannot be confirmed by a high-resolution TEM image. Therefore, it can be said that a decrease in electron mobility due to grain boundaries hardly occurs in a CAAC-OS film.

[0241] When observing a high-resolution TEM image of a cross-section of a CAAC-OS film from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms reflects the irregularities of the surface (also called the film-forming surface) or the upper surface of the CAAC-OS film. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0242] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction approximately perpendicular to the sample surface. This confirms that in the crystalline region, the metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0243] Furthermore, when electron diffraction is performed on the CAAC-OS film, oriented spots (bright spots) can be observed. It is measured. For example, on the upper surface of the CAAC-OS film, an electric field of, for example, between 1 nm and 30 nm is measured. When electron diffraction using a sub-beam (also called nanobeam electron diffraction) is performed, a spot is observed. (Figure 22A).

[0244] High-resolution TEM images of the cross-section and high-resolution TEM images of the planar region of the CAAC-OS film It can be seen that it has orientation.

[0245] Furthermore, most of the crystalline parts contained in the CAAC-OS film are cubes with sides less than 100 nm long. It is small enough to fit inside. Therefore, the crystalline portion contained in the CAAC-OS film has a side length of 10n. This also includes cases that fit within a cube smaller than m, smaller than 5 nm, or smaller than 3 nm. Furthermore, multiple crystalline regions contained in the CAAC-OS film are linked together, forming one large crystalline region. This can sometimes form. For example, in a high-resolution planar TEM image, at 2500 nm 2 That's all. , 5μm 2 or greater than 1000 μm 2 In some cases, crystal regions exceeding the above size may be observed.

[0246] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing vertically.

[0247] On the other hand, in the CAAC-OS film, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plane configuration. In analysis using the ne method, a peak may appear when 2θ is around 56°. This peak is... It is attributed to the (110) plane of the InGaZnO4 crystal. InGaZnO4 single-crystal oxide. For semiconductor films, fix 2θ to around 56° and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while analysis (φ scan) is performed, it is possible to return to a crystal plane equivalent to the (110) plane. Six peaks belonging to this group are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 56 Even when fixed near ° and scanned at φ, no clear peak appears.

[0248] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in that direction. Therefore, as confirmed by the high-resolution TEM observation of the cross-section mentioned above, Each layer of metal atoms arranged in layers is a plane parallel to the ab-plane of the crystal.

[0249] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed at that time. As described above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. The vector may not be parallel to the normal vector of the top surface.

[0250] Furthermore, in the CAAC-OS film, the distribution of c-axis oriented crystalline regions does not need to be uniform. For example, the crystalline portion of the CAAC-OS film is formed by crystal growth from near the top surface of the CAAC-OS film. When formed in this way, the region near the top surface has more c-axis-oriented crystal parts than the region near the surface being formed. The proportion can be high. Also, when impurities are added to the CAAC-OS film, the impurities The added region is altered, and regions with different proportions of partially c-axis-oriented crystals are formed. Sometimes.

[0251] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0252] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0253] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0254] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Transistors using oxide semiconductor films exhibit electrical characteristics where the threshold voltage is negative (no Also called Marion.) It rarely becomes high-purity genuine or substantially high-purity genuine. Oxide semiconductor films, being of a certain nature, have few carrier traps. Therefore, the oxide semiconductor film Transistors using this technology exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the time required to release the charge trapped in the carrier trap of the oxide semiconductor film is [time]. The interval is long, and it can behave as if it were a fixed charge. Therefore, the impurity concentration is high. Transistors using oxide semiconductor films with a high defect level density exhibit unstable electrical properties. There are cases where this is the case.

[0255] OS transistors using CAAC-OS films exhibit electrical properties under irradiation with visible and ultraviolet light. It has low variability and high reliability.

[0256] CAAC-OS films are made using, for example, a polycrystalline metal oxide target, and sputtering The film is formed by the ion deposition method. When ions collide with the target, the ions contained in the target... The crystal region is cleaved from the ab plane and has a flat or pellet-like shape with a plane parallel to the ab plane. They may peel off as puttering particles. In this case, the flat or pellet-shaped particles... The sputtered particles reach the substrate while maintaining their crystalline state, resulting in CAAC-OS A film can be formed.

[0257] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities present in the processing room (hydrogen, water, carbon dioxide, and nitrogen, etc.) It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0258] Furthermore, by increasing the substrate heating temperature during film formation, flat plate or pellet-shaped sputtering can be achieved. When particles reach the substrate, migration occurs on the substrate, and the sputtering particles A flat surface adheres to the substrate. For example, the substrate heating temperature is preferably between 100°C and 740°C. Alternatively, the temperature should be between 200°C and 500°C.

[0259] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. This can reduce the amount of oxygen in the film-forming gas, preferably 30% by volume or more. It can be set to 100% by volume.

[0260] <Microcrystalline oxide semiconductor film> Next, we will explain microcrystalline oxide semiconductor films.

[0261] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0262] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the film. In some cases, nc-OS films are indistinguishable from amorphous oxide semiconductor films depending on the analytical method. There are cases where XRD equipment using X-rays with a diameter larger than that of the crystalline region is used on nc-OS films. When structural analysis is performed using this method, the out-of-plane method reveals the crystal planes. No peaks are detected. Also, for nc-OS films, the probe diameter is larger than that of the crystalline region. For example, electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or greater. Then, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal region. When this is done, a spot is observed. Furthermore, nanobeam electron diffraction is performed on the nc-OS film. In some cases, a region of high brightness may be observed in a circular (ring-shaped) pattern. - When nanobeam electron diffraction is performed on the OS film, multiple spots are observed within a ring-shaped region. This may occur (Figure 22B).

[0263] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0264] <Amorphous oxide semiconductor film> Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0265] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0266] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0267] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0268] When an oxide semiconductor film has multiple structures, its structure can be analyzed using nanobeam electron diffraction. It may be possible.

[0269] Figure 23 shows an example of a transmission electron diffraction measurement device. Figure 23A shows the external view of the transmission electron diffraction measurement device. The external view is shown, and its internal structure is shown in Figure 23B.

[0270] The transmission electron diffraction analyzer 9000 consists of an electron gun chamber 9010, an optical system 9012, and a sample chamber 9014. It has an optical system 9016, an observation room 9020, and a film room 9022. Observation room 902 Camera 9018 and fluorescent board 9032 are installed in 0. Camera 9018 is connected to the fluorescent board It is installed facing 9032. Note that it is not necessary to have a film chamber 9022.

[0271] Inside the transmission electron diffraction measuring device 9000, the electron gun installed in the electron gun chamber 9010 The electrons emitted from there are directed to the material 9028 placed in the sample chamber 9014 via the optical system 9012. The electrons that have passed through material 9028 are irradiated onto the fluorescent screen 9032 via the optical system 9016. It is incident on the fluorescent screen 9032. A pattern appears that corresponds to the intensity of the incident electrons. It is possible to measure the transmission electron diffraction pattern.

[0272] Camera 9018 is positioned facing fluorescent board 9032, and when the fluorescent board 9032 appears, It is possible to photograph the turn. The center of the lens of camera 9018 and the fluorescent screen 90 The angle between the straight line passing through the center of 32 and the top surface of the fluorescent board 9032 is, for example, 15° or more. The angle shall be less than or equal to 30° to 75°, or between 45° and 70°. However, the transmission electron diffraction pattern captured by camera 9018 will be highly distorted. If the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. It is also possible.

[0273] In some cases, camera 9018 may be installed in film chamber 9022. For example, Camera 9018 is installed in film chamber 9022 so as to be opposite to the direction of incidence of electron 9024. This is also possible. In this case, a transmission electron diffraction pattern with minimal distortion can be obtained from the back surface of the fluorescent plate 9032. It can be photographed.

[0274] Sample chamber 9014 is equipped with a holder for fixing the sample substance 9028. The holder has a structure that allows electrons to pass through material 9028. The holder is, For example, it may have a function to move material 9028 along the X, Y, and Z axes. The movement function of the luda is, for example, between 1 nm and 10 nm, between 5 nm and 50 nm, and 10 nm. Examples include m to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, etc. It is sufficient to have the precision to move within a certain range. These ranges depend on the structure of material 9028. Then you just need to set the optimal range.

[0275] Next, the transmission electron diffraction pattern of the material is measured using the transmission electron diffraction analyzer 9000. I will explain the method.

[0276] For example, as shown in Figure 23B, the illumination of material 9028 by electrons 9024, which is a nanobeam. By changing the firing position (scanning), we can observe how the structure of substance 9028 changes. This can be confirmed. In this case, if substance 9028 is a CAAC-OS film, then Figure 22A A diffraction pattern like the one shown is observed. Alternatively, if material 9028 is an nc-OS film A diffraction pattern like the one shown in Figure 22B is observed.

[0277] By the way, even if substance 9028 is a CAAC-OS film, it may be partially an nc-OS film. Similar diffraction patterns may be observed. Therefore, the quality of the CAAC-OS film This is the percentage of the region in which the diffraction pattern of the CAAC-OS film is observed within a certain range (CA It can sometimes be expressed as (also called AC conversion rate). For example, a high-quality CAAC-OS film In that case, the CAAC conversion rate should be 60% or more, preferably 80% or more, and more preferably 90% The percentage is % or higher, more preferably 95% or higher. A diffraction pattern different from that of the CAAC-OS film can be observed. The measured region is referred to as the non-CAAC rate.

[0278] For example, immediately after film deposition (indicated as as-depo), after heat treatment at 350°C or 450°C Three types of samples with CAAC-OS films after heat treatment were prepared, and for these samples, A transmission electron diffraction pattern was acquired while scanning the top surface. Here, a speed of 5 nm / second was used. The diffraction pattern is observed while scanning at speed for 60 seconds, and the observed diffraction pattern is set to 0. The CAAC conversion rate was derived by converting to a still image every 5 seconds. As for the electron beam, a probe was used. A nanobeam electron beam with a diameter of 1 nm was used.

[0279] Figure 24 shows the CAAC conversion rate for each sample, compared to immediately after film deposition and after heat treatment at 350°C. This shows that the CAAC conversion rate is high after heat treatment at 450°C. In other words, at temperatures higher than 350°C... Heat treatment at temperatures above 400°C (e.g., 400°C) reduces the non-CAAC conversion rate (CA It can be seen that the AC conversion rate will increase.

[0280] Here, most of the diffraction patterns that differ from those of the CAAC-OS film are similar to those of the nc-OS film. It was a pattern. Therefore, by heat treatment, it had a structure similar to that of an nc-OS film. This suggests that the region is undergoing CAAC transformation due to the influence of the structure of adjacent regions. Using such measurement methods, it becomes possible to analyze the structure of oxide semiconductor films that have multiple structures. There are cases where this is the case.

[0281] (Embodiment 5) A transistor according to one embodiment of the present invention can be used to construct various electronic devices. For example For example, as an electronic device, it includes a display device, a personal computer, and an image playback device equipped with a recording medium. (Typically, recording media such as DVDs: Digital Versatile Discs) It can be used in a device that has a display capable of reproducing and displaying the image. In addition, as an electronic device that can use a transistor according to one embodiment of the present invention, a portable electric device Talking, portable game consoles, personal digital assistants, e-books, video cameras, digital still cameras Cameras such as Mera, goggle-type displays (head-mounted displays), navigation Sound systems, audio playback devices (car audio, digital audio players, etc.), Photocopiers, fax machines, printers, multifunction printers, automated teller machines (AT) Examples include vending machines. Specific examples of these electronic devices are shown in Figure 20.

[0282] Figure 20A shows a portable game console, consisting of a casing 5001, a casing 5002, a display unit 5003, and a display unit. Part 5004, Microphone 5005, Speaker 5006, Operation Key 5007, Stylus It has S5008, etc. Display unit 5003 or display unit 5004, or other integrated circuits, A transistor according to one embodiment of the present invention can be used. The game console has two display units 5003 and 5004, but the portable game The number of display units the device has is not limited to this.

[0283] Figure 20B shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit 56 03, it has a second display unit 5604, a connection unit 5605, an operation key 5606, etc. First display unit 5603 is located in the first enclosure 5601, and the second display unit 5604 is located in the second enclosure 5602 It is provided in the first housing 5601 and the second housing 5602 are connected by a connection part 5605 They are connected by the first housing 5601 and the second housing 5602, and the angle between them is the connection part 56 It can be changed by 05. The video in the first display unit 5603 is connected to the connection unit 560 The configuration is switched according to the angle between the first housing 5601 and the second housing 5602 in 5. You may do so. The first display unit 5603 or the second display unit 5604 or other integrated circuits may be configured with this A transistor according to one embodiment of the invention can be used.

[0284] Figure 20C shows a notebook-type personal computer, comprising a casing 5401, a display unit 5402, It has a keyboard 5403, a pointing device 5404, etc., a display unit 5402, A transistor according to one embodiment of the present invention can be used in other integrated circuits.

[0285] Figure 20D shows a wristwatch, consisting of a casing 5201, a display unit 5202, operation buttons 5203, and a band. It has 5204, etc. Display unit 5202 and other integrated circuits, according to one embodiment of the present invention A transistor can be used.

[0286] Figure 20E shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 5803. It has an operation key 5804, a lens 5805, a connector 5806, etc. Operation key 5804 and The lens 5805 is located in the first housing 5801, and the display unit 5803 is located in the second housing 58 It is located at 02. And the first housing 5801 and the second housing 5802 are connected at the connection part 58 The connection is made by 06, and the angle between the first housing 5801 and the second housing 5802 is the connection part This can be changed by 5806. The video switching in the display unit 5803 is connected Configuration performed according to the angle between the first housing 5801 and the second housing 5802 in the extension 5806. It is also possible to use a transistor according to one embodiment of the present invention in the display unit 5803 or other integrated circuits. You can use sta.

[0287] Figure 20F shows a mobile phone, with a housing 5901 containing a display unit 5902, a microphone 5907, and a speaker. A car 5904, a camera 5903, an external connection unit 5906, and an operation button 5905 are provided. The display unit 5902 and other integrated circuits contain transistors according to one embodiment of the present invention. It can be used. Furthermore, a transistor according to one embodiment of the present invention can be placed on a flexible substrate. When formed in this manner, the display section 5902 having a curved surface as shown in Figure 20F is in one embodiment of the present invention. It is possible to apply such transistors.

[0288] A transistor according to one embodiment of the present invention is formed on a single-crystal silicon wafer. By combining it with a sta, it is possible to configure various semiconductor devices. For example, memo Programmable devices such as CPUs, microcontrollers, FPGAs, and RFID Examples include tags. Here, we will explain the use of RFID tags.

[0289] RFID tags have a wide range of applications. These applications include, for example, banknotes, coins, and securities. , bearer bonds, certificates (driver's license, resident registration, etc., Figure 21A), packaging containers (wrapping paper and Bottles, etc. (Figure 21C), recording media (DVDs, videotapes, etc., Figure 21B), vehicles Categories include: bicycles (and other similar items, see Figure 21D), personal belongings (bags, glasses, etc.), food products, plants, animals, and the human body. Clothing, household goods, medical products including medicines and drugs, or electronic devices (liquid crystal displays, EL displays) Display devices, smartphones, mobile phones, watches, wristwatches, and other items, or items attached to each of these items. It can be used by attaching it to tags (Figures 21E, 21F), etc.

[0290] The RFID tag 4000 is attached to an item by being attached to or embedded in its surface. For example, in the case of a book, it would be embedded in the paper, and in the case of a package made of organic resin, the organic resin would be embedded in the package. It is embedded inside and secured to each item. The RFID tag 4000 is small, thin, and lightweight. Therefore, even after being fixed to an item, it does not impair the design of the item itself. RFID tags 4000 are attached to banknotes, coins, securities, bearer bonds, or other documents. By doing so, an authentication function can be added. This authentication function can be used to prevent forgery. It can be stopped. Also, packaging containers, recording media, personal belongings, food products, clothing, and daily life By attaching RFID tags 4000 to supplies or electronic devices, the inspection system can be implemented. Furthermore, it can improve the efficiency of systems such as inventory management systems. Also, RF can be used for vehicles. Attaching ID tag 4000 can enhance security. [Explanation of Symbols]

[0291] 11 transistors 12 transistors 13 transistors 100 circuit boards 101 Insulating layer 102 Insulating layer 111 Insulating Film 112 Insulating film 113 Insulating Film 114 Insulating Film 115 Insulating film 120 Conductive film 121 Front gate electrode 130 Oxide semiconductor (OS) layer 131 Metal oxide films (oxide semiconductor films) 132 Metal oxide film 140D drain electrode 140S Source Electrode 141 Conductive film 142 Conductive film 150 Back Guard 151 Back gate 152 Electrode 153 Electrode 172 Aperture 173 Aperture

Claims

1. It has first to third transistors, One of the source electrode or drain electrode of the first transistor is always in electrical contact with the first power line. The source electrode or drain electrode of the first transistor is always in electrical contact with the source electrode or drain electrode of the second transistor. The first gate electrode of the first transistor is always in conductivity with the first clock signal line. The second gate electrode of the first transistor is always in conductivity with the first clock signal line. The source electrode or the other drain electrode of the second transistor is always in contact with the output signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the source electrode or drain electrode of the third transistor. The first gate electrode of the second transistor is always in conductivity with the first signal line. The second gate electrode of the second transistor is always in conductivity with the first signal line. The source electrode or the other of the drain electrode of the third transistor is always in electrical contact with the second power line. The first gate electrode of the third transistor is always in electrical contact with either the source electrode or the drain electrode of the third transistor. The second gate electrode of the third transistor is always in contact with the second clock signal line. The first transistor described above is An oxide semiconductor layer having a channel-forming region, The first conductive layer having the function of the first gate electrode, A second conductive layer having the function of the second gate electrode, The first insulating layer, It has a second insulating layer, The oxide semiconductor layer has a region that overlaps with the first conductive layer via the first insulating layer, The oxide semiconductor layer has a region that overlaps with the second conductive layer via the second insulating layer, The first conductive layer has a region that is in contact with the second conductive layer through openings provided in the first insulating layer and the second insulating layer. Semiconductor equipment.

2. It has first to third transistors, One of the source electrode or drain electrode of the first transistor is always in electrical contact with the first power line. The source electrode or drain electrode of the first transistor is always in electrical contact with the source electrode or drain electrode of the second transistor. The first gate electrode of the first transistor is always in conductivity with the first clock signal line. The second gate electrode of the first transistor is always in conductivity with the first clock signal line. The source electrode or the other drain electrode of the second transistor is always in contact with the output signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the source electrode or drain electrode of the third transistor. The first gate electrode of the second transistor is always in conductivity with the first signal line. The second gate electrode of the second transistor is always in conductivity with the first signal line. The source electrode or the other of the drain electrode of the third transistor is always in electrical contact with the second power line. The first gate electrode of the third transistor is always in electrical contact with either the source electrode or the drain electrode of the third transistor. The second gate electrode of the third transistor is always in contact with the second clock signal line. The first transistor described above is An oxide semiconductor layer having a channel-forming region, The first conductive layer having the function of the first gate electrode, A second conductive layer having the function of the second gate electrode, The first insulating layer, It has a second insulating layer, The oxide semiconductor layer has a region that overlaps with the first conductive layer via the first insulating layer, The oxide semiconductor layer has a region that overlaps with the second conductive layer via the second insulating layer, The first conductive layer has a region that is in contact with the second conductive layer through openings provided in the first insulating layer and the second insulating layer. In a cross-sectional view in the channel width direction, the end of the second conductive layer has a region located outside the end of the oxide semiconductor layer. In a cross-sectional view along the channel length, the end of the second conductive layer has a region located outside the end of the oxide semiconductor layer. Semiconductor equipment.

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