Memory systems and information processing systems

Abstract

To provide a memory system and an information processing system that can verify whether the parity for data recovery is correct or not. [Solution] The memory system according to the embodiment is configured to generate a first parity based on first data stored in a first memory system and second data stored in a second memory system, write it to a non-volatile memory, receive a third data which is update data for the first data from a host, receive the first data from the first memory system, read the first parity from the non-volatile memory, generate a second parity based on the first parity, the first data, and the third data, generate first restored data based on the second parity, the first parity, and the first data, and compare the first restored data with the third data.

Description

Technical Field

[0001] The embodiments described herein generally relate to memory systems and information processing systems.

Background Art

[0002] In recent years, memory systems including non-volatile memories and information processing systems including a host and a plurality of memory systems have been widely spread. As one of such memory systems, a solid state drive (SSD) including a NAND type flash memory is known. The SSD is used as a main storage of various computing devices.

[0003] To improve the fault tolerance of an information processing system, Redundant Arrays of Inexpensive (or Independent) Disks (RAID) may be used. RAID is a technology for storing data in a plurality of memory systems and improving the redundancy and access performance of the stored data. For example, in RAID-5, data and parity for the data are stored in a distributed manner in a plurality of memory systems. An example of parity is an Error Correction Code (ECC). Thereby, for example, even if a memory system in which certain data is stored fails, the data stored in the failed memory system can be restored using other data and parity stored in other memory systems. As another example of RAID, RAID-6 in which two parities for data are stored is known.

[0004] Parity is generated based on data, but if the generated parity is incorrect, the data cannot be restored.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] The object of the present invention is to provide a memory system and an information processing system that can verify whether the parity for data recovery is correct or not. [Means for solving the problem]

[0007] The memory system according to the embodiment includes a host and an interface circuit capable of communicating with a plurality of external memory systems, a non-volatile memory, and a controller. The controller is configured to generate a first parity based on first data stored in a first memory system among the plurality of external memory systems and second data stored in a second memory system among the plurality of external memory systems, write the first parity to the non-volatile memory, receive third data which is update data for the first data from the host via the interface circuit, receive first data from the first memory system via the interface circuit, read the first parity from the non-volatile memory, generate a second parity based on the first parity, the first data, and the third data, generate first restored data based on the second parity, the first parity, and the first data, and compare the first restored data with the third data received from the host. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram illustrating an example of the configuration of an information processing system according to an embodiment. [Figure 2] A block diagram illustrating an example of the configuration of a memory system according to the embodiment. [Figure 3] A diagram illustrating an example of RAID-6 configured with the memory system according to this embodiment. [Figure 4] A diagram illustrating an example of the processing sequence for partial updates according to the embodiment. [Figure 5] A diagram illustrating an example of the processing sequence for full-stripe lights according to the embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. The following description illustrates devices and methods for realizing the technical concept of the embodiments, and the technical concept of the embodiments is not limited to the structure, shape, arrangement, material, etc. of the components described below. Modifications that a person skilled in the art can easily conceive of are naturally included in the scope of disclosure. In order to make the explanation clearer, the size, thickness, planar dimensions, or shape of each element may be schematically represented in the drawings with changes from the actual elements. Multiple drawings may include elements with different dimensional relationships or ratios. In multiple drawings, the same reference numeral may be used for corresponding elements to omit redundant explanations. Some elements may be given multiple names, but these examples of names are merely illustrative and do not preclude the use of other names for these elements. Elements that do not have multiple names may also be given other names. "Connection" may include not only direct connections but also connections via other elements. If the number of elements is not explicitly stated as multiple, the element may be singular or plural.

[0010] (Example of an information processing system configuration) Figure 1 is a diagram illustrating an example of the configuration of an information processing system 1 according to an embodiment. The information processing system 1 includes a host device 2, a plurality of memory systems 3, and a switch 4.

[0011] The host device 2 may be a storage server that stores large amounts of diverse data in multiple memory systems 3, or it may be a server or a personal computer. In this specification, the host device 2 will be referred to as host 2.

[0012] Multiple memory systems 3 constitute RAID-5 or RAID-6. RAID-5, which stores one parity for the data, includes at least three memory systems. RAID-6, which stores two parities for the data, includes at least four memory systems. This specification illustrates the case where multiple memory systems 3 constitute RAID-6. Figure 1 shows a case where the multiple memory systems 3 consist of five memory systems 3-1, 3-2, 3-3, 3-4, and 3-5. In this specification, an unspecified memory system 3 among the multiple memory systems 3 may be referred to as memory system 3.

[0013] Memory system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory. Memory system 3 is also referred to as a storage device. An example of memory system 3 is a solid-state drive (SSD). An example of non-volatile memory is NAND flash memory. Memory system 3 can be used as storage for host 2. Memory system 3 may be built into host 2 or connected to host 2 via cables or a network.

[0014] Switch 4 is a device that interconnects the host 2 and the multiple memory systems 3. Switch 4 includes a control circuit (not shown) that controls communication between the host 2 and the multiple memory systems 3.

[0015] The interface for connecting host 2 and multiple memory systems 3 via switch 4 is PCI Express. TM (PCIe TM ), NVM Express TM (NVMe TMComplies with standards such as. In this specification, the switch 4 is also referred to as the PCIe switch 4.

[0016] The respective configuration examples of the host 2 and the memory system 3 will be described below.

[0017] (Configuration example of host 2) The host 2 may include a central processing unit (CPU) 21 and a random access memory (RAM) 22.

[0018] The CPU 21 is at least one processor. The CPU 21 controls the operations of various components within the host 2. The CPU 21 controls the communication between the host 2 and the memory system 3. The CPU 21 transmits various commands to the memory system 3. Examples of commands transmitted to the memory system 3 include read commands and write commands. The host 2 may include a control circuit (interface), not shown, that controls the communication between the host 2 and the memory system 3. The CPU 21 communicates with the memory system 3 via this control circuit.

[0019] The RAM is a volatile memory, for example. The RAM 22 may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). The storage area of the RAM 22 may be allocated as a buffer area where data is temporarily stored. The buffer area may store data to be written to the memory system 3 and data read from the memory system 3.

[0020] (Configuration example of memory system 3) FIG. 2 is a block diagram for explaining an example of the configuration of the memory system 3 according to the embodiment.

[0021] The memory system 3 may include a non-volatile memory 5, a volatile memory 6, and a controller 7.

[0022] An example of non-volatile memory 5 is NAND flash memory. In this specification, non-volatile memory 5 is referred to as NAND flash memory 5. An example of volatile memory 6 is DRAM or SRAM. In this specification, volatile memory 6 is referred to as DRAM 6.

[0023] The NAND flash memory 5 includes a plurality of blocks BLK0, BLK1, BLK2, ..., BLK(m-1). Each of the plurality of blocks BLK0, BLK1, BLK2, ..., BLK(m-1) includes a plurality of pages PG0, ..., PG(n-1). In this specification, an unspecified block among the plurality of blocks may be referred to as a block BLK. An unspecified page among the plurality of pages may be referred to as a page PG. A block BLK functions as the smallest unit of data erasure operation. A block BLK may also be referred to as an “erasure block” or “physical block”. Each of the plurality of pages PG0, ..., PG(n-1) includes a plurality of memory cells commonly connected to a single word line. A page PG functions as the unit of data write operation and data read operation. A word line may function as the unit of data write operation and data read operation.

[0024] The DRAM 6 may be provided with a firmware storage area, a cache area for the logical / physical address translation table 31, and a buffer area for temporarily storing data.

[0025] The firmware is a program for controlling the operation of the controller 7. The firmware may be loaded from the NAND flash memory 5 into the DRAM 6 when the memory system 3 is started.

[0026] The logical / physical address translation table 31 manages the mapping between each logical address and each physical address of the NAND flash memory 5. A logical address is an address used by the host 2 to address the storage area of ​​the memory system 3. An example of a logical address is a logical block address (LBA).

[0027] Controller 7 functions as a memory controller configured to control the NAND flash memory 5. Controller 7 is configured, for example, as a system-on-a-chip (SoC).

[0028] Data can only be written to one page of the NAND flash memory 5 once per program / erase cycle (P / E cycle). Therefore, the controller 7 writes the update data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous data corresponding to that logical address is stored. The controller 7 invalidates the previous data by updating the logical / physical address translation table 31 to associate this logical address with this different physical memory location. Data referenced by the logical / physical address translation table 31 (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address is called invalid data. Valid data is data that may be requested to be read by the host 2 in the future. Invalid data is data that may no longer be requested to be read by the host 2.

[0029] The controller 7 may include a host interface circuit (host I / F) 11, a NAND interface circuit (NAND I / F) 12, a DRAM interface circuit (DRAM I / F) 13, and a CPU 14. These host I / F 11, NAND I / F 12, DRAM I / F 13, and CPU 14 may be connected via a bus 10.

[0030] The host interface 11 functions as a circuit that receives various commands and data from host 2 via PCIe switch 4. The host interface 11 may also function as a circuit that receives various commands, data, and responses to commands from another memory system 3 via PCIe switch 4. The host interface 11 forwards the received commands, data, and responses to one of the NAND interface 12, DRAM interface 13, and CPU 14.

[0031] The host interface 11 also functions as a circuit that transmits command responses and data to the host 2 via the PCIe switch 4. The host interface 11 may also function as a circuit that transmits commands, data, and command responses to another memory system 3 via the PCIe switch 4. The host interface 11 receives commands, data, and responses to be transmitted from either the NAND interface 12, the DRAM interface 13, or the CPU 14.

[0032] The NAND I / F12 electrically connects the controller 7 and the NAND flash memory 5. The NAND I / F12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0033] The NAND I / F 12 functions as a NAND control circuit configured to control the NAND flash memory 5. The NAND I / F 12 may be connected to multiple memory chips within the NAND flash memory 5 via multiple channels. By driving multiple memory chips in parallel, the access to the NAND flash memory 5 can be made wider bandwidth.

[0034] The DRAM I / F13 functions as a DRAM control circuit configured to control access to DRAM6.

[0035] The CPU 14 is a processor configured to control the host I / F 11, NAND I / F 12, and DRAM I / F 13. The CPU 14 performs various processes by executing firmware loaded from the NAND flash memory 5 into the DRAM 6. The firmware is a control program containing a set of instructions for the CPU 14 to perform various processes. The CPU 14 can perform command processing and other operations to handle various commands from the host 2. The operation of the CPU 14 is controlled by the firmware executed by the CPU 14.

[0036] The functions of each part within the controller 7 may be implemented by dedicated hardware within the controller 7, or by the CPU 14 executing firmware.

[0037] The CPU 14 may function as a command control unit 141, a read control unit 142, an exclusive OR (XOR) calculation unit 143, and a write control unit 144. The CPU 14 may function as each of these units by executing firmware.

[0038] The command control unit 141 receives commands sent from host 2 or another memory system 3. Based on the received commands, the command control unit 141 controls the read control unit 142, the XOR calculation unit 143, and the write control unit 144.

[0039] When the command control unit 141 receives a read command, it instructs the read control unit 142 to read data from the NAND flash memory 5. When the command control unit 141 receives a parity generation command, it instructs the XOR calculation unit 143 to perform an XOR operation on two or more data points. The result of the XOR operation on two or more data points is the parity for those two or more data points. Hereinafter, the result of the XOR operation will be referred to as parity.

[0040] When the command control unit 141 receives a write command, it instructs the write control unit 4 to write data to the NAND flash memory 5.

[0041] The command control unit 141 sends a response to a command to the host 2 or memory system 3 that sent the command. The command control unit 141 may also send the command and data to another memory system 3. The command control unit 141 may also perform a comparison of two or more pieces of data.

[0042] The read control unit 142 reads data from the NAND flash memory 5 in response to instructions from the command control unit 141.

[0043] The XOR calculation unit 143 performs an XOR operation on two or more data points in response to instructions from the command control unit 141 and generates parity.

[0044] The write control unit 144 writes data to the DRAM 6 or NAND flash memory 5 in response to instructions from the command control unit 141.

[0045] (RAID example) Figure 3 is a diagram illustrating an example of RAID-6 configured by a memory system 3 according to the embodiment. In RAID-6, parity is generated for each data of a certain size (referred to as stripe data) among the data stored in the multiple memory systems 3. In RAID-6, two parities, P and Q, are generated. In the example shown in Figure 3, RAID-6 is configured by three memory systems 3-1, 3-2, and 3-3 for data storage, a memory system 3-4 for storing parity P, and a memory system 3-5 for storing parity Q. Memory system 3-1 stores data segment D0. Memory system 3-2 stores data segment D1. Memory system 3-3 stores data segment D2. Host 2 or memory system 3-4 generates parity P from the stripe data containing data segments D0, D1, and D2 stored in memory systems 3-0, 3-1, and 3-2, respectively. Memory system 3-4 stores parity P. Host 2 or memory systems 3-5 generate parity Q from stripe data containing data segments D0, D1, and D2 stored in memory systems 3-0, 3-1, and 3-2, respectively. Memory system 3-5 stores parity Q.

[0046] (Overview of the partial update) Host 2 may write (i.e., overwrite) data of a different value to a logical address range (e.g., LBA range) of a data segment. This overwrite is called a data segment update. This section describes a partial update of data in a data stripe stored in some memory systems of the RAID-6 memory system (here, data segment D2 stored in memory system 3-3). Data segments D0 and D1 are not updated.

[0047] When data segment D2 is updated, parity P and Q are also updated. The pre-update parity Old P is expressed by Equation 1 using data segments D0 and D1 and the pre-update data segment Old D2.

[0048]

number

[0049]

number

[0050] The pre-update parity Old Q is expressed by Equation 3.

[0051]

number

[0052] The updated parity New Q is expressed by Equation 4.

[0053]

number

[0054] Equation 4, which calculates the updated parity New Q, can be transformed as follows.

[0055]

number

[0056]

number

[0057] Similar to equations 5 and 6, in the case of a partial update of data D2, equation 2, which calculates the updated parity New P, is transformed as follows.

[0058]

number

[0059]

number

[0060] As shown in Equations 5 and 6, in the case of a partial update of data segment D2, the updated parity New Q is generated using the intermediate data New Q', the updated data segment New D2, and the coefficient g2. The intermediate data New Q' is generated from the pre-update parity Old Q and the pre-update data segment Old D2.

[0061] As shown in Equations 7 and 8, in the case of a partial update of data segment D2, the updated parity New P is generated using the intermediate data New P' and the updated data segment New D2. The intermediate data New P' is generated from the pre-update parity Old Q and the pre-update data segment Old D2.

[0062] The updated parity values ​​New P and New Q are verified to be correct. If both New P and New Q are verified to be correct, the updated data segment New D2 is written to memory system 3-3, the updated parity New P is written to memory system 3-4, and the updated parity New Q is written to memory system 3-5.

[0063] In the case of a partial update of data segment D2, the logical address ranges of the pre-update data segment Old D2 and the post-update data segment New D2 are the same, but the data values ​​of these data segments are different. Similarly, in the case of a partial update of data segment D0 or D1, the logical address ranges of the pre-update data segments Old D0 and D1 and the post-update data segments New D0 and D1 are the same, but the data values ​​of these data segments are different.

[0064] (Overview of Full Stripe Lights) This describes a full stripe write operation, which updates the entire data stripe stored in all memory systems of a RAID-6 configuration. Data segments D0, D1, and D2 are updated.

[0065] When data segments D0, D1, and D2 are updated, parity P and Q are also updated. The pre-update parity Old P is expressed in Equation 9 using the pre-update data segments Old D0, Old D1, and Old D2.

[0066]

number

[0067] The updated parity New P is expressed in Equation 10 using the updated data segments New D0, New D1, and New D2.

[0068]

number

[0069] The pre-update parity Old Q is expressed by Equation 11.

[0070]

number

[0071] The updated parity New Q is expressed by Equation 12.

[0072]

number

[0073] Equation 12, which calculates the updated parity New Q, can be transformed as follows.

[0074]

number

[0075]

number

[0076] Similar to equations 13 and 14, in the case of full stripe lights, equation 10 for calculating the updated parity New P is transformed as follows.

[0077]

number

[0078]

number

[0079] As shown in Equations 13 and 14, in the case of a full stripe write, the updated parity New Q is generated using the intermediate data New Q'', the updated data segment New D2, and the coefficient g2. The intermediate data New Q'' is generated from the updated data segment New D0, the updated data segment New D1, and the coefficients g0 and g1.

[0080] As shown in Equations 15 and 16, in the case of a full stripe write, the updated parity New P is generated using the intermediate data New P'' and the updated data segment New D2. The intermediate data New P'' is generated from the updated data segment New D0 and the updated data segment New D1.

[0081] In the case of a full stripe write, the validity of the updated parity New P and New Q is verified. If both the updated parity New P and New Q are verified to be valid, the updated data segment New D0 is written to memory system 3-1, New D1 is written to memory system 3-2, New D2 is written to memory system 3-3, the updated parity New P is written to memory system 3-4, and the updated parity New Q is written to memory system 3-5.

[0082] The above explanation concerns the verification of update parity during data updates, but the initial parity generated during the first data write is also verified in the same way. During the first data write, new data segments are written to memory systems 3-1, 3-2, and 3-3, so the explanation of a full stripe write applies.

[0083] (Overview of parity verification) In the case of a partial update, as shown in Equation 5, the updated parity New Q is generated from the intermediate data New Q', the updated data segment New D2, and the coefficient g2. Therefore, as shown in Equation 17, the memory system 3-5 can restore the updated data segment New D2 as the restored data segment Rebuild D2(Q) from the updated parity New Q, the intermediate data New Q', and the coefficient g2.

[0084]

number

[0085] The intermediate data New Q' is generated from the pre-update parity Old Q, the pre-update data segment Old D2, and the coefficient g2, as shown in Equation 6.

[0086] If the restored data segment Rebuild D2(Q), which is reconstructed using Equation 17 from the updated parity New Q, matches the updated data segment New D2, then the updated parity New Q is considered correct.

[0087] In the case of a partial update, as shown in Equation 7, the post-update parity New P is generated from the intermediate data New P' and the post-update data segment New D2. Therefore, as shown in Equation 18, the memory system 3-4 can restore the post-update data segment New D2 as the restored data segment Rebuild D2(P) from the post-update parity New P and the intermediate data New P'.

[0088]

number

[0089] The intermediate data New P' is generated from the pre-update parity Old P and the pre-update data segment Old D2, as shown in Equation 8.

[0090] If the restored data segment Rebuild D2(P), which is reconstructed using Equation 18 from the updated parity New P, matches the updated data segment New D2, then the updated parity New P is judged to be correct.

[0091] The above explanation of partial updates describes the case where data segment D2 is updated. In the case of a partial update in which data segment D0 or D1 is updated, memory system 3-5 can determine whether the updated parity New Q is correct by restoring the updated data segment New D0 or D1 as the restored data segment Rebuild D0(Q) or D1(Q) as shown in Equation 17 and comparing it with the updated data segment New D0 or D1. Similarly, memory system 3-4 can determine whether the updated parity New P is correct by restoring the updated data segment New D0 or D1 as the restored data segment Rebuild D0(P) or D1(P) as shown in Equation 18 and comparing it with the updated data segment New D0 or D1.

[0092] In the case of a full stripe write, the updated parity New Q is generated from the intermediate data New Q'', the updated data segment New D2, and the coefficient g2, as shown in Equation 13. Thus, the memory system 3-5 can restore the updated data segment New D2 as the restored data segment Rebuild D2(Q) from the updated parity New Q'', the intermediate data New Q'', and the coefficient g2, as shown in Equation 19.

[0093]

number

[0094] The intermediate data "New Q" is generated from the updated data segments New D0 and New D1 and the coefficients g0 and g1, as shown in Equation 14.

[0095] If the restored data segment Rebuild D2(Q), which is reconstructed using Equation 17 from the updated parity New Q, matches the updated data segment New D2, then the updated parity New Q is considered correct.

[0096] In the case of a full stripe write, the updated parity New P is generated from the intermediate data New P'' and the updated data segment New D2, as shown in Equation 15. Thus, the memory system 3-4 can restore the updated data segment D2 as the restored data segment Rebuild D2(P) from the updated parity New P and the intermediate data New P'', as shown in Equation 20.

[0097]

number

[0098] The intermediate data "New P" is generated from the updated data segments New D0 and New D1, as shown in Equation 16.

[0099] If the restored data segment Rebuild D2(P), which is reconstructed using the updated parity New P, matches the updated data segment New D2, then the updated parity New P is considered correct.

[0100] In the case of a full stripe write, verification of the post-update parity may be performed by restoring data segment D0 or D1 instead of data segment D2. That is, memory systems 3-5 can determine whether the post-update parity New Q is correct by restoring the updated data segment New D0 or D1 as the restored data segment Rebuild D0(Q) or D1(Q) as shown in Equation 19 and comparing it with the updated data segment New D0 or D1. Similarly, memory systems 3-4 can determine whether the post-update parity New P is correct by restoring the updated data segment New D0 or D1 as the restored data segment Rebuild D0(P) or D1(P) as shown in Equation 20 and comparing it with the updated data segment New D0 or D1.

[0101] (Partial update process) Figure 4 is a diagram illustrating an example of the partial update processing sequence according to the embodiment. Figure 4 shows an example in which data segment D2 stored in memory system 3-3 is updated, while data segments D0 and D1 stored in memory systems 3-1 and 3-2, respectively, are not updated. For the sake of simplicity, the explanation of the generation, verification, and updating of parity P is omitted from Figure 4.

[0102] When updating data segment D2, host 2 sends the updated data segment New D2 to memory system 3-5 for storage in DRAM6 of memory system 3-5 (#12).

[0103] Host 2 sends a read command to memory system 3-3 to read the pre-update data segment Old D2 (#14). This read command includes an instruction to transfer the read pre-update data segment Old D2 to memory system 3-5.

[0104] The read control unit 142 of memory system 3-3 reads the pre-update data segment Old D2 from the NAND flash memory 5. The command control unit 141 of memory system 3-3 sends the pre-update data segment Old D2 to memory system 3-5 for storage in the DRAM 6 of memory system 3-5 (#16). The command control unit 141 of memory system 3-3 sends a read response to host 2 indicating the completion of the read (#18).

[0105] Host 2 sends a read command to memory system 3-5 to read the pre-update parity Old Q (#20). This read command includes an instruction to store the read pre-update parity Old Q in DRAM 6.

[0106] The read control unit 142 of the memory system 3-5 reads the pre-update parity Old Q from the NAND flash memory 5. The read control unit 142 of the memory system 3-5 stores the read pre-update parity Old Q in the DRAM 6. The command control unit 141 of the memory system 3-5 sends a read response (#22) to the host 2 indicating the completion of the read.

[0107] Host 2 sends a command to generate parity Q to memory system 3-5 (#24). The command to generate parity Q specifies the coefficients g0, g1, and g2.

[0108] The XOR calculation unit 143 of the memory system 3-5 generates intermediate data New Q' for generating the updated parity New Q, using the pre-update parity Old Q, the pre-update data segment Old D2, and the coefficient g2, based on equation 6 (#26).

[0109] The XOR calculation unit 143 of the memory system 3-5 generates the updated parity New Q using the intermediate data New Q', the updated data segment New D2, and the coefficient g2 based on equation 5 (#28).

[0110] The XOR calculation unit 143 of the memory system 3-5 generates the reconstructed data segment Rebuild D2(Q) based on equation 17, using the updated parity New Q, the intermediate data New Q', and the coefficient g2 (#30).

[0111] The command control unit 141 of the memory system 3-5 compares the generated restored data segment Rebuild D2(Q) with the updated data segment New D2 (#32). If the two match, the command control unit 141 of the memory system 3-5 determines that the generation of parity Q was successful. If the two do not match, the command control unit 141 of the memory system 3-5 determines that the generation of parity Q was unsuccessful.

[0112] The command control unit 141 of memory system 3-5 sends a parity generation response to host 2 indicating whether the generation of parity Q was successful or unsuccessful (#34). If host 2 receives a response indicating generation failure, it may resend the parity generation command to memory system 3-5, notify the user of an error, or stop writing to memory system 3-3.

[0113] When host 2 receives a response indicating successful generation, it sends a write command to memory system 3-5 to write the updated parity New Q (#36). The write control unit 144 of memory system 3-5 writes the updated parity New Q to the NAND flash memory 5.

[0114] The command control unit 141 of the memory system 3-5 sends a write response to the host 2 (#38) indicating that the write operation is complete.

[0115] Host 2 sends a write command to memory system 3-3 to write the updated data segment New D2 (#40). This write command includes an instruction to receive the updated data segment New D2 from memory system 3-5. The command control unit 141 of memory system 3-3 reads the updated data segment New D2 stored in the DRAM 6 of memory system 3-5. The updated data segment New D2 is sent from memory system 3-5 to memory system 3-3 (#42). The write control unit 144 of memory system 3-3 writes the updated data segment New D2 to the NAND flash memory 5. Alternatively, Host 2 may transfer the updated data segment New D2 to memory system 3-3 along with the write command (#40) to write the updated data segment New D2. In this case, reading the updated data segment New D2 from memory system 3-5 and sending the updated data segment New D2 to memory system 3-3 (#42) is unnecessary.

[0116] The command control unit 141 of the memory system 3-3 sends a write response to the host 2 (#44) indicating that the write operation is complete.

[0117] Host 2 sends parity generation commands to memory systems 3-4 for parity P, just as it does for parity Q, and then verifies and updates it.

[0118] (Processing of full stripe lights) Figure 5 illustrates an example of a full stripe write processing sequence. Figure 5 shows an example where data segments D0, D1, and D2, stored in memory systems 3-1, 3-2, and 3-3 respectively, which constitute the stripe data, are updated. For simplicity, the generation, verification, and updating of parity P are omitted from Figure 5.

[0119] If data segments D0, D1, and D2 are updated, host 2 sends the updated data segments New D0, New D1, and New D2 to memory system 3-5 for storage in DRAM6 of memory system 3-5 (#62, #64, #66).

[0120] Host 2 sends a command to generate parity Q to memory system 3-5 (#68). The command to generate parity Q specifies the coefficients g0, g1, and g2.

[0121] The XOR calculation unit 143 of the memory system 3-5 generates intermediate data New Q'' for generating the updated parity New Q, using the updated data segments New D0 and New D1 and coefficients g0 and g1 based on equation 14 (#70).

[0122] The XOR calculation unit 143 of the memory system 3-5 generates the updated parity New Q using the intermediate data New Q'', the updated data segment New D2, and the coefficient g2 based on equation 13 (#72).

[0123] The XOR calculation unit 143 of the memory system 3-5 generates the reconstructed data segment Rebuild D2(Q) based on equation 19, using the updated parity New Q, the intermediate data New Q'', and the coefficient g2 (#74).

[0124] The command control unit 141 of the memory system 3-5 compares the generated restored data segment Rebuild D2(Q) with the updated data segment New D2 (#76). If the two match, the command control unit 141 of the memory system 3-5 determines that the generation of parity Q was successful. If the two do not match, the command control unit 141 of the memory system 3-5 determines that the generation of parity Q was unsuccessful.

[0125] The command control unit 141 of memory system 3-5 sends a parity generation response to host 2 indicating whether the generation of parity Q was successful or unsuccessful (#78). If host 2 receives a response indicating generation failure, it may resend the parity generation command to memory system 3-5, notify the user of an error, or stop writing to memory systems 3-1, 3-2, and 3-3.

[0126] When host 2 receives a response indicating successful generation, it sends a write command (#80) to memory system 3-5 to write the updated parity New Q. The write control unit 144 of memory system 3-5 writes the updated parity New Q to the NAND flash memory 5.

[0127] The command control unit 141 of the memory system 3-5 sends a write response (#82) to the host 2 indicating that the write operation is complete.

[0128] Host 2 sends write commands to memory systems 3-1, 3-2, and 3-3 respectively to write the updated data segments New D0, New D1, and New D2 (#84, #90, #96). These write commands include instructions to receive the updated data segments New D0, New D1, and New D2 from memory system 3-5, respectively. The command control units 141 of memory systems 3-1, 3-2, and 3-3 read the updated data segments New D0, New D1, and New D2 stored in the DRAM 6 of memory system 3-5, respectively (#86, #92, #98). The write control units 144 of memory systems 3-1, 3-2, and 3-3 write the updated data segments New D0, New D1, and New D2 to the NAND flash memory 5, respectively. Alternatively, host 2 may transfer the updated data segments New D0, New D1, and New D2 to memory systems 3-1, 3-2, and 3-3, respectively, along with write commands (#84, #90, #96) to write the updated data segments New D0, New D1, and New D2. In this case, reading the updated data segments New D0, New D1, and New D2 from memory system 3-5 to memory systems 3-1, 3-2, and 3-3, and sending the updated data segments New D0, New D1, and New D2 to memory systems 3-1, 3-2, and 3-3, respectively (#86, #92, #98) is unnecessary.

[0129] The command control units 141 of memory systems 3-1, 3-2, and 3-3 each send a write response to host 2 indicating the completion of the write operation (#88, #94, #100).

[0130] Host 2 sends generation commands to memory systems 3-4 for parity P, just as it does for parity Q, and then verifies and updates it.

[0131] Figure 5 illustrates an example where three updated data segments are updated sequentially in chronological order. However, the three updated data segments may be updated in parallel and simultaneously.

[0132] The above explanation illustrates the case where multiple memory systems 3 constitute RAID-6, but the same configuration applies when multiple memory systems 3 constitute RAID-5. RAID-5 includes memory systems 3-1, 3-2, and 3-3 for data storage and memory system 3-4 for storing parity P.

[0133] According to at least one embodiment described above, the memory system can verify whether the generated parity was correct or not. This improves the reliability of the information processing system comprising the memory system according to the embodiment.

[0134] According to at least one embodiment described above, the memory system 3-4 or 3-5 includes an interface circuit 11 capable of communicating with the host 2 and a plurality of external memory systems 3-1, 3-2, 3-3, a NAND flash memory 5 as non-volatile memory, and a controller 7. The controller 7 generates a first parity Old Q based on a first data Old D2 stored in the first memory system 3-3 of the plurality of external memory systems and a second data Old D1 stored in the second memory system 3-2 of the plurality of external memory systems, and writes the first parity Old Q to the NAND flash memory 5. In a partial update in which the first data Old D2 is updated to the third data New D2, the controller 7 is configured to receive the third data New D2, which is the update data for the first data Old D2, from the host 2 via the interface circuit 11, receive the first data Old D2 from the first memory system 3-3 via the interface circuit 11, read the first parity Old Q from the NAND flash memory 5, generate the second parity New Q based on the first parity Old Q, the first data Old D2, and the third data New D2, generate the first restored data Rebuild D2(Q) based on the second parity New Q, the first parity Old Q, and the first data Old D2, and compare the first restored data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0135] In a full stripe write operation in which the first data Old D2 is updated to the third data New D2 and the second data Old D1 is updated to the fourth data New D1, the controller 7 is further configured to receive the fourth data New D1, which is the updated data for the second data Old D1, from the host 2 via the interface circuit 11, generate a third parity New Q based on the third data New D2 and the fourth data New D1, generate a second reconstructed data Rebuild D2(Q) based on the third parity New Q and the fourth data New D1, and compare the second reconstructed data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0136] In the initial data write, the controller 7 is further configured to receive first data Old D2 from host 2 via interface circuit 11, receive second data Old D1 from host 2 via interface circuit 11, generate first parity Old Q based on first data Old D2 and second data Old D1, generate third restored data Rebuild D2(Q) based on first parity Old Q and second data Old D1, and compare third restored data Rebuild D2(Q) with first data Old D2 received from host 2.

[0137] According to at least one embodiment described above, the information processing system 1 comprises a host 2 and a plurality of memory systems 3, each including a NAND flash memory 5 as a non-volatile memory and a controller 7 electrically connected to the NAND flash memory 5. The plurality of memory systems 3 include at least a first memory system 3-3, a second memory system 3-2, and a third memory system 3-5. The first controller 7, which is the controller 7 of the first memory system 3-3, is configured to store first data Old D2 in the first NAND flash memory 5, which is the NAND flash memory 5 of the first memory system 3-3. The second controller 7, which is the controller 7 of the second memory system 3-2, is configured to store second data Old D1 in the second NAND flash memory 5, which is the NAND flash memory 5 of the second memory system 3-2. The third controller 7, which is the controller 7 of the third memory system 3-5, generates a first parity Old Q based on the first data Old D2 and the second data Old D1, and stores the first parity Old Q in the third NAND flash memory 5, which is the NAND flash memory 5 of the third memory system 3-5. In a partial update in which the first data Old D2 is updated to the third data New D2, the third controller 7 is configured to receive the third data New D2, which is the update data for the first data Old D2, from the host 2, receive the first data Old D2 from the first controller 7, read the first parity Old Q from the third NAND flash memory 5, generate the second parity New Q based on the first parity Old Q, the first data Old D2, and the third data New D2, generate the first restored data Rebuild D2(Q) based on the second parity New Q, the first parity Old Q, and the first data Old D2, and compare the first restored data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0138] In a full stripe write operation in which the first data Old D2 is updated to the third data New D2 and the second data Old D1 is updated to the fourth data New D1, the third controller 7 of the third memory system 3-5 is further configured to receive the fourth data New D1, which is the update data for the second data Old D1, from the host 2, generate a third parity New Q based on the third data New D2 and the fourth data New D1, generate a second reconstructed data Rebuild D2(Q) based on the third parity New Q and the fourth data New D1, and compare the second reconstructed data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0139] In the initial data write operation, the third controller 7 of the third memory system 3-5 is further configured to receive first data Old D2 from host 2, receive second data Old D1 from host 2, generate first parity Old Q based on first data Old D2 and second data Old D1, generate third restored data Rebuild D2(Q) based on first parity Old Q and second data Old D1, and compare the third restored data Rebuild D2(Q) with first data Old D2 received from host 2.

[0140] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0141] 2…Host, 3…Memory system, 4…Switch, 5…NAND flash memory, 7…Controller, 11…Host I / F, 141…Command control unit, 142…Read control unit, 143…XOR calculation unit, 144…Write control unit

Claims

1. An interface circuit capable of communicating with the host and multiple external memory systems, Non-volatile memory and A first parity is generated based on the first data stored in the first memory system of the plurality of external memory systems and the second data stored in the second memory system of the plurality of external memory systems, and the first parity is written to the non-volatile memory. The interface circuit receives the third data, which is update data for the first data, from the host. The first data is received from the first memory system via the interface circuit. The first parity is read from the non-volatile memory, A second parity is generated based on the first parity, the first data, and the third data. Based on the second parity, the first parity, and the first data, the first reconstructed data is generated. The first restored data is compared with the third data received from the host. A controller configured as follows, A memory system equipped with the following features.

2. The aforementioned controller, The memory system according to claim 1, further configured to write the second parity to the non-volatile memory if the first restored data matches the third data received from the host.

3. The aforementioned controller, If the first restored data and the third data received from the host match, a first response indicating the success of generating the second parity is transmitted to the host via the interface circuit. The memory system according to claim 2, further configured to transmit a second response indicating failure to generate the second parity to the host via the interface circuit if the first restored data and the third data received from the host do not match.

4. The aforementioned controller, The memory system according to claim 1, configured to generate the first parity by calculating the exclusive OR of the first data and the second data.

5. The aforementioned controller, The memory system according to claim 4, configured to generate the second parity by calculating the exclusive OR of the first parity, the first data, and the third data.

6. The aforementioned controller, The interface circuit receives the fourth data, which is update data for the second data, from the host. A third parity is generated based on the third data and the fourth data. Based on the third parity and the fourth data, a second reconstructed data is generated. The memory system according to claim 1, further configured to compare the second restored data with the third data received from the host.

7. The aforementioned controller, The memory system according to claim 6, further configured to write the third parity to the non-volatile memory if the second restored data matches the third data received from the host.

8. The aforementioned controller, If the second restored data matches the third data received from the host, a third response indicating the success of generating the third parity is transmitted to the host via the interface circuit. The memory system according to claim 7, further configured to transmit a fourth response indicating failure to generate the third parity to the host via the interface circuit if the second restored data and the third data received from the host do not match.

9. The aforementioned controller, The first data is received from the host via the interface circuit. The second data is received from the host via the interface circuit. Based on the first data and the second data, the first parity is generated. Based on the first parity and the second data, a third reconstructed data is generated. The memory system according to claim 1, further configured to compare the third restored data with the first data received from the host.

10. The aforementioned controller, The memory system according to claim 1, further configured to transmit the third data received from the host to the first memory system via the interface circuit.

11. 11. A host comprising a plurality of memory systems, each including a non-volatile memory and a controller electrically connected to the non-volatile memory, wherein the plurality of memory systems include at least a first memory system, a second memory system, and a third memory system. The first controller, which is the controller of the first memory system, is configured to store first data in the first non-volatile memory, which is the non-volatile memory of the first memory system. The second controller, which is the controller of the second memory system, is configured to store the second data in the second non-volatile memory, which is the non-volatile memory of the second memory system. The third controller, which is the controller of the third memory system, A first parity is generated based on the first data and the second data. The first parity is stored in the third non-volatile memory, which is the non-volatile memory of the third memory system. The host receives a third data, which is an update data for the first data. The first controller receives the first data, The first parity is read from the third non-volatile memory, A second parity is generated based on the first parity, the first data, and the third data. Based on the second parity, the first parity, and the first data, the first reconstructed data is generated. The first restored data is compared with the third data received from the host. It is configured in such a way. Information processing system.

12. If the third controller finds that the first restored data matches the third data received from the host, it sends a first response to the host indicating the success of generating the second parity. Upon receiving the first response, the host sends a first write command to the third memory system requesting the writing of the second parity. The information processing system according to claim 11, wherein the third controller is further configured to write the second parity to the third non-volatile memory in response to receiving the first write command.

13. The third controller is, The information processing system according to claim 11, further configured to send a second response to the host indicating a failure to generate the second parity if the first restored data and the third data received from the host do not match.

14. The third controller is, The first parity is generated by calculating the exclusive OR of the first data and the second data. The information processing system according to claim 11, configured to generate the second parity by calculating the exclusive OR of the first parity, the first data, and the third data.

15. The third controller is, The host receives the fourth data, which is an update data for the second data. A third parity is generated based on the third data and the fourth data. Based on the third parity and the fourth data, a second reconstructed data is generated. The information processing system according to claim 11, further configured to compare the second restored data with the third data received from the host.

16. If the third controller finds that the second restored data matches the third data received from the host, it sends a third response to the host indicating the success of generating the third parity. Upon receiving the third response, the host sends a second write command to the third memory system requesting the writing of the third parity. The information processing system according to claim 15, wherein the third controller is further configured to write the third parity to the third non-volatile memory in response to receiving the second write command.

17. The third controller is, The host receives the first data, The host receives the second data, Based on the first data and the second data, the first parity is generated. Based on the first parity and the second data, a third reconstructed data is generated. The information processing system according to claim 11, further configured to compare the third restored data with the first data received from the host.

18. The third controller is, The information processing system according to claim 11, further configured to transmit the third data received from the host to the first controller.

19. The aforementioned plurality of memory systems further include a fourth memory system, The fourth controller, which is the controller of the fourth memory system, A fourth parity is generated based on the first data and the second data. The fourth parity is stored in the fourth non-volatile memory, which is the non-volatile memory of the fourth memory system. The host receives the third data, The first controller receives the first data, A fifth parity is generated based on the fourth parity, the first data, and the third data. Based on the fifth parity, the fourth parity, and the first data, a fourth reconstruction data is generated. The information processing system according to claim 11, configured to compare the fourth restored data with the third data received from the host.

20. The fourth controller is, The fourth parity is generated by calculating the exclusive OR of the first data and the second data using coefficients different from those used to generate the first parity. The information processing system according to claim 19, configured to generate the fifth parity by calculating the exclusive OR of the fourth parity, the first data, and the third data using coefficients different from those used to generate the second parity.

Images