Semiconductor equipment

Abstract

In semiconductor devices with small-capacity memory, the goal is to achieve a reasonable balance between area reduction and high speed. [Solution] The semiconductor device comprises multiple read bit lines RBL[i] for transferring read data from multiple latch cells in a latch cell array LCARY, as well as multiple precharge circuits PRE. Each of the multiple latch cells consists of 10 or 12 MOS transistors, including a first CMOS switch for transferring write data and a second CMOS switch for transferring read data. The multiple precharge circuits PRE precharge the multiple read bit lines RBL[i] to an intermediate voltage between the high-potential and low-potential power supply voltages before the second CMOS switch is controlled to turn on.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a memory.

Background Art

[0002] Non-Patent Document 1 shows a SRAM macro including a memory cell composed of 12 transistors. The memory cell is composed of a write port circuit, a latch circuit, and a read port circuit. The write port circuit is composed of a transfer gate composed of 2 transistors. The latch circuit is composed of 6 transistors including two cross-coupled CMOS inverter circuits. The read port circuit is composed of a driver circuit composed of 4 transistors.

[0003] Non-Patent Document 2 shows a SRAM macro including a memory cell composed of 16 transistors. The memory cell is composed of a write port circuit, a latch circuit, and a read port circuit. The write port circuit is composed of a driver circuit composed of 4 transistors. The latch circuit includes two cross-coupled CMOS inverter circuits and is composed of 8 transistors also corresponding to a bit write mask operation. The read port circuit is composed of a driver circuit composed of 4 transistors.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] In recent years, semiconductor devices that handle various AI (Artificial Intelligence) processing, such as image recognition, have become widespread. Such semiconductor devices require the temporary storage of processing data at various points distributed within the device. Therefore, high-speed, relatively small-capacity memory is necessary. Flip-flops and SRAM (Static Random Access Memory) are known examples of such memory.

[0006] In the case of a single-port SRAM, for example, the memory cell can be composed of six transistors. However, SRAM requires peripheral circuits including various circuits such as decoders, sense amplifiers, write assist circuits, and read assist circuits. Therefore, in SRAM, the area per bit increases as the capacity decreases, meaning that the area efficiency decreases. On the other hand, a flip-flop only requires a decoder as peripheral circuitry. However, a flip-flop is composed of two D latches, each consisting of about 20 transistors. Therefore, flip-flops have a large area per bit and are only practically applicable when the capacity is sufficiently small.

[0007] Therefore, a memory that complements SRAM and flip-flops is needed to achieve high speed while improving area efficiency. Specifically, a memory suitable for holding approximately 16 to 64 128-bit data points is required. One such memory is the D-latch macro. A D-latch macro can be composed of a memory cell consisting of 16 transistors, or in other words, a latch cell, as shown in Non-Patent Document 2.

[0008] However, considering cases such as the placement of numerous small-capacity D-latch macros within a semiconductor device, further reduction in the area of ​​the D-latch macros is desirable. On the other hand, reducing the area of ​​the D-latch macros can make it difficult to achieve high speed. For example, to achieve high speed, it is conceivable to use a latch cell that includes a driver circuit, as shown in Non-Patent Document 2. Alternatively, it is conceivable to provide a sense amplifier similar to that in the case of SRAM for the read bit line connected to the latch cell. These methods significantly hinder area reduction. Therefore, a technology is needed that can appropriately balance area reduction and high speed.

[0009] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0010] A semiconductor device according to one embodiment includes a pair of write selection lines activated during a write operation, a pair of read selection lines activated during a read operation, and a plurality of latch cells connected thereto. The semiconductor device also includes a plurality of read bit lines for transferring read data from the plurality of latch cells, and a plurality of write bit lines for transferring write data to the plurality of latch cells. Furthermore, the semiconductor device includes a plurality of precharge circuits connected to the plurality of read bit lines. Each of the plurality of latch cells includes first and second storage nodes, first, second, third, fourth, and fifth nMOS transistors, and first, second, third, fourth, and fifth pMOS transistors. The first and second storage nodes store complementary data. The first nMOS transistor is connected between the first storage node and the first intermediate node, with its gate connected to the second storage node. The second nMOS transistor is connected between the second storage node and the low-potential power supply node, with its gate connected to the first storage node. A third nMOS transistor is connected between the first intermediate node and the low-potential power supply node and is controlled by a pair of write select lines. The first, second, and third pMOS transistors are provided between the high-potential power supply node and the first, second, and third nMOS transistors in the same manner as the first, second, and third nMOS transistors. A fourth nMOS transistor and a fourth pMOS transistor constitute a first CMOS switch controlled by a pair of write select lines, which, when controlled to be ON, connects a predetermined write bit line to the first storage node. A fifth nMOS transistor and a fifth pMOS transistor constitute a second CMOS switch controlled by a pair of read select lines, which, when controlled to be ON, connects a predetermined read bit line to the second storage node. Multiple precharge circuits precharge multiple read bit lines to an intermediate voltage between the high-potential and low-potential power supply voltages before the second CMOS switch is controlled to be ON. [Effects of the Invention]

[0011] According to the above embodiment, a semiconductor device having a small-capacity memory can achieve a reasonable balance between area reduction and high speed. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a schematic diagram showing an example of the configuration of a semiconductor device according to one embodiment. [Figure 2] Figure 2 is a schematic diagram showing an example of the configuration of the main peripheral circuits in the memory shown in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing an example of the latch cell configuration in Figure 1. [Figure 4] Figure 4 is a schematic diagram showing an example of the operation of the pre-charge circuit in Figure 2. [Figure 5A] Figure 5A is a timing chart showing an example of a write operation using the latch cell shown in Figure 3. [Figure 5B] Figure 5B is a schematic diagram that provides supplementary explanation for the operation shown in Figure 5A. [Figure 6A] Figure 6A is a timing chart showing an example of a read operation using the latch cell shown in Figure 3. [Figure 6B] Figure 6B is a schematic diagram that provides supplementary explanation to the operation shown in Figure 6A. [Figure 7A] Figure 7A is a timing chart showing an example of bit write mask operation using the latch cell shown in Figure 3. [Figure 7B] Figure 7B is a schematic diagram that provides supplementary explanation to the operation shown in Figure 7A. [Figure 8] Figure 8 is a circuit diagram showing a more detailed example of the data input / output circuit in Figure 1. [Figure 9] Figure 9 is a schematic diagram showing an example of the operation of the pre-charge circuit in Figure 8. [Figure 10] Figure 10 is a circuit diagram showing an example of a latch cell configuration for comparison purposes. [Modes for carrying out the invention]

[0013] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a partial or entire modification, detail, supplementary explanation, etc. of the other. Also, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number. That is, the number of elements may be more than or less than the specific number.

[0014] Also, in the embodiments, the constituent elements (including element steps) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of the constituent elements, etc., unless otherwise specified or clearly considered not to be so in principle, it includes those substantially approximate or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0015] Also, in the embodiments, a MOSFET (MOS Field Effect Transistor) is referred to as a MOS transistor. A p-channel type MOSFET and an n-channel type MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively. In the embodiments, for simplicity of explanation, a MOS transistor using an oxide film as the gate insulating film will be used for the explanation. However, the gate insulating film is not necessarily limited to an oxide film.

[0016] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated description thereof will be omitted.

[0017] <Schematic of Semiconductor Device> Figure 1 is a schematic diagram showing an example configuration of a semiconductor device according to one embodiment. Figure 2 is a schematic diagram showing an example configuration of the main peripheral circuit in the memory MEM shown in Figure 1. The semiconductor device according to one embodiment includes at least a memory MEM as shown in Figure 1. The memory MEM is, for example, a D latch macro composed of hard macros. The semiconductor device includes, for example, various logic circuits that are responsible for various AI processing. In this case, the semiconductor device may have memory MEMs as shown in Figure 1 distributed and mounted in various locations within the device in order to temporarily store the processing data of the various logic circuits.

[0018] The memory MEM shown in Figure 1 comprises a latch cell array LCARY, a memory control circuit CTRL, a word driver circuit WD, and a data input / output circuit IOC. The memory control circuit CTRL, the word driver circuit WD, and the data input / output circuit IOC are peripheral circuits of the latch cell array LCARY. The latch cell array LCARY comprises "N (=n+1)*M (=m+1)" latch cells LC[0,0]-LC[n,m] arranged in a matrix. In this specification, multiple latch cells LC[0,0]-LC[n,m] are collectively referred to as latch cells LC.

[0019] The memory control circuit CTRL controls the entire memory MEM. As shown in Figure 2, the memory control circuit CTRL mainly comprises a clock generation circuit CKG and an address decoder ADEC. The clock generation circuit CKG receives inputs from outside the memory MEM, such as a clock signal CLK, a chip enable signal CEN, and a write enable signal WEN. Based on these input signals, the clock generation circuit CKG outputs a write decode instruction signal DECW or a read decode instruction signal DECR to the address decoder ADEC. The clock generation circuit CKG also outputs a write enable signal WTEN or a read enable signal RDEN to the data input / output circuit IOC.

[0020] The address decoder ADEC receives an address signal ADR from outside the memory MEM. In response to the write decode instruction signal DECW, the address decoder ADEC activates one write word line WWLN[k] based on the address signal ADR. This write word line WWLN[k] is one of the N write word lines WWLN[n:0] shown in Figure 1. Similarly, in response to the read decode instruction signal DECR, the address decoder ADEC activates one read word line RWLN[k] based on the address signal ADR. This read word line RWLN[k] is one of the N read word lines RWLN[n:0] shown in Figure 1.

[0021] The word driver circuit WD drives a pair, specifically N pairs, of complementary signal lines, called read selection lines RCP[n:0] and RCPN[n:0], as shown in Figure 1. The N read selection lines RCP[n:0] are the non-inverting signal lines. In this specification, these N read selection lines RCP[n:0] are collectively referred to as the non-inverting read selection lines RCP, or simply as read selection lines RCP. On the other hand, the remaining N read selection lines RCPN[n:0] are the inverting signal lines. In this specification, these N read selection lines RCPN[n:0] are collectively referred to as the inverting read selection lines RCPN, or simply as read selection lines RCPN.

[0022] Furthermore, the word driver circuit WD drives a pair, specifically N pairs, of complementary signal lines, namely the write selection lines WCP[n:0] and WCPN[n:0]. The N write selection lines WCP[n:0] are the non-inverting signal lines. In this specification, these N write selection lines WCP[n:0] are collectively referred to as the non-inverting write selection lines WCP, or simply as the write selection lines WCP. On the other hand, the remaining N write selection lines WCPN[n:0] are the inverting signal lines. In this specification, these N write selection lines WCPN[n:0] are collectively referred to as the inverting write selection lines WCPN, or simply as the write selection lines WCPN.

[0023] As shown in Figure 2, the word driver circuit WD receives the signal from each read word line RWLN[k] and drives each inverted read selection line RCPN[k]. The word driver circuit WD also drives each non-inverted read selection line RCP[k] by inverting the signal from each read word line RWLN[k]. Similarly, the word driver circuit WD receives the signal from each write word line WWLN[k] and drives each inverted write selection line WCPN[k]. The word driver circuit WD also drives each non-inverted write selection line WCP[k] by inverting the signal from each write word line WWLN[k].

[0024] The data input / output circuit (IOC) controls the input and output of data to and from the memory (MEM) and its external environment. Specifically, the data input / output circuit (IOC) primarily comprises a write latch circuit (DLT) and a write driver (WDV) as its write circuit. The data input / output circuit (IOC) primarily comprises a read switch (RSW) and a read latch circuit (QLT) as its read circuit. Furthermore, although details will be described later, the data input / output circuit (IOC) also comprises a precharge circuit (PRE) as its read circuit.

[0025] First, during a write operation, the data input / output circuit IOC receives M-bit input data D[m:0] from outside the memory MEM, as shown in Figure 1. The write latch circuit DLT latches the M-bit input data D[m:0] as write data in accordance with the write enable signal WTEN. The write driver WDV transfers the latched M-bit write data to the latch cell array LCARY via M inverted write bit lines WBLN[m:0].

[0026] The M bits of write data transferred from the write driver WDV are written to M latch cells LC connected to the activated write selection line WCP. In this specification, the inverted write bit lines WBLN[m:0] of these M lines are collectively referred to as the inverted write bit lines WBLN, or simply the write bit lines WBLN.

[0027] On the other hand, during a read operation, the data input / output circuit IOC receives the read data from M latch cells LC via M non-inverting read bit lines RBL[m:0]. These M latch cells LC are cells connected to the activated read selection line RCP. In this specification, these M non-inverting read bit lines RBL[m:0] are collectively referred to as non-inverting read bit lines RBL, or simply read bit lines RBL.

[0028] The read latch circuit QLT receives and latches read data from M latch cells LC via the read switch RSW in response to the read enable signal RDEN. In other words, unlike a typical SRAM, the read latch circuit QLT receives and latches read data without going through a sense amplifier. The read latch circuit QLT then outputs the M-bit read data to the outside as the M-bit output data Q[m:0].

[0029] Furthermore, as shown in Figure 1, the data input / output circuit IOC also receives an M-bit bit write mask signal BWM[m:0] from outside the memory MEM. The bit write mask signal BWM[m:0] is used to mask some bits of the M-bit input data D[m:0] during the write operation. This eliminates the need for, for example, read-modify-write operations.

[0030] During bit write mask operation, the write driver WDV shown in Figure 2 outputs a high impedance to the write bit line WBLN[k] of the bit to be masked. As a result, the latch cell LC connected to the write bit line WBLN[k] can maintain the data it currently stores regardless of the write operation.

[0031] Furthermore, during bit write mask operation, the data input / output circuit IOC drives a pair of complementary signal lines, specifically M pairs of bit write mask selection lines BW[m:0] and BWB[m:0]. As will be described in detail later, by driving these selection lines, the latch cell LC can maintain the data it currently stores. In this specification, the M inverted bit write mask selection lines BWB[m:0] are collectively referred to as the inverted bit write mask selection line BWB, or simply the bit write mask selection line BWB. Similarly, the M non-inverted bit write mask selection lines BW[m:0] are collectively referred to as the non-inverted bit write mask selection line BW, or simply the bit write mask selection line BW.

[0032] In Figure 1, the value of M (=m+1), which represents the bit width, is, for example, 128, 256, 512, or 1024. The value of N (=n+1), which represents the word line count, is, for example, 16, 32, or 64. Generally, within this range of memory capacity, the D-latch macro can be advantageous compared to flip-flops and SRAM in terms of area efficiency. The D-latch macro can also be described as a macro whose area ratio between data storage area and peripheral circuit area is intermediate between that of flip-flops and SRAM.

[0033] For example, SRAM may include a number of sense amplifiers and various assist circuits within its data input / output circuit (IOC) corresponding to the bit width. Therefore, as the bit width increases, the area ratio of the data input / output circuit (IOC) increases. On the other hand, D-latch macros do not require such sense amplifiers or assist circuits. Consequently, the area ratio of the data input / output circuit (IOC) does not increase significantly even as the bit width increases. As a result, D-latch macros can improve area efficiency even with larger bit widths.

[0034] Note that Figure 1 shows an example where memory MEM is a single-port memory. However, memory MEM may be a two-port memory that can perform read and write operations independently. In this case, memory MEM receives read address signals and write address signals from an external source. Accordingly, the read selection line RCP and the write selection line WCP may be activated simultaneously.

[0035] <Configuration of a latch cell (embodiment)> Figure 3 is a circuit diagram showing an example configuration of the latch cell LC in Figure 1. The latch cell LC shown in Figure 3 comprises a write port circuit WTC, a latch circuit LT, and a read port circuit RDC. The latch cell LC also includes an inverting storage node (first storage node) SNb and a non-inverting storage node (second storage node) SNt that store complementary data.

[0036] The latch circuit LT comprises four nMOS transistors MN1-MN3, MN6 and four pMOS transistors MP1-MP3, MP6. The pMOS transistor (first pMOS transistor) MP1 and the nMOS transistor (first nMOS transistor) MN1 constitute a first inverter circuit. This first inverter circuit performs signal inversion using the non-inverting memory node SNt and the inverting memory node SNb as input and output.

[0037] The pMOS transistor (second pMOS transistor) MP2 and the nMOS transistor (second nMOS transistor) MN2 constitute a second inverter circuit. This second inverter circuit performs signal inversion using the inverting memory node SNb and the non-inverting memory node SNt as input and output.

[0038] The pMOS transistor (third pMOS transistor) MP3 is connected between the first inverter circuit and the high-potential power supply node Nvd. The nMOS transistor (third nMOS transistor) MN3 is connected between the first inverter circuit and the low-potential power supply node Nvs. The high-potential power supply node Nvd is supplied with the high-potential power supply voltage VDD. The low-potential power supply node Nvs is supplied with the low-potential power supply voltage VSS.

[0039] Furthermore, the pMOS transistor (the sixth pMOS transistor) MP6 is connected in parallel with the pMOS transistor MP3. The nMOS transistor (the sixth nMOS transistor) MN6 is connected in parallel with the nMOS transistor MN3. As will be explained in detail later, the pMOS transistor MP6 and the nMOS transistor MN6 are provided to implement the bit write mask function. Therefore, the pMOS transistor MP6 and the nMOS transistor MN6 can be omitted if the bit write mask function is not required.

[0040] The write port circuit (WTC) consists of a pMOS transistor (the fourth pMOS transistor) MP4 and an nMOS transistor (the fourth nMOS transistor) MN4. The pMOS transistor MP4 and the nMOS transistor MN4 constitute a CMOS (Complementary MOS) switch (the first CMOS switch) CSW1, in other words, a transfer gate. When controlled to be ON, the CMOS switch CSW1 transfers the write data to the inverting memory node SNb.

[0041] On the other hand, the read port circuit RDC consists of a pMOS transistor (the fifth pMOS transistor) MP5 and an nMOS transistor (the fifth nMOS transistor) MN5. The pMOS transistor MP4 and the nMOS transistor MN4 constitute a CMOS switch (the second CMOS switch) CSW2, in other words, a transfer gate. When controlled to be ON, the CMOS switch CSW2 transfers read data from the non-inverting memory node SNt.

[0042] Here, the latch cell LC shown in Figure 3 is connected, more specifically, to eight signal lines (WCP, WCPN, RCP, RCPN, BW, BWB, WBLN, RBL) as described in Figures 1 and 2. A pair of write selection lines WCP and WCPN are activated during write operations. A pair of read selection lines RCP and RCPN are activated during read operations. The read bit line RBL transfers read data from the latch cell LC. The write bit line WBLN transfers write data to the latch cell LC.

[0043] The pair of bit write mask selection lines BW and BWB are activated when performing a bit write mask operation. Specifically, the pair of bit write mask selection lines BW and BWB are activated when performing a high-impedance write operation on any of the multiple latch cells LC. In other words, these signal lines are activated to maintain data stored in any of the multiple latch cells regardless of the write operation.

[0044] The nMOS transistor (first nMOS transistor) MN1 is connected between the inverting memory node SNb and the intermediate node (first intermediate node) ND1. The gate of nMOS transistor MN1 is connected to the non-inverting memory node SNt. The nMOS transistor (second nMOS transistor) MN2 is connected between the non-inverting memory node SNt and the low-potential power supply node Nvs. The gate of nMOS transistor MN2 is connected to the inverting memory node SNb. The nMOS transistor (third nMOS transistor) MN3 is connected between the intermediate node ND1 and the low-potential power supply node Nvs. The gate of nMOS transistor MN3 is connected to the inverting write selection line WCPN.

[0045] The first pMOS transistor MP1 is connected between the inverting memory node SNb and the intermediate node (second intermediate node) ND2. The gate of pMOS transistor MP1 is connected to the non-inverting memory node SNt. The second pMOS transistor MP2 is connected between the non-inverting memory node SNt and the high-potential power supply node Nvd. The gate of pMOS transistor MP2 is connected to the inverting memory node SNb. The third pMOS transistor MP3 is connected between the intermediate node ND2 and the high-potential power supply node Nvd. The gate of pMOS transistor MP3 is connected to the non-inverting write selection line WCP.

[0046] The nMOS transistor (fourth nMOS transistor) MN4 and the pMOS transistor (fourth pMOS transistor) MP4 are connected in parallel between the write bit line WBLN and the inverting memory node SNb. The gate of the nMOS transistor MN4 is connected to the non-inverting write selection line WCP. The gate of the pMOS transistor MP4 is connected to the inverting write selection line WCPN. Thus, the CMOS switch CSW1 is controlled by the pair of write selection lines WCP,WCPN.

[0047] The nMOS transistor (the fifth nMOS transistor) MN5 and the pMOS transistor (the fifth pMOS transistor) MP5 are connected in parallel between the read bit line RBL and the non-inverting memory node SNt. The gate of the nMOS transistor MN5 is connected to the non-inverting read selection line RCP. The gate of the pMOS transistor MP5 is connected to the inverting read selection line RCPN. Thus, the CMOS switch CSW2 is controlled by the pair of read selection lines RCP,RCPN.

[0048] The nMOS transistor (the sixth nMOS transistor) MN6 is connected between the intermediate node ND1 and the low-potential power supply node Nvs. The gate of nMOS transistor MN6 is connected to the non-inverting bit write mask selection line BW. The pMOS transistor (the sixth pMOS transistor) MP6 is connected between the intermediate node ND2 and the high-potential power supply node Nvd. The gate of pMOS transistor MP6 is connected to the inverting bit write mask selection line BWB. Thus, nMOS transistor MN6 and pMOS transistor MP6 are controlled by a pair of bit write mask selection lines BW,BWB.

[0049] <Regarding the memory used as a comparative example> Figure 10 is a circuit diagram showing an example configuration of a comparative latch cell LCx. The comparative latch cell LCx differs from the configuration example shown in Figure 3 in the configuration of the write port circuit WTC and the read port circuit RDC. The write port circuit WTC shown in Figure 10 consists of a driver circuit consisting of two pMOS transistors MP7 and MP8 and two nMOS transistors MN7 and MN8. The read port circuit RDC consists of a driver circuit consisting of a pMOS transistor MP9 and an nMOS transistor MN9, and a transfer gate. The transfer gate consists of a pMOS transistor MP5 and an nMOS transistor MN5, as in the case of Figure 3.

[0050] As shown above, the comparative latch cell LCx consists of a total of 16 transistors. On the other hand, the latch cell LC shown in Figure 3 consists of a total of 12 transistors, or 10 transistors if the bit write mask function is not required. As a result, area reduction can be achieved in semiconductor devices with small capacity memory. More specifically, area reduction of the semiconductor device can be achieved by using the D latch macro itself. In addition, by reducing the number of transistors in the latch cell LC, the area of ​​the D latch macro itself can be reduced, further reducing the area of ​​the semiconductor device. In particular, even when D latch macros are distributed throughout the semiconductor device, the increase in area can be suppressed.

[0051] However, as shown in Figure 3, if the read port circuit RDC is composed only of a transfer gate, it may become difficult to increase the speed of the memory, and more specifically, to shorten the read access time. To explain in more detail, first, the read bit line RBL shown in Figure 3 is driven to either the "H" level or the "L" level depending on the read data. Then, the read bit line RBL maintains the "H" level or "L" level by parasitic capacitance for the period until the next read operation is performed.

[0052] Consequently, the latch cell LC shown in Figure 3 may drive the read bit line RBL, which is holding an "H" level, to an "L" level during read operation. This "L" level needs to be sufficiently close to the low-potential power supply voltage VSS in order to confirm the input data to the read latch circuit QLT shown in Figure 2. Similarly, the latch cell LC may drive the read bit line RBL, which is holding an "L" level, to an "H" level. This "H" level needs to be sufficiently close to the high-potential power supply voltage VDD.

[0053] Unlike the case in Figure 10, the latch cell LC shown in Figure 3 does not have a driver circuit (MP9, MN9) within the read port circuit RDC. Therefore, the transition from the "H" level to the "L" level, or from the "L" level to the "H" level of the read bit line RBL, may take time. As a result, the read access time becomes longer, which may make it difficult to speed up the memory MEM.

[0054] On the other hand, to speed up the memory MEM, for example, in the data input / output circuit IOC shown in Figure 2, a sense amplifier similar to that in the case of SRAM can be provided before the read latch circuit QLT. In this case, the sense amplifier can be activated when the voltage of the read bit line RBL approaches the high-potential power supply voltage VDD or the low-potential power supply voltage VSS to some extent. Then, after activating the sense amplifier, the read latch circuit QLT can perform latching with almost no delay. However, sense amplifiers generally require a large circuit area. As a result, it may be difficult to reduce the memory area. Therefore, the pre-charge circuit PRE shown in Figure 2 is provided.

[0055] <Overview of the pre-charge circuit> The precharge circuit PRE shown in Figure 2 is connected to each of the M read bit lines RBL[m:0] shown in Figure 1. Each precharge circuit PRE precharges the read bit line RBL to an intermediate voltage VM before the CMOS switch CSW2 shown in Figure 3 is controlled to turn ON. Specifically, each precharge circuit PRE maintains the read bit line RBL at the intermediate voltage VM, for example, during the period when the CMOS switch CSW2 is OFF. The intermediate voltage VM is a voltage that has an intermediate value between the high-potential supply voltage VDD and the low-potential supply voltage VSS, for example, if "VSS = 0V", then "VM = VDD / 2".

[0056] Figure 4 is a schematic diagram showing an example of operation of the pre-charge circuit PRE in Figure 2. For comparison, an example of operation without the pre-charge circuit PRE is also shown. In Figure 4, without the pre-charge circuit PRE, the latch cell LC had to drive the read bit line RBL, which was holding at the VDD level, up to the VSS level. Alternatively, the latch cell LC had to drive the read bit line RBL, which was holding at the VSS level, up to the VDD level. As a result, the read transition time Tf1 to the "L" level and the read transition time Tr1 to the "H" level of the read bit line RBL could become longer.

[0057] On the other hand, with the pre-charge circuit PRE, the latch cell LC only needs to drive the read bit line RBL, which holds an intermediate voltage VM (in this case, "VM = VDD / 2"), up to the VSS level. Alternatively, the latch cell LC only needs to drive the read bit line RBL, which holds the VM level, up to the VDD level. This shortens the read transition time Tf2 to the "L" level and the read transition time Tr2 to the "H" level of the read bit line RBL. Ideally, with the pre-charge circuit PRE, the read transition time can be halved compared to when the pre-charge circuit PRE is not present.

[0058] This reduces read access time and speeds up the memory MEM. Furthermore, although a detailed configuration example will be described later, the pre-charge circuit PRE can be implemented in a smaller area than the sense amplifier. Therefore, the area overhead associated with the increased speed of the memory MEM can also be suppressed. In other words, by using the memory MEM according to one embodiment, a reasonable balance between area reduction and high speed can be achieved. Note that the intermediate voltage VM is not necessarily limited to "VM = VDD / 2"; it should be lower than the high-potential power supply voltage VDD and higher than the low-power supply voltage VSS. For example, if there is a difference between the rising and falling transition times of a signal, an offset in the direction of canceling this difference may be added to the intermediate voltage VM.

[0059] <Operation of a latch cell> [Writing operation] Figure 5A is a timing chart showing an example of a write operation using the latch cell LC shown in Figure 3. Figure 5B is a schematic diagram to supplement the operation shown in Figure 5A. Figure 5B shows the state of each signal line and the on / off state of each transistor in the latch cell LC during the write period. In Figure 5A, the write period Twt is the period from time t1 to time t2, which is one period of the clock signal CLK.

[0060] During the write period Twt, the read selection line RCP is inactive, specifically at the "L" level. Therefore, the pMOS transistor MP5 and nMOS transistor MN5 are in the off state. Additionally, an intermediate voltage VM is applied to the read bit line RBL by the precharge circuit PRE.

[0061] Meanwhile, the write selection line WCP transitions from an inactive state to an active state, specifically from the "L" level to the "H" level. Consequently, pMOS transistor MP4 and nMOS transistor MN4 switch from the off state to the on state. Also, pMOS transistor MP3 and nMOS transistor MN3 switch from the on state to the off state. Since no bit write mask operation is performed here, the bit write mask selection line BW transitions from an active state to an inactive state, specifically from the "H" level to the "L" level. Consequently, pMOS transistor MP6 and nMOS transistor MN6 switch from the on state to the off state.

[0062] In this state, let's consider a case where the inverted memory node SNb is rewritten from the "L" level to the "H" level. The write bit line, specifically the inverted write bit line WBLN, is at the "H" level at time t1. The ON state pMOS transistor MP4 and nMOS transistor MN4 transfer this "H" level to the "L" level memory node SNb.

[0063] In this process, the write bit line WBLN is driven by the write driver WDV shown in Figure 2. Meanwhile, the power supply voltage VSS to the nMOS transistor MN1 is cut off. As a result, the inverting memory node SNb can be rewritten to the "H" level. Furthermore, by inputting this "H" level, the nMOS transistor MN2 can rewrite the non-inverting memory node SNt from the "H" level to the "L" level.

[0064] Subsequently, the write selection line WCP transitions from the active state to the inactive state. The bit write mask selection line BW transitions from the inactive state to the active state. Consequently, the pMOS transistor MP4 and the nMOS transistor MN4 switch from the on state to the off state. The two pMOS transistors MP3 and MP6 and the two nMOS transistors MN3 and MN6 switch from the off state to the on state. This completes the write operation.

[0065] [Read operation] Figure 6A is a timing chart showing an example of readout operation using the latch cell LC shown in Figure 3. Figure 6B is a schematic diagram to supplement the operation shown in Figure 6A. Figure 6B shows the state of each signal line in the latch cell LC and the on / off state of each transistor during the readout period. In Figure 6A, the readout period Trd is the period from time t3 to time t4, which is one period of the clock signal CLK.

[0066] During the read period Trd, the write selection line WCP is inactive, at the "L" level. Therefore, pMOS transistor MP4 and nMOS transistor MN4 are in the off state. pMOS transistor MP3 and nMOS transistor MN3 are in the on state. Also, the bit write mask selection line BW is active, at the "H" level. Therefore, pMOS transistor MP6 and nMOS transistor MN6 are in the on state.

[0067] Meanwhile, the read selection line RCP transitions from an inactive state to an active state, in this case from the "L" level to the "H" level. Consequently, the pMOS transistor MP5 and the nMOS transistor MN5 switch from the off state to the on state. The read enable signal RDEN, shown in Figure 2, also transitions in a similar manner to the read selection line RCP. In this case, the read latch circuit QLT outputs the read data input during the "H" level period of the read enable signal RDEN. Then, during the "L" level period of the read enable signal RDEN, the read data at the falling edge of the read enable signal RDEN is latched and output.

[0068] In this state, let's consider the case where we read out the non-inverting storage node SNt, which is storing the "L" level. The read bit line RBL is at the voltage level of the intermediate voltage VM at time t3. The ON state pMOS transistor MP5 and nMOS transistor MN5 connect the non-inverting storage node SNt to the read bit line RBL, which has the VM level.

[0069] During this time, the voltage level of the non-inverting memory node SNt may temporarily rise slightly from the "L" level. Accordingly, the voltage level of the inverting memory node SNb may also temporarily fall slightly from the "H" level. Furthermore, during the ON state of the pMOS transistor MP5 and the nMOS transistor MN5, the precharge circuit PRE is disconnected from the read bit line RBL.

[0070] Subsequently, the read selection line RCP transitions from the active state to the inactive state. Consequently, the pMOS transistor MP5 and the nMOS transistor MN5 switch from the on state to the off state. This completes the read operation. Furthermore, once the read operation is complete, the precharge circuit PRE precharges the read bit line RBL again to the intermediate voltage VM. Here, the time from time t3 until the read bit line RBL reaches the VSS level is the read access time tAC. As shown in Figure 4, shortening the read transition time Tf2 can also shorten the read access time tAC.

[0071] [Bitlight mask operation] Figure 7A is a timing chart showing an example of bit write mask operation using the latch cell LC shown in Figure 3. Figure 7B is a schematic diagram to supplement the operation shown in Figure 7A. Figure 7B shows the state of each signal line in the latch cell LC and the on / off state of each transistor during the bit write mask period. In Figure 7A, the period from time t5 to time t6, which is one period of the clock signal CLK, is the bit write mask period Tbwm.

[0072] The state of the bit write mask selection line BW differs between the bit write mask period Tbwm and the write period Twt shown in Figure 5A. Specifically, during the bit write mask period Tbwm, the bit write mask selection line BW is in the active state, in this case at the "H" level. Consequently, the pMOS transistor MP6 and the nMOS transistor MN6 are in the ON state. As a result, the inverting memory node SNb is driven by either the high-potential power supply voltage VDD or the low-potential power supply voltage VSS, unlike in the case of Figure 5A.

[0073] In this state, let's assume, for example, that the inverting memory node SNb is storing a "H" level. As described in Figures 1 and 2, the write bit line WBLN is high impedance during the bit write mask period Tbwm. That is, the voltage level of the write bit line WBLN is undefined. The ON state pMOS transistor MP4 and nMOS transistor MN4 connect the write bit line WBLN, which has an undefined voltage level, to the inverting memory node SNb.

[0074] In this case, if the write bit line WBLN is at the "L" level, the voltage level of the inverting memory node SNb may temporarily drop slightly from the "H" level. Accordingly, the voltage level of the non-inverting memory node SNt may also temporarily rise slightly from the "L" level. However, since each memory node SNb and SNt is driven by the high-potential power supply voltage VDD or the low-potential power supply voltage VSS, their original voltage levels can be maintained. As a result, the inverting memory node SNb can maintain the "H" level regardless of the write operation.

[0075] <Details of the data input / output circuit> Figure 8 is a circuit diagram showing a more detailed configuration example of the data input / output circuit IOC in Figure 1. The data input / output circuit IOC shown in Figure 8 comprises a write circuit WCT and a read circuit RCT. The write circuit WTCT comprises a bit write mask latch circuit BWMLT and a NOR gate NR, in addition to the write latch circuit DLT and write driver WDV shown in Figure 2. As described in Figure 2, the write latch circuit DLT latches the input data D[i] as write data in accordance with the write enable signal WTEN. The write driver WDV drives the write bit line WBLN[i] based on the latched write data.

[0076] On the other hand, the bit write mask latch circuit BWMLT latches the external bit write mask signal BWM[i] in accordance with the write enable signal WTEN. The bit write mask latch circuit BWMLT then outputs the bit write mask enable signal BWE, which is the result of the latch. For example, if the bit write mask signal BWM[i] is at the "H" level, i.e., the assert level, then the bit write mask enable signal BWE will also be at the "H" level.

[0077] Here, the write driver WDV is a tristate circuit controlled by the bit write mask enable signal BWE. When the bit write mask enable signal BWE is at the "H" level, the write driver WDV outputs a high impedance to the write bit line WBLN[i]. On the other hand, when the bit write mask enable signal BWE is at the "L" level, the write driver WDV drives the write bit line WBLN[i] based on the write data from the write latch circuit DLT.

[0078] The NOR gate NR takes the inverted write enable signal WTENB (the inverted signal of the write enable signal WTEN) and the bit write mask enable signal BWE as inputs and performs a NOR operation. The NOR gate NR then outputs the signal obtained by the NOR operation to the inverted bit write mask selection line BWB[i]. The NOR gate NR also outputs the signal obtained by the NOR operation to the non-inverted bit write mask selection line BW[i] via an inverter circuit.

[0079] For example, when the write enable signal WTEN is at the "L" level, i.e., in non-write operation, the inverting bit write mask select line BWB[i] is fixed at the "L" level. On the other hand, when the write enable signal WTEN is at the "H" level, the voltage level of the inverting bit write mask select line BWB[i] is controlled based on the bit write mask enable signal BWE. That is, the voltage level of the inverting bit write mask select line BWB[i] is controlled to the "L" / "H" level when the bit write mask enable signal BWE is at the "H" / "L" level, respectively.

[0080] The read circuit RCT, as in Figure 2, includes a read latch circuit QLT, a read switch RSW, and a precharge circuit PRE. As described in Figure 2, the read latch circuit QLT receives the read data from the read bit line RBL[i] via the read switch RSW and latches it in accordance with the read enable signal RDEN. The read latch circuit QLT then outputs the latched read data to the outside as output data Q[i].

[0081] The read switch RSW is, for example, composed of a CMOS switch. The read switch RSW is controlled by the read enable signal RDEN and its inverted signal, the inverted read enable signal RDENB. When the read enable signal RDEN is at the "H" level, i.e., the assert level, the read switch RSW connects the read bit line RBL[i] to the read latch circuit QLT.

[0082] The precharge circuit PRE includes, for example, a charge / discharge circuit CDC and a voltage maintenance circuit KEP. The voltage maintenance circuit KEP maintains the voltage of the read bit line RBL[i] at an intermediate voltage VM during the "L" level period, i.e., the negate period, of the read enable signal RDEN. As shown in Figure 6A, the negate period of the read enable signal RDEN is also the off period of the CMOS switch CSW2.

[0083] The voltage maintenance circuit KEP comprises, in detail, three pMOS transistors MP12-MP14 and three nMOS transistors MN12-MN14. The three pMOS transistors MP12-MP14 are connected in series between the high-potential power supply node Nvd and the read bit line RBL[i]. The three nMOS transistors MN12-MN14 are connected in series between the low-potential power supply node Nvs and the read bit line RBL[i].

[0084] The two pMOS transistors MP12 and MP13 are voltage dividers configured in a diode connection. Similarly, the two nMOS transistors MN12 and MN13 are also voltage dividers configured in a diode connection. These voltage dividers, consisting of pMOS and nMOS transistors, form a voltage divider circuit that divides the high-potential power supply voltage VDD with respect to the low-potential power supply voltage VSS at a predetermined voltage division ratio. The voltage division ratio is, for example, 1 / 2.

[0085] On the other hand, the pMOS transistor MP14 and the nMOS transistor MN14 are controlled to be ON during the negate period of the read enable signal RDEN and OFF during the assert period. Thus, the pMOS transistor MP14 and the nMOS transistor MN14 act as precharge switches (first precharge switches). These precharge switches connect the voltage divider circuit to the read bit line RBL[i] during the negate period of the read enable signal RDEN.

[0086] Here, when the precharge switch is turned on, both the diode-connected pMOS transistors MP12, MP13 and the nMOS transistors MN12, MN13 are connected to the read bit line RBL[i]. Therefore, the voltage maintenance circuit KEP alone may not be able to bring the voltage level from the "H" or "L" level to the intermediate voltage VM level "M" level relatively quickly. For this reason, the charge / discharge circuit CDC is provided.

[0087] Furthermore, the voltage maintenance circuit KEP can set the voltage level of the read bit line RBL[i] to the "M" level and maintain it there, once the voltage level of the read bit line RBL[i] has approached the "M" level to some extent. In other words, the voltage maintenance circuit KEP can maintain the voltage level of the read bit line RBL[i] to the "M" level even if, for example, a leakage current occurs in the read bit line RBL[i].

[0088] The charge / discharge circuit CDC charges or discharges the read bit line RBL[i] according to the latch data of the read latch circuit QLT during the negate period of the read enable signal RDEN. In other words, the charge / discharge circuit CDC uses charging and discharging depending on the logic level of the output data Q[i]. This allows the charge / discharge circuit CDC to bring the voltage level of the read bit line RBL[i] closer to the "M" level relatively quickly when the read enable signal RDEN is negated.

[0089] The charge / discharge circuit CDC comprises, in detail, two nMOS transistors MN10 and MN11 and two pMOS transistors MP10 and MP11. The two nMOS transistors MN10 and MN11 are connected in series between the high-potential power node Nvd and the read bit line RBL[i]. The two pMOS transistors MP10 and MP11 are connected in series between the low-potential power node Nvs and the read bit line RBL[i].

[0090] The nMOS transistor MN10 is a charging nMOS transistor that charges the read bit line RBL[i] towards a voltage obtained by adding a threshold voltage drop to the high-potential power supply voltage VDD. The nMOS transistor MN10 is controlled to turn on when the output data Q[i] is at the "L" level and the inverted output data QN[i] is at the "H" level. On the other hand, the pMOS transistor MP10 is a discharging pMOS transistor that discharges the read bit line RBL[i] towards a voltage obtained by adding a threshold voltage rise to the low-potential power supply voltage VSS. The pMOS transistor MP10 is controlled to turn on when the output data Q[i] is at the "H" level and the inverted output data QN[i] is at the "L" level.

[0091] The nMOS transistor MN11 and the pMOS transistor MP11 are controlled to be ON during the negate period of the read enable signal RDEN and OFF during the assert period. Thus, the nMOS transistor MN11 and the pMOS transistor MP11 act as precharge switches (second precharge switches). These precharge switches connect the charge / discharge circuit CDC, specifically the nMOS transistor MN10 or the pMOS transistor MP10, to the read bit line RBL[i] during the negate period of the read enable signal RDEN.

[0092] Figure 9 is a schematic diagram showing an example of the operation of the pre-charge circuit PRE in Figure 8. Figure 9 shows the state after a read operation has been performed. First, when a read operation is performed that outputs output data Q[i] at the "L" level, the read bit line RBL[i] maintains the "L" level.

[0093] In this case, after the read operation is performed, the paths on the nMOS transistors MN10 and MN11 become conductive. As a result, the voltage level of the read bit line RBL[i] rises relatively quickly from the "L" level to the "M" level. The voltage maintenance circuit KEP sets the voltage level of the read bit line RBL[i] to the "M" level when it approaches the "M" level to some extent. The voltage maintenance circuit KEP then maintains the "M" level until the next read operation is performed.

[0094] On the other hand, when a read operation is performed that outputs output data Q[i] at the "H" level, the read bit line RBL[i] maintains the "H" level. In this case, after the read operation is performed, the paths on the pMOS transistors MP10 and MP11 become conductive. As a result, the voltage level of the read bit line RBL[i] decreases somewhat rapidly from the "H" level to the "M" level. The voltage maintenance circuit KEP sets the voltage level of the read bit line RBL[i] to the "M" level when it approaches the "M" level to some extent. The voltage maintenance circuit KEP then maintains the "M" level until the next read operation is performed.

[0095] Here, the pre-charge circuit PRE does not require the same high speed as the sense amplifier. Also, the pMOS transistors MP12, MP13 and nMOS transistors MN12, MN13 in the voltage maintenance circuit KEP shown in Figure 8 operate with a resistance balance between them. As a result, the transistor size of each MOS transistor constituting the pre-charge circuit PRE can be relatively small. Therefore, the area overhead caused by providing the pre-charge circuit PRE is also smaller compared to the case where a sense amplifier is provided. Note that the pre-charge circuit PRE is not limited to the configuration shown in Figure 8; any configuration that can apply the intermediate voltage VM to the read bit line RBL[i] with a small area overhead is acceptable.

[0096] <Main effects of one embodiment> In the embodiment described above, each latch cell LC constituting the D latch macro is composed of 10 or 12 MOS transistors. Furthermore, a precharge circuit PRE is provided within the D latch macro to precharge the read bit line RBL to an intermediate voltage VM in preparation for read operation. This makes it possible to achieve a reasonable balance between area saving and high speed in semiconductor devices with small capacity memory.

[0097] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0098] BW Non-inverted bit write mask selection line BWB Inverted BitWrite Mask Selection Line CDC charge / discharge circuit KEP Voltage Maintenance Circuit LC latch cell MN1-MN6, MN10-MN14 nMOS transistors MP1-MP6, MP10-MP14 pMOS transistors ND1, ND2 intermediate nodes Nvd High-potential power node Nvs low-potential power node PRE (Pre-charge circuit) QLT read latch circuit RBL Read Bit Line RCP non-inverted readout selection line RCPN inverted readout selection line SNb inverted memory node SNt non-inverted memory node VDD High-potential power supply voltage VSS Low-potential power supply voltage WBLN write bit line WCP non-inverted side write selection line WCPN Inverted side write selection line

Claims

1. During the write operation, it is activated and is a pair of complementary signal lines, which are the write selection lines, Activated during readout operations, a pair of readout selection lines, which are complementary signal lines, A plurality of latch cells connected to the pair of write selection lines and the pair of read selection lines, Multiple read bit lines for transferring read data from the multiple latch cells, Multiple write bit lines for transferring write data to the multiple latch cells, Multiple pre-charge circuits connected to the multiple read bit lines, It has, Each of the aforementioned plurality of latch cells is A first storage node and a second storage node that store complementary data, A first nMOS transistor is connected between the first memory node and the first intermediate node, and its gate is connected to the second memory node. A second nMOS transistor is connected between the second memory node and a low-potential power supply node to which a low-potential power supply voltage is supplied, and whose gate is connected to the first memory node. A third nMOS transistor is connected between the first intermediate node and the low-potential power supply node and controlled by the pair of write selection lines, A first pMOS transistor is connected between the first memory node and the second intermediate node, and its gate is connected to the second memory node. A second pMOS transistor is connected between the second memory node and a high-potential power supply node to which a high-potential power supply voltage is supplied, and whose gate is connected to the first memory node. A third pMOS transistor is connected between the second intermediate node and the high-potential power supply node and controlled by the pair of write selection lines, A first CMOS switch controlled by the pair of write selection lines comprises a fourth nMOS transistor and a fourth pMOS transistor that, when controlled to be ON, connect a predetermined write bit line among the plurality of write bit lines to the first storage node, A second CMOS switch is configured, controlled by the pair of read selection lines, and when controlled to be ON, a fifth nMOS transistor and a fifth pMOS transistor connect the second storage node to a predetermined read bit line among the plurality of read bit lines, Equipped with, The plurality of precharge circuits precharge the plurality of read bit lines to an intermediate voltage between the high-potential power supply voltage and the low-potential power supply voltage before the second CMOS switch is controlled to turn ON. Semiconductor equipment.

2. In the semiconductor device described in claim 1, Each of the aforementioned multiple pre-charge circuits is A voltage divider circuit that divides the power supply voltage on the high potential side based on the power supply voltage on the low potential side, A first precharge switch connects the voltage divider circuit to the predetermined read bit line during the off period of the second CMOS switch, Equipped with, Semiconductor equipment.

3. In the semiconductor device described in claim 2, The aforementioned voltage divider circuit is A pMOS transistor for voltage division, configured as a diode connection, is connected between the high-potential power supply node and the predetermined read bit line, An nMOS transistor for voltage division, connected between the low-potential power supply node and the predetermined read bit line, and configured in a diode connection, Equipped with, Semiconductor equipment.

4. In the semiconductor device described in claim 3, Furthermore, the system includes a plurality of read latch circuits that latch the read data transferred to the plurality of read bit lines, Each of the aforementioned pre-charge circuits further, A charge / discharge circuit that charges or discharges the predetermined read bit line according to the latch data of a predetermined read latch circuit among the plurality of read latch circuits, A second precharge switch connects the charge / discharge circuit to the predetermined read bit line during the off period of the second CMOS switch, Equipped with, The aforementioned charging and discharging circuit is A charging nMOS transistor is connected between the high-potential power node and the predetermined read bit line, and is controlled to turn on when the predetermined read latch circuit is latching at an "L" level. A discharge pMOS transistor is connected between the low-potential power supply node and the predetermined read bit line, and is controlled to turn on when the predetermined read latch circuit is latching at a "H" level. Equipped with, Semiconductor equipment.

5. In the semiconductor device described in claim 1, Furthermore, it is activated when a high-impedance write operation is performed on any of the aforementioned latch cells, and is equipped with multiple pairs of bit write mask selection lines that are complementary signal lines. Each of the aforementioned plurality of latch cells further, A sixth nMOS transistor connected between the first intermediate node and the low-potential power supply node, and controlled by a pair of bit write mask selection lines which are any of the plurality of pairs of bit write mask selection lines, A sixth pMOS transistor is connected between the second intermediate node and the high-potential power supply node and controlled by the pair of bit write mask selection lines, Equipped with, Semiconductor equipment.

6. In the semiconductor device described in claim 1, Furthermore, the system includes a read latch circuit that inputs and latches the read data transferred to the plurality of read bit lines without going through a sense amplifier. Semiconductor equipment.

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