Indication device

Abstract

The present invention provides a display device that can distribute the pressure applied to the chip pads of the display panel and the wiring surrounding the chip pads. [Solution] The display device according to the embodiment of this specification includes a substrate including a display area and a non-display area surrounding the display area, a chip pad area located in the non-display area of ​​the substrate and having a plurality of chip pads arranged to constitute a plurality of pad rows, a drive circuit chip mounted in the chip pad area, and at least one pressure distribution structure superimposed on the drive circuit chip and positioned adjacent to the plurality of pad rows.

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] Display devices are applied to various electronic devices such as TVs, mobile phones, notebook computers, and tablets.

[0003] Display devices include an organic light emitting display (OLED) that emits light by itself, a liquid crystal display (LCD) that requires a separate light source, and the like.

[0004] A display device includes a display panel including a plurality of sub-pixels, a driving unit that drives the display panel, and the like. The driving unit includes a scan driving unit that supplies a scan signal (or a gate signal) to the display panel, a data driving unit that supplies a data signal to the display panel, and the like.

[0005] In recent years, a technology called COP (Chip on Plastic) technology, which directly mounts a driving circuit chip of a display device on a flexible plastic substrate of a display panel, has been used.

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the case of COP technology, an anisotropic conductive film is used to mount a driving circuit chip on a display panel. In the process of mounting a driving circuit chip on a pad region of a display panel, pressure is applied to the flexible plastic substrate of the display panel. Due to these pressures, the plastic substrate in the pad region of the display panel may be deformed. At this time, cracks may occur in the pads arranged in the pad region where the driving circuit chip is mounted and the wirings around them. As a result, a poor electrical connection between the driving circuit chip and the display panel may occur.

[0007] This specification aims to provide a display device in which the pressure applied to the chip pads of the display panel and the wiring surrounding the chip pads can be distributed when a drive circuit chip is mounted.

[0008] This specification aims to provide a display device that can efficiently absorb shocks applied to the chip pads of the display panel and the wiring surrounding the chip pads when a drive circuit chip is mounted.

[0009] This specification aims to provide a display device that can prevent cracks from occurring in the pads of the display panel connected to the drive circuit chip, and in the wiring surrounding them.

[0010] This specification aims to provide a display device that can reduce production energy and greenhouse gas emissions by reducing the defect rate.

[0011] The problems described herein are not limited to those mentioned above, and any other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0012] The display device according to the embodiments herein includes a chip pad region located in a non-display area of ​​a substrate, in which a plurality of chip pads constituting a plurality of pad rows are arranged, and includes at least one pressure distribution structure superimposed on a drive circuit chip and positioned adjacent to the plurality of pad rows.

[0013] A display device according to an embodiment of this specification includes a chip pad area located in a non-display area of ​​a substrate and including a plurality of pads, a planar layer covering the edges of the plurality of pads and disposed on the substrate, a drive circuit chip mounted on the chip pad area, and at least one pressure distribution structure disposed between the planar layer and the drive circuit chip, wherein the at least one pressure distribution structure is located between the bumps of the drive circuit chip, and the upper surface of the at least one pressure distribution structure is located closer to the upper surface of the bumps of the drive circuit chip than the lower surface of the bumps of the drive circuit chip. [Effects of the Invention]

[0014] According to embodiments of this specification, a pressure distribution structure is arranged around the chip pad of the display panel, and when the drive circuit chip is mounted, the drive circuit chip is supported by the pressure distribution structure, thereby distributing the pressure applied to the chip pad of the display panel and the wiring around the chip pad during the mounting of the drive circuit chip.

[0015] According to the embodiments of this specification, the pressure distribution structure is made of an organic insulating material, which allows for efficient absorption of shocks applied to the chip pads of the display panel and the wiring surrounding the chip pads when the drive circuit chip is mounted.

[0016] According to the embodiments described herein, when mounting the drive circuit chip, the pressure applied to the chip pad of the display panel is distributed and the impact is absorbed, thereby preventing cracks from occurring in the chip pad of the display panel located below the drive circuit chip, and in the wiring surrounding the chip pad.

[0017] According to the embodiments of this specification, the pressure distribution structure is composed of a buffer section and an enclosure section surrounding the edge of the buffer section, so that the height of the pressure distribution structure can be easily adjusted by adjusting the height of the buffer section. Therefore, in the mounting process of the drive circuit chip, the pressure distribution structure can be formed at the same height as the bump of the drive circuit chip so that the pressure distribution structure can support the lower surface of the drive circuit chip.

[0018] According to the embodiments described herein, the failure rate of display devices due to defects such as cracks in the display panel pads can be reduced, the production energy required for the production of display devices can be reduced, and greenhouse gas emissions can be reduced.

[0019] The effects described herein are not limited to those mentioned above, and any other effects not mentioned can be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0020] [Figure 1] It is an exploded perspective view of a display device according to an embodiment of the present specification. [Figure 2] It is a plan view of a display panel according to an embodiment of the present specification. [Figure 3] It is a plan view showing a chip pad region according to an embodiment of the present specification. [Figure 4] It is a cross-sectional view showing a display device cut along the line I-I' in FIG. 2. [Figure 5] It is a cross-sectional view showing a display device cut along the line II-II' in FIG. 3. [Figure 6] It is a cross-sectional view showing a display device cut along the line III-III' in FIG. 3. [Figure 7] It is a cross-sectional view showing a method for manufacturing a pressure dispersion structure according to an embodiment of the present specification. [Figure 8] It is a cross-sectional view showing a method for manufacturing a pressure dispersion structure according to an embodiment of the present specification. [Figure 9] It is a cross-sectional view showing a method for manufacturing a pressure dispersion structure according to an embodiment of the present specification. [Figure 10] It is a cross-sectional view showing a method for manufacturing a pressure dispersion structure according to an embodiment of the present specification. [Figure 11] It is a plan view showing a pressure dispersion structure according to an embodiment of the present specification. END]] [Figure 12] It is a plan view showing a pressure dispersion structure according to an embodiment of the present specification. [Figure 13] It is a plan view showing a pressure dispersion structure according to an embodiment of the present specification. [Figure 14] It is a plan view showing a pressure dispersion structure according to an embodiment of the present specification.

Mode for Carrying Out the Invention

[0021] The advantages and features of this specification, and the methods for achieving them, will become clear with reference to the examples described below in detail, along with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms. These examples are provided to complete the disclosure of this specification and to fully inform those who have ordinary skill in the art to which this specification pertains.

[0022] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for illustrative purposes are illustrative, and this specification is not limited to those depicted. The same reference numerals throughout the specification refer to the same components. In addition, if a specific description of the relevant known technology is deemed to obscure the gist of this specification, such description will be omitted. Where "includes," "has," or "becomes" is used as referred to in this specification, other parts may be added unless "only" or similar is used. When a component is shown singularly, it includes multiple components unless otherwise explicitly stated.

[0023] When interpreting the constituent elements, even if there is no explicit mention of the error range, it shall be interpreted as including the error range.

[0024] When describing the positional relationship between two parts, for example, using phrases like "on top of," "above," "below," "to the side," or "adjacent," one or more other parts may be located between the two parts, unless phrases like "immediately," "directly," or "near" are used.

[0025] When describing temporal relationships, expressions such as "after," "following," "next," or "before" may include non-consecutive events, unless "immediately" or "directly" is used.

[0026] While terms such as "First," "Second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0027] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. These terms are used to distinguish a component from other components, and the terms do not limit the nature, order, sequence, or number of the component.

[0028] Where it is stated that one component “connects,” “joins,” “connects,” or “adheres” to another component, that component may also be directly connected, joined, connected, or adhered to that other component, and other components may be interposed between each component that is indirectly connected, joined, connected, or adhered to, unless otherwise explicitly stated.

[0029] Where it is stated that a component or layer "contacts" or "overlaps" with another component or layer, it should be understood that while the component or layer may directly contact or overlap with another component or layer, other components may be interposed between each component that may indirectly contact or overlap, unless otherwise explicitly stated.

[0030] "At least one" must be understood to include any combination of one or more of the relevant components. For example, "at least one of the first, second, and third components" can be interpreted as including not only the first, second, or third component alone, but any combination of two or more of the first, second, and third components.

[0031] The terms "first direction," "second direction," "third direction," "X-axis direction," "Y-axis direction," and "Z-axis direction" are not to be interpreted as merely geometric relationships where the relationships are perpendicular to each other, but may also mean that there are broader directions within the range in which the configuration of this specification can function.

[0032] The features of the various embodiments described herein can be combined or linked together, either partially or entirely, and are technically capable of various interconnections and drives. Each embodiment can be implemented independently of the others or in conjunction with them.

[0033] The following describes various embodiments of this specification in detail with reference to the attached drawings.

[0034] Figure 1 is an exploded perspective view of a display device according to an embodiment of this specification. Figure 2 is a plan view of a display panel according to an embodiment of this specification.

[0035] Referring to Figures 1 and 2, the display device 100 may include a display panel (DP), a drive circuit chip (DIC), a printed circuit board (PCB), and a control circuit chip (CIC).

[0036] A display panel (DP) may include multiple pixels (PX), multiple chip pads (CPD), and multiple pads (PD). The multiple pixels (PX) may be arranged in the display area (AA) of the display panel (DP), and the multiple chip pads (CPD) and multiple pads (PD) may be arranged in the non-display area (NAA).

[0037] The shapes of the display area (AA) shown in Figures 1 and 2 are illustrative, and the shape of the display area (AA) can be changed without limitation as needed. The non-display area (NAA) is the area surrounding the display area (AA) and is the area where no image is displayed. The non-display area (NAA) can define the bezel area of ​​the display device 100. The non-display area (NAA) may completely or partially enclose the display area (AA). For example, the display area (AA) may have the shape of a rectangle, square, circle, ellipse, triangle, polygon, etc. For example, the non-display area (NAA) may extend from the display area (AA). For example, at least part or all of the non-display area (NAA) may not be visible from the front (viewing side) of the display panel (DP), and may, for example, curve towards the rear side of the display panel (DP), but is not limited to this.

[0038] Wiring may be arranged in the non-display area (NAA) to provide electrical signals to or from the display area (AA). A gate drive unit (not shown) may be arranged in the non-display area (NAA) to supply gate signals to multiple pixels (PX) of the display area (AA). The gate drive unit may be arranged on one or both sides of the non-display area (NAA) of the display panel (DP) using the GIP (Gate In Panel) method. For example, the gate drive unit does not have to be arranged in the non-display area (NAA). For example, the gate drive unit may be arranged separately on a separate panel and connected to the display panel (DP), and may be connected by methods such as Tape Automated Bonding (TAB), Chip On Glass (COG), Chip On Panel (COP), Chip On Film (COF), etc., but is not limited thereto.

[0039] The non-display area (NAA) includes a chip pad area (CPA) on which multiple chip pads (CPDs) are arranged. A driver circuit chip (DIC) may be mounted in the chip pad area (CPA). The driver circuit chip (DIC) may be arranged so as to overlap the multiple chip pads (CPDs). The multiple chip pads (CPDs) may include multiple output pads (CPD1) and multiple input pads (CPD2). The output bumps of the driver circuit chip (DIC) can be electrically connected to the output pads (CPD1) of the display panel (DP) by an anisotropic conductive film, and the input bumps of the driver circuit chip (DIC) can be electrically connected to the input pads (CPD2) of the display panel (DP) by an anisotropic conductive film.

[0040] Multiple chip pads (CPDs) can be electrically connected to multiple pixels (PX) via multiple data lines. A drive circuit chip (DIC) can transmit data signals to multiple pixels (PX) of the display area (AA) via the multiple chip pads (CPDs) and multiple data lines. The drive circuit chip (DIC) may also be a data drive circuit chip.

[0041] The chip pad area (CPA) may contain not only multiple chip pads (CPDs) but also pressure distribution structures (PDS). The pressure distribution structures (PDS) may be placed around the multiple chip pads (CPDs). The pressure distribution structures (PDS) may be placed in multiple areas of the chip pad area (CPA), including the area between the output pad (CPD1) and the input pad (CPD2). The pressure distribution structures (PDS) can distribute the pressure applied to the multiple chip pads (CPDs) when the drive circuit chip (DIC) is mounted on the chip pad area (CPA). Therefore, the occurrence of cracks in the multiple chip pads (CPDs) or pad connection wiring during the process of bonding the drive circuit chip (DIC) to the chip pad area (CPA) of the display panel (DP) can be reduced or prevented.

[0042] A printed circuit board (PCB) can be electrically connected to multiple pads (PDs), for example, by an anisotropic conductive film. A control circuit chip (CIC) may be mounted on the printed circuit board (PCB). The printed circuit board (PCB) may be a flexible printed circuit board.

[0043] The control circuit chip (CIC) can control the drive circuit chip (DIC) and the gate drive unit.

[0044] The bending area (BA) of the display panel (DP) may be bent, and the printed circuit board (PCB) and the drive circuit chip (DIC) may be positioned below the display area (AA) of the display panel (DP). This may reduce the non-display area (NAA) of the display device 100.

[0045] The bending region (BA) may be the region located between the display panel (DP) and the drive circuit chip (DIC). For example, the bending region (BA) may be a part of the non-display area (NAA) of the display panel (DP) where the drive circuit chip (DIC) is not mounted. The embodiments are not limited thereto. For example, the design may omit the bending region (BA) or provide two or more bending regions (BA).

[0046] Figure 3 is a plan view showing the tip pad area according to the embodiments described herein.

[0047] Referring to Figure 3, the chip pad area (CPA) of the display panel (DP) can have multiple chip pads (CPDs) arranged in multiple rows to form multiple pad rows (PRs). The chip pad area (CPA) may also contain multiple output pads (CPD1) and multiple input pads (CPD2). For example, the multiple output pads (CPD1) may include multiple first output pads (CPD1a) and multiple second output pads (CPD1b). For example, multiple first output pads (CPD1a) can be arranged in the first direction (DR1) to form a first pad row (PR1). For example, multiple second output pads (CPD1b) can be arranged in the first direction (DR1) to form a second pad row (PR2). For example, multiple input pads (CPD2) can be arranged in the first direction (DR1) to form a third pad row (PR3). In other embodiments, multiple output pads (CPD1) may be arranged in one row or in three or more rows. And in other embodiments, multiple input pads (CPD2) may be arranged in two or more rows. The tip pad area (CPA) is located away from one side of the display area (AA) in a second direction (DR2) perpendicular to the first direction (DR1).

[0048] At least one pressure distribution structure (PDS) may be located in the chip pad area (CPA) of the display panel (DP). At least one pressure distribution structure (PDS) may overlap the drive circuit chip (DIC) partially or entirely and be located adjacent to multiple pad rows (PR). Multiple pressure distribution structures (PDS) may be located around multiple pad rows (PR). In this embodiment, multiple pressure distribution structures (PDS) may be located above and below each of the multiple pad rows (PR). Multiple pressure distribution structures (PDS) may be located in the area between the multiple pad rows (PR), above the first pad row (PR1) and below the third pad row (PR3). In one embodiment, multiple pressure distribution structures (PDS) may be located only in the area between the multiple pad rows (PR). In one embodiment, multiple pressure distribution structures (PDS) may be located only above the first pad row (PR1) and below the third pad row (PR3). Each pad row (PR1, PR2, or PR3) includes multiple tip pads (CPDs) arranged in a first direction (DR1). The first pad row (PR1) includes multiple first output pads (CPD1a) arranged in a first direction (DR1). The second pad row (PR1) includes multiple second output pads (CPD1b) arranged in a first direction (DR1). The third pad row (PR3) includes multiple input pads (CPD2) arranged in a first direction (DR1).

[0049] Each pressure distribution structure (PDS) may have the shape of a line extending in a first direction (DR1). Here, the shape of the line includes both straight and curved shapes. Depending on the arrangement of the multiple tip pads (CPDs), the shape of the pressure distribution structures (PDS) may also differ. As shown in Figure 3, when multiple tip pads (CPDs) are arranged along multiple straight lines to form multiple rows, the multiple pressure distribution structures (PDS) may have a straight shape. In one embodiment, when multiple tip pads (CPDs) are arranged along multiple curves to form multiple rows, the multiple pressure distribution structures (PDS) may also have a curved shape. Each pressure distribution structure (PDS) may extend continuously within the tip pad area (CPA), from the left side to the right side of the CPA.

[0050] Figure 4 is a cross-sectional view showing the display device cut along the line I-I' in Figure 2. Figure 4 schematically shows the subpixels of the display device.

[0051] Referring to Figure 4, the display device may include a plurality of thin-film transistors 120, 130, one capacitor (Cst), and a light-emitting element 140 arranged on a substrate 110. The plurality of thin-film transistors 120, 130 may include a first thin-film transistor 120 and a second thin-film transistor 130. For example, the first thin-film transistor 120 and the second thin-film transistor 130 may contain the same semiconductor material or different semiconductor materials. The semiconductor material may include a polycrystalline semiconductor material, an oxide semiconductor material, an amorphous semiconductor material, a compound semiconductor material, or an organic semiconductor material. For example, the first thin-film transistor 120 may contain a polycrystalline semiconductor material, and the second thin-film transistor 130 may contain an oxide semiconductor material.

[0052] Each subpixel includes a light-emitting element 140 and a pixel driving circuit that applies a driving current to the light-emitting element 140. The pixel driving circuit is disposed on the substrate 110, and the light-emitting element 140 is disposed on the pixel driving circuit. The pixel driving circuit may include a driving thin-film transistor, one or more switching thin-film transistors, and a capacitor. The first and second thin-film transistors 120, 130 may be driving thin-film transistors and / or switching thin-film transistors. For example, one or more thin-film transistors and one or more capacitors may be further included.

[0053] The substrate 110 may be a flexible substrate or a rigid substrate. For example, the substrate 110 may be a flexible plastic substrate made of an organic insulating material such as polyimide. The substrate 110 can be embodied in a multi-layer structure in which organic insulating materials and inorganic insulating materials are alternately laminated. For example, the substrate 110 may be a structure in which an organic insulating material such as polyimide and an inorganic insulating material such as silicon oxide (SiOx) are alternately laminated to each other. For example, the substrate 110 may have a three-layer structure in which a silicon oxide layer is placed between two polyimide layers.

[0054] A first lower buffer layer 112 and a second lower buffer layer 114 are formed on the substrate 110. The first and second lower buffer layers 112 and 114 are for blocking moisture or oxygen that may penetrate from the outside, and may be single-layer or multi-layer structures made of inorganic insulating materials such as silicon oxide (SiOx) or silicon nitride (SiNx). A first light-shielding layer 113 may be placed between the first lower buffer layer 112 and the second lower buffer layer 114.

[0055] An auxiliary buffer layer 116 may be further arranged on the second lower buffer layer 114 to block moisture or oxygen that may penetrate from the outside. The auxiliary buffer layer 116 may be a single layer or multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0056] A first thin-film transistor 120 may be placed on the auxiliary buffer layer 116. The first thin-film transistor 120 includes a first active layer 121 made of a polycrystalline semiconductor material, a first gate electrode 123 superimposed on the channel region of the first active layer 121, a first source electrode 125s connected to the source region of the first active layer 121, and a first drain electrode 125d connected to the drain region of the first active layer 121.

[0057] The first active layer 121 may be placed on the auxiliary buffer layer 116. A first gate insulating layer 122 is placed between the first gate electrode 123 and the first active layer 121. The first gate insulating layer 122 covers the first active layer 121 and may be placed on the auxiliary buffer layer 116. The first gate insulating layer 122 may be a single layer or multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0058] Between the first lower buffer layer 112 and the second lower buffer layer 114, the first light-shielding layer 113 is positioned to overlap with the first active layer 121, thereby blocking or reducing the light incident on the first active layer 121 and ensuring the reliability of the first thin-film transistor 120. The first light-shielding layer 113 may be made of a metallic material. For example, the first light-shielding layer 113 can also be electrically coupled with the first gate electrode 123 to form a dual gate. For example, the first light-shielding layer 113 may be floated. For example, the first light-shielding layer 113 may be a single layer or multiple layer made of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, depending on the design, the first light-shielding layer 113 may be omitted.

[0059] The capacitor (Cst) includes a first electrode 127 and a second electrode 128. The first electrode 127 may be located on a first gate insulating layer 122. For example, the first electrode 127 may be formed from the same material as the first gate electrode 123 of the first thin-film transistor 120. For example, the first gate electrode 123 and the first electrode 127 may be composed of a metallic material. For example, the first gate electrode 123 and the first electrode 127 may be a single layer or multiple layer made of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the first electrode 127 may be located on a different layer from the first gate electrode 123, and may be formed from a different material than the first gate electrode 123.

[0060] A first interlayer insulating layer 124 may be disposed on the first gate electrode 123 and the first electrode 127. The first interlayer insulating layer 124 may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0061] The second electrode 128 and second light-shielding layer 129 of the capacitor (Cst) may be arranged on the first interlayer insulating layer 124. The second electrode 128 may be formed of the same material as the second light-shielding layer 129. The second electrode 128 and the second light-shielding layer 129 are made of a metallic material. For example, the second electrode 128 and the second light-shielding layer 129 may be a single layer or multiple layers made of any of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. For example, the second electrode 128 and the second light-shielding layer 129 of the capacitor (Cst) may be arranged on different layers or made of different materials. For example, the second light-shielding layer 129 may be omitted depending on the design.

[0062] An upper buffer layer 126 may be disposed on the second electrode 128 and the second light-shielding layer 129. A second thin-film transistor 130 may be disposed on the upper buffer layer 126. The second thin-film transistor 130 includes a second active layer 131 made of an oxide semiconductor material, a second gate electrode 133 superimposed on the channel region of the second active layer 131, a second source electrode 135s connected to the source region of the second active layer 131, and a second drain electrode 135d connected to the drain region of the second active layer 131. The upper buffer layer 126 provides a substrate that can form the second active layer 131 by separating it from the first active layer 201 made of a polycrystalline semiconductor material. The upper buffer layer 126 may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0063] The second active layer 131 may be placed on the upper buffer layer 126. A second gate insulating layer 132 is placed between the second gate electrode 133 and the second active layer 131. The second gate insulating layer 132 may cover the second active layer 131 and be placed on the upper buffer layer 126. The second gate insulating layer 132 may be a single layer or multilayer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0064] The second gate electrode 133 may be composed of a metallic material. For example, the second gate electrode 133 may be a single layer or multiple layers made of any of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0065] The second light-shielding layer 129 is positioned to overlap with the second active layer 131, thereby blocking or reducing the light incident on the second active layer 131 and ensuring the reliability of the second thin-film transistor 130. For example, the second light-shielding layer 129 can also be electrically coupled to the second gate electrode 133 to form a dual gate. For example, the second light-shielding layer 129 may be floated. For example, the second light-shielding layer 129 may be omitted depending on the design.

[0066] The second interlayer insulating layer 134 covering the second gate electrode 133 may be placed on the second gate insulating layer 132.

[0067] The first source electrode 125s, the first drain electrode 125d, the second source electrode 135s, and the second drain electrode 135d may be arranged on the second interlayer insulating layer 134. The first source electrode 125s, the first drain electrode 125d, the second source electrode 135s, and the second drain electrode 135d may be formed simultaneously on the second interlayer insulating layer 134 from the same material. The first source electrode 125s and the first drain electrode 125d may be connected to the source region and drain region of the first active layer 121, respectively, via through-holes penetrating the second interlayer insulating layer 134, the second gate insulating layer 132, the upper buffer layer 126, the first interlayer insulating layer 124, and the first gate insulating layer 122. The second source electrode 135s and the second drain electrode 135d may be connected to the source region and drain region of the second active layer 131, respectively, via through holes penetrating the second interlayer insulating layer 134 and the second gate insulating layer 132.

[0068] The second drain electrode 135d or second source electrode 135s of the second thin-film transistor 130 can be electrically connected to the second electrode 128 of the capacitor (Cst) via a through-hole that penetrates the second interlayer insulating layer 134, the second gate insulating layer 132, and the upper buffer layer 126. However, the connection relationship of the capacitor (Cst) can change depending on the pixel driving circuit.

[0069] On the other hand, a first planarization layer 136 and a second planarization layer 138 are sequentially arranged on the pixel driving circuit to flatten the step created by the pixel driving circuit. The first planarization layer 136 and the second planarization layer 138 may be made of an organic insulating material such as polyimide or acrylic resin.

[0070] Furthermore, a light-emitting element 140 may be formed on the second planarization layer 138.

[0071] The light-emitting element 140 includes an anode electrode 141, a cathode electrode 145, and a light-emitting layer 143 disposed between the anode electrode 141 and the cathode electrode 145.

[0072] The light-emitting element 140 may be electrically connected to the pixel driving circuit via an intermediate electrode 137 placed on the first planarization layer 136, or it may be directly connected to the pixel driving circuit without the intermediate electrode 137. For example, the anode electrode 141 of the light-emitting element 140 may be connected to the first drain electrode 135d of the second thin-film transistor 130 via the intermediate electrode 137.

[0073] The anode electrode 141 may be connected to the intermediate electrode 137 via a contact hole that penetrates the second planarization layer 138. Alternatively, the intermediate electrode 137 may be connected to the second drain electrode 135d via a contact hole that penetrates the first planarization layer 136.

[0074] The intermediate electrode 137 may be a single layer or multiple layers made of any of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0075] The anode electrode 141 may be formed from a conductive material. For example, the anode electrode 141 may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film may consist of a material with a relatively large work function, such as indium-tin oxide (ITO) or indium-zinc oxide (IZO), and the opaque conductive film may consist of a single layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode electrode 141 may be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or as a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked.

[0076] The light-emitting layer 143 may include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer on the anode electrode 141. The examples are not limited thereto. For example, at least one or all of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer may be omitted depending on the design.

[0077] The bank layer 142 may be a pixel-defining film that exposes a portion (e.g., the central portion) of each anode electrode 141. The bank layer 142 may be composed of an organic insulating material. For example, the bank layer 142 may contain one of the following: photosensitive polyimide, photoacrylic, and benzocyclobutene (BCB). The bank layer 142 may be formed of an opaque material to prevent or reduce optical interference between adjacent pixels. In this case, the bank layer 142 contains a light-shielding material consisting of at least one of the following: color pigment, organic black, and carbon.

[0078] Spacers 144 may be further arranged on the bank layer 142. A fine metal mask, which is a deposition mask, can be used to form the light-emitting layer 143. Spacers 144 may be arranged on the bank layer 142 to maintain a certain distance between the bank layer 142 and the deposition mask, and to prevent or reduce damage to the bank layer 142 and anode electrode 141 that may occur due to contact with the deposition mask. For example, depending on the design, the spacers 144 may be omitted.

[0079] The spacer 144 may be composed of the same material as the bank layer 142 and may be formed simultaneously with the bank layer 142 in a single process, but is not limited to this. The spacer 144 may be composed of a different material than the bank layer 142 and may be formed on the bank layer 142 by a separate process. The spacer 144 may be composed of an organic insulating material. The spacer 144 may contain one of the following: photosensitive polyimide, photoacrylic, and benzocyclobutene (BCB).

[0080] The cathode electrode 145 may be formed integrally over the entire display area (AA) or for each pixel. When applied to a full-surface-emitting organic light-emitting display device, the cathode electrode 145 may consist of a transparent conductive film such as indium-tin oxide (ITO) or indium-zinc oxide (IZO).

[0081] A sealing layer 150 to suppress moisture penetration may be further arranged on the cathode electrode 145. The sealing layer 150 may contain an inorganic or organic substance. For example, the sealing layer 150 may include a first inorganic sealing layer 152, an organic sealing layer 154, and a second inorganic sealing layer 156 that are sequentially stacked.

[0082] The first inorganic sealing layer 152 and the second inorganic sealing layer 156 of the sealing layer 150 may be formed from an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The organic sealing layer 154 of the sealing layer 150 may be formed from an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0083] Figure 5 is a cross-sectional view showing the display device cut along the line II-II' in Figure 3. Figure 6 is a cross-sectional view showing the display device cut along the line III-III' in Figure 3. The cross-sectional structures of the tip pad area (CPA) and pressure distribution structure (PDS) according to the embodiments herein will be described with reference to Figures 5 and 6.

[0084] Referring to Figures 5 and 6, chip pads (CPDs, see Figure 3) may be placed on the substrate 110. Although only a first output pad (CPD1a) and a second output pad (CPD1b) placed on the substrate 110 are shown in the drawings, an input pad (CPD2, see Figure 3) may also be placed on the substrate 110. A drive circuit chip (DIC) may be mounted on the first and second output pads (CPD1a, CPD1b) and the input pad (CPD2) by an anisotropic conductive film 210. The first output bump (DBP1a) of the drive circuit chip (DIC) can be electrically connected to the first output pad (CPD1a) by conductive particles 212 of the anisotropic conductive film 210, and the second output bump (DBP1b) of the drive circuit chip (DIC) can be electrically connected to the second output pad (CPD1b) by conductive particles 212 of the anisotropic conductive film 210. Although not shown, the input bumps of the drive circuit chip (DIC) can be electrically connected to the input pads (CPD2) by the conductive particles 212 of the anisotropic conductive film 210.

[0085] A first and second lower buffer layer 112, 114, an auxiliary buffer layer 116, and a first gate insulating layer 122 may be arranged on the substrate 110. A pad connection wiring 223 may be arranged on the first gate insulating layer 122. The pad connection wiring 223 can electrically connect the first output pad (CPD1a) and the second output pad (CPD1b). The pad connection wiring 223 may be formed simultaneously with the first gate electrode 123 from the same material. The embodiments are not limited thereto. For example, the pad connection wiring 223 may be arranged on a layer different from the first gate insulating layer 122. For example, the pad connection wiring 223 may be formed from a different material than the first gate electrode 123, and the pad connection wiring 223 and the first gate electrode 123 may be formed separately.

[0086] A first interlayer insulating layer 124, an upper buffer layer 126, a second gate insulating layer 132, and a second interlayer insulating layer 134 may be arranged on the pad-connected wiring 223. The embodiments are not limited thereto. For example, at least one of the first interlayer insulating layer 124, the upper buffer layer 126, the second gate insulating layer 132, and the second interlayer insulating layer 134 may be omitted by design.

[0087] A first output pad (CPD1a), a second output pad (CPD1b), and an input pad (not shown) may be arranged on the second interlayer insulating layer 134. The first output pad (CPD1a) and the second output pad (CPD1b) may include a lower pad layer 235 and an upper pad layer 237. The input pad (not shown) may also include a lower pad layer 235 and an upper pad layer 237. The upper pad layer 237 may be arranged directly on the lower pad layer 235. The lower pad layer 235 may be connected to the pad connection wiring 223 via through-holes that penetrate the first interlayer insulating layer 124, the upper buffer layer 126, the second gate insulating layer 132, and the second interlayer insulating layer 134. For example, the lower pad layer 235 may be formed simultaneously from the same material as the first source electrode 125s and the first drain electrode 125d. For example, the lower pad layer 235 may be formed from a different material than the first source electrode 125s and the first drain electrode 125d. For example, the upper pad layer 237 may be formed from the same material as the intermediate electrode 137 at the same time. For example, the upper pad layer 237 may be formed from a different material than the intermediate electrode 137. The embodiments are not limited thereto. For example, the first output pad (CPD1a), the second output pad (CPD1b), and the input pad may be arranged in different layers other than the second interlayer insulating film 134. For example, the first output pad (CPD1a), the second output pad (CPD1b), and the input pad may be arranged in the same layer or in different layers. For example, each of the first output pad (CPD1a) and the second output pad (CPD1b) may consist of a single layer or two or more layers. For example, the upper pad layer 237 may be superimposed on the lower pad layer 235. For example, the upper pad layer 237 can either cover both ends of the lower pad layer 235 or expose one of the ends of the lower pad layer 235. For example, the upper pad layer 237 can expose a portion of the upper surface of the lower pad layer 235.

[0088] The second planarization layer 138 may cover the edges of the multiple chip pads (CPDs) and be positioned on the second interlayer insulating layer 134. The second planarization layer 138 may include multiple openings that expose a portion (e.g., the center) of the multiple chip pads (CPDs).

[0089] A pressure distribution structure (PDS) may be placed on the second flattening layer 138. The pressure distribution structure (PDS) may be placed in the region between the first output pad (CPD1a) and the second output pad (CPD1b). Although not shown, a pressure distribution structure (PDS) may also be placed in the region between the second output pad (CPD1b) and the input pad (CPD2).

[0090] The pressure distribution structure (PDS) may be positioned between the first output bump (DBP1a) and the second output bump (DBP1b) of the drive circuit chip (DIC). The pressure distribution structure (PDS) may also be positioned in the region between the second output bump (DBP1b) and the input bump of the drive circuit chip (DIC). The pressure distribution structure (PDS) may protrude into the space between the bumps of the drive circuit chip (DIC). For example, the upper surface of the pressure distribution structure (PDS) may be positioned closer to the upper surface of the bumps of the drive circuit chip (DIC) than the lower surface of the bumps of the drive circuit chip (DIC).

[0091] The pressure distribution structure (PDS) may include a buffer section 254 and an enclosure section 240 surrounding the buffer section 254. The enclosure section 240 can define the area in which the buffer section 254 is located. The enclosure section 240 confines the buffer section 254 so that it can maintain a predetermined shape. The height or thickness of the buffer section 254 may be greater or thicker than the height or thickness of the enclosure section 240. The buffer section 254 may have a bulging upper surface. The upper surface of the buffer section 254 may be located closer to the upper surface of the bumps on the drive circuit chip (DIC) than the lower surface of the bumps on the drive circuit chip (DIC).

[0092] For example, the buffer section 254 may be made of the same material as the organic sealing layer 154 of the display area (AA). The enclosure section 240 may include a lower layer 242 and an upper layer 244 placed on the lower layer 242. For example, the lower layer 242 of the enclosure section 240 may be made of the same material as the bank layer 142 of the display area (AA). The upper layer 244 of the enclosure section 240 may be made of the same material as the spacer 144 of the display area (AA). If the bank layer 142 and the spacer 144 of the display area (AA) are made of the same material and are formed simultaneously in a single process, the lower layer 242 and the upper layer 244 of the enclosure section 240 are also formed simultaneously from the same material in a single process, so the lower layer 242 and the upper layer 244 may not be distinguishable.

[0093] The anisotropic conductive film 210, which is placed between the pressure distribution structure (PDS) and the drive circuit chip (DIC), may include an adhesive layer 214 in which conductive particles 212 are dispersed.

[0094] The pressure distribution structure (PDS) may have a height or thickness similar to the height or thickness of the output bumps and input bumps of the drive circuit chip (DIC). The pressure distribution structure (PDS) may be bonded to the drive circuit chip (DIC) by an anisotropic conductive film 210 present between the pressure distribution structure (PDS) and the drive circuit chip (DIC). For example, some of the conductive particles 212 of the anisotropic conductive film 210 can simultaneously contact the upper surface of the pressure distribution structure (PDS) and the lower surface of the drive circuit chip (DIC). In one example, the pressure distribution structure (PDS) can contact the lower surface of the drive circuit chip (DIC). For example, the distance between the upper surface of the pressure distribution structure (PDS) and the lower surface of the drive circuit chip (DIC) may be similar to, but not limited to, the diameter of some of the conductive particles 212.

[0095] According to one embodiment of this specification, a pressure distribution structure (PDS) is arranged around the chip pad (CPD) of the display panel (DP), and when the drive circuit chip (DIC) is mounted, the drive circuit chip (DIC) is supported by the pressure distribution structure (PDS), thereby distributing the pressure applied to the chip pad (CPD) of the display panel (DP) and the wiring around the chip pad when the drive circuit chip (DIC) is mounted.

[0096] According to one embodiment of this specification, the pressure distribution structure (PDS) is made of an organic insulating material, thereby efficiently absorbing the impact applied to the chip pad (CPD) of the display panel (DP) and the wiring surrounding the chip pad when the drive circuit chip (DIC) is mounted.

[0097] According to one embodiment of this specification, when mounting the drive circuit chip (DIC), the pressure applied to the chip pad (CPD) of the display panel (DP) is distributed and the shock is absorbed, thereby preventing or reducing the occurrence of cracks in the chip pad (CPD) of the display panel (DP) and the wiring surrounding the chip pad, which are located below the drive circuit chip (DIC).

[0098] According to one embodiment of this specification, the pressure distribution structure (PDS) is composed of a buffer portion 254 and an enclosure portion 240 surrounding the edge of the buffer portion 254, so that the height or thickness of the pressure distribution structure (PDS) can be easily adjusted by adjusting the height or thickness of the buffer portion 254. This allows the pressure distribution structure (PDS) to be formed with a height or thickness similar to the height or thickness of the bumps on the drive circuit chip (DIC) so that the pressure distribution structure (PDS) can support the lower surface of the drive circuit chip (DIC) during the drive circuit chip (DIC) mounting process.

[0099] Figures 7 to 9 are cross-sectional views showing a method for manufacturing a pressure-distributing structure according to the embodiments of this specification.

[0100] Referring to Figure 7, the display area (AA) may have a first light-shielding layer 113, a first thin-film transistor 120, a capacitor (Cst), a second light-shielding layer 129, a second thin-film transistor 130, an intermediate electrode 137, and an anode electrode 141 formed on the substrate 110. As explained with reference to Figure 4, various insulating layers necessary in the process of forming the above-described configuration may also be formed. The anode electrode 141 may be placed on the second planarization layer 138 and connected to the intermediate electrode 137 placed on the first planarization layer 136, penetrating the second planarization layer 138.

[0101] In the non-display area (NAA) chip pad area (CPA), chip pads (CPDs) including pad-connecting wiring 223 and first and second output pads (CPD1a, CPD1b) may be formed on the substrate 110. As described with reference to Figures 5 and 6, various insulating layers necessary in the process of forming the above-described configuration may also be formed. The second planarization layer 138 may cover the edges of the chip pads (CPDs) including the first and second output pads (CPD1a, CPD1b) and be placed on the second interlayer insulating layer 134.

[0102] Referring to Figure 8, a bank layer 142 and a spacer 144 may be formed in the display area (AA), and an enclosure portion 240 including a lower layer 242 and an upper layer 244 may be formed in the chip pad area (CPA) of the non-display area (NAA). The lower layer 242 of the enclosure portion 240 may be formed simultaneously with the bank layer 142 of the display area (AA) from the same material. The upper layer 244 of the enclosure portion 240 may be formed simultaneously with the spacer 144 of the display area (AA) from the same material. If the bank layer 142 and spacer 144 of the display area (AA) are made of the same material and are formed simultaneously in a single process, the lower layer 242 and upper layer 244 of the enclosure portion 240 may also be formed simultaneously with the same material.

[0103] Referring to Figure 9, the display area (AA) has an emissive layer 143, a cathode electrode 145, a first inorganic encapsulation layer 152, an organic encapsulation layer 154, and a second inorganic encapsulation layer 156 formed therein, and the non-display area (NAA) has a buffer section 254 formed within the enclosure section 240 in the chip pad area (CPA). For example, the buffer section 254 may be made of the same organic insulating material as the organic encapsulation layer 154. Alternatively, the buffer section 254 may not be formed at the same time as the organic encapsulation layer 154, but may be formed by a separate process. The buffer section 254 may be formed, for example, by an inkjet process.

[0104] Referring to Figure 10, the drive circuit chip (DIC) may be mounted on the chip pad area (CPA) of the non-display area (NAA) using an anisotropic conductive film 210. After positioning the anisotropic conductive film 210 and the drive circuit chip (DIC) on the chip pad area (CPA), the drive circuit chip (DIC) is pressed with a predetermined pressure to bring the bumps of the drive circuit chip (DIC) into contact with the pads of the chip pad area (CPA). At this time, the pressure distribution structure (PDS) supports the lower surface of the drive circuit chip (DIC) via the anisotropic conductive film 210, and the pressure applied to the chip pad area (CPA) by the bumps of the drive circuit chip (DIC) can be distributed.

[0105] Figures 11 to 14 are plan views showing pressure distribution structures according to embodiments of this specification.

[0106] Referring to Figure 11, at least one of the multiple pressure distribution structures (PDS1) can be divided into multiple spaced pressure distribution patterns (PDS'). As shown in Figure 11, all of the pressure distribution structures (PDS1) can be divided into multiple spaced pressure distribution patterns (PDS'). In one embodiment, some of the multiple pressure distribution structures (PDS1) can be divided into multiple spaced pressure distribution patterns (PDS'). Figure 11 illustrates, but is not limited to, a case where one pressure distribution structure (PDS1) is divided into three spaced pressure distribution patterns (PDS').

[0107] Referring to Figure 12, each of the multiple pad rows (PRs) may have multiple first pressure distribution structures (PDSa) positioned above and below each of them, and two second pressure distribution structures (PDSb) may be positioned on the left and right sides of the multiple pad rows (PRs). For example, the two second pressure distribution structures (PDSb) may be connected to the ends of the multiple first pressure distribution structures (PDSa) or separated from the ends of the multiple first pressure distribution structures (PDSa). The above and below of each of the multiple pad rows (PRs) may be opposite sides in the second direction (DR2) of each of the multiple pad rows (PRs). The left and right sides of each of the multiple pad rows (PRs) may be opposite sides in the first direction (DR1) of each of the multiple pad rows (PRs). The multiple first pressure distribution structures (PDSa) may extend in the first direction (DR1), and the second pressure distribution structures (PDSb) may extend in the second direction (DR2). For example, multiple first pressure distribution structures (PDSa) and two second pressure distribution structures (PDSb) can be formed together to constitute a single pressure distribution structure (PDS). Alternatively, multiple first pressure distribution structures (PDSa) and two second pressure distribution structures (PDSb) can constitute separate parts.

[0108] Referring to Figure 13, a plurality of first pressure distribution structures (PDSa') are arranged above and below each of a plurality of pad rows (PRs), and two second pressure distribution structures (PDSb) may be arranged on the left and right sides of the plurality of pad rows (PRs), connected to the ends of the plurality of first pressure distribution structures (PDSa'). At least one of the plurality of first pressure distribution structures (PDSa') may be divided into a plurality of first pressure distribution patterns (PDS') spaced apart from each other. As shown in Figure 13, all of the first pressure distribution structures (PDSa') may be divided into a plurality of pressure distribution patterns (PDS'). In one embodiment, some of the plurality of pressure distribution structures (PDSa') may be divided into a plurality of pressure distribution patterns (PDS') spaced apart from each other. The second pressure distribution structure (PDSb) may be connected to one end of the outermost first pressure distribution pattern (PDS') among a plurality of first pressure distribution patterns (PDS').

[0109] Referring to Figure 14, each of the multiple pad rows (PRs) is positioned above and below each of the multiple pad rows (PRs), and may further include multiple second pressure distribution structures (PDSc) connected to the ends of two adjacent first pressure distribution structures (PDSa) on the left and right sides of the multiple pad rows (PRs). The multiple second pressure distribution structures (PDSc) may be alternately positioned on the left or right side of different rows. For example, the multiple second pressure distribution structures (PDSc) may be positioned to the right of each odd-numbered pad row and to the left of each even-numbered pad row in the plan view of the display panel, but are not limited thereto. For example, the multiple first pressure distribution structures (PDSa) and the multiple second pressure distribution structures (PDSc) can be formed together to constitute a single pressure distribution structure (PDS4). In one embodiment, two second pressure distribution structures (PDSc) may be located on either side of the odd-numbered pad row. In this case, a ring-shaped pressure distribution structure may be formed.

[0110] Although the illustrations and descriptions show the pressure distribution structure (PDS) being positioned in a first direction (DR1) or a second direction (DR2), the embodiments are not limited thereto. For example, the pressure distribution structure (PDS) may be positioned in a direction other than the first direction (DR1) or the second direction (DR2).

[0111] The display devices according to the various embodiments of this specification can be described as follows.

[0112] A display device according to the embodiments of this specification includes a substrate including a display area and a non-display area surrounding the display area; a chip pad area located in the non-display area of ​​the substrate and having a plurality of chip pads arranged to constitute a plurality of pad rows; a drive circuit chip mounted in the chip pad area; and at least one pressure distribution structure superimposed on the drive circuit chip and positioned adjacent to the plurality of pad rows.

[0113] According to some embodiments of this specification, each pad row includes a plurality of tip pads arranged in a first direction, and at least one pressure distribution structure may extend in the first direction.

[0114] According to some embodiments of this specification, at least one pressure distribution structure may be placed on a planarization layer covering the edges of a plurality of chip pads and bonded to the drive circuit chip by an anisotropic conductive film.

[0115] According to some embodiments of this specification, some of the conductive particles of an anisotropic conductive film can simultaneously contact the upper surface of at least one pressure-distributing structure and the lower surface of a drive circuit chip.

[0116] According to some embodiments of this specification, at least one pressure distribution structure may protrude into the space between the bumps of the drive circuit chip.

[0117] According to some embodiments of this specification, at least one pressure distribution structure can be divided into a plurality of pressure distribution patterns spaced apart from each other.

[0118] According to some embodiments of this specification, at least one pressure distribution structure may include a plurality of first pressure distribution structures positioned above and below each of a plurality of pad rows, and may further include at least one second pressure distribution structure connected to the ends of the plurality of first pressure distribution structures on at least one of the left and right sides of the plurality of pad rows.

[0119] According to some embodiments of this specification, at least one pressure distribution structure may include a buffer section and an enclosure section surrounding the buffer section.

[0120] According to some embodiments of this specification, the height of the buffer section may be even greater than the height of the enclosure section.

[0121] According to some embodiments of this specification, the buffer portion may have a bulging upper surface.

[0122] According to some embodiments of this specification, the buffer portion may be made of the same material as the organic sealing layer of the display area.

[0123] According to some embodiments of this specification, the enclosure includes a lower layer and an upper layer disposed on the lower layer, wherein the lower layer of the enclosure may be made of the same material as the bank layer of the display area, and the upper layer of the enclosure may be made of the same material as the spacer of the display area.

[0124] A display device according to an embodiment of this specification includes a substrate including a display area and a non-display area surrounding the display area; a chip pad area located in the non-display area of ​​the substrate and including a plurality of pads; a planar layer covering the edges of the plurality of pads and disposed on the substrate; a drive circuit chip disposed in the chip pad area by an anisotropic conductive film; and at least one pressure distribution structure disposed between the planar layer and the drive circuit chip, wherein the at least one pressure distribution structure is disposed between the bumps of the drive circuit chip, and the upper surface of the at least one pressure distribution structure is located closer to the upper surface of the bumps of the drive circuit chip than the lower surface of the bumps of the drive circuit chip.

[0125] According to some embodiments of this specification, some of the conductive particles of an anisotropic conductive film can simultaneously contact the upper surface of at least one pressure-distributing structure and the lower surface of a drive circuit chip.

[0126] According to some embodiments of this specification, at least one pressure distribution structure includes a buffer section and an enclosure section surrounding the buffer section.

[0127] According to some embodiments of this specification, the buffer and enclosure may be made of an organic insulating material.

[0128] According to some embodiments of this specification, the height of the buffer section may be greater than the height of the enclosure section, and the buffer section may have a bulging upper surface.

[0129] According to some embodiments of this specification, the multiple pads constitute multiple pad rows, and the at least one pressure distribution structure may be positioned adjacent to the multiple pad rows.

[0130] According to some embodiments of this specification, each pad row includes a plurality of tip pads arranged in a first direction, and at least one pressure distribution structure may extend in the first direction.

[0131] According to some embodiments of this specification, at least one pressure distribution structure can be divided into a plurality of pressure distribution patterns spaced apart from each other.

[0132] According to some embodiments of this specification, at least one pressure distribution structure may include a plurality of first pressure distribution structures positioned above and below each of a plurality of pad rows, and further include a second pressure distribution structure connected to the ends of the plurality of first pressure distribution structures on the left and right sides of the plurality of pad rows.

[0133] While the embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments, and various modifications are possible within the scope of the technical concept of this specification. Therefore, the embodiments disclosed herein are not intended to limit the technical concept of this specification, but rather to illustrate it, and the scope of the technical concept of this specification is not limited by these embodiments. Accordingly, the embodiments described above should be understood to be illustrative and not limiting in all respects. [Explanation of symbols]

[0134] DP display panel CPA Tippad Area CPD Chippad CPD1 Output Pad CPD1a 1st Output Pad CPD1b 2nd Output Pad CPD2 Input Pad PR Pad Line PDS pressure distribution structure 240 Enclosure section 254 Buffer section DIC drive circuit chip PD pad

Claims

1. A substrate including a display area and a non-display area surrounding the display area, A chip pad region located in the non-display area of ​​the substrate, in which a plurality of chip pads are arranged, A drive circuit chip mounted in the aforementioned chip pad area, The drive circuit chip is superimposed on the multi-chip pad and includes at least one pressure distribution structure positioned adjacent to the multi-chip pads, Display device.

2. The aforementioned multiple chip pads are arranged in multiple rows to constitute multiple pad rows. The display device according to claim 1.

3. Each pad row includes multiple tip pads arranged in the first direction. The at least one pressure-distributing structure extends in the first direction, The chip pad region is separated from one side of the display region in a second direction intersecting the first direction. The display device according to claim 2.

4. The at least one pressure distribution structure is positioned on a flattening layer covering the edges of the plurality of chip pads and is bonded to the drive circuit chip by an anisotropic conductive film. The display device according to claim 1.

5. Some of the conductive particles of the anisotropic conductive film are in contact with the upper surface of the at least one pressure distribution structure and the lower surface of the drive circuit chip simultaneously. The display device according to claim 4.

6. The at least one pressure distribution structure protrudes into the space between the bumps of the drive circuit chip. The display device according to claim 1.

7. The at least one pressure distribution structure is divided into a plurality of pressure distribution patterns spaced apart from each other. The display device according to claim 1.

8. The at least one pressure distribution structure is positioned adjacent to each of the plurality of pad rows. The display device according to claim 1.

9. The aforementioned at least one pressure distribution structure is A plurality of first pressure distribution structures are arranged above and below each of the plurality of pad rows in the plan view, At least one second pressure distribution structure located on at least one of the left and right sides of the plurality of pad rows in the plan view, including, The display device according to claim 8.

10. In the plan view, the at least one pressure-distributing structure is connected to the ends of the plurality of first pressure-distributing structures. The display device according to claim 9.

11. The at least one pressure distribution structure includes a buffer section and an enclosure section surrounding the buffer section. The display device according to claim 1.

12. The height of the buffer section is even greater than the height of the enclosure section. The display device according to claim 11.

13. The buffer portion has a bulging upper surface, The display device according to claim 11.

14. The buffer portion is made of the same material as the organic sealing layer of the display area. The display device according to claim 11.

15. The enclosure portion includes a lower layer and an upper layer disposed on the lower layer. The lower layer of the enclosure is made of the same material as the bank layer of the display area. The upper layer of the enclosure is made of the same material as the spacer of the display area. The display device according to claim 11.

16. A substrate including a display area and a non-display area surrounding the display area, A chip pad area located in the non-display area of ​​the substrate, which includes a plurality of pads, A planarization layer covering the edges of the plurality of pads and disposed on the substrate, A drive circuit chip mounted on the chip pad area by an anisotropic conductive film, It includes at least one pressure distribution structure disposed between the planarization layer and the drive circuit chip, The at least one pressure distribution structure is positioned between the bumps of the drive circuit chip, The upper surface of the at least one pressure distribution structure is located closer to the upper surface of the bump of the drive circuit chip than the lower surface of the bump of the drive circuit chip. Display device.

17. Some of the conductive particles of the anisotropic conductive film are in contact with the upper surface of the at least one pressure distribution structure and the lower surface of the drive circuit chip simultaneously. The display device according to claim 16.

18. The at least one pressure distribution structure includes a buffer section and an enclosure section surrounding the buffer section. The buffer section and the enclosure section are made of an organic insulating material. The display device according to claim 16.

19. The height of the buffer section is even greater than the height of the enclosure section, and the buffer section has a bulging upper surface. The display device according to claim 18.

20. In the plan view, the multiple pads are arranged in multiple pad rows, forming multiple pad rows. The at least one pressure distribution structure is positioned adjacent to the plurality of pad rows. The display device according to claim 18.

Images