Bias supply circuit and amplification circuit

Abstract

This invention provides a bias supply circuit capable of reducing transient changes in output power. [Solution] The bias supply circuit comprises a first inductor connected between a bias supply terminal that supplies a bias voltage to the amplifier and a power supply terminal connected to a power supply, a second inductor connected in series with the first inductor between the bias supply terminal and the power supply terminal and connected between the first inductor and the power supply terminal, a first capacitor shunt-connected to a first node between the first inductor and the second inductor, and a second capacitor shunt-connected to a second node between the second inductor and the power supply terminal.

Description

Technical Field

[0006] , , , , ,

[0001] The present disclosure relates to a bias supply circuit and an amplifier circuit.

Background Art

[0002] An amplifier circuit has a bias supply circuit that supplies a bias voltage to an amplifier such as a transistor. It is known to reduce a surge voltage generated in a power conversion circuit such as an inverter using an inductor (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the input power of an amplifier circuit increases rapidly, the output power may increase rapidly and then transiently decrease. Even when using an inductor as in Patent Documents 1 and 2, the transient change in the output power is not sufficiently reduced.

[0005] An object of the present disclosure is to provide a bias supply circuit and an amplifier circuit capable of reducing a transient change in output power.

Means for Solving the Problems

[0006] Embodiments of the present disclosure are bias supply circuits comprising: a first inductor connected between a bias supply terminal that supplies a bias voltage to an amplifier and a power supply terminal connected to a power supply; a second inductor connected in series with the first inductor between the bias supply terminal and the power supply terminal and connected between the first inductor and the power supply terminal; a first capacitor shunt-connected to a first node between the first inductor and the second inductor; and a second capacitor shunt-connected to a second node between the second inductor and the power supply terminal. [Effects of the Invention]

[0007] According to this disclosure, transient changes in output power can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram of the amplifier circuit according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the bias supply circuit in the first embodiment. [Figure 3] Figure 3 is a circuit diagram of the bias supply circuit for the first comparison configuration. [Figure 4] Figure 4 is a schematic diagram showing voltage, input power, and output power as a function of time in the first comparison configuration. [Figure 5] Figure 5 shows the output power as a function of time in the first comparison configuration. [Figure 6] Figure 6 is a circuit diagram of the bias supply circuit relating to the second comparison configuration. [Figure 7] Figure 7 is a schematic diagram showing the voltage against time in the second comparison mode. [Figure 8] Figure 8 is a circuit diagram of the bias supply circuit relating to the third comparison configuration. [Figure 9] Figure 9 is a schematic diagram showing the voltage against time in the third comparison configuration. [Figure 10] Figure 10 shows the output power as a function of time in the third comparison configuration. [Figure 11] FIG. 11 is a circuit diagram of a bias supply circuit according to a fourth comparative form. [Figure 12] FIG. 12 is a schematic diagram showing the voltage with respect to time in the fourth comparative form. [Figure 13] FIG. 13 is a diagram showing the output power with respect to time in the fourth comparative form. [Figure 14] FIG. 14 is a schematic diagram showing the voltage with respect to time in the first embodiment. [Figure 15] FIG. 15 is a diagram showing the output power with respect to time in the first embodiment. [Figure 16] FIG. 16 is a circuit diagram of a bias supply circuit according to a second embodiment. [Figure 17] FIG. 17 is a schematic diagram showing the voltage with respect to time in the second embodiment. [Figure 18] FIG. 18 is a circuit diagram of a bias supply circuit according to a third embodiment. [Figure 19] FIG. 19 is a plan view of an amplifier circuit according to a fourth embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0009] [Description of Embodiments of the Present Disclosure] First, the embodiments of the present disclosure will be listed and described.

[0010] (1) An embodiment of the present disclosure includes a first inductor connected between a bias supply terminal for supplying a bias voltage to an amplifier and a power supply terminal connected to a power supply, and a second inductor connected in series with the first inductor between the bias supply terminal and the power supply terminal and connected between the first inductor and the power supply terminal, a first capacitor shunt-connected to a first node between the first inductor and the second inductor, and a second capacitor shunt-connected to a second node between the second inductor and the power supply terminal. This can reduce a transient change in output power. (2) In the above (1), the bias supply terminal is connected to a node between the output terminal of the amplifier and the output terminal that outputs the high-frequency signal amplified by the amplifier, and the bias supply circuit may include a circuit for reducing leakage of the high-frequency signal to the power supply terminal between the bias supply terminal and the first inductor. Thereby, it is possible to reduce the influence of the first inductor, the second inductor, and the first capacitor on the high-frequency signal output by the amplifier. (3) In the above (1) or (2), a first resistor connected in parallel with the first inductor between the bias supply terminal and the first node, and a second resistor connected in parallel with the second inductor between the first node and the second node may be provided. Thereby, a decrease in the bias voltage can be reduced. (4) In any of the above (1) to (3), the capacitance value of the first capacitor may be smaller than the capacitance value of the second capacitor. Thereby, a transient change in the output power can be reduced. (5) In any of the above (1) to (4), the inductance of the first inductor may be smaller than the inductance of the second inductor. Thereby, a transient change in the output power can be reduced. (6) In any of the above (1) to (5), between the bias supply terminal and the power supply terminal, a third inductor connected in series with the first inductor and the second inductor and connected between the first node and the second inductor, and a third capacitor shunt-connected to a third node between the third inductor and the second inductor may be provided. Thereby, a transient change in the output power can be reduced. (7) In the above (6), a first resistor connected in parallel with the first inductor between the bias supply terminal and the first node, a second resistor connected in parallel with the second inductor between the third node and the second node, and a third resistor connected in parallel with the third inductor between the first node and the third node may be provided. Thereby, a decrease in the bias voltage can be reduced. (8) Embodiments of the present disclosure are amplification circuits comprising the bias supply circuit described in any of (1) to (7) above and the amplifier. This makes it possible to reduce transient changes in the output power of the amplification circuit. (9) In the above (8), the amplifier may operate in pulse mode. This reduces the change in output power when the output power is prone to change. (10) In (8) or (9) above, the maximum output power of the amplifier may be 100W or more. This reduces the fluctuation in output power when the output power is prone to changing.

[0011] [Details of the embodiments of this disclosure] Specific examples of bias supply circuits and amplification circuits according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples and is intended to include all modifications within the meaning and scope of the claims as indicated by the claims.

[0012] (First Embodiment) Figure 1 is a block diagram of an amplification circuit according to the first embodiment. As shown in Figure 1, the amplification circuit 100 includes an amplifier 10, bias supply circuits 11 and 12, matching circuits 16 and 18, an input terminal Tin, and an output terminal Tout.

[0013] Amplifier 10 amplifies the input signal Sin, which is input from the input terminal Tin via the matching circuit 16, and outputs the amplified signal as the output signal Sout to the output terminal Tout via the matching circuit 18. The input signal Sin and the output signal Sout are high-frequency signals, such as microwaves (300 MHz to 30 GHz) or millimeter waves (30 GHz to 300 GHz).

[0014] Amplifier 10 includes, for example, a transistor Q. Transistor Q is, for example, a FET (Field Effect Transistor) and has a source S, a gate G, and a drain D. The source S is grounded. An input signal Sin is input to the gate G. An output signal Sout is output from the drain D. Transistor Q is, for example, a GaN HEMT (Gallium Nitraide High Electron Mobility Transistor).

[0015] Matching circuit 16 matches the impedance seen from input terminal Tin to matching circuit 16 with the impedance seen from matching circuit 16 to amplifier 10. Matching circuit 18 matches the impedance seen from amplifier 10 to matching circuit 18 with the impedance seen from matching circuit 18 to output terminal Tout. Node Nin is the node between matching circuit 16 and amplifier 10. Node Nout is the node between amplifier 10 and matching circuit 18. Bias supply circuit 11 supplies a gate bias voltage from power supply 13 to node Nin, reducing leakage of the input signal Sin passing through node Nin to power supply 13. Bias supply circuit 12 supplies a drain bias voltage from power supply 14 to node Nout, reducing leakage of the input signal Sin passing through node Nout to power supply 13.

[0016] Figure 2 is a circuit diagram showing the bias supply circuit in the first embodiment. As shown in Figure 2, the bias supply circuit 12 comprises circuits 20, 24, 26, capacitor C2, power supply terminal Ts, and bias supply terminal Tb. Power supply terminal Ts is electrically connected to power supply 14 and is supplied with power supply voltage. Bias supply terminal Tb is electrically connected to node Nout and supplies bias voltage to amplifier 10.

[0017] Circuit 20 includes parallel circuits 22A and 22B and capacitor C1. Parallel circuit 22A has an inductor L1 and a resistor R1 connected in parallel between nodes Nm and N1. Parallel circuit 22B has an inductor L2 and a resistor R2 connected in parallel between nodes N1 and N2. Capacitor C1 is shunt-connected to node N1. Capacitor C2 is shunt-connected to node N2 between circuit 20 and power supply terminal Ts.

[0018] Circuit 24 includes a transmission line L4 and a capacitor C4. The first and second ends of transmission line L4 are electrically connected to the bias supply terminal Tb and node Nm, respectively. The first end of capacitor C4 is electrically connected to the node between transmission line L4 and node Nm, and the second end of capacitor C4 is electrically connected to ground. Transmission line L4 is a λ / 4 transmission line with a length of approximately λ / 4, where λ is the wavelength corresponding to the center frequency of the operating band of amplifier 10. The length of transmission line L4 may be, for example, greater than λ / 8 and less than 3λ / 8, or between 3λ / 16 and 5λ / 16. Circuit 24 reduces leakage of the output signal Sout to the power supply 14.

[0019] Circuit 26 includes capacitors C5 and C6. Capacitors C5 and C6 are connected in parallel between node Nm and ground. The capacitance values ​​of capacitors C5 and C6 are greater than the capacitance value of capacitor C4. Circuit 26 allows signals in the output signal Sout with frequencies lower than the operating bandwidth of amplifier 10 to pass to ground. Circuit 26 is optional.

[0020] (First comparative form) To explain the operation of circuit 20, a comparison configuration will be described. Figure 3 is a circuit diagram of the bias supply circuit according to the first comparison configuration. As shown in Figure 3, in the bias supply circuit 12A of the amplifier circuit 110 according to the first comparison configuration, no inductor or capacitor is provided in circuit 20A. Nodes Nm and N2 are electrically connected.

[0021] Figure 4 is a schematic diagram showing voltage, input power, and output power against time in the first comparison configuration. In Figure 4, the horizontal axis represents time t, and the vertical axis represents the voltage Vd at node Nm in Figure 3, the input power Pin at the input signal Sin, and the output power Pout at the output signal Sout.

[0022] As shown in Figure 4, during the period up to time t1, the input power Pin is small and the output power Pout is also small. The voltage Vd is voltage Vd0. Capacitor C2 is charged. During the period between times t1 and t2, the input signal Sin of power Pin0 is input as input power Pin. The output power Pout increases at time t1 but gradually decreases towards time t2. Thus, the output power Pout fluctuates when a pulsed power is input as input power Pin. This is because when amplifier 10 amplifies the input power Pin, the temperature of amplifier 10 rises. When the temperature of amplifier 10 rises, the power gain of amplifier 10 decreases, and the output power Pout decreases. As the output power Pout increases, current is supplied to amplifier 10 from the bias supply circuit 12A. When the current increases rapidly, the current supplied from power supply 14 is limited, but since current is supplied from capacitor C2 in addition to power supply 14, the voltage Vd is voltage Vd0 and remains almost constant during the period between times t1 and t2.

[0023] An 800W GaN HEMT was used as amplifier 10, and the output power Pout was measured when an input signal Sin with a frequency of 3GHz and a pulse width of 200μsec was input. The capacitance values ​​of capacitors C2, C4, C5, and C6 are 1000μF, 10pF, 1000pF, and 0.22μF, respectively. The voltage Vd0 is 50V.

[0024] Figure 5 shows the output power as a function of time in the first comparison configuration. The power Pin0 in Figure 4 is applied between 0 μsec and 200 μsec. As shown in Figure 5, the output power Pout is approximately 57.75 dBm at 0 μsec, but at 200 μsec, the output power is approximately 56.6 dBm. The difference between the maximum and minimum values ​​of the output power Pout between 0 μsec and 200 μsec is approximately 1.2 dB. Thus, in the first comparison configuration, the fluctuation of the output power Pout is large.

[0025] (Second comparative form) Figure 6 is a circuit diagram of the bias supply circuit for the second comparison configuration. As shown in Figure 6, in the bias supply circuit 12B of the amplifier circuit 112 for the second comparison configuration, circuit 20B has an inductor L1. The first and second ends of inductor L1 are connected to nodes Nm and N2, respectively. The other configurations are the same as in the first comparison configuration and are therefore omitted from the explanation.

[0026] Figure 7 is a schematic diagram showing the voltage against time in the second comparison configuration. In Figure 7, L1 Small indicates that the inductance of inductor L1 is small, and L1 Large indicates that the inductance of inductor L1 is large.

[0027] When the input power Pin increases at time t1, a current is rapidly supplied from the bias supply circuit 12B to the amplifier 10, and the current flowing through inductor L1 increases. If the current flowing through inductor L1 is I, a back electromotive force of Vd' = -L1(dI / dt) is generated. As a result, as shown in Figure 7, at time t1, the voltage Vd decreases, and then the voltage Vd gradually returns to voltage Vd0. When the inductance of inductor L1 is small, the amount of decrease ΔVd of voltage Vd from voltage Vd0 is small. Because the time constant of voltage Vd is small, the period T over which voltage Vd returns to voltage Vd0 is short. When the inductance of inductor L1 is large, the amount of decrease ΔVd of voltage Vd from voltage Vd0 is large. Because the time constant of voltage Vd is large, the period T over which voltage Vd returns to voltage Vd0 is long. Thus, if we try to lengthen the period T over which voltage Vd decreases from voltage Vd0, the amount of decrease ΔVd of voltage Vd becomes large.

[0028] (Third comparative form) Figure 8 is a circuit diagram of the bias supply circuit for the third comparison configuration. As shown in Figure 8, in the bias supply circuit 12C of the amplifier circuit 114 for the third comparison configuration, circuit 20C has a parallel circuit 22A. The parallel circuit 22A has an inductor L1 and a resistor R1 connected in parallel. The other configurations are the same as in the second comparison configuration and are omitted from the explanation.

[0029] Figure 9 is a schematic diagram showing the voltage against time in the third comparison configuration. In Figure 9, 20B and 20C represent the second and third comparison configurations, respectively. Compared to circuit 20B of the second embodiment, circuit 20C of the third embodiment can reduce the voltage drop ΔVd at time t1. This is because at time t1, current flows through resistor R1 in parallel with inductor L1.

[0030] In the third comparison configuration, the output power Pout was measured. The capacitance values ​​of capacitors C2, C4, C5, and C6 were the same as in Figure 5 of the first comparison configuration, and the inductance of inductor L1 and the resistance of resistor R1 were set to 10 μH and 0.5 Ω, respectively.

[0031] Figure 10 shows the output power as a function of time in the third comparison mode. As shown in Figure 10, in the range of 50, from 0 μsec to 40 μsec, the output power Pout is lower than in Figure 5 of the first comparison mode. This is because, as shown in Figure 9, the voltage Vd becomes lower than the voltage Vd0 after time t1. However, above 40 μsec, the decrease in output power Pout is about the same as in the first comparison mode in Figure 5. The difference between the maximum and minimum values ​​of output power Pout between 0 μsec and 200 μsec is approximately 0.5 dB. Thus, the reason why the fluctuation of output power Pout is large above 40 μsec is because the period T is short, as shown in Figure 9.

[0032] (Fourth comparative form) Figure 11 is a circuit diagram of the bias supply circuit for the fourth comparison configuration. As shown in Figure 11, in the bias supply circuit 12D of the amplifier circuit 116 for the fourth comparison configuration, circuit 20D has parallel circuits 22A and 22B. Parallel circuits 22A and 22B are connected in series between nodes Nm and N2. Parallel circuit 22B includes an inductor L2 and a resistor R2 connected in parallel. The other configurations are the same as in the third comparison configuration and are therefore omitted from the explanation.

[0033] Figure 12 is a schematic diagram showing the voltage against time in the fourth comparison configuration. In Figure 12, 20C and 20D represent the third and fourth comparison configurations, respectively. Compared to circuit 20C of the third embodiment, circuit 20D of the fourth embodiment allows for a longer period T during which the voltage Vd decreases from voltage Vd0. However, at time t1, when current begins to flow in parallel circuit 22A, current also begins to flow in parallel circuit 22B because the current is supplied from capacitor C2 and power supply 14. As a result, the back electromotive force from parallel circuit 22A and the back electromotive force from parallel circuit 22B increase the amount of voltage Vd decrease from voltage Vd0, ΔVd.

[0034] In the fourth comparison configuration, the output power Pout was measured. The capacitance values ​​of capacitors C2, C4, C5, and C6 were the same as in Figure 5 of the first comparison configuration, and the inductance of inductor L1 and the resistance of resistor R1 were set to 4.7 μH and 0.5 Ω, respectively. The inductance of inductor L2 and the resistance of resistor R2 were set to 10 μH and 0.5 Ω, respectively.

[0035] Figure 13 shows the output power as a function of time in the fourth comparison mode. As shown in Figure 13, the fluctuation of the output power Pout after 40 μsec is smaller than in Figure 5 of the first comparison mode and Figure 10 of the third comparison mode. However, in the range of 50, between 0 μsec and 20 μsec, the output power Pout is lower than the output power Pout at 200 μsec. Therefore, the difference between the maximum and minimum values ​​of the output power Pout between 0 μsec and 200 μsec is approximately 0.6 dB, which is larger than in Figure 10 of the third comparison mode. This is because the decrease in voltage Vd, ΔVd, is large, as shown in Figure 12.

[0036] (Description of the first embodiment) Figure 14 is a schematic diagram showing voltage against time in the first embodiment. In Figure 14, capacitors C1 and C2 are charged up to time t1. At time t1, current is rapidly supplied to amplifier 10 from bias supply circuit 12. In the dashed circle range 50A, current mainly flows from capacitor C1 to parallel circuit 22A. By reducing the inductance of inductor L1, the back electromotive force of parallel circuit 22A can be reduced. Due to capacitor C1, the voltage drop at node N1 is slower compared to the fourth comparison form. When the voltage at node N1 begins to drop, current flows from capacitor C2 to parallel circuit 22B in range 50B. Due to the back electromotive force of parallel circuit 22B, the voltage Vd becomes lower than voltage Vd0. In this way, by providing capacitor C1, a time difference is created in the currents flowing through parallel circuits 22A and 22B, so that the period T during which voltage Vd is decreasing from voltage Vd0 can be extended.

[0037] In the first embodiment, the output power Pout was measured. The capacitance values ​​of capacitors C2, C4, C5, and C6 were the same as in Figure 5 of the first comparison form, with the capacitance value of capacitor C1 being 120 μF, and the inductance of inductor L1 and the resistance of resistor R1 being 4.7 μH and 0.5 Ω, respectively. The inductance of inductor L2 and the resistance of resistor R2 were 10 μH and 0.5 Ω, respectively.

[0038] Figure 15 shows the output power as a function of time in the first embodiment. As shown in Figure 15, the decrease in output power Pout around 0 μsec is smaller compared to Figure 13 of the fourth embodiment. The fluctuation in output power Pout after 40 μsec is smaller than in Figure 5 of the first comparison form and Figure 10 of the third comparison form. As a result, the difference between the maximum and minimum values ​​of output power Pout between 0 μsec and 200 μsec is approximately 0.4 dB, which is smaller than in the first, third, and fourth comparison forms. This is because, in Figure 14, the decrease in voltage Vd ΔVd was appropriately reduced, and the period T during which voltage Vd decreases from voltage Vd0 was appropriately extended. Thus, in the first embodiment, transient phenomena of output power Pout can be reduced by appropriately setting the capacitance values ​​of capacitors C1 and C2, the inductance of inductors L1 and L1, and the resistance values ​​of resistors R1 and R2.

[0039] (Second Embodiment) Figure 16 is a circuit diagram of the bias supply circuit according to the second embodiment. As shown in Figure 16, in the bias supply circuit 12E of the amplifier circuit 102 according to the second embodiment, circuit 20E has parallel circuits 22A, 22B and 22C. Parallel circuit 22C is connected in series with parallel circuits 22A and 22B between nodes Nm and N2, and is connected between parallel circuits 22A and 22B. Parallel circuit 22C has an inductor L3 and a resistor R3 connected in parallel. Capacitor C3 is shunt-connected to node N3 between parallel circuits 22C and 22B. The other configurations are the same as in the first embodiment and are omitted from the description.

[0040] Figure 17 is a schematic diagram showing the voltage as a function of time in the second embodiment. As shown in Figure 17, by connecting the parallel circuits 22A to 22C in series, the period T during which the voltage Vd decreases from the voltage Vd0 can be made longer compared to Figure 14 of the first embodiment. In the third embodiment, three or more parallel circuits 22A to 22C may be provided, and three or more capacitors C1 to C3 may be provided.

[0041] (Third embodiment) Figure 18 is a circuit diagram of the bias supply circuit according to the third embodiment. As shown in Figure 18, in the bias supply circuit 12F of the amplifier circuit 104 according to the third embodiment, circuit 20F has inductors L1, L2 and capacitor C1, but does not have resistors R1 and R2. The other configurations are the same as in the first embodiment and will not be described. As in the third embodiment, if the amount of voltage Vd drop from voltage Vd0 is appropriate, at least one of resistors R1 and R2 may not be provided. In the second embodiment, at least one of resistors R1 to R3 connected between nodes Nm and N2 may not be provided.

[0042] (Fourth Embodiment) The fourth embodiment is an example in which the bias supply circuit of the first embodiment is provided on a substrate. Figure 19 is a plan view of the amplifier circuit according to the fourth embodiment. As shown in Figure 19, the amplifier circuit 106 according to the fourth embodiment includes a substrate 30, semiconductor components 32, inductor components 34A, 34B, resistor components 35A, 35B, capacitor components 36A, 36B, 36C, transmission lines 31, and matching circuit 18.

[0043] The substrate 30 is an insulating substrate, such as a glass epoxy resin substrate or a ceramic substrate. The semiconductor component 32, inductor components 34A and 34B, resistor components 35A and 35B, and capacitor components 36A, 36B, and 36C are mounted on the substrate 30. The semiconductor component 32 corresponds to the amplifier 10 having a transistor. The inductor components 34A and 34B correspond to inductors L1 and L2, respectively. The resistor components 35A and 35B correspond to resistors R1 and R2, respectively. The capacitor components 36A, 36B, and 36C correspond to capacitors C1, C2, and C4, respectively. The transmission line 31 is a metal layer formed on the substrate 30 and electrically connects the semiconductor component 32, inductor components 34A and 34B, resistor components 35A and 35B, and capacitor components 36A, 36B, and 36C. A portion of the transmission line 31A corresponds to transmission line L4.

[0044] The bias supply circuit 12 includes circuit 20, capacitor components 36B and 36C, transmission line 31A, and power terminal Ts. Circuit 20 includes inductor components 34A and 34B, resistor components 35A and 35B, and capacitor component 36A. As in the fourth embodiment, the bias supply circuits of the first to third embodiments may be provided on the substrate 30.

[0045] According to the first to fourth embodiments, as shown in Figures 2 and 18, inductor L1 (first inductor) is connected between the bias supply terminal Tb and the power supply terminal Ts. Inductor (second inductor) is connected in series with inductor L1 between the bias supply terminal Tb and the power supply terminal Ts, and is connected between inductor L1 and the power supply terminal Ts. Capacitor C1 (first capacitor) is shunt-connected to node N1 (first node) between inductors L1 and L2. Capacitor C2 (second capacitor) is shunt-connected to node N2 (second node) between inductor L2 and the power supply terminal Ts. As a result, as shown in Figure 14, when the input power Pin of the input signal Sin increases rapidly, the voltage Vd decreases, and then the voltage Vd gradually returns to voltage Vd0. Therefore, transient changes in output power Pout can be reduced even when the temperature of amplifier 10 rises. By appropriately setting the capacitance values ​​of capacitors C1 and C2, and the inductances of inductors L1 and L2, optimization is easily achieved to reduce the fluctuation of output power Pout compared to the first to fourth comparison configurations.

[0046] As shown in Figures 1 and 2, the bias supply terminal Tb is connected to the node between the output terminal and output terminal Tout of amplifier 10. Circuit 24 reduces leakage of high-frequency signals to the power supply terminal Ts between the bias supply terminal Tb and inductor L1. This reduces the influence of inductors L1, L2 and capacitor C1 on the high-frequency signal output by the amplification circuit 100.

[0047] As shown in Figure 2, resistor R1 (first resistor) is connected in parallel with inductor L1 between the bias supply terminal Tb and node N1. Resistor R2 (second resistor) is connected in parallel with inductor L2 between nodes N1 and N2. This reduces the drop in voltage Vd from voltage Vd0.

[0048] In the range 50A shown in Figure 14, current is supplied from capacitor C1 to inductor L1, and in the range 50B, current is supplied from capacitor C2 to inductors L1 and L2. From this perspective, the capacitance value of capacitor C1 can be smaller than the capacitance value of capacitor C2. The capacitance value of capacitor C1 can be 1 / 2 or less of the capacitance value of capacitor C2, and can also be 1 / 5 or less.

[0049] From the perspective of minimizing the drop in voltage Vd from voltage Vd0 in the range of 50A, the inductance of inductor L1 can be made smaller than the inductance of inductor L2. The inductance of inductor L1 can be 3 / 4 or less of the inductance of inductor L2, and can also be 1 / 2 or less.

[0050] The capacitance value of capacitor C1 may be greater than the capacitance value of capacitor C2, and the inductance of inductor L1 may be greater than the inductance of inductor L2.

[0051] As shown in Figure 16 of the second embodiment, inductor L3 (third inductor) is connected in series with inductors L1 and L2 between the bias supply terminal Tb and the power supply terminal Ts, and is connected between node N1 and inductor L2. Capacitor C3 (third capacitor) is shunt-connected to node N3 (third node) between inductors L3 and L2. As a result, as shown in Figure 17, the time it takes for the voltage Vd to drop from voltage Vd0 can be extended. Therefore, even when the pulse width of the input signal Sin is large, the fluctuation of the output power Pout can be reduced.

[0052] Resistor R3 (the third resistor) is connected in parallel with inductor L3 between nodes N1 and N3. This reduces the voltage drop of Vd from voltage Vd0.

[0053] The capacitance values ​​of capacitor C1 and capacitor C3 may be smaller than the capacitance value of capacitor C2. Also, the inductances of inductor L1 and inductor L3 may be smaller than the inductance of inductor L2.

[0054] The capacitance values ​​of capacitors C1 and C3 are, for example, between 10 μF and 500 μF. The capacitance value of capacitor C2 is, for example, between 100 μF and 5000 μF. The inductances of inductors L1 to L3 are, for example, between 0.1 μH and 100 μH. The resistance values ​​of resistors R1 to R3 are, for example, between 0.05 Ω and 10 Ω. The capacitance values ​​of capacitors C1 to C3, the inductances of inductors L1 to L3, and the resistance values ​​of resistors R1 to R3 can be appropriately designed to minimize fluctuations in output power Pout.

[0055] As shown in Figure 4, when amplifier 10 operates in pulse mode, the output power Pout is prone to fluctuations. Therefore, inductors L1 and L2, and capacitors C1 and C2 are provided. When amplifier 10 operates in pulse mode, the rise time of the input power is, for example, 10 μsec or less. The pulse width is, for example, 50 μsec or more and 5 msec or less.

[0056] When the output power Pout of amplifier 10 is large, amplifier 10 generates heat, and the output power Pout tends to fluctuate. Therefore, inductors L1, L2 and capacitors C1 and C2 are provided when the maximum output power of amplifier 10 is 100W or more, 200W or more, or 500W or more.

[0057] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications in the sense and scope equivalent to the claims are intended. [Explanation of symbols]

[0058] 10 Amplifiers 11, 12, 12A, 12B, 12C, 12D, 12E, 12F Bias supply circuit 13, 14 Power supply 16, 18 matching circuit Circuits 20, 20A, 20B, 20C, 20D, 20E, 20F, 24, 26 22A, 22B, 22C parallel circuit 30 circuit boards 31, 31A track 32 Semiconductor Components 34A, 34B Inductor Components 35A, 35B Resistor Components 36A, 36B, 36C Capacitor Components Ranges 50, 50A, 50B 100, 102, 104, 106, 110, 112, 114, 116 amplification circuit C1 (first capacitor), C2 (second capacitor), C3 (third capacitor) Capacitors L1 (first inductor), L2 (second inductor), L3 (third inductor) Inductors L4 track R1 (1st resistance), R2 (2nd resistance), R3 (3rd resistance) Resistance N1 (1st node), N2 (2nd node), N3 (3rd node) Nodes Ts power terminal Tb bias supply terminal Tin input terminal Tout output terminal

Claims

1. A first inductor is connected between the bias supply terminal that supplies a bias voltage to the amplifier and the power supply terminal that is connected to the power supply, Between the bias supply terminal and the power supply terminal, a second inductor is connected in series with the first inductor, and between the first inductor and the power supply terminal, A first capacitor is shunt-connected to the first node between the first inductor and the second inductor, A second capacitor is shunt-connected to the second node between the second inductor and the power supply terminal, A bias supply circuit equipped with this.

2. The bias supply terminal is connected to the node between the output terminal of the amplifier and the output terminal that outputs the high-frequency signal amplified by the amplifier. The bias supply circuit includes a circuit between the bias supply terminal and the first inductor to reduce leakage of the high-frequency signal to the power supply terminal. The bias supply circuit according to claim 1.

3. A first resistor connected in parallel with the first inductor between the bias supply terminal and the first node, A second resistor connected in parallel with the second inductor between the first node and the second node, A bias supply circuit according to claim 1 or claim 2, comprising:

4. The bias supply circuit according to claim 1 or claim 2, wherein the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.

5. The bias supply circuit according to claim 1 or claim 2, wherein the inductance of the first inductor is smaller than the inductance of the second inductor.

6. Between the bias supply terminal and the power supply terminal, a third inductor is connected in series with the first inductor and the second inductor, and is connected between the first node and the second inductor. A third capacitor is shunt-connected to the third node between the third inductor and the second inductor, A bias supply circuit according to claim 1 or claim 2, comprising:

7. A first resistor connected in parallel with the first inductor between the bias supply terminal and the first node, A second resistor connected in parallel with the second inductor between the third node and the second node, A third resistor connected in parallel with the third inductor between the first node and the third node, The bias supply circuit according to claim 6, comprising:

8. A bias supply circuit according to claim 1 or claim 2, The aforementioned amplifier, An amplification circuit equipped with the following features.

9. The amplifier is a pulse-operated amplifier circuit according to claim 8.

10. The amplification circuit according to claim 8, wherein the maximum output power of the amplifier is 100W or more.

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