Bipolar decoder for non-volatile memory with spike attenuation for threshold selector switch

Abstract

The present invention provides a non-volatile memory device and method. [Solution] A memory system 100 comprising a controller 102, a non-volatile memory 104 for storing data, and a local memory 106, wherein the controller comprises a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. The FEP circuit and BEP circuits operate in a master-slave configuration, with the FEP circuit being the master and each BEP circuit being a slave. The non-volatile memory comprises a plurality of memory packages. Each memory package comprises one or more memory dies. The controller then communicates with a host 120, which includes a host processor 122, host memory 124, and PCIe interface 126 connected along a bus 128, using a PCIe interface 130 connected to one or more non-volatile memory dies.

Description

[Technical Field]

[0001] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory can store and retain information even when not connected to a power source (e.g., a battery).

[0002] An example of non-volatile memory is magnetoresistive random-access memory (MRAM), which uses magnetization to represent stored data, in contrast to some other memory technologies that use electric charge to store data. Generally, MRAM consists of a number of magnetic memory cells formed on a semiconductor substrate, each memory cell representing (at least) one bit of data. Bits of data are written to the memory cell by changing the direction of magnetization of the magnetic elements within the memory cell, and bits are read out by measuring the resistance of the memory cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). As used herein, the direction of magnetization is the direction in which the magnetic moment is oriented.

[0003] Some non-volatile memory arrays are arranged in a crosspoint configuration where word lines extend perpendicularly to bit lines, and memory cells are formed at their intersections. Some crosspoint memory arrays have two or more stories or levels of memory cells.

[0004] Read / write circuits may be used to read data from and write data to non-volatile memory cells. Data may be read by sensing current or voltage at a sensing node while current flows through a selected memory cell. Sensing amplifiers may be provided to perform sensing. Sensing amplifiers and / or other read / write circuits may occupy a considerable area on the memory die. Efficient design may reduce the area occupied by sensing amplifiers and / or other circuits. [Brief explanation of the drawing]

[0005] Elements with similar numbering refer to common components in different drawings. [Figure 1] This is a block diagram of one embodiment of a memory system connected to a host. [Figure 2] This is a block diagram of one embodiment of a memory package. [Figure 3] This is a block diagram of one embodiment of a memory die. [Figure 4] This is a block diagram of one embodiment of an integrated memory assembly. [Figure 5] An example of a sense amplifier is shown. [Figure 6] An example of a memory access operation (read operation) is shown. [Figure 7A] A perspective view shows one embodiment of a memory array that forms a crosspoint architecture. [Figure 7B] Figure 7A shows a side view and a top view of the cross point structure, respectively. [Figure 7C] Figure 7A shows a side view and a top view of the cross point structure, respectively. [Figure 7D] A perspective view shows one embodiment of a two-level memory array that forms a crosspoint architecture. [Figure 8] This shows one embodiment of the structure of an MRAM memory cell. [Figure 9]A particular embodiment of an MRAM memory cell design implemented in a cross-point array is shown in more detail. [Figure 10A] Writing of an MRAM memory cell by use of a spin torque transfer (STT) mechanism is shown. [Figure 10B] Writing of an MRAM memory cell by use of a spin torque transfer (STT) mechanism is shown. [Figure 11] An embodiment including a threshold switching selector within an MRAM memory array having a cross-point architecture is shown. [Figure 12A] Reading of an MRAM cell is shown. [Figure 12B] Reading of an MRAM cell is shown. [Figure 13A] The flow of current in the read operation of different stories in a multi-story non-volatile memory structure is shown. [Figure 13B] The flow of current in the read operation of different stories in a multi-story non-volatile memory structure is shown. [Figure 14A] An example including different sense amplifiers for different stories is shown. [Figure 14B] An example including different sense amplifiers for different stories is shown. [Figure 15A] Aspects of the present technology including a sense amplifier and a control circuit configured to enable the sense amplifier to read non-volatile memory cells of different stories are shown. [Figure 15B] Aspects of the present technology including a sense amplifier and a control circuit configured to enable the sense amplifier to read non-volatile memory cells of different stories are shown. [Figure 15C] Aspects of the present technology including a sense amplifier and a control circuit configured to enable the sense amplifier to read non-volatile memory cells of different stories are shown. [Figure 16] An example of a memory die including a common sense amplifier is shown. [Figure 17] A part of a data storage system according to an example of the present technology is shown. [Figure 18A] An example of a method is shown which involves connecting a sensing amplifier to the bit line and word line according to the story in which the non-volatile memory cells are located. [Figure 18B] This example demonstrates using the same sensing amplifier to sense non-volatile memory cells in different stories. [Figure 19A] An embodiment of a bipolar decoder is presented, with two figures showing different parts of the circuit, both constituting an embodiment of the circuit. [Figure 19B] An embodiment of a bipolar decoder is presented, with two figures showing different parts of the circuit, both constituting an embodiment of the circuit. [Figure 20] This is a schematic diagram of a memory cell formed from an ovonic threshold switch (OTS) or other threshold selector switch and a programmable resistor memory cell. [Figure 21] This shows the current spikes and resulting snapback that occur when the OTS (Over-the-Screen Switch) is activated. [Figure 22A] These indicate the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cells before the OTS is activated. [Figure 22B] These indicate the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cells before the OTS is activated. [Figure 23A] These indicate the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cell when the OTS first activates. [Figure 23B] These indicate the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cell when the OTS first activates. [Figure 24A] These indicate the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cells after the OTS has been operating for a certain interval. [Figure 24B]These indicate the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cells after the OTS has been operating for a certain interval. [Figure 25A] As shown in Figures 22A and 22B, the array and address decoder that drive the selected local word line and selected local bit line are shown before the threshold switching selector is activated. [Figure 25B] As shown in Figures 22A and 22B, the array and address decoder that drive the selected local word line and selected local bit line are shown before the threshold switching selector is activated. [Figure 26A] As shown in Figures 24A and 24B, the array and address decoder that drive the selected local word line and selected local bit line are shown after the threshold switching selector has been activated. [Figure 26B] As shown in Figures 24A and 24B, the array and address decoder that drive the selected local word line and selected local bit line are shown after the threshold switching selector has been activated. [Figure 27] This demonstrates the spike attenuation and snapback mitigation effect on the current Icell and voltage levels passing through the memory cell. [Figure 28] To reduce the impact when a threshold selector switch is activated, one embodiment is shown in which local selection gates for the bit and word lines of the selected memory cell use regulators to apply lower gate drives. [Figure 29] One embodiment is shown in which multiple levels of adjustment can be applied to the gate of a local word line selection transistor. [Figure 30] This is a flowchart of one embodiment for a read operation, for example, to access MRAM memory cells within a crosspoint array structure. [Modes for carrying out the invention]

[0006] In a memory array with a crosspoint architecture, a first set of conductive wires (e.g., word wires or WLs) extends across the surface of the substrate, and a second set of conductive wires (e.g., bit wires or BLs) extends on the substrate perpendicular to the first set of conductive wires. Memory cells are located at the crosspoint junctions of the two sets of conductive wires. Embodiments of memory cells may include programmable resistive elements, such as MRAM elements, which can be connected in series with a selector switch (selector) in the crosspoint memory structure.

[0007] In some memory structures, including crosspoint MRAM memory structures, memory cells may be formed in two or more stories (e.g., a first story formed between the first word line layer and the bit line layer, and a second story formed between the bit line layer and the second word line layer). Accessing memory cells in such structures can be difficult. For example, if the current direction is the same in both layers (e.g., current flows upward through the memory cell), the current flows from the word line to the bit line in the first story and from the bit line to the word line in the second story. This may require dedicated circuitry for each story (e.g., a sense amplifier).

[0008] In MRAM and other memory cell technologies that use threshold selector switches, such as obonic threshold switches, when accessing a selected memory cell for read operations, the voltage across the memory cell must be sufficient to turn on the threshold selector switch. This results in a current spike that can damage the memory cell and disrupt the data value written to it. To mitigate such spikes, local selector switches biasing the selected word line and selected bit line may be biased to limit the current flow from the decoding circuit when the threshold selector switch is turned on.

[0009] Figure 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. The memory system 100 can implement the techniques presented herein for managing the error rate. Many different types of memory systems can be used with the techniques proposed herein. Exemplary memory systems include solid-state drives ("SSDs"), memory cards containing dual in-line memory modules (DIMMs) for DRAM replacement, and embedded memory devices. However, other types of memory systems may also be used.

[0010] The memory system 100 in Figure 1 comprises a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 comprises a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, the FEP circuit 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, the integrated controller ASIC can combine both front-end and back-end functions. The ASICs for the BEP circuits 112 and the FEP circuits 110, respectively, are implemented on the same semiconductor so that the controller 102 is manufactured as a system-on-a-chip ("SoC"). Both the FEP circuits 110 and the BEP circuits 112 include their own processors. In one embodiment, the FEP circuit 110 and BEP circuits 112 operate in a master-slave configuration, with the FEP circuit 110 being the master and each BEP circuit 112 being a slave. For example, the FEP circuit 110 implements a flash translation layer (FTL) or media management layer (MML) that performs memory management (e.g., garbage collection, wear leveling), logic address to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuits 112 manage memory operations on the memory package / die as required by the FEP circuit 110. For example, the BEP circuits 112 can perform read, erase, and programming processes. Furthermore, the BEP circuits 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), and control the toggle-mode interface to the memory package. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages.

[0011] In one embodiment, the non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Thus, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die within the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as resistive random-access memory (ReRAM, MRAM, FeRAM, or RRAM, etc.) or storage class memory (SCM) based on phase-change memory (PCM). In other embodiments, BEP or FEP may be included on the memory die.

[0012] The controller 102 communicates with the host 120, for example, via an interface 130 that implements protocols such as NVM Express (NVMe) or Compute Express Link (CXL) over PCI Express (PCIe), or using a JEDEC standard double data rate or low-power double data rate (DDR or LPDDR) interface such as DDR5 or LPDDR5. To cooperate with the memory system 100, the host 120 includes a host processor 122 connected along a bus 128, host memory 124, and a PCIe interface 126. The host memory 124 is the host's physical memory and can be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage device. The host 120 is external to and isolated from the memory system 100. In one embodiment, the memory system 100 is integrated into the host 120.

[0013] Figure 2 is a block diagram of one embodiment of a memory package 104 including a plurality of memory dies 292 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 is connected to a toggle mode interface 296 for communicating with the TM interface of a BEP circuit. In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one embodiment, each memory package includes eight or sixteen memory dies. However, other numbers of memory dies may also be implemented. In another embodiment, the toggle interface is instead a JEDEC standard DDR or LPDDR with or without variations such as a relaxed time set or a smaller page size. The techniques described herein are not limited to any particular number of memory dies.

[0014] Figure 3 is a block diagram showing an example of a memory system 500 that can implement the technology described herein. The memory system 500 includes a memory array 502 which may include any of the memory cells described below. The array terminal lines of the memory array 502 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations may also be implemented. The memory system 500 includes a row control circuit 520 connected to each word line of the memory array 502 via line 508. The row control circuit 520 receives row address signals and one or more various control signals from the system control logic 560 and may typically include circuits such as a row decoder 522 and a word line (WL) driver 524 for both read and write operations.

[0015] The memory system 500 also includes a column control circuit 510, the input / output 506 of which is connected to each bit line of the memory array 502. Although only a single block is shown for the memory array 502, the memory die may include multiple arrays or “tiles” that can be accessed individually. The column control circuit 510 receives column address signals and one or more different control signals from the system control logic 560 and may typically include circuits such as a column decoder 512, a bit line (BL) driver 514, and a read / write (R / W) circuit 516, which may include, for example, a sensing amplifier for reading.

[0016] The system control logic 560 receives data and commands from the host and provides output data and status to the host. In other embodiments, the system control logic 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host. In some embodiments, the system control logic 560 may include a state machine that provides die-level control of memory operation. In one embodiment, the state machine is programmable by software. In other embodiments, the state machine does not use software and is fully implemented in hardware (e.g., electrical circuitry). In another embodiment, the state machine is replaced by a microcontroller, which may be on or off the memory chip. The system control logic 560 may also include a power control module that controls the power and voltage supplied to the rows and columns of the memory array 502 during memory operation and may include charge pump and regulator circuits for generating regulated voltages. The system control logic 560 may include one or more state machines, registers, and other control logic for controlling the operation of the memory system 500.

[0017] In some embodiments, all elements of the memory system 500, including the system control logic 560, may be formed as part of a single die (for example, the memory die 292 in Figure 2). In other embodiments, some or all of the system control logic 560 may be formed on different dies.

[0018] For the purposes of this specification, the phrase "one or more control circuits" may include other control circuits represented by the controller, state machine, microcontroller, and / or system control logic 560, and / or other similar circuits used to control non-volatile memory.

[0019] In one embodiment, the memory structure 502 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed on a single substrate such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions located on a silicon (or other type) substrate. In another embodiment, the memory structure 502 includes a two-dimensional memory array of non-volatile memory cells.

[0020] The exact type of memory array architecture or memory cell included in memory structure 502 is not limited to any specific example. Many different types of memory array architectures or memory technologies can be used to form memory structure 502. Examples of suitable technologies for memory cells in memory structure 502 include NAND flash memory, ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, and phase-change memory (e.g., PCM). Examples of suitable technologies for memory cell architectures in memory structure 502 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, and vertical bit-line arrays.

[0021] An example of a ReRAM crosspoint memory includes a reversible resistive switching element arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. Conductive bridge memory elements are sometimes called programmable metallization cells. Conductive bridge memory elements can be used as state change elements based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature rises, the mobility of ions also increases, reducing the programming threshold of the conductive bridge memory cell. Thus, conductive bridge memory elements can have a wide programming threshold with respect to temperature.

[0022] Another example is magnetoresistive random-access memory (MRAM), which stores data using magnetic memory elements. The element is formed from two ferromagnetic layers, each capable of holding a magnetization separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity, and the magnetization of the other layer can be changed to match the magnetization of an external magnetic field for memory storage. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is positioned perpendicular to each other, parallel to the cell, one above the cell and one below the cell, between a pair of write lines. As current passes through them, an induced magnetic field is generated. Embodiments of MRAM-based memory are described in more detail below.

[0023] Phase-change memory (PCM) utilizes the inherent behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the coordination state of germanium atoms using programming current pulses. Note that the use of “pulse” as herein does not require a square wave and includes (continuous or discontinuous) oscillations or bursts of sound, current, voltage, light, or other waves. The memory elements within each selectable memory cell or bit may include further series elements, such as an obonic threshold switch or a selector such as a metal-insulating substrate.

[0024] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather cover many related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0025] The elements in Figure 3 can be grouped into two parts: the memory structure 502 (including the memory cells) and the peripheral circuitry, which includes all other elements. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die of the memory system 500 allocated to the memory structure 502. However, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose very strict limitations on these peripheral elements. For example, the need to fit the sensing amplifier circuitry within the available area can be a significant constraint on the sensing amplifier design architecture. With respect to the system control logic 560, the reduction in area availability can limit the available functions that can be implemented on-chip. Therefore, the fundamental trade-off in the design of the memory die for the memory system 500 is the amount of area allocated to the memory structure 502 versus the amount of area allocated to the peripheral circuitry.

[0026] Another area where the memory structure 502 and peripheral circuits often conflict lies in the processing involved in forming these areas, as these areas often involve different processing techniques and involve trade-offs in having different techniques on a single die. For example, if the memory structure 502 is NAND flash, it is an NMOS structure, but the peripheral circuits are often CMOS-based. For example, elements such as sensing amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 560 often use PMOS devices. The processing operations for manufacturing CMOS dies differ in many ways from the processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0027] To overcome these limitations, the embodiments described below allow the elements of Figure 3 to be separated onto separately formed dies, which are then joined together. More specifically, the memory structure 502 can be formed on one die, and some or all of the peripheral circuit elements, including one or more control circuits, can be formed on separate dies. For example, the memory die may be formed solely from memory elements such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or arrays of memory cells of other memory types. Some or all of the peripheral circuits, even if they include elements such as decoders and sensing amplifiers, can be moved to separate dies. This allows each memory die to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements moved onto separate peripheral circuit dies that can be optimized for CMOS processing. This allows for more space for peripheral elements and can incorporate additional capabilities that could not be easily incorporated when limited to the margins of the same die holding the memory cell array. The two dies can then be joined together in a joined multi-die memory circuit, with the array on one die connected to the peripheral elements on the memory circuit of the other die. While the following focuses on a joined memory circuit with one memory die and one peripheral die, other embodiments may utilize more dies, such as two memory dies and one peripheral die.

[0028] Figure 4 shows an alternative arrangement to the arrangement in Figure 3, which may be implemented using wafer-to-wafer bonding to provide bonded die pairs for the integrated memory assembly 600. Figure 4 shows an example of peripheral circuits, including control circuits, coupled to a memory structure 602 formed within the memory die 601 or formed within the control die 611. Similar to 502 in Figure 3, the memory die 601 may contain multiple independently accessible arrays or “tiles”. Common components are labeled as in Figure 3 (e.g., 502 is here 602, 510 is here 610, etc.). It can be seen that the system control logic 660, row control circuit 620, and column control circuit 610 (which may be formed by a CMOS process) are located within the control die 611. Additional elements, such as functions from the controller 102, can also be moved to the control die 611. The system control logic 660, row control circuit 620, and column control circuit 610 may be formed by a common process (e.g., a CMOS process), and as a result, additional elements and functions more typically found on the memory controller 102 may require little or no additional process steps (i.e., the same process steps used to manufacture the controller 102 may also be used to manufacture the system control logic 660, row control circuit 620, and column control circuit 610). Therefore, moving such circuitry from a die such as the memory die of the memory system 500 may reduce the number of steps required to manufacture such a die, while adding such circuitry to a die such as the control die 611 may require no additional process steps at all.

[0029] Figure 4 shows a column control circuit 610 on a control die 611 coupled to a memory structure 602 on a memory die 601 via an electrical path 606. For example, the electrical path 606 may provide electrical connections between the column decoder 612, driver circuit 614, and R / W circuit 616 and the bit lines of the memory structure 602. The electrical path may extend from the column control circuit 610 in the control die 611 through pads on the control die 611 bonded to corresponding pads on the memory die 601 connected to the bit lines of the memory structure 602. Each bit line of the memory structure 602 may have a corresponding electrical path in the electrical path 606, which includes a pair of bonding pads connected to the column control circuit 610. Similarly, a row control circuit 620, including a row decoder 622, array driver 624, and block selector 626, is coupled to the memory structure 602 via an electrical path 608. Each electrical path 608 may correspond to a word line, dummy word line, or selector gate line. An additional electrical path may be provided between the control die 611 and the memory die 601.

[0030] In relation to Figure 3, the on-die control circuit in Figure 4 can include additional features within its logic elements, including both more general capabilities and some CPU capabilities than those typically found in the memory controller 102, but it can also include application-specific features.

[0031] Hereinafter, the system control logic 560 / 660, column control circuits 510 / 610, row control circuits 520 / 620, and / or controller 102 (or equivalent circuits) may be considered as part of one or more control circuits that perform the functions described herein, in combination with all or a subset of the other circuits shown in Figure 3, or on the control die 611 in Figure 4. A control circuit may consist of hardware only, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, integrated circuit, or other types of circuitry.

[0032] In the following description, the memory arrays 502 / 602 in Figures 3 and 4 are described primarily in the context of a crosspoint architecture, but much of the description can be applied more generally. The following description mainly focuses on embodiments based on a crosspoint architecture using MRAM memory cells, but much of the description can be applied more generally to non-volatile memory cells.

[0033] Figure 5 shows an example of a sensing amplifier 570 (for example, in a read / write circuit 516 or 616). Figure 5 shows a sensing node 572 which can be connected to a selected non-volatile memory cell (for example, via a selected bit line which can be selected by a column decoder 512 or 612). A current mirror 574 connected to a supply voltage VNN controls the current flowing through the selected non-volatile memory cell during sensing. The sensing amplifier 570 includes a comparator 576 that receives a voltage from the sensing node 572 and compares it to a reference voltage (Vref) from a reference voltage source 578. For example, the comparator 576 may generate a digital output (logic 1 or 0) depending on whether the voltage at the sensing node 572 is higher or lower than the reference voltage. The digital output from the comparator 576 is latched to a data latch 580 and output as sensing data.

[0034] Figure 6 illustrates a read operation for a selected memory cell 680 located at the intersection of a selected word line 682 and a selected bit line 684 (for example, in structure 502 / 602). The word line driver 542 generates a first supply voltage VPP (e.g., a positive voltage), which is then applied to the word line 682 selected by the row decoder 522. The column decoder 512 selects the bit line 684 and connects it to a sensing node 572, where a voltage is sensed by the sensing amplifier 570 as current flows through a current mirror that receives a second supply voltage VNN (e.g., a negative voltage) from the bit line driver 514. The sensing amplifier 570 can sense the state of the selected memory cell 680 from the voltage at the sensing node 572 while a predetermined current flows through the selected memory cell 680 from the current mirror 574.

[0035] Figure 7A is a perspective view showing one embodiment of a portion of a memory array forming a crosspoint architecture. The memory array 502 / 602 in Figure 7A is an example of an implementation of the memory array 502 in Figure 3 or the memory array 602 in Figure 4, and the memory die can include multiple such array structures. The bit lines BL1-BL5 are arranged in a first direction (e.g., the “bit line direction” as expressed to extend within a page) with respect to the substrate (not shown) beneath the die, and the word lines WL1-WL5 are arranged in a second direction (e.g., the “word line direction” as expressed to extend within a page) perpendicular to the first direction (across a page). Figure 7A is an example of a horizontal crosspoint structure in which both the word lines WL1-WL5 and BL1-BL5 extend horizontally with respect to the substrate, and two of these memory cells, indicated by 701, carry current (I cell The lines (as shown in the diagram) are oriented to flow vertically. In a memory array with additional layers of memory cells, as described below with respect to Figure 7D, there are corresponding additional layers of bit lines and word lines.

[0036] As shown in Figure 7A, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 may include rewritable memory cells, such as those that can be implemented using ReRAM, MRAM, PCM, FeRAM, or other materials having programmable resistance. The current in the memory cell at the first memory level is indicated by arrow I cell Although it is shown as flowing upwards, as illustrated by [the diagram], current can flow in any direction, as will be explained in more detail below.

[0037] Figures 7B and 7C show the side and top views, respectively, of the crosspoint structure in Figure 7A. The side view in Figure 7B shows one lower wire or word line WL1 and upper wires or bit lines BL1~BL n This shows that PCM, FeRAM, ReRAM, or other technologies may be used, but each crosspoint between the upper and lower wires contains an MRAM memory cell. Figure 7C shows M lower wires WL1~WL Mand N upper wires BL1 to BL N is a top view showing a cross-point structure for. In the binary embodiment, the MRAM cells at each cross-point can be programmed to one of two resistive states, namely, high and low. Further details regarding embodiments for MRAM memory cell design and techniques for their programming are given below.

[0038] The cross-point array of FIG. 7A has one layer (one story) of word lines and bit lines and shows an embodiment where MRAM or other memory cells are located at the intersections of two sets of conductive lines. To increase the storage density of the memory die, multiple layers (stories) of such memory cells and conductive lines can be formed. An example of two layers (two stories) is shown in FIG. 7D.

[0039] <L FIG. 7D shows a perspective view of an embodiment of a portion of a two-level (two-story) memory array forming a cross-point architecture. Similar to FIG. 7A, FIG. 7D shows the first layer 718 (the first story) of the memory cells 701 of the array 502 / 602 connected at the cross-points of the first layer of word lines WL 1,1 to WL 1,4 and bit lines BL1 to BL5. The second layer (the second story) of the memory cells 720 is above the bit lines BL1 to BL5 and is formed between these bit lines and a second set of word lines WL 2,1 to WL 2,4 FIG. 7D shows two layers (stories) 718 and 720 of memory cells, but this structure can be extended upward through additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array of FIG. 7D can be biased for read or program operations such that the current within each layer flows from the word line layer to the bit line layer or vice versa.

[0040] The use of a crosspoint architecture enables arrays with a small footprint, and several such arrays can be formed on a single die. Memory cells formed at each intersection may be resistive memory cells in which data values ​​are encoded as different resistance levels. Depending on the embodiment, the memory cells may be binary values ​​having either a low-resistance state or a high-resistance state, or they may be multilevel cells (MLCs) that may have additional resistance between the low-resistance and high-resistance states. The crosspoint array described herein may be used as memory die 292 in Figure 4 to replace local memory 106, or both.

[0041] Figure 8 shows one embodiment of the structure of an MRAM memory cell. The voltage applied across the memory cell between the corresponding word line and bit line of the memory cell is the voltage source V app Represented as 813, the memory cell includes a lower electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by an isolation or tunneling layer of magnesium oxide (MgO) 805 in this example, and an upper electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 803 and the free layer 807. If the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low-resistance state (LRS), and if they have opposite orientations, the memory cell is in an antiparallel (AP) high-resistance state (HRS). Embodiments of the MLC include additional intermediate states. The orientation of the reference layer 803 is fixed and is upward in the example in Figure 15. The reference layer 803 is also known as the fixed layer or pinned layer.

[0042] Data is written to the MRAM memory cell by programming the free layer 807 to have the same or opposite orientation. The reference layer 803 is formed to maintain its orientation when the free layer 807 is programmed. The reference layer 803 may have a more complex design, including a composite antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the figures and descriptions, and only the fixed magnetic layers, which are primarily responsible for the tunnel magnetoresistance within the cell, are considered.

[0043] Figure 9 shows in more detail one embodiment of an MRAM memory cell design that can be implemented in a crosspoint array. When arranged in a crosspoint array, the upper and lower electrodes of the MRAM memory cell are two of the adjacent layers of wires in the array, for example, the upper and lower wires of a 2-level or 2-deck array. In the embodiment shown here, the lower electrode is the word line 901 of the memory cell and the upper electrode is the bit line 911, although in some embodiments these can be reversed by reversing the orientation of the memory elements. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are also separated by an isolated MgO barrier 905. In the embodiment shown in Figure 9, an MgO cap 908 is also formed on the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. Liners 921 and 923 are located on either side of the memory cell structure; although they may be part of the same structure, they appear separate in the cross-sectional view of Figure 9. On either side of liners 921 and 923 are portions of filler material 925 and 927, which are used to fill other empty areas of the crosspoint structure.

[0044] With respect to the free layer 907, embodiments include a CoFe or CoFeB alloy having a thickness of about 1-2 nm, the Ir layer can be scattered within the free layer in close proximity to the MgO barrier 905, and the free layer 907 can be doped with Ta, W, or Mo. Embodiments of the base layer 903 may include a CoFeB and CoPt multilayer bilayer bonded to an Ir or Ru spacer 902. The MgO cap 908 is optional but can be used to increase the anisotropy of the free layer 907. The conductive spacer can be a conductive metal such as Ta, W, Ru, CN, TiN, and TaN, among others.

[0045] To sense the data state stored in MRAM, V app A voltage represented by is applied across the memory cell to determine its resistance state. To read the MRAM memory cell, the voltage difference V app A bias can be applied in either direction. However, MRAM memory cells are directional, and therefore, in some situations, reading in one direction is preferred over other directions. For example, the optimal current amplitude for writing a bit to AP (high resistance state, HRS) may be 50% or more greater than the optimal current amplitude for writing to P (low resistance state), and therefore, when reading to AP (2AP), the bit error rate (read failure) is less likely to occur. Some of these situations and the resulting read directionality are described below. The directionality of the bias comes into play in particular in some embodiments for programming MRAM memory cells.

[0046] The following description primarily concerns perpendicular spin-transfer torque MRAM memory cells, which include a switchable magnetization direction in which the free layers 807 / 907 in Figures 8 and 9 are perpendicular to the plane of the free layer. Spin-transfer torque ("STT") is an effect that can be used to correct the orientation of magnetic layers within a magnetic tunnel junction using a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum inherent to the carrier. Currents are generally unpolarized (e.g., consisting of 50% spin-up electrons and 50% spin-down electrons). A spin-polarized current is one in which there are more electrons of either spin (e.g., a majority of spin-up electrons or a majority of spin-down electrons). A spin-polarized current can be generated by passing a current through a thick magnetic layer (reference layer). When this spin-polarized current is directed to a second magnetic layer (free layer), the angular momentum is transferred to this second magnetic layer, changing the direction of magnetization in the second magnetic layer. This is called spin-transfer torque. Figures 10A and 10B illustrate the use of spin-transfer torque for programming or writing to MRAM memory. Spin-transfer torque magnetic random-access memory (STT MRAM) has the advantages of lower power consumption and better scalability than MRAM variants such as toggle MRAM. Compared to other MRAM implementations, STT switching technology requires relatively low power, virtually eliminates the problem of adjacent bit interference, and has better scaling for higher memory cell density (reduced MRAM cell size). The latter issue is also advantageous for STT MRAM, where the magnetization of the free layer and reference layer is oriented perpendicular to the film plane rather than in-plane.

[0047] Since the STT phenomenon is more easily explained in terms of electron behavior, Figures 10A and 10B and their explanations are given in terms of electron current, and the direction of the write current is defined as the direction of electron flow. Therefore, the term write current in reference to Figures 10A and 10B refers to electron current. Since electrons are negatively charged, electron current is in the opposite direction to conventionally defined current, and as a result, electron current flows from low voltage levels to high voltage levels instead of the conventional current flow from high voltage levels to low voltage levels.

[0048] Figures 10A and 10B illustrate writing and reading of an MRAM memory cell using an STT mechanism and show a simplified schematic diagram of an example of an STT-switchable MRAM memory cell 1000 in which both the reference layer magnetization and the free layer magnetization are perpendicular. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002 comprising an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier 1014 (TB) as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is a free layer FL whose magnetization direction can be switched. The lower ferromagnetic layer 1012 is a reference (or fixed) layer RL whose magnetization direction cannot be switched. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across memory cell 1000 is relatively high. The data ("0" or "1") of memory cell 1000 is read by measuring the resistance of memory cell 1000. In this regard, the conductors 1006 / 1008 attached to memory cell 1000 are used to read the MRAM data. By design, both parallel and antiparallel configurations remain stable in a quiescent state and / or during read operations (with sufficiently low read currents).

[0049] For both the reference layer RL 1012 and the free layer FL 1010, the direction of magnetization is perpendicular (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figures 10A and 10B show the magnetization direction of the reference layer RL 1012 as upward, and the magnetization direction of the free layer FL 1010 as switchable between upward and downward, which is also perpendicular to the plane.

[0050] In one embodiment, the tunnel barrier 1014 is made of magnesium oxide (MgO), but other materials can also be used. The free layer 1010 is a ferromagnetic metal having the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys can be used to form the free layer 1010. In one embodiment, the free layer 1010 includes an alloy of cobalt, iron, and boron. The base layer 1012 can be many different types of materials, including (but not limited to) multiple layers of cobalt and platinum and / or cobalt and iron alloys.

[0051] To "set" the MRAM memory cell bit values ​​(i.e., select the direction of free layer magnetization), an electronic write current 1050 is applied from conductor 1008 to conductor 1006, as shown in Figure 10A. To generate the electronic write current 1050, the upper conductor 1006 is placed at a higher voltage level than the lower conductor 1008 due to the negative charge of electrons. Since the reference layer 1012 is a ferromagnetic metal, electrons in the electronic write current 1050 are spin-polarized as they pass through the reference layer 1012. As the spin-polarized electrons tunnel across the tunnel barrier 1014, the conservation of angular momentum may impart a spin transfer torque to both the free layer 1010 and the reference layer 1012, but this torque is (by design) insufficient to influence the magnetization direction of the reference layer 1012. In contrast, this spin-transfer torque is (by design) sufficient to switch the magnetization orientation within the free layer 1010 to be parallel (P) to the magnetization orientation of the reference layer 1012, if the initial magnetization orientation of the free layer 1010 was antiparallel (AP) with respect to the reference layer 1012, a process called antiparallel-parallel (AP2P) writing. The parallel magnetization remains stable before and after such an electronic writing current is turned off.

[0052] In contrast, if the magnetizations of the free layer 1010 and the reference layer 1012 are initially parallel, the direction of the magnetization of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electronic writing current in the opposite direction to that described above. For example, the electronic writing current 1052 is applied from conductor 1006 to conductor 1008 by applying a higher voltage level to the lower conductor 1008, as shown in Figure 10B. This writes the free layer 1010 from a P state to an AP state, and is called parallel-antiparallel (P2AP) writing. Thus, by the same STT physics, the direction of the magnetization of the free layer 1010 can be deterministically set to one of two stable orientations by a wise choice of the direction (polarity) of the electronic writing current.

[0053] The data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit, but sometimes other rules apply. A read current can be applied across the memory cell (e.g., across the magnetic tunnel junction 1002) by applying an electronic read current from conductor 1008 to conductor 1006, flowing as shown at 1050 in Figure 10A ("AP2P direction"). Alternatively, the electronic read current can be applied from conductor 1006 to conductor 1008 and flow as shown at 1052 in Figure 10B ("P2AP direction"). If the electronic write current is too high during a read operation, it can disrupt the data stored in the memory cell and change its state. For example, if the electronic read current uses the P2AP direction in Figure 10B, a current or voltage level that is too high can switch any memory cell from a low-resistance P state to a high-resistance AP state. As a result, MRAM memory cells can be read in either direction, but the directional nature of the write operation can make one read direction preferable to the other, as in various embodiments such as the P2AP direction, more current is required to write bits in that direction.

[0054] The explanations for Figures 10A and 10B relate to the electron current in relation to the read current and write current, but the following explanations will relate to conventional currents unless otherwise specified.

[0055] Regardless of whether a selected memory cell in the array structure shown in Figures 7A to 7D is being read or written, the bit and word lines corresponding to the selected memory cell are biased to apply a voltage across the selected memory cell and induce an electron flow, as shown with respect to Figure 10A or Figure 10B. This can also apply a voltage across the unselected memory cells in the array and induce a current in the unselected memory cells. This wasted power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high-resistance and low-resistance states, but this still increases current and power consumption and imposes additional design constraints on the design of the memory cells and array.

[0056] One approach to address this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, a selector transistor can be placed in series with each resistive memory cell element in Figures 7A-7D, so that memory cell 701 is, in this case, a combination of a selector and a programmable resistor. However, the use of transistors requires the introduction of additional control lines in order to turn on the corresponding transistor of the selected memory cell. Furthermore, transistors often do not scale as well as resistive memory elements, and as a result, the use of transistor-based selectors can become a limiting factor as memory arrays move to smaller sizes.

[0057] An alternative approach to selector elements is the use of a threshold switching selector device in series with a programmable resistor element. A threshold switching selector has high resistance (off or non-conducting) when biased to a voltage lower than its threshold voltage, and low resistance (on or conducting) when biased to a voltage higher than its threshold voltage. The threshold switching selector remains on until its current drops below the holding current or its voltage drops below the holding voltage. Once this occurs, the threshold switching selector returns to the off state. Therefore, to program a memory cell at a crosspoint, the associated threshold switching selector must be turned on, and sufficient voltage or current must be applied to set or reset the memory cell. Similarly, to read a memory cell, the threshold switching selector must be activated by being turned on before the resistance state of the memory cell can be determined. An example of a set of threshold switching selectors is the ovonic threshold switching material of an ovonic threshold switch (OTS).

[0058] Figure 11 shows one embodiment of incorporating a threshold switching selector into an MRAM memory array having a crosspoint architecture. The example in Figure 11 shows two MRAM cells in a two-layer (two-story) crosspoint array as shown in Figure 7D, in a side view. Figure 11 shows the lower first conductive wire (within the first or lower word line layer) of word line 1 1100, the upper first conductive wire (within the second or upper word line layer) of word line 2 1120, and the intermediate conductive wire (within the bit line layer) of bit line 1110. In Figure 11, all of these lines are shown extending from left to right across the page for ease of presentation. In a crosspoint array, they are represented more precisely as in the perspective view of Figure 7D, where the word lines or first conductive wires or wires extend in one direction parallel to the surface of the underlying substrate, and the bit lines or second conductive wires or wires extend in a second direction parallel to the surface of the substrate, substantially perpendicular to the first direction. MRAM memory cells are also represented in a simplified form showing only the reference layer, free layer, and intermediate tunnel barrier; however, actual implementations will typically include the additional structures described above with respect to Figure 9.

[0059] The MRAM device 1102, which includes a free layer 1101, a tunnel barrier 1103, and a reference layer 1105, is formed on top of the threshold switching selector 1109. This series combination of the MRAM device 1102 and the threshold switching selector 1109 together forms a story 0 cell between the bit line 1110 and the word line 1100. The series combination of the MRAM device 1102 and the threshold switching selector 1109 operates primarily as described above with respect to Figures 10A and 10B, except for some voltage drop across the threshold switching selector 1109 when the threshold switching selector 1109 is turned on. However, firstly, the threshold switching selector 1109 has a threshold voltage V th It must be turned on by applying a voltage exceeding a certain value, and then the bias current or voltage must be maintained at a sufficiently high level above the holding current or holding voltage of the threshold switching selector 1109 so that it remains on during subsequent read or write operations.

[0060] In story 1, the MRAM device 1112 includes a free layer 1111 and a tunnel barrier 1113, and the reference layer 1115 is formed on top of the threshold switching selector 1119. The series combination of the MRAM device 1112 and the threshold switching selector 1119 together forms a story 1 cell between the bit line 1110 and the word line 2 1120. The story 1 cell operates similarly to the story 0 cell, except that the lower conductor corresponds here to the bit line 1110, and the upper conductor corresponds here to the word line, word line 2 1120.

[0061] In the embodiment shown in Figure 11, the threshold switching selector 1109 / 1119 (selector) is formed beneath the MRAM devices 1102 / 1112, so that the selector 1109 contacts the first word line 1100 of the first word line layer, and the MRAM device 1102 is formed between the selector 1109 and the bit line 1110. In alternative embodiments, the threshold switching selector can be formed above the MRAM devices for one or both layers. As described with respect to Figures 10A and 10B, the MRAM memory cells are directional. In Figure 11, the MRAM devices 1102 and 1112 have the same orientation, and the free layers 1101 / 1111 are above the reference layers 1105 / 1115 (for a substrate not shown). Forming stories between conductive lines having the same structure can have several advantages with respect to processing, in particular, because each of the two stories, as well as subsequent stories in embodiments with more stories, can be formed according to the same processing sequence when forming a multi-story non-volatile memory structure.

[0062] Reading data from or writing data to an MRAM memory cell involves supplying current to the memory cell. In embodiments where a threshold switching selector is arranged in series with the MRAM device, the threshold switching selector must be turned on by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM device before current can pass through the MRAM device.

[0063] Figure 12A shows a schematic diagram of an example of reading a non-volatile memory cell 1220, which includes an MRAM cell 1222 connected in series with selector 1224. The MRAM cell 1222 has a resistor R corresponding to the resistance of the MRAM cell 1222 in the parallel and antiparallel states. P and R AP It is schematically shown as two resistors having V. MRAM However, depending on whether MRAM cell 1222 is in a parallel state or an antiparallel state, it can have two different values ​​(for example, V MRAM =Iread* R P or V MRAM =Iread * R AP ) The constant current Iread is maintained through the MRAM cell 1222 during reading (e.g., by a current mirror such as current mirror 574). The selector 1224 is schematically represented as a voltage source that provides a constant voltage difference Voffset when in the ON state (e.g., exceeding a threshold voltage). The sense amplifier 570 is connected to sense the voltage at the sense node 572 (e.g., the voltage varies depending on the resistance of the MRAM cell 1222 and the resulting voltage V MRAM which is different).

[0064] FIG. 12B shows the voltage distributions that can be compared by the comparator (e.g., comparator 576) of the sense amplifier 570 during the sensing operation. The first voltage distribution marked "P" (at the sense node 572, for example) corresponds to the parallel or "P" state of the MRAM cell. The second voltage distribution marked "AP" corresponds to the anti-parallel or "AP" state of the MRAM cell. There is a reference voltage Vref (e.g., from the Vref source 578) between these distributions. By comparing the voltage at the sense node 572 with the reference voltage Vref, a determination can be made as to which state the MRAM cell is in (e.g., a sensed voltage < Vref indicates the P state and a sensed voltage > Vref indicates the AP state).

[0065] In a non-volatile memory cell including a selector connected in series with the MRAM cell, a conventional current may flow from the selector side to the MRAM side. In a multi-story non-volatile memory structure as shown in FIG. 11, this can cause some differences when accessing non-volatile memory cells in different stories.

[0066] Figures 13A and 13B illustrate the differences in accessing non-volatile memory cells in different stories. In the first story (story 0 in Figure 13A), current flows from the word line side to the bit line side. For example, Figure 13A shows the word line selected via the WL driver 624 (variable resistor R) so that the current Iread flows from the word line side to the bit line side. WL A positive voltage VPP is applied to the selected bit line (which is schematically shown as a variable resistor R), and the selected bit line (variable resistor R) is also shown. BL The negative voltage VNN applied to (r shown schematically as) is shown. In contrast, in the second story (story 1 in Figure 13B), the current flows from the bit line side to the word line side. For example, Figure 13B shows the bit line (R selected via the BL driver 614) such that the current Iread flows from the bit line side to the word line side. BL The positive voltage VPP applied to ) and the selected word line (R WL The negative voltage VNN applied to ) and the result are shown.

[0067] To read memory cells from different stories within a multi-story MRAM memory structure (for example, as shown in Figure 11), the read / write circuit may include separate sensing amplifiers for reading memory cells within each story. For example, Figures 14A and 14B show an example where two different sensing amplifiers are used to read non-volatile memory from different stories.

[0068] Figure 14A shows an example of a read operation directed towards a non-volatile memory cell in the first story (story 0 readout), for example, in the story 0 cell in Figure 11. The positive voltage VPP is controlled by switch 1470 (e.g., the switch on the WL decoder) and the selected word line (e.g., the variable resistor R). WL The selected non-volatile memory cell 1472 is connected via the first word line 1100 (as schematically shown). The selected bit line (e.g., R BLA bit line (1110, shown schematically) connects a selected non-volatile memory cell 1472 to a current mirror 574 via a switch 1474 (e.g., a switch on the BL decoder) which is connected to a negative voltage VNN and configured to maintain the read current Iread during read operations. A low-voltage sensing amplifier 1478 is connected to sense the voltage between the selected bit line and the current mirror 574 (for example, the low-voltage sensing amplifier 1478 may be configured to sense low voltages including negative voltages in the range of, for example, -2.5 volts to -3.0 volts).

[0069] Figure 14B shows an example of a second story (story 1 readout), for example, a readout operation directed to a non-volatile memory cell in story 1 cell in Figure 11. The positive voltage VPP is applied to switch 1480 and the selected bit line (e.g., R BL The selected non-volatile memory cell 1482 is connected via the bit line 1110 (which is schematically shown as R). WL A word line (1120, schematically shown as such) connects a selected non-volatile memory cell 1482 to a negative voltage VNN via a switch 1484. A high-voltage sensing amplifier 1483 is connected to sense the voltage between the selected bit line and the current mirror 574 (for example, the high-voltage sensing amplifier 1483 may be configured to sense high voltages including positive voltages in the range of, for example, 2.5 volts to 3.0 volts).

[0070] Embodiments of this technology include using a single sensing amplifier to perform sensing during read operations directed to memory cells of two different stories (for example, as shown in Figure 11), wherein the current flow is different for reading the memory cells of the different stories (for example, the first story, from the word line to the bit line in story 0, and the second story, from the bit line to the word line in story 1).

[0071] Figure 15A shows an example of a control circuit connected to a non-volatile memory cell 1552 (for example, a non-volatile memory cell in any story within an MRAM memory structure as shown in Figure 11). The non-volatile memory cell 1552 is connected to bit line switches 1554 and word line switches 1556, respectively, via bit line R BL and word line R WL The bit line switch 1554 includes a first set of switches 1558 connected between the first voltage VPP (e.g., positive voltage) and the bit line, and a second set of switches 1560 connected between the bit line and the sense amplifier 1478. The word line switch 1556 includes a third set of switches 1562 connected between the first voltage VPP and the word line, and a fourth set of switches 1564 connected between the word line and the sense amplifier 1478. Each switch may correspond to a different switching scale and transistor type. For example, the first letter shown next to each transistor / switch may indicate the scale (e.g., L = local, G = global, and P = plane). The second letter indicates whether it is connected to a line extending in the x or y direction (e.g., Y is the bit line, X is the word line). The third letter indicates the type of transistor (for example, P indicates PMOS and N indicates NMOS, so that the first switch 1558 and the third switch 1562 are formed by PMOS transistors, and the second switch 1560 and the fourth switch 1564 are formed by NMOS transistors). Figure 15A also shows a bank control circuit 1566 and a module control circuit 1568 that can control the signals used to turn the bit line switch 1554 and the word line switch 1556 on / off. For example, the control gates of the first, second, third, and fourth sets of transistors may be connected to the module control circuit 1568 and / or the bank control circuit 1566 (control lines are omitted for clarity). The sensing amplifier 1478 is connected on top of the current mirror 574 connected to a second voltage VNN (e.g., a negative voltage).

[0072] Figure 15B shows an example of a read operation directed to a first non-volatile memory cell 1552 in a first story (e.g., story 0 cell in Figure 11). In this example, a first voltage VPP (e.g., positive voltage) is connected to the first non-volatile memory cell 1552 via a selected word line by turning on a third switch 1562. A sensing amplifier 1478 and a first voltage VNN (e.g., negative voltage) are connected to the first non-volatile memory cell 1552 via a bit line by turning on a second switch 1560. The first switch 1558 and the fourth switch 1564 are turned off for this read operation. In this configuration, the read current Iread flows through switch 1562, the selected bit line, the first non-volatile memory cell 1552, the selected bit line, switch 1560, and the current mirror 574, as indicated by the dotted arrow. The sensing amplifier 1478 senses a voltage above the current mirror 574 to determine the state of the first non-volatile memory cell 1552.

[0073] Figure 15C shows an example of a read operation directed to a second non-volatile memory cell 1592 in a second story (e.g., cell 1 in story 11). In this example, a first voltage VPP (e.g., positive voltage) is connected to the second non-volatile memory cell 1592 via a selected bit line by turning on a first switch 1558. A sensing amplifier 1478 and a first voltage VNN (e.g., negative voltage) are connected to the second non-volatile memory cell 1592 via a word line by turning on a fourth switch 1564. Switches 1560 and 1562 are turned off for this read operation. In this configuration, the read current Iread flows through switch 1558, the selected bit line, the second non-volatile memory cell 1592, the selected word line, switch 1564, and the current mirror 574, as indicated by the dotted arrow. The sensing amplifier 1478 senses a voltage above the current mirror 574 to determine the state of the second non-volatile memory cell 1592.

[0074] The bank control circuit 1566 and / or module control circuit 1568 (in combination with other control circuits, for example, system control logic 560 / 660) may control the first, second, third, and fourth switches 1558, 1560, 1562, and 1564 such that when reading memory cells from a first story (e.g., story 0), the connection is configured as shown in Figure 15B, and when reading memory cells from a second story (e.g., story 1), the connection is configured as shown in Figure 15C. For example, a control circuit (e.g., bank control circuit 1566, module control circuit 1568, and / or system control logic 560 / 660) can receive the address of a selected non-volatile memory cell and determine the story in which the selected non-volatile memory cell is located from a plurality of stories, including a first story between a first word line layer and a bit line layer (e.g., story 0 between word line 1 1100 and bit line 1110 in Figure 11) and a second story between the bit line layer and a second word line layer (e.g., story 1 between bit line 1110 and word line 2 1120). The control circuit can then apply appropriate voltages to the first, second, third, and fourth switches to perform configuration according to the story in which the non-volatile memory cell is located. The bank control circuit 1566, module control circuit 1568, bit line switch 1554, and word line switch 1556 (either alone or in combination with additional switches such as system control logic 560 / 660) can be considered examples of means for reading non-volatile memory cells located in a plurality of stories, including a first story between a first word line layer and a bit line layer (e.g., story 0 in Figure 11) and a second story between a bit line layer and a second word line layer (e.g., story 1 in Figure 11), and include connecting a sense amplifier to a first selected non-volatile memory cell in the first story via a bit line in the bit line layer (see, for example, Figure 15B), and connecting a sense amplifier to a second selected non-volatile memory cell in the second story via a second word line in the second word line layer (see, for example, Figure 15C).Although the examples in Figures 15B and 15C refer to read operations, any memory access operation (e.g., write operations) can be similarly applied to memory cells in different stories using aspects of this technology.

[0075] Figure 16 shows a simplified schematic diagram of a memory die 1600 implementing an embodiment of the present technology. For example, Figure 16 shows a bit line switch 1554 connected to the bit lines of the memory array 502 via an input / output 506, and a word line switch 1556 connected to the word lines of the memory array 502 via an input / output line 508. The bit line switch 1554 and the word line switch 1556 are connected to a common control circuit 1602, which includes a common sensing amplifier 1604 and a common driver 1606. For example, each sensing amplifier of the common sensing amplifier 1604 may be connected to either a bit line (via the bit line switch 1554) or a word line (via the word line switch 1556), and in this way may be used to sense nonvolatile memory cells of different stories. Similarly, each driver of the common driver 1606 may be connected to either a bit line (via the bit line switch 1554) or a word line (via the word line switch 1556), and in this way may be used to drive appropriate voltages (e.g., VPP and VNN) on the bit line or word line. In this way, the common driver 1606 may be used for read operations directed to memory cells in different stories. Other components of the memory die 1600 may be similar to those of the memory system 500 and will not be described further here. The integrated memory assembly may be implemented using WL switches, bit line switches, and common circuits that may be connected to either (for example, the integrated memory assembly 600 may be configured to include a word line switch 1665, a bit line switch 1554, and a common control circuit 1602).

[0076] Figure 17 shows an exemplary implementation of an aspect of the technology in a data storage system including a core formed from N banks, each bank having n modules. Figure 17 also shows an example of a control circuit that may be used to control a switch connecting a common sense amplifier and / or driver to word lines and bit lines.

[0077] The digital media control circuit 1780 receives address 1782 (e.g., a logic address in a read command directed to one or more nonvolatile memory cells). The digital media control circuit 1780 can use address 1782 to generate location information 1786 (e.g., a physical address) in an appropriate format. For example, location information 1786 may include the bank, module, story, and coordinates (e.g., bit lines and word lines) where the selected nonvolatile memory cell to be read is located (e.g., the memory structure has stories or layers with different characteristics as shown in Figure 11).

[0078] The digital media control circuit 1780 transmits location information 1786 to the bank control circuit 1566. The bank control circuit can use the location information 1786 to determine which story (e.g., the first story, story 0, or the second story, story 1) the nonvolatile memory cell is located in. The bank control circuit 1566 sends signal 1792 to the module control circuit 1568. The module control circuit 1568 generates signals to enable / disable the bit line switches 1554 (e.g., switches 1558 in the first set and switches 1560 in the second set) and the word line switches 1556 (e.g., switches 1562 in the third set and switches 1564 in the fourth set). For example, in the case of a read operation directed to a non-volatile memory cell in the first story, the module control circuit 1568 may generate signals to configure a switch as shown in Figure 15B, and in the case of a read operation directed to a non-volatile memory cell in the second story, the module control circuit 1568 may generate signals to configure a switch as shown in Figure 15C. Figure 17 shows a specific arrangement of components, but the technology is not limited to any specific arrangement and can be implemented using a wide range of components.

[0079] Figure 18A shows an example of a method that includes receiving a first address of a first selected nonvolatile memory cell at the intersection of a first word line and a first bit line in a nonvolatile memory cell structure 1820 (e.g., the lower cell in Figure 11), determining that the first selected nonvolatile memory cell is in a first story 1822 (e.g., story 0), and, in response to determining that the first selected nonvolatile memory cell is in a first story, connecting a sensing amplifier to the first bit line (e.g., as shown in Figure 15B) to read out the first selected nonvolatile memory cell 1824. The method further includes receiving the second address of a second selected nonvolatile memory cell at the intersection of a first bit line and a second word line in a nonvolatile memory cell structure 1826 (e.g., the upper cell in Figure 11), determining that the second selected nonvolatile memory cell is in a second story (e.g., story 1) 1828, and, in response to determining that the second selected nonvolatile memory cell is in a second story, connecting a sensing amplifier to the second word line (e.g., as shown in Figure 15C) to read out the second selected nonvolatile memory cell 1830.

[0080] Figure 18B shows method steps that may be performed alone or in combination with the steps shown in Figure 18A. These steps include reading a first non-volatile memory cell by passing a first current through a first word line, a first non-volatile memory cell, a first bit line, and a current mirror 1840 (e.g., Iread in Figure 15B); sensing the first non-volatile memory cell with a sensing amplifier and passing a first current 1842 by comparing a sensing voltage between the first bit line and the current mirror with a reference voltage; reading a second non-volatile memory cell by passing a first current through a first bit line, a second non-volatile memory cell, a second word line, and a current mirror 1844 (e.g., Iread in Figure 15C); and sensing a second non-volatile memory cell with a sensing amplifier, which includes comparing a sensing voltage between the second word line and the current mirror with a reference voltage while passing a first current 1846.

[0081] The embodiments of the memory device presented above utilize a crosspoint architecture in which each MRAM cell is constructed in a cross-sectional area between a vertical bit line (on one level) and a horizontal word line (constructed above or below). To conserve die size, embodiments may utilize an architecture that allows CMOS selection transistors to be located below the memory array. Accessing a given memory cell requires charging one of several (e.g., 256, 512, 1024, or 2048) bit lines and word lines through a set of selection transistors in a decoder (multiplexer) circuit, such as within the row control circuits 520 / 620 and column control circuits 510 / 610 in Figure 3 or 4. As described above, embodiments of the MRAM crosspoint array utilize both positive and negative bias levels. The following description presents embodiments of such bipolar decoder circuits. The exemplary embodiments used in this description relate to a crosspoint MRAM memory in which the decoder circuit is located beneath the memory cells on the same die as the memory cells, but can be applied more generally to other embodiments such as those based on other programmable resistive elements such as ReRAM, FeRAM, RRAM, or PCM memory cells, and embodiments in which the decoder circuit is formed around the memory array or on a separate control die, as in the embodiment of Figure 4.

[0082] Next, the decoder circuit and its requirements are described. A decoder is a multiplexing circuit that provides a unique connection (and current delivery capability) to each of the lines it drives. In an exemplary embodiment, a bit-line decoder drives one of 1024 bit lines, and a word-line decoder drives one of 1024 word lines. In a crosspoint structure, the decoder may be the same in both cases. In the inactive state, a deselector transistor drives the bit line and word line to ground (0V). To program the MRAM cell (i.e., to change its state from logic 1 to logic 0, or vice versa), current must flow from the bit line to the word line, or vice versa. As a result, the decoder must be able to source current (when driving a line positively) and sink current (when driving a line negatively). The cell is bipolar. Therefore, the decoder must be bipolar.

[0083] Figures 19A and 19B present one embodiment of a bipolar decoder, where the two figures show different parts of the circuit and together constitute an embodiment of the circuit. The decoder includes a positive decoding path (above the upper dashed horizontal line), a ground decoding path (between the dashed horizontal lines), and a negative decoding path (below the lower dashed line). Figures 19A and 19B relate to a bit-line decoder, but a word-line decoder can be configured similarly. In the exemplary embodiment shown, hierarchical decoding is used first at the "pane" (i.e., crosspoint array section) level, then at the global level, and finally at the local level. Considering pane selection, the local control signal 1911 is connected to a positive pane selection PMOS switch PPS 1913 and a positive pane deselection NMOS switch PPD 1915 to supply a bias level pos_MUX to the pos_pane supply line when a pane is selected (low local value), which is supplied to 32 global selections (in this example). The positive bias level pos_MUX depends on the operation being performed. Global Positive Selection Switch GPS <0> 1903-0~GPS <31> 1903-31 is connected to the pos_pane and receives their enable signals pos_global_enb (where 1903 is a PMOS, so "b" represents a bar or inverter) via a set of inverters / drivers from the level shifter 1901 from the termination circuit 1900, and supplies the corresponding pos_global signals to the 32 local select switches (in this example as well). The pos_global line is connected to the global positive deselect switch GPD. <0> 1905-0~GPS <31> It is connected to ground via 1905-31 and receives local control signal 1907.

[0084] Each positive global supply line pos_global for each global select / deselect switch GPS 1903 / GPD 1905 is connected to the corresponding set of bit lines via a local positive select switch. For example, as shown in Figures 19A and 19B, GPS <0> The pos_global line from 1903-0 is connected to the respective local positive selection switch LPS. <0> 1925-0~LPS <31> Local bit line LBL via 1925-31 <0> ~LBL <31> Connected to GPS <31> The pos_global line from 1903-31 is connected to the respective local positive selection switch LPS. <0> 1927-0~LPS <31> Local bit line LBL via 1927-31 <991> ~LBL <1023> It is connected to, and other bit lines not shown are connected in the same way. The control signal for the local positive select switch (pos_local_enable) is again provided from the level shifter 1921 in the termination circuit 1900 through a set of drivers in the termination circuit 1900. An additional driver / inverter 1923 is for each of the 32 local positive control signals for the local positive select switch pos_local_enb to drive the PMOS select gate, and as will be further described below, the additional driver / inverter 1923 is located near the actual switch. The positive and negative local deselector signals are part of the ground decoding path of the termination circuit 1900. For the positive decoding side, the level shifter 1941 provides the positive deselector enable signal (pos_desel_en) via a set of drivers / inverters to the GPS <0> For the bit lines supplied by 1903-0, PMOS LPD <0> 1947-0~LPD <31> Provided to the 1947-31 local positive deselection switch, GPS <31> For the bit lines supplied by 1903-31, PMOS LPD <0> 1949-0~LPD <31> Provides local positive deselector switch for 1949-31.When a bit line is deselected, regardless of whether positive or negative is used for the selected bit line, the deselected bit line is set to ground, so an additional set of driver / inverter 1945s are again placed around the array to generate an inverted desel_enb from pos_desel_en and from the negative deselection enable signal neg_desel_en from the level shifter 1943. Thus, in this exemplary embodiment, there is one pane selection (PPS) fed into 32 global selections (GPS). Each global selection is fed into 32 local selections (LPS), resulting in 1024 unique bit line connections. In the off / idle state, the deselections (PPD, GPD, LPD) drive grounding to each level in the decoding path.

[0085] Considering the remainder of the negative portion of the decoder, the negative decoding path mirrors the positive decoding path and is laid out similarly, but the selection here is between ground and the negative voltage neg_MUX for selected operation, the negative voltage is selected through an NMOS device, and the deselection connection to ground is done through a PMOS device. More specifically, pane level selection connects the line neg_pane to ground via NPD 1993 or to neg_MUX by NPS 1995 based on the local control signal 1991. Global decoding to provide the neg_global signal, if selected, is performed by switching the NMOS GNS based on the control signal neg_global_en from level shifter 1981. <0> 1985-0~GNS <31> Executed by 1985-31, and when deselected, the PMOS switch GND based on local control signal 1987. <0> 1983-0~GND <31> This is performed by 1983-31. For local decoding of local bit lines, deselection is as described above for the positive decoding side. To decode the selected local bit line, the control signal neg_local_enb is provided by level shifter 1961 through a set of driver / inverters, which include an extra relative driver / inverter since the switch here is NMOS. The neg_local_en signal is then generated again by driver / inverter 1963, which is located closer to the decoding switch. Next, the negative local enable signal is used by GNS <0> Switch LNS for local switches supplied by 1985-0 <0> 1965-0~LNS <31> It was supplied to the control gates of 1965-31 and GNS <0> Switch LNS for local switches supplied by 1985-31 <0> 1967-0~LNS <31> The same applies to the 1967-31 control gate and other switches not shown.

[0086] In the crosspoint memory architecture for the memory device presented above, each memory cell is constructed in the cross-sectional area between a vertical bit line (on one level) and a horizontal word line (built above or below). The cell stack consists of programmable resistive memory cells and inline threshold switching selectors, such as obonic threshold selectors. Figure 20 illustrates this structure.

[0087] Figure 20 is a schematic diagram of a memory cell formed from an OTS 2003 or other threshold selector switch and a programmable resistor memory cell 2001. While the exemplary embodiments given above have focused on the example of MRAM for programmable memory cell elements, other embodiments may use different technologies such as phase-change memory or selector-only memory, in which case the OTS or other threshold selector has a programmable resistor and provides both functions. The OTS selector 2003 operates as a voltage-dependent switch. When the voltage across the cell (VBL-VWL) is less than the turn-on voltage or threshold voltage Vth of the OTS 2003, it operates as an open circuit, as shown on the right side of Figure 20. However, when the cell voltage exceeds Vth of the OTS 2003, the switch closes, allowing a connection between the bit line BL and the word line WL, which can result in a current spike through the pair of cell 2001 and OTS 2003. This can be illustrated with respect to Figure 21.

[0088] Figure 21 shows the current spike and resulting snapback that occur when the OTS is activated (i.e., turned on). Figure 21 is a plot of the current Icell through the cell as a function of time (t) when biased for sensing operation. As the voltage across the cell increases, it eventually reaches the Vth level of the OTS 2003. An ideal threshold switching selector is shown in 2121, where, once the voltage difference reaches a sufficient bias level, the OTS switches with a constant current until the bias voltage is removed. In a real OTS 2003 or other threshold switching selector, when a voltage is applied, charge accumulates on the capacitances of the bit and word lines. When the voltage across the memory cell reaches the Vth of the OTS 2003, it turns on, and the capacitances on the bit and word lines immediately share charge through the memory cell. This results in a current spike and subsequent snapback at the Icell level. This undesirable transient impulse of current through the cell can unintentionally program the cell (readout failure) and degrade the cell more rapidly due to the electrical transfer effect (lower endurance). Figure 21 shows both a bad case 2123 with larger spikes and a better case 2125 with lower amplitude spikes, where larger spikes result in higher levels of interference and device degradation. A common characteristic of OTS and other threshold switching selectors is that the Vth value tends to drift over time, increasing as the time since the last operation increases. Figures 22A to 24B illustrate the process in more detail.

[0089] Figures 22A and 22B show the bias and charge-up / charge-down of the word and bit lines, respectively, and the current and voltage levels across the cell before the OTS 2203 is activated. The current source 2205 drives the bit line BL connected to the memory cell 2201 and OTS 2203 pair, and the bit line capacitance represented by 2207 is charged by the current 2211 while the OTS 2203 is not yet activated. On the bit word line WL side, the word line WL is connected to a negative voltage bias level via a typical closed switch 2217, charging the word line capacitance 2209. Referring to Figure 22B, the voltage 2221 on the word line VWL ramps down to a negative supply level (lower dashed line), and the voltage 2223 on the bit line VBL ramps up to a voltage difference of Von = Vth (upper dashed line). Until the OTS 2203 is activated, there is still no current through the device, and the Icell is flat.

[0090] Figures 23A and 23B show the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cell when the OTS 2203 is first activated. As indicated by arrow 2315, when the OTS 2203 is activated, the bit line BL and word line WL share charge through the cell by discharging the charge stored on capacitor 2207 as shown in 2311 and on capacitor 2209 as shown in 2313. At this moment, the V vs t graph is as shown in Figure 22B, but a current spike 2317 occurs because the OTS is conducting. The amplitude of the spike depends on the sum of the word line resistance, the bit line resistance, and the resistance programmed into the programmable resistor element 2201.

[0091] Figures 24A and 24B show the bias and charge-up / down of the word and bit lines, respectively, and the current and voltage levels across the cell after the OTS2203 has been operating for a certain period of time. These figures are arranged and numbered similarly to Figures 22A, 22B, 23A, and 23B, but show the behavior after the OTS 2203 has been operating for a period of time. The current flowing through the memory cell when the OTS 2203 is conducting is represented by 2417. As illustrated, after a certain time, the path reaches a steady state, the current through the path stabilizes at a DC level, and the time to reach the steady state is determined by the RC constant of the path. Referring to Figure 24B and the Icell graph, as shown in 2427, when the OTS 2203 is operating at 2325, the current asymptotically decreases to the steady-state current at 2429. For voltage levels 2423 on the bit line and 2421 on the word line, when OTS 2202 is activated, these asymptotically settle to the steady-state levels of the dashed lines separated by Voffset.

[0092] Figures 25A and 25B show the array and address decoder that drive the selected local word line and selected local bit line before the threshold switching selector is activated, as shown in Figures 22A and 22B. On the left side of Figure 25A is a word line decoder 2521, which may be similar to the embodiments in Figures 19A and 19, providing the local word line LWL 2525 bias level to the array 2501. On one side (bottom of the figure), the decoder is connected to receive a negative level neg_MUX from a negative multiplexer 2505 connected to provide a neg_MUX level selected from a negative supply level. On the other side (top of the figure), the decoder is connected to receive a positive level pos_MUX from a positive current level multiplexer 2505 connected to provide a pos_MUX level selected from a positive supply level, and a sense amplifier SA is also included in 2503.

[0093] On the right side of Figure 25B is a bit line decoder 2523, which is also similar to the embodiments in Figures 19A and 19, and can provide a local bit line LWL 2527 bias level to array 2501. On one side (bottom of the figure), the decoder is connected to receive a negative level neg_MUX from a negative multiplexer 2505 connected to provide a neg_MUX level selected from a negative supply level. On the other side (top of the figure), the decoder is connected to receive a positive level pos_MUX from a positive current level multiplexer 2505 connected to provide a pos_MUX level selected from a positive supply level, and a sense amplifier SA is also included in 2503.

[0094] As shown in Figures 22A and 22B, when the bit line voltage VBL ramps up as indicated by 2223, a positive charge is accumulated in the bit line capacitance 2207 due to the adjacent bit line and decoding path 2521. As the word line voltage VWL ramps down as indicated by 2221, a negative charge is accumulated in the word line capacitance 2209 due to the adjacent word line and decoding path 2523. These voltage levels 2221 and 2223 are also schematically represented in Figure 25A on the selected local word line LWL 2525 and the selected local bit line LBL 2527.

[0095] Figure 25B is a magnified detail view of Figure 25A to better illustrate the features of array 2501. The local word line selection line LWL 2525 is connected to the selected upper story word line WL 2565 by a via represented by 2505, which also shows the path to the selected cell 2569 and OTS 2567 pair as a resistive line. The local bit line selection line LBL 2527 is connected to the selected bit line BL 2563 by a via represented by 2509, which also shows the path to the selected cell 2569 and OTS 2567 pair as a resistive line. Bit line ramp-up and word line ramp-down are again schematically shown in 2223 and 2221, respectively. For the selected crosspoint memory cell of the programmable resistor element 2569 and threshold selector switch OTS 2567 connected in series, the switch is shown as open because the voltage difference across OTS 2567 has not yet been activated. Furthermore, the bit-line capacitance and word-line capacitance, such as 2561, which accumulate charge before OTS 2567 is activated, are also schematically shown.

[0096] Figures 26A and 26B show the array and address decoders that drive the selected local word line and selected local bit line after the threshold switching selector is activated, as shown in Figures 24A and 24B. Figures 26A and 26B repeat the elements of Figures 25A and 25B, which are similarly numbered, but here also include the positive and negative decoding voltage levels at the pane level, global level, and local level. When the selected memory cell OTS 2567 is activated, the current 2421 from the negative supply to the selected local word line supply 2525 flows from the negative supply multiplexer 2505, and the current 2423 from the positive supply to the selected local bit line supply 2527 flows from the positive supply multiplexer 2503. The decay profile or tail 2427 in Figure 24B is a function of how much path capacitance discharges between the selected bit line and the selected word line. In addition to the embodiments described below, to help reduce current spikes when the threshold selector switch is activated, transistors 2603 or 2605 can be included on one or both of the positive and negative supply sides to regulate the current flow. With or without regulation, when the OTS is activated, all capacitances along the entire bit line path and word line path discharge.

[0097] Figure 26B is a detailed diagram showing the currents within array 2501. Charges accumulated along the decoding path and within the array discharge, as indicated by the arc error on OTS 2567. For a selected word line 2565, it has capacitance with adjacent word lines, as represented by 2671 and 2673. A selected bit line 2563 has capacitance with adjacent bit lines, as represented by 2675. The charge flow from the word line path is represented by 2605, which includes the current from LWL 2525 through via 2505, as well as the charge from capacitances 2671 and 2673. The charge flow from the bit line path is represented by 2603, which includes the current from LBL 2527 through via 2509, and the charge from capacitance 2675.

[0098] To minimize transient spikes in the Icell current 2427, attenuation techniques are applied. Referring back to Figure 25A or Figure 26A, array 2501, along with several examples numbered in Figures 25B and 26B (e.g., 2561, 2671, 2673, 2675), has some amount of parasitic word-line and bit-line capacitance, as represented in the array. While these capacitance values ​​can be controlled to some extent, they are primarily determined by other array design issues and are not easily controlled. Moving outward from array 2501 to decoders 2521 and 2523, all devices contribute some parasitic capacitance to charge-sharing events. Embodiments presented herein electrically isolate these “peripheral” capacitances to prevent them from discharging freely, similar to a dam blocking a swift river.

[0099] Figure 27 shows the spike attenuation snapback mitigation effect on the current Icell and voltage levels through the memory cell. Figure 27 is configured similarly to Figure 24B, where Icell 2727, positive voltage discharge 2733, and negative voltage charge 2731 correspond to the unmitigated waveforms 2427, 2423, and 2421. The embodiments presented herein reduce the snapback current as shown in 2737, the positive voltage discharge rate as shown in 2733, and the negative voltage charge rate as shown in 2731. Figure 28 shows an example of such an embodiment.

[0100] Figure 28 shows one embodiment in which local selection gates for the bit and word lines of the selected memory cell use regulators to apply lower gate drives in order to reduce the impact when the threshold selector switch is activated. Figure 26A repeats the elements of Figure 26A, but does not show the termination of either decoder 2521 or 2523, and only shows the drivers for the active local selection gates on either side of array 2501. Currents 2421 and 2423 are also shown here with lighter weights to show their attenuation. The local selection switches are also labeled here as LXP, LXD, and LXN, corresponding to local selection switches 1925-i, 1947-i, and 1965-i in Figures 19A and 19B, respectively.

[0101] On the left, the selected word line is supplied to the word line decoder 2521 via a local negative select switch NMOS LXN 2801. On the right, the selected bit line is supplied to the bit line decoder 2523 via a local positive select switch PMOS LXP 2803. The NMOS LXN 2801 and PMOS LXP 2803 have gates biased by regulators 2805 and 2807, respectively. Regulators 2805 and 2807 can correspond to the driver / inverter 1963 and 1923 in Figure 19A.

[0102] The device LXN 2801 has a regulator 2805 that applies lower gate drive to its NMOS device. Instead of operating in the linear region like a switch, the device is saturated before the OTS (2567 in Figure 26B) is activated. Then, as the OTS snaps, instead of allowing the capacitance upstream of the OTS in the decoder 2521 to discharge freely, the LXN 2801 acts as a source follower voltage clamper. When its source voltage rises, it enters a weak inversion, preventing further discharge of the decoder's capacitance.

[0103] Similarly, device LXP 2803 performs the same function on the positive side. Instead of allowing the capacitance of the preceding decoder element to discharge freely, when its source discharges downward, regulator 2807 reduces its source voltage, causing it to weakly invert and limiting the flow of charge. Figure 28 shows the use of both regulators 2805 and 2807, but other embodiments may use one or the other individually. The PMOS local select switch LXP 2803 tends to have a higher resistance than the NMOS local select switch LXN 2801, which relatively reduces the current through the PMOS local select switch LXP 2803, and therefore, in some embodiments, only the negative supply switch, such as the NMOS local select switch LXN 2801, is thus regulated by regulator 2805.

[0104] In one embodiment, different levels of adjustment can be used for the local selection gates based on conditions such as the address location or temperature of the selected memory cells in the array. For example, regulators 2805 and 2803 can correspond to multiple regulators that can provide local selection gates 2801 and 2803 with one of several selected control gate levels based on address, temperature, or other operating conditions. This is schematically shown in Figure 29.

[0105] Figure 29 shows one embodiment in which multiple levels of adjustment can be applied to the gate of the local word line selection transistor LXN 2801. The adjacent circuit of Figure 28 is also shown. The corresponding arrangement can also be used for the local bit line selection transistor 2803 and regulator 2807 of Figure 28. In the embodiment of Figure 29, an example of three regulators 2805a, 2805b, and 2805c is shown. The output voltages of the three regulators 2805a, 2805b, and 2805c are connected to the local selection gate 2801 through a multiplexer 2901, and a control circuit, such as in a row control circuit 520 or a column control circuit 510, can provide a selection signal to the MUX 2901 to select the bias level for the control gate of the local selection device LXN 2801.

[0106] Figure 30 is a flowchart of one embodiment for accessing MRAM memory cells in a crosspoint array structure, for example, for a read operation. As described above, in Figures 7A to 7D, etc., in the crosspoint memory structure, each memory cell is connected between a corresponding first control line (such as a word line) and a corresponding second control line (such as a bit line). Each memory cell includes an OTS or other threshold switching selector connected in series with a programming resistor (which may be direction-dependent) such as an MRAM or PCM device, or includes a selector-specific memory cell whose threshold switching selector also has a programmable resistor level.

[0107] Starting from step 3001, memory cells are selected for a read operation or other access operation. The selected memory cells (e.g., 2567 and 2569) are biased with a positive voltage via a first local select switch, such as via switch LXP 2803 in Figure 28, through local bit line supply 2527, in step 3003. Simultaneously with step 3003, in step 3005, the selected memory cells are biased with a negative local select switch, such as LXN 2801, via local word line supply 2525. As part of step 3005, before the threshold switching selector OTS 2567 of the selected memory cells is turned on, step 3007 biases a second local select switch, such as via regulator 2805, to a saturated state. When the threshold switching selector OTS 2567 of the selected memory cells is turned on, step 3007 biases the second local select switch, such as regulator 2805, to act as a source follower voltage clamp, as shown with respect to Figure 27.

[0108] According to a first set of embodiments, the non-volatile memory device comprises a control circuit configured to connect to an array comprising a plurality of non-volatile memory cells, each having a threshold switching selector, wherein the array comprises a control circuit having a crosspoint structure in which each memory cell is connected between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of word lines. The control circuit comprises a bipolar bit-line decoder connected to an array and configured to selectively bias the corresponding bit lines of selected memory to one of a positive voltage level or a negative voltage level, wherein the bipolar bit-line decoder comprises a plurality of bit-line local negative select switches each configured to supply a negative voltage level to the corresponding bit lines of selected memory, and a plurality of bit-line local positive select switches each configured to supply a positive voltage level to the corresponding bit lines of selected memory; and a bipolar word-line decoder connected to an array and configured to selectively bias the corresponding word lines of selected memory to one of a positive voltage level or a negative voltage level, wherein the bipolar word-line decoder comprises a plurality of word-line local negative select switches each configured to supply a negative voltage level to the corresponding word lines of selected memory, and a plurality of word-line local positive select switches each configured to supply a positive voltage level to the corresponding word lines of selected memory.The control circuit is configured to bias the selected memory cell via the corresponding bit-line local negative select switch and the corresponding word-line local positive select switch, or via the corresponding word-line local negative select switch and the corresponding bit-line local positive select switch, in order to turn on the threshold switching selector for the selected memory cell, thereby biasing and turning on the control gate on either the corresponding bit-line or word-line local negative select switch that is biasing the selected memory cell, and as a result turning on the current through either the corresponding bit-line or word-line local negative select switch that is biasing the selected memory cell, and limiting the current level through either the corresponding bit-line or word-line local negative select switch that is biasing the selected memory cell after the threshold switching selector for the selected memory cell has been switched on.

[0109] According to another set of embodiments, the method includes, for a read operation, selecting a memory cell of a crosspoint array, each memory cell having a threshold switching selector, connected between a corresponding one of a plurality of first control lines and a corresponding one of a plurality of second control lines; biasing the selected memory cell at a positive voltage level through a first local select switch connected to the corresponding first control line; and simultaneously biasing the selected memory cell at a positive voltage level through the first local selector and a second local select switch connected to the corresponding second control line, wherein the voltage difference between the positive and negative voltage levels is greater than the on-voltage of the threshold switching selector of the selected memory cell, biasing the second local select switch to a saturated state before the threshold switching selector of the selected memory cell is turned on, and biasing the second local select switch to act as a source follower voltage clamp after the threshold switching selector of the selected memory cell is turned on.

[0110] In another set of embodiments, the memory device comprises a non-volatile memory cell structure including a plurality of non-volatile memory cells in a crosspoint arrangement, each memory cell having a programmable resistor connected in series with a threshold switching selector and between a corresponding one of a plurality of first control lines and a corresponding one of a plurality of second control lines; and one or more control circuits connected to the memory cell structure. The one or more control circuits are configured to select memory cells in the crosspoint array for a read operation, bias the selected memory cell at a positive voltage level through a first local selection switch connected to the corresponding first control line, and simultaneously bias the selected memory cell at a negative voltage level through a second local selection switch connected to the corresponding second control line, wherein the voltage difference between the positive and negative voltage levels is greater than the ON voltage of the threshold switching selector of the selected memory cell, bias the second local selection switch to a saturated state before the threshold switching selector of the selected memory cell turns ON, and bias the second local selection switch to act as a source follower voltage clamp after the threshold switching selector of the selected memory cell turns ON.

[0111] For the purposes of this specification, references to “embodiments,” “one embodiment,” “several embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0112] For the purposes of this specification, connections may be direct or indirect (e.g., through one or more other parts). Where it is referred that one element is connected or coupled to another, that element may be directly connected to the other element or indirectly connected to the other element through an intervening element. When it is said that one element is directly connected to another, there is no intervening element between that element and the other element. Two devices are “communicating” if they are connected directly or indirectly so that electronic signals can be communicated between them.

[0113] For the purposes of this specification, the term "based on" may be read as "based at least in part on."

[0114] For the purposes of this specification, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, may not imply an ordering of objects, but rather may be used for identifying purposes to distinguish different objects.

[0115] In this specification, the term “set” of objects may refer to one or more “sets” of objects.

[0116] The detailed description above is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosed form to the exact form. Many modifications and variations are possible in light of the above teachings. The embodiments described have been selected to best illustrate the principles of the proposed art and its practical application, thereby enabling other persons skilled in the art to best utilize it in various embodiments and with various modifications suitable for the specific use to be intended. The scope is intended to be defined by the claims appended herein.

Claims

1. A non-volatile memory device, A control circuit configured to connect to an array comprising a plurality of nonvolatile memory cells, each having a threshold switching selector, wherein the array comprises a control circuit having a crosspoint structure in which each of the memory cells is connected between a corresponding bit line and a corresponding word line, and the control circuit is A bipolar bit line decoder connected to the array and configured to selectively bias the corresponding bit line of a selected memory cell to one of a positive voltage level or a negative voltage level, wherein the bipolar bit line decoder is A plurality of bit-line local negative selector switches, each configured to supply a negative voltage level to the corresponding bit line of the selected memory cell, A bipolar bit-line decoder comprising: a plurality of bit-line local positive selector switches, each configured to supply a positive voltage level to the corresponding bit line of the selected memory cell; A bipolar word line decoder connected to the array and configured to selectively bias the corresponding word line of the selected memory cell to one of a positive voltage level or a negative voltage level, wherein the bipolar word line decoder A plurality of word-line local negative selector switches, each configured to supply the negative voltage level to the corresponding word line of the selected memory cell, A bipolar word line decoder comprising: a plurality of word line local positive selector switches, each configured to supply the positive voltage level to the corresponding word line of the selected memory cell; The aforementioned control circuit is To turn on the threshold switching selector of the selected memory cell, the selected memory cell is biased via the corresponding bit-line local negative select switch and the corresponding word-line local positive select switch, or via the corresponding word-line local negative select switch and the corresponding bit-line local positive select switch. A non-volatile memory device configured to bias and turn on a control gate on the local negative select switch on either the corresponding bit line or word line biasing the selected memory memory, thereby turning on the current through the local negative select switch on either the corresponding bit line or word line biasing the selected memory memory, and limiting the current level through the local negative select switch on either the corresponding bit line or word line biasing the selected memory memory after the threshold switching selector for the selected memory memory has been switched on.

2. The non-volatile memory device according to claim 1, wherein the bit-line local positive selector switch and the word-line local positive selector switch are PMOS devices, and the bit-line local negative selector switch and the word-line local negative selector switch are NMOS devices.

3. To turn on the threshold switching selector for the selected memory cell, via the corresponding bit-line local negative select switch and the corresponding word-line local positive select switch, or to bias the selected memory cell via the corresponding word-line local negative select switch and the corresponding bit-line local positive select switch, the control circuit shall The non-volatile memory device according to claim 2, configured to bias and turn on the control gate on the local negative select switch on either the corresponding bit line or word line that biases the selected memory, thereby bringing the select switch on either the corresponding bit line or word line that biases the selected memory into a saturation region.

4. The control circuit biases and turns on the control gate on the local negative select switch on either the corresponding bit line or word line biasing the selected memory, thereby turning on the current through the local negative select switch on either the corresponding bit line or word line biasing the selected memory, and after the threshold switching selector for the selected memory is switched on, in order to limit the current level through the local negative select switch on either the corresponding bit line or word line biasing the selected memory, The non-volatile memory device according to claim 3, further configured to bias and turn on the control gate on the local negative select switch on either the corresponding bit line or word line biasing the selected memory, thereby causing the select switch on either the corresponding bit line or word line biasing the selected memory to function as a source follower voltage clamp.

5. The aforementioned control circuit is The non-volatile memory device according to claim 1, further configured to bias and turn on a control gate on the local positive select switch on either the corresponding bit line or word line biasing the selected memory, thereby turning on the current through the local positive select switch on either the corresponding bit line or word line biasing the selected memory, and limiting the current level through the local negative select switch on either the corresponding bit line or word line biasing the selected memory after the threshold switching selector for the selected memory cell has been switched on.

6. The bipolar bit-line decoder is further configured to be connected to the array and to selectively bias the corresponding bit lines to ground voltage level, and the bipolar bit-line decoder is The memory further comprises a plurality of bit-line local grounding select switches, each configured to set the corresponding bit line of the selected memory to the grounding voltage level. The bipolar word line decoder is further configured to be connected to the array and to selectively bias the corresponding word line of the selected memory to a ground voltage level or a negative voltage level, and the bipolar word line decoder is A plurality of word line local grounding selector switches, each configured to supply the negative voltage level to the corresponding word line of the selected memory, The system further comprises a plurality of word-line local positive selector switches, each configured to set the corresponding bit line of the selected memory to the ground voltage level. The non-volatile memory device according to claim 1.

7. The non-volatile memory device according to claim 1, wherein each of the non-volatile memory cells further comprises a programmable resistance magnetoresistive random access memory (MRAM) element.

8. The non-volatile memory device according to claim 1, wherein each of the non-volatile memory cells further comprises a programmable resistive phase-change memory (PCM) element.

9. The non-volatile memory device according to claim 1, wherein each of the non-volatile memory cells is a self-selecting memory cell having a programmable resistor for the threshold switching selector.

10. The non-volatile memory device according to claim 1, further comprising the array, wherein the array is arranged on a die on the control circuit.

11. The control circuit is formed on a control die, and the non-volatile memory device is The non-volatile memory device according to claim 1, further comprising a memory die including the array, wherein the memory die is separated from the control die and bonded to the control die.

12. It is a method, For read operations, multiple memory cells, each equipped with a threshold switching selector, select memory cells in a crosspoint array connected between a corresponding one of a plurality of first control lines and a corresponding one of a plurality of second control lines, The selected memory cell is biased at a positive voltage level through a first local selection switch connected to the corresponding first control line, The selected memory cell is biased at a positive voltage level through the first local selection and simultaneously biased at a negative voltage level through a second local selection switch connected to the corresponding second control line, wherein the voltage difference between the positive voltage level and the negative voltage level is greater than the ON voltage of the threshold switching selector of the selected memory cell. Before the threshold switching selector of the selected memory cell is turned on, the second local selection switch is biased to a saturated state, This includes, after the threshold switching selector of the selected memory cell is turned on, biasing the second local selection switch so that it acts as a source follower voltage clamp, Methods that include...

13. By biasing the selected memory cell at the positive voltage level via the connected first local selection switch, Before the threshold switching selector of the selected memory cell is turned on, the first local selection switch is biased to a saturated state, The method according to claim 12, further comprising biasing the first local selection switch to act as a source follower voltage clamp after the threshold switching selector of the selected memory cell is turned on.

14. The method according to claim 12, wherein the threshold switching selector is an ovonic threshold switch (OTS).

15. The method according to claim 12, wherein the first control line is a bit line and the second control line is a word line.

16. After the threshold switching selector of the selected memory cell is turned on, the current passing through the selected memory cell is determined. The method according to claim 12, further comprising:

17. A memory device, A non-volatile memory cell structure comprising a plurality of non-volatile memory cells arranged in a crosspoint configuration, wherein each memory cell is in series with a threshold switching selector and has a programmable resistive element connected between a corresponding one of a plurality of first control lines and a corresponding one of a plurality of second control lines, The memory cell structure comprises one or more control circuits connected to the memory cell structure, and the control circuits are For read operations, select a memory cell in the crosspoint array. The selected memory cell is biased at a positive voltage level through a first local selection switch connected to the corresponding first control line. The selected memory cell is biased at the positive voltage level through the first local selection and simultaneously biased at the negative voltage level through a second local selection switch connected to the corresponding second control line, wherein the voltage difference between the positive voltage level and the negative voltage level is greater than the ON voltage of the threshold switching selector of the selected memory cell. Before the threshold switching selector of the selected memory cell is turned on, the second local selection switch is biased to a saturated state. A memory device configured such that, after the threshold switching selector of the selected memory cell is turned on, the second local selection switch is biased to act as a source follower voltage clamp.

18. The one or more connected control circuits are Before the threshold switching selector of the selected memory cell is turned on, the first local selection switch is biased to a saturated state. The memory device according to claim 17, further configured to bias the first local selection switch to act as a source follower voltage clamp after the threshold switching selector of the selected memory cell is turned on.

19. The one or more connected control circuits are The memory device according to claim 17, further configured to determine the current passing through the selected memory cell after the threshold switching selector of the selected memory cell is turned on.

20. The memory device according to claim 17, wherein the first control line is a bit line and the second control line is a word line.

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