Semiconductor device, display device, and method for manufacturing a semiconductor device.

Abstract

To suppress the decrease in channel resistance of semiconductor devices using oxide semiconductors. [Solution] A method for manufacturing a semiconductor device includes forming an oxide semiconductor layer on a first insulating layer, forming a second insulating layer on the oxide semiconductor layer, forming a conductive layer on the second insulating layer, forming a resist mask on the second insulating layer and the conductive layer having openings that overlap with at least a portion of the oxide semiconductor layer, and using the resist mask to inject impurities into the oxide semiconductor layer through the second insulating layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor, a display device including the same, and a method for manufacturing a semiconductor device.

Background Art

[0002] In recent years, development of semiconductor devices using oxide semiconductors has been underway instead of silicon semiconductors using amorphous silicon, low-temperature polysilicon, and single-crystalline silicon (see, for example, Patent Document 1). For example, a transistor that uses an oxide semiconductor layer including an oxide semiconductor as a channel can be manufactured with a simple structure and a low-temperature process, similar to a transistor including an amorphous silicon layer. A transistor including an oxide semiconductor layer is known to have a higher field-effect mobility than a transistor including an amorphous silicon layer.

Prior Art Documents

Patent Documents

[0003] [[ID=**21**]] [[ID=**22**]]

Patent Document **1**

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a transistor that uses an oxide semiconductor layer as a channel, deterioration of electrical characteristics due to a decrease in channel resistance often becomes a problem. For example, when hydrogen diffuses excessively into the oxide semiconductor constituting the channel, there is a problem that the channel resistance decreases and the transistor operates in the depletion mode unintentionally. [[ID=**37**]]

[0005] [[ID=**38**]] One embodiment of the present invention has an object to suppress a decrease in channel resistance of a semiconductor device using an oxide semiconductor.

Means for Solving the Problems

[0006] Note: The tags to and

[0005] to are repeated in the original text, so they are repeated in the translation as well. If there is an error in the original text regarding these tags, it may need to be corrected according to the actual situation. A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming an oxide semiconductor layer on a first insulating layer, forming a second insulating layer on the oxide semiconductor layer, forming a conductive layer on the second insulating layer, forming a resist mask having openings that overlap with at least a portion of the oxide semiconductor layer on the second insulating layer and the conductive layer, and using the resist mask to inject impurities into the oxide semiconductor layer through the second insulating layer.

[0007] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer on a first insulating layer, a second insulating layer on the oxide semiconductor layer, and a conductive layer on the second insulating layer, wherein the oxide semiconductor layer includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer, and the concentration of a predetermined impurity contained in the region of the second insulating layer overlapping with the second region is higher than the concentration of the impurity contained in the region of the second insulating layer not overlapping with the oxide semiconductor layer.

[0008] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer on a first insulating layer, a second insulating layer on the oxide semiconductor layer, and a conductive layer on the second insulating layer, wherein the oxide semiconductor layer includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer, and the concentration of a predetermined impurity contained in the region of the first insulating layer overlapping with the second region is higher than the concentration of the impurity contained in the region of the first insulating layer not overlapping with the oxide semiconductor layer. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic plan view showing the configuration of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 2] This is a schematic circuit diagram showing the equivalent circuit of a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 4]This is a flowchart illustrating a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 9] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 10A] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 10B] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 12] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 13] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 14] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 15] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 16] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 17] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 18] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 19A] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 19B] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 20A] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 20B] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 21] It is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 22] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 23] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 24] It is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are naturally included in the scope of the present invention. For the sake of clearer explanation, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of the components as compared with the actual aspect. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification, the claims, and the drawings (hereinafter referred to as "this specification, etc."), components similar to the above-described components in the already presented drawings may be denoted by the same reference numerals, and detailed descriptions may be appropriately omitted.

[0011] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the illustration. Also, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be arranged between the substrate and the oxide semiconductor layer. Upward or downward refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a plan view. On the other hand, when referring to a pixel electrode vertically above a semiconductor device, it means that the semiconductor device and the pixel electrode overlap in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0012] In this specification, multiple elements formed by processing a single film, such as etching, may be described as elements having different functions or roles. These multiple elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer. That is, when it is stated in this specification that "A and B are the same layer," it means that both element A and element B are elements formed by processing a single layer.

[0013] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other components.

[0014] In this specification, "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are included as forms of semiconductor devices. The semiconductor devices of the embodiments shown below can be used, for example, in display devices, integrated circuits (ICs) such as microprocessing units (MPUs), or memory circuits.

[0015] In this specification, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, although an organic EL display device including an organic EL layer will be used as an example to describe the embodiments described later, the structure in this embodiment can be applied to other display devices including the electro-optical layers described above.

[0016] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0017] The source and drain of a transistor may have their functions reversed depending on the voltage supplied to them. Therefore, in this specification, the terms "source" and "drain" may be interchangeable as needed.

[0018] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0019] <First Embodiment> (Display device configuration) The following describes a display device 10 according to one embodiment of the present invention. In this embodiment, an organic EL display device is exemplified as the display device 10. The organic EL display device is a display device in which each pixel includes an organic EL element as a light-emitting element and a semiconductor device for driving the light-emitting element.

[0020] Figure 1 is a schematic plan view showing the configuration of a display device 10 including a semiconductor device according to one embodiment of the present invention. As shown in Figure 1, the display device 10 includes a display unit 12 and a peripheral unit 19 provided on a substrate 11. The display unit 12 has a plurality of pixels 13 arranged in a matrix. Each of the plurality of pixels 13 has a semiconductor device composed of a plurality of transistors, which will be described later, and a light-emitting element. A touch sensor 20 is arranged on the display unit 12 and on the display unit 12.

[0021] The peripheral portion 19 is provided so as to surround the display unit 12. The peripheral portion 19 refers to the portion of the substrate 11 from the display unit 12 to the edge of the substrate 11. In other words, the peripheral portion 19 refers to the portion of the substrate 11 other than the portion on which the display unit 12 is provided (specifically, the portion outside the display unit 12). The peripheral portion 19 has gate drive circuits 14-1 and 14-2 and a terminal portion 17 including a plurality of terminals 16. The gate drive circuits 14-1 and 14-2 are provided so as to sandwich the display unit 12. A flexible printed circuit 18 equipped with a driver IC 15 is connected to the terminal portion 17. A plurality of wires (not shown) included in the flexible printed circuit 18 are connected to the driver IC 15 and the terminal portion 17. In the example shown in Figure 1, the source drive circuit is incorporated into the driver IC 15. However, the source drive circuit is not limited to this example and may be formed on the substrate 11 using transistors.

[0022] The driver IC 15 is connected to gate drive circuits 14-1 and 14-2 and to multiple video signal lines VL. Gate drive circuit 14-1 or gate drive circuit 14-2 is connected to the pixels 13 via selection control lines Sg. Of the multiple selection control lines Sg, for example, the selection control lines Sg for odd-numbered rows are connected to gate drive circuit 14-1, and the selection control lines Sg for even-numbered rows are connected to gate drive circuit 14-2. The video signal lines VL are connected to the pixels 13. The display unit 12 is supplied with a control signal SG (see Figure 2) from the driver IC 15 via the gate drive circuits 14-1 and 14-2 and the selection control lines Sg to select each pixel 13. The display unit 12 is also supplied with a video signal Vsig (see Figure 2) from the driver IC 15 via the video signal lines VL. These signals drive multiple transistors included in the pixels 13, enabling the display unit 12 to display an image corresponding to the video signal Vsig. The high-potential power line SLa and the low-potential power line SLb, connected to the pixel 13, are each connected to different terminals 16.

[0023] The substrate 11 can be a glass substrate, a quartz substrate, a ceramic substrate, a flexible plastic substrate, or a resin substrate. When a flexible plastic substrate or a resin substrate is used as the substrate 11, the substrate 11 can be bent between the display unit 12 and the terminal unit 17. This reduces the area of ​​the bezel portion of the display device 10.

[0024] (Pixel circuit configuration) Figure 2 is a schematic circuit diagram showing the circuit configuration of a pixel 13 including a semiconductor device according to one embodiment of the present invention. Each pixel 13 constituting the display device 10 is connected to a high-potential power line SLa, a low-potential power line SLb, a selection control line Sg, and a video signal line VL. The high-potential power line SLa is connected to a high-potential power supply Pvdd. The low-potential power line SLb is connected to a low-potential power supply Pvss. The selection control line Sg is connected to gate drive circuits 14-1 and 14-2. The video signal line VL is connected to a driver IC 15 that supplies the video signal Vsig.

[0025] Each pixel 13 has at least a drive transistor DRT, a selection transistor SST, and a light-emitting element OLED. A high-potential power supply Pvdd is connected to the anode of the light-emitting element OLED via the drive transistor DRT. A low-potential power supply Pvss is connected to the cathode of the light-emitting element OLED. In this embodiment, the anode of the light-emitting element OLED is connected to the pixel electrode 200 (see Figure 3), and the cathode is connected to the common electrode 230 (see Figure 3).

[0026] The drive transistor DRT is connected in series with the light-emitting element OLED between the high-potential power line SLa and the low-potential power line SLb. The drive transistor DRT functions as a current control element that controls the current flowing to the light-emitting element OLED according to the gate-source voltage. The selection transistor SST functions as a switching element that selects conduction or non-conductivity between two nodes and applies a voltage to the gate of the drive transistor DRT that corresponds to the luminescence brightness of the light-emitting element OLED. A retaining capacitor Cs is provided between the gate and source of the drive transistor DRT. The retaining capacitor Cs maintains the gate-source voltage of the drive transistor DRT.

[0027] The selection transistor SST has its gate connected to the selection control line Sg, one of its source or drain connected to the video signal line VL, and the other of its source or drain connected to the gate and retaining capacitance Cs of the drive transistor DRT. The drive transistor DRT has its drain connected to the high-potential power line SLa, and its source connected to the retaining capacitance Cs and the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is connected to the low-potential power line SLb. The drive transistor DRT outputs a drive current to the light-emitting element OLED in an amount corresponding to the video signal Vsig.

[0028] Although not shown in the diagram, pixel 13 may further include other transistors such as a correction transistor for correcting the threshold of the drive transistor DRT, and a reset transistor for resetting the voltage held in the holding capacitance Cs.

[0029] In this embodiment, oxide semiconductors are used as the semiconductors for the selection transistor SST and the drive transistor DRT. Transistors using oxide semiconductors have the advantage of low power consumption because they have a low off-leak current and can be driven at low frequencies. Therefore, by configuring pixels using oxide semiconductors, the power consumption of the display device 10 can be reduced. Furthermore, transistors using oxide semiconductors have the advantage of not exhibiting a kink effect and having good saturation characteristics compared to transistors using so-called low-temperature polysilicon.

[0030] (Pixel structure) Figure 3 is a schematic cross-sectional view showing the configuration of a pixel 13 including a semiconductor device according to one embodiment of the present invention. The pixel 13 shown in Figure 3 includes a drive transistor DRT that supplies current to the light-emitting element OLED as a semiconductor device. Although not shown in Figure 3, the pixel 13 also includes a selection transistor SST as shown in Figure 2. The pixel 13 shown in Figure 3 may include many more transistors in addition to the drive transistor DRT and the selection transistor SST.

[0031] The drive transistor DRT of this embodiment includes a conductive layer 110, an insulating layer 120, an oxide semiconductor layer 130, an insulating layer 140, a conductive layer 150, an insulating layer 160, a conductive layer 181, and a conductive layer 182, which are provided on a substrate 100 having an insulating surface.

[0032] The substrate 100 is, for example, a glass substrate on which one or more insulating layers are formed, each layer being made of a material selected from insulating oxides such as silicon oxide (SiOx) or silicon oxide nitride (SiOxNy), or insulating nitrides such as silicon nitride (SiNx) or silicon oxide nitride (SiNxOy). Here, silicon oxide nitride (SiNxOy) is a silicon oxide containing oxygen in a smaller proportion than nitrogen (x>y). Silicon oxide nitride (SiOxNy) is a silicon nitride containing nitrogen (N) in a smaller proportion than oxygen (O) (x>y).

[0033] In this embodiment, a substrate 100 having an insulating surface is constructed by laminating a silicon nitride layer and a silicon oxide layer on a glass substrate in that order from bottom to top. The silicon nitride layer serves as a protective layer to prevent the intrusion of contaminants (e.g., alkaline substances) from the glass substrate. However, this is not limited to this example, and a quartz substrate, ceramic substrate, plastic substrate, or resin substrate may be used instead of the glass substrate. Furthermore, the lamination order of the silicon oxide layer, silicon nitride layer, silicon oxide-nitride layer, or silicon nitride-oxide layer is arbitrary.

[0034] The conductive layer 110 is provided on the substrate 100. The conductive layer 110 functions as the lower gate electrode in the drive transistor DRT. The conductive layer 110 can be made of materials such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material for the conductive layer 110. The conductive layer 110 also functions as a light-shielding layer that reduces the amount of light reaching the oxide semiconductor layer 130 from the lower layer.

[0035] The insulating layer 120 is provided on top of the conductive layer 110. The insulating layer 120 functions as the lower gate insulating layer in the drive transistor DRT. As the insulating layer 120, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be used. In this embodiment, as the insulating layer 120, an insulating layer is used in which a silicon nitride layer and a silicon oxide layer are stacked in order from bottom to top. As will be described later, since an oxide semiconductor layer 130 is provided on top of the insulating layer 120, it is preferable that the surface of the insulating layer 120 that is in contact with the oxide semiconductor layer 130 is a silicon oxide layer.

[0036] The thickness of the insulating layer 120 is not particularly limited. In this embodiment, the thickness of the insulating layer 120 is 200 nm or more and 600 nm or less (preferably 300 nm or more and 500 nm or less, and more preferably 350 nm or more and 450 nm or less). In this embodiment, a laminated structure consisting of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm is used as the insulating layer 120.

[0037] The oxide semiconductor layer 130 is provided on top of the insulating layer 120. The oxide semiconductor layer 130 functions as the active layer in the drive transistor DRT. As the material constituting the oxide semiconductor layer 130, an amorphous oxide semiconductor (for example, IGZO) can be used. The thickness of the oxide semiconductor layer 130 can be 10 nm or more and 100 nm or less (preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 40 nm or less).

[0038] In this embodiment, the oxide semiconductor layer 130 can be formed using a sputtering method. The composition of the oxide semiconductor layer 130 formed using the sputtering method depends on the composition of the sputtering target.

[0039] Furthermore, as shown in Figure 3, the oxide semiconductor layer 130 is divided into a channel region CR, a source region SR, and a drain region DR. The channel region CR is a region that overlaps with the conductive layer 150, which functions as a gate electrode, and forms a channel when a gate voltage is applied to the conductive layer 150. The source region SR and the drain region DR are regions with lower resistance than the channel region CR and function as conductive regions. In other words, the source region SR and the drain region DR have higher electrical conductivity than the channel region CR. To put it another way, the source region SR and the drain region DR have the properties of a conductor, while the channel region has the properties of a semiconductor. As will be described later, the source region SR and the drain region DR are formed by adding impurities to the oxide semiconductor layer 130 using methods such as ion implantation.

[0040] The insulating layer 140 is provided on top of the oxide semiconductor layer 130. The insulating layer 140 functions as the upper gate insulating layer in the drive transistor DRT. As the insulating layer 140, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be used. In this embodiment, a silicon oxide layer is used as the insulating layer 140. It is preferable that the insulating layer 140 has few defects and a composition close to the stoichiometric ratio. Specifically, the insulating layer 140 is electron spin resonance (Electron It is preferable that no defects are observed when evaluated by the Spin Resonance (ESR) method. The thickness of the insulating layer 140 is not particularly limited. In this embodiment, the thickness of the insulating layer 140 is 50 nm or more and 300 nm or less (preferably 60 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less).

[0041] The conductive layer 150 is provided on top of the insulating layer 140. The conductive layer 150 functions as the gate electrode on the upper side of the drive transistor DRT. The materials that make up the conductive layer 150 can be aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material that makes up the conductive layer 150. The conductive layer 150 also functions as a light-shielding layer that reduces the amount of light reaching the oxide semiconductor layer 130 from the upper side.

[0042] As described above, the conductive layer 150 functions as the upper gate electrode in the drive transistor DRT, but at the same time, it also functions as gate wiring. In other words, the conductive layer 150 functions as gate wiring, and the portion of the gate wiring that overlaps with the oxide semiconductor layer that functions as the active layer of the transistor functions as the gate electrode. Therefore, for the sake of explanation, the gate electrode and gate wiring may be described separately in this specification, but they may be a single integrated component.

[0043] The insulating layer 160 is provided on top of the conductive layer 150. The insulating layer 160 functions as an interlayer insulating layer in the drive transistor DRT. As the insulating layer 160, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon oxide nitride layer can be used. In this embodiment, a laminated structure including a silicon oxide layer and a silicon nitride layer is used as the insulating layer 160.

[0044] The conductive layers 181 and 182 are provided on the insulating layer 160. Conductive layer 181 is connected to the source region SR of the oxide semiconductor layer 130 via a contact hole 161 provided in the insulating layer 160 and functions as the source electrode in the drive transistor DRT. Conductive layer 182 is connected to the drain region DR of the oxide semiconductor layer 130 via a contact hole 162 provided in the insulating layer 160 and functions as the drain electrode in the drive transistor DRT. In other words, conductive layers 181 and 182 each function as terminal electrodes in the drive transistor DRT.

[0045] The materials that make up the conductive layers 181 and 182 can be aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a laminated structure including a titanium layer and an aluminum layer is used as the material that makes up the conductive layers 181 and 182.

[0046] As described above, the drive transistor DRT of this embodiment is a dual-gate transistor that includes a lower gate electrode (conductive layer 110) facing the oxide semiconductor layer 130 via an insulating layer 120, and an upper gate electrode (conductive layer 150) facing the oxide semiconductor layer 130 via an insulating layer 140. However, it is not limited to this example, and the drive transistor DRT may also be a top-gate transistor. For example, if the conductive layer 110 shown in Figure 3 is not used as a gate electrode, such as by applying a fixed voltage to the conductive layer 110, the drive transistor DRT functions as a top-gate transistor.

[0047] An insulating layer 190, made of resin material, is provided on the drive transistor DRT as a planarization layer. The pixel electrode 200 is connected to the conductive layer 181 (i.e., the source electrode of the drive transistor DRT) via a contact hole 191 provided in the insulating layer 190. In this embodiment, a laminated structure of a layer containing silver (Ag) and a layer containing a metal oxide (e.g., ITO) is used as the pixel electrode 200, but the invention is not limited to this example.

[0048] A bank 210 made of resin material is provided above the pixel electrode 200. The bank is also called a partition or rib. The bank 210 is provided so as to cover a portion of the pixel electrode 200. In other words, the bank 210 has an opening 212 at a position that overlaps with the pixel electrode 200. The portion of the pixel electrode 200 not covered by the bank 210 (exposed region) functions as the light-emitting region of the pixel 13. A light-emitting layer 220 made of organic EL (electroluminescent) material is provided so as to cover the exposed region of the pixel electrode 200.

[0049] Furthermore, a common electrode 230 is provided so as to cover the bank 210 and the light-emitting layer 220. Although not shown in Figure 3, the common electrode 230 is arranged to span multiple pixels 13. The pixel electrode 200, the light-emitting layer 220, and the common electrode 230 constitute a light-emitting OLED. The pixel electrode 200 functions as the anode of the light-emitting OLED. The common electrode 230 functions as the cathode of the light-emitting OLED.

[0050] A sealing layer 240 is provided on top of the light-emitting element OLED. The sealing layer 240 is a protective layer to prevent the intrusion of moisture and other external elements. In this embodiment, a laminated structure is used for the sealing layer 240, in which an inorganic insulating layer, an organic insulating layer, and another inorganic insulating layer are stacked in that order from the bottom. For example, a silicon nitride layer can be used as the inorganic insulating layer. For example, an organic resin layer (for example, a resin layer composed of polyimide or acrylic) can be used as the organic insulating layer.

[0051] As explained above, pixel 13 is equipped with a drive transistor DRT, and in relation to the manufacturing method described later, a characteristic impurity distribution exists around the drive transistor DRT. This point will be described in detail below along with the manufacturing method of the semiconductor device.

[0052] (Method of manufacturing pixels) Figure 4 is a flowchart illustrating a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. Figures 5 to 18 are schematic cross-sectional views showing a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. As shown in Figure 4, the method for manufacturing a semiconductor device according to this embodiment includes steps S1010 to S1130. Steps S1010 to S1130 will be described in order below, but the order of the steps in the method for manufacturing a semiconductor device according to this embodiment may be changed. In addition, in the method for manufacturing a semiconductor device according to this embodiment, one or more steps may be omitted, or further steps may be included.

[0053] First, as shown in Figures 4 and 5, a conductive layer 110 (first conductive layer) having a predetermined pattern shape is formed on the substrate 100 (step S1010). The patterning of the conductive layer 110 is performed using photolithography. In this embodiment, the conductive layer 110 functions as a light-shielding layer.

[0054] Next, as shown in Figures 4 and 6, an insulating layer 120 (first insulating layer) is formed to cover the conductive layer 110. The insulating layer 120 is deposited using chemical vapor deposition (CVD). In this embodiment, the insulating layer 120 is a laminated structure consisting of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm.

[0055] Next, as shown in Figures 4 and 7, an oxide semiconductor layer 130 having a predetermined pattern shape is formed on the insulating layer 120 (step S1030). The oxide semiconductor layer 130 is formed to overlap with the conductive layer 110. The oxide semiconductor layer 130 is formed by patterning an oxide semiconductor film, which has been deposited using a sputtering method, into a predetermined shape using photolithography.

[0056] Amorphous oxide semiconductor films can be easily patterned using photolithography. When etching oxide semiconductor films, either wet etching or dry etching may be used. When using wet etching, an acidic etching solution can be used to etch the oxide semiconductor film. For example, oxalic acid solution, PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) solution, sulfuric acid solution, hydrogen peroxide solution, or hydrofluoric acid solution can be used as the etching solution.

[0057] Furthermore, the oxide semiconductor layer 130 having a predetermined pattern shape is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1030 will be referred to as "OS annealing". In OS annealing, the oxide semiconductor layer 130 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300°C or higher and 500°C or lower (preferably 350°C or higher and 450°C or lower). The holding time at the temperature is 15 minutes or higher and 120 minutes or lower (preferably 30 minutes or higher and 60 minutes or lower).

[0058] Next, as shown in Figures 4 and 8, an insulating layer 140 (second insulating layer) is formed on the oxide semiconductor layer 130 (step S1040). In this embodiment, a silicon oxide layer with a thickness of 100 nm is used as the insulating layer 140. Furthermore, the insulating layer 140 is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1040 will be referred to as "oxidation annealing". Due to the formation of the oxide semiconductor layer 130 and the insulating layer 140, many oxygen vacancies are generated inside the oxide semiconductor layer 130. When oxidation annealing is performed, oxygen is supplied from the insulating layer 140 to the oxide semiconductor layer 130, and the oxygen vacancies in the oxide semiconductor layer 130 are repaired.

[0059] In this embodiment, an example is shown in which an oxide annealing is performed after the insulating layer 140 has been formed. However, a process to introduce oxygen into the insulating layer 140 may be performed before the oxide annealing. For example, an aluminum oxide layer may be formed on the insulating layer 140 by sputtering, and the oxide annealing may be performed with the aluminum oxide layer formed. In this case, oxygen is injected into the interior of the insulating layer 140 when the aluminum oxide layer is formed, increasing the amount of oxygen inside the insulating layer 140. As a result, a sufficient amount of oxygen can be supplied to the oxide semiconductor layer 130 by the oxide annealing.

[0060] Next, as shown in Figures 4 and 9, a conductive layer 150 (second conductive layer) is formed on the insulating layer 140 (step S1050). In this embodiment, the conductive layer 150 functions as gate wiring. In this embodiment, a metal film made of a molybdenum-tungsten alloy is formed using a sputtering method, and the conductive layer 150 is formed by patterning the metal film into a predetermined shape. In this embodiment, the thickness of the conductive layer 150 is 300 nm, but it is not limited to this example.

[0061] Next, as shown in Figures 4, 10A, and 10B, a resist mask RM is formed on the insulating layer 140 (step S1060). In this embodiment, the resist mask RM is formed in a region that does not overlap with the oxide semiconductor layer 130. Specifically, the resist mask RM has an opening RM1 that overlaps with the entire oxide semiconductor layer 130. That is, as shown in Figure 10A, the position of the inner wall of the opening RM1 and the position of the edge of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. In other words, as shown in Figures 10A and 10B, in a plan view, the outer shape of the edge of the opening RM1 provided in the resist mask RM coincides with the outer shape of the edge of the oxide semiconductor layer 130. Here, "coincides" includes not only cases where they perfectly coincide, but also cases where they fall within the range of error in the alignment when forming the resist mask RM. For example, even if the position of the outer shape of the edge of the opening RM1 and the position of the outer shape of the edge of the oxide semiconductor layer 130 differ by a range of 1.5 μm (preferably 1.0 μm, more preferably 0.5 μm), the outer shape of the edge of the opening RM1 and the outer shape of the edge of the oxide semiconductor layer 130 are considered to be the same.

[0062] Next, as shown in Figures 4 and 11, impurities are implanted into the oxide semiconductor layer 130 via the insulating layer 140 (step S1070). The impurities can be implanted into the oxide semiconductor layer 130, for example, by ion implantation. Examples of impurities that can be used include argon (Ar), phosphorus (P), or boron (B). However, other elements may also be used, not limited to these examples.

[0063] In this embodiment, since the conductive layer 150 is formed on the oxide semiconductor layer 130, the conductive layer 150 functions as a mask, inhibiting the implantation of impurities into a portion of the oxide semiconductor layer 130. Therefore, in the oxide semiconductor layer 130, impurities are not implanted in the region overlapping with the conductive layer 150, and a channel region CR is formed in that region. In addition, in the oxide semiconductor layer 130, a source region SR and a drain region DR are formed in the region where impurities are implanted because the oxide semiconductor layer 130 does not overlap with the conductive layer 150. In the source region SR and drain region DR, oxygen vacancies are generated inside the oxide semiconductor layer 130 by the implantation of impurities, and hydrogen is trapped in these oxygen vacancies. As a result, the source region SR and drain region DR are conductive and have higher electrical conductivity than the channel region CR.

[0064] Here, the technical significance of placing the resist mask RM in this embodiment will be explained. In this embodiment, impurities are added to the oxide semiconductor layer 130 by passing through the insulating layer 140. In this embodiment, since a silicon oxide layer is used as the insulating layer 140, Si-O bonds and Si-H bonds contained in the silicon oxide layer may be broken by collisions with impurities. As a result, oxygen and hydrogen are generated in the region of the insulating layer 140 through which the impurities passed during ion implantation. In particular, the generated hydrogen easily moves within the insulating layer 140 when heat is applied in a later process. Such hydrogen diffusion can be a factor that leads to, for example, a decrease in the resistance of the channel region CR (i.e., a decrease in channel resistance).

[0065] Therefore, in this embodiment, a resist mask RM is placed around the oxide semiconductor layer 130 to minimize the area of ​​the insulating layer 140 exposed to ion implantation. In the region where the resist mask RM is placed, impurities cannot pass through the inside of the insulating layer 140, thus preventing the generation of hydrogen inside the insulating layer 140. During ion implantation, the region where the oxide semiconductor layer 130 is not formed occupies a significantly larger area than the region where the oxide semiconductor layer 130 is formed. In other words, by placing the resist mask RM around the oxide semiconductor layer 130, the amount of hydrogen generated near the oxide semiconductor layer 130 can be significantly reduced, and the decrease in channel resistance due to hydrogen diffusion can be efficiently suppressed.

[0066] As described above, in this embodiment, when impurities are added to the oxide semiconductor layer 130 to form the source region SR and drain region DR, a resist mask RM is placed around the oxide semiconductor layer 130 to reduce the amount of hydrogen generated inside the insulating layer 140. This suppresses the decrease in channel resistance due to hydrogen diffusion and enables the manufacture of a highly reliable semiconductor device.

[0067] Incidentally, when impurities are added by ion implantation, the acceleration voltage and dose are determined to target the oxide semiconductor layer 130 in the depth direction. In other words, the impurities implanted into the oxide semiconductor layer 130 and the insulating layer 140 by ion implantation have a predetermined distribution in the depth direction, and the acceleration voltage is adjusted so that the peak of the distribution is located in the oxide semiconductor layer 130. Conversely, according to this embodiment, the insulating layer 120 contains impurities that have passed through the oxide semiconductor layer 130, and the insulating layer 140 contains impurities that have not reached the oxide semiconductor layer 130. This means that when the process shown in Figure 11 is carried out, a characteristic impurity distribution is formed around the oxide semiconductor layer 130.

[0068] Figure 12 is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. Figure 12 shows a diagram (bottom) showing the state immediately after performing the process shown in Figure 11, and an enlarged view (top) of the vicinity of the source region SR of the oxide semiconductor layer 130. In the enlarged view shown in Figure 12, the insulating layers 120 and 140 are each divided into three regions. Each of these divisions will be described below.

[0069] The insulating layer 120 is divided into a first region BR1, a second region BR2, and a third region BR3. The first region BR1 is a region that overlaps with both the oxide semiconductor layer 130 and the conductive layer 150. The second region BR2 is a region that overlaps with the oxide semiconductor layer 130 but not with the conductive layer 150. The third region BR3 is a region that does not overlap with either the oxide semiconductor layer 130 or the conductive layer 150. In this embodiment, the insulating layer 120 has a laminated structure composed of a silicon nitride layer and a silicon oxide layer, in that order from the substrate 100 side. That is, the above three divisions in the insulating layer 120 substantially correspond to three regions obtained by dividing the silicon oxide layer in contact with the oxide semiconductor layer 130.

[0070] The insulating layer 140, like the insulating layer 120, is divided into a first region GR1, a second region GR2, and a third region GR3. The first region GR1 is the region that overlaps with both the oxide semiconductor layer 130 and the conductive layer 150. The second region GR2 is the region that overlaps with the oxide semiconductor layer 130 but not with the conductive layer 150. The third region GR3 is the region that does not overlap with either the oxide semiconductor layer 130 or the conductive layer 150.

[0071] According to this embodiment, since the conductive layer 150 and the resist mask RM function as masks, no impurities are added directly beneath the conductive layer 150 and the resist mask RM. In other words, in the case of the insulating layer 120, the first region BR1 and the third region BR3 do not contain impurities, while the second region BR2 contains impurities. To put it another way, the concentration of impurities in the region of the insulating layer 120 that overlaps with the source region SR (second region BR2) is higher than the concentration of impurities in the region of the insulating layer 120 that does not overlap with the oxide semiconductor layer 130 (third region BR3). Furthermore, the concentration of impurities in the region of the insulating layer 120 that overlaps with the source region SR (second region BR2) is higher than the concentration of impurities in the region of the insulating layer 120 that overlaps with the channel region CR (first region BR1). The difference in impurity concentration varies depending on the acceleration voltage and dose, but it can be said that the concentration of impurities in the second region BR2 is 100 times (preferably 1000 times) or more than the concentration of impurities in the first region BR1 and the third region BR3.

[0072] The same applies to the insulating layer 140 as to the insulating layer 120. That is, in the case of the insulating layer 140, the first region GR1 and the third region GR3 do not contain impurities, while the second region GR2 contains impurities. In other words, the concentration of impurities in the region of the insulating layer 140 that overlaps with the source region SR (second region GR2) is higher than the concentration of impurities in the region of the insulating layer 140 that does not overlap with the oxide semiconductor layer 130 (third region GR3). Furthermore, the concentration of impurities in the region of the insulating layer 140 that overlaps with the source region SR (second region GR2) is higher than the concentration of impurities in the region of the insulating layer 140 that overlaps with the channel region CR (first region GR1). The difference in impurity concentration varies depending on the acceleration voltage and dose amount, but it can be said that the concentration of impurities in the second region GR2 is 100 times (preferably 1000 times) or more than the concentration of impurities in the first region GR1 and the third region GR3.

[0073] As described above, when the process shown in Figure 11 is carried out, it is possible to clearly distinguish whether or not impurities are contained in the insulating layer 120 or the insulating layer 140 depending on whether or not they are superimposed on the oxide semiconductor layer 130. In other words, by analyzing the impurity concentration around the oxide semiconductor layer 130 using SIMS or the like, it is possible to easily determine whether or not the process shown in Figure 11 has been carried out.

[0074] Next, as shown in Figures 4 and 13, a third insulating layer (insulating layer 160) is formed to cover the conductive layer 150 (step S1080). In this embodiment, the insulating layer 160 has a laminated structure in which a silicon oxide layer and a silicon nitride layer are stacked in order from the bottom layer by plasma CVD. The insulating layer 160 may have a laminated structure in which a silicon nitride layer and a silicon oxide layer are stacked in order from the bottom layer, or it may have a single-layer structure of a silicon nitride layer or a silicon oxide layer. Furthermore, contact holes 161 and 162 are formed in the portions of the insulating layers 140 and 160 that overlap with the source region SR and drain region DR of the oxide semiconductor layer 130, respectively.

[0075] Next, as shown in Figures 4 and 14, a third conductive layer (conductive layers 181 and 182) is formed on the insulating layer 160 (step S1090). Specifically, a three-layer metal layer consisting of a titanium layer, an aluminum layer, and a titanium layer in that order is formed by sputtering, and the conductive layers 181 and 182 are formed by patterning the metal layer into a predetermined shape. The conductive layers 181 and 182 are electrically connected to the oxide semiconductor layer 130 via contact holes 161 and 162, respectively. That is, conductive layer 181 is connected to the source region SR and functions as a source electrode, and conductive layer 182 is connected to the drain region DR and functions as a drain electrode.

[0076] Next, as shown in Figures 4 and 15, a fourth insulating layer (insulating layer 190) is formed to cover the conductive layers 181 and 182 (step S1100). The insulating layer 190 in this embodiment is formed by applying a resin material (for example, acrylic or polyimide) by a solution coating method. In this embodiment, a photosensitive acrylic material is used as the insulating layer 190. By performing exposure and photosensitization using a photosensitive resin material, an insulating layer 190 having contact holes 191 can be formed. In this embodiment, contact holes 191 are formed in the portion of the insulating layer 190 that overlaps with the conductive layer 181.

[0077] In this embodiment, an example is shown in which the insulating layer 190 is formed by a solution coating method, but it is not limited to this example, and it is also possible to form it by other methods such as printing. The insulating layer 190 functions as a planarization layer. Therefore, it is preferable that the thickness of the insulating layer 190 be 1 μm or more and 4 μm or less (preferably 2 μm or more and 3 μm or less).

[0078] Next, as shown in Figures 4 and 16, a pixel electrode 200 is formed on the insulating layer 190 (step S1110). Specifically, a transparent conductive film (metal oxide film) is deposited on the insulating layer 190 by sputtering, and the pixel electrode 200 is formed by patterning it into a predetermined pattern shape. In this embodiment, ITO (indium tin oxide), a metal oxide, is used as the material constituting the pixel electrode 200. The pixel electrode 200 is electrically connected to the conductive layer 181, which functions as a source electrode, via a contact hole 191.

[0079] Next, as shown in Figures 4 and 17, a bank 210 is formed on the pixel electrode 200 (step S1120). A resin material (for example, a photosensitive acrylic material) can be used as the material for the bank 210. Specifically, after applying the resin material by a solution coating method or the like, exposure and development are performed to form a bank 210 including an opening 212. As shown in Figure 17, the opening 212 provided in the bank 210 exposes most of the upper surface of the pixel electrode 200.

[0080] After forming the bank 210, an emissive layer 220 made of organic EL material is formed so as to overlap with the opening 212. In this embodiment, the emissive layer 220 is formed by vapor deposition using an organic EL material that emits red, green, or blue light. The emissive layer 220 is formed with different emission colors for each pixel 13. That is, a red-emitting organic EL material is used for pixels 13 that emit red light, a green-emitting organic EL material is used for pixels 13 that emit green light, and a blue-emitting organic EL material is used for pixels 13 that emit blue light. In addition to the emissive layer made of emissive material, the emissive layer 220 may also include an electron injection layer, an electron transport layer, an electron blocking layer, a hole injection layer, a hole transport layer, or a hole blocking layer as a functional layer made of functional material.

[0081] A common electrode 230 is formed on the light-emitting layer 220. In this embodiment, a layer containing magnesium silver is formed as the common electrode 230 by a vapor deposition method. The common electrode 230 may be provided across multiple pixels. With the formation of the common electrode 230, a light-emitting OLED composed of the pixel electrode 200, the light-emitting layer 220, and the common electrode 230 is formed.

[0082] Finally, as shown in Figures 4 and 18, a sealing layer 240 is formed to cover the light-emitting element OLED (step S1130). Although not shown, the sealing layer 240 has a laminated structure in which a silicon nitride layer, an organic resin layer (e.g., an acrylic layer), and a silicon nitride layer are stacked in order from the bottom layer. However, this is not limited to this example, and a silicon oxide layer or an amorphous silicon layer may be provided between the silicon nitride layer and the organic resin layer. By providing these layers, the adhesion between the silicon nitride layer and the organic resin layer can be improved. Also, in this embodiment, since a touch sensor 20 (see Figure 1) is provided on the sealing layer 240, an overcoat layer may be provided on the sealing layer 240 for the purpose of planarization.

[0083] Through the process described above, a pixel 13 including a drive transistor DRT is completed as a semiconductor device. In this embodiment, the amount of hydrogen generated in the insulating layer 120 and insulating layer 140 during ion implantation can be significantly reduced. Therefore, hydrogen diffusion after ion implantation can be effectively suppressed, and a highly reliable semiconductor device with suppressed decrease in channel resistance can be manufactured.

[0084] (Modification of the first embodiment) As shown in Figures 10A and 10B, this embodiment exemplifies a configuration in which the position of the inner wall of the opening RM1 of the resist mask RM and the position of the edge of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. However, the embodiment is not limited to this example, and the size of the opening RM1 may be larger or smaller than the size of the oxide semiconductor layer 130.

[0085] Figures 19A and 19B are schematic cross-sectional views showing a method for manufacturing a pixel 13 including a semiconductor device according to a modified example of one embodiment of the present invention. In this modified example, the resist mask RM is arranged to overlap the edge of the oxide semiconductor layer 130 by a predetermined distance (here, L1). Specifically, as shown in Figure 19B, the resist mask RM is arranged along the outer circumference of the oxide semiconductor layer 130 so as to overlap by a width of L1. There are no particular restrictions on the range of distance L1, but it is desirable to set it to 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less). If the distance L1 is too large, it will reduce the effective area of ​​the oxide semiconductor layer 130. Also, if the distance L1 is too small, when the resist mask RM shifts position, there may be a portion where the oxide semiconductor layer 130 and the resist mask RM do not overlap.

[0086] As described above, in the case of Modification 1, the size of the opening RM1 of the resist mask RM is smaller than the size of the oxide semiconductor layer 130. In other words, in a plan view, the outline (contour) of the edge of the oxide semiconductor layer 130 encompasses the outline (contour) of the edge of the opening RM1. With this configuration, the area in which impurities are added in the insulating layer 140 can be made as small as possible. Therefore, the amount of hydrogen generated around the oxide semiconductor layer 130 can be significantly suppressed.

[0087] Next, Figures 20A and 20B are schematic cross-sectional views showing a method for manufacturing a pixel 13 including a semiconductor device according to a modified example of one embodiment of the present invention. In this modified example, the resist mask RM is positioned so as to be separated from the edge of the oxide semiconductor layer 130 by a predetermined distance (here, L2). Specifically, as shown in Figure 20B, the resist mask RM is positioned along the outer circumference of the oxide semiconductor layer 130 so as to be separated from the oxide semiconductor layer 130 by a width of L2. There are no particular restrictions on the range of distance L2, but it is desirable to set it to 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less). If the distance L2 is too large, the exposed area of ​​the insulating layer 140 will increase, which may lead to an increase in the amount of hydrogen generated inside the insulating layer 140. Also, if the distance L2 is too small, the oxide semiconductor layer 130 and the resist mask RM may overlap when the resist mask RM is misaligned, which may reduce the effective area of ​​the oxide semiconductor layer 130.

[0088] As described above, in the case of Modification 2, the size of the opening RM1 of the resist mask RM is larger than the size of the oxide semiconductor layer 130. In other words, in a plan view, the outer shape (contour) of the edge of the opening RM1 encompasses the outer shape (contour) of the edge of the oxide semiconductor layer 130. With this configuration, the oxide semiconductor layer 130 (especially the source region SR and the drain region DR) can be made to the designed size without compromising its area. Therefore, it is possible to prevent problems such as poor contact between the conductive layer 181 and the source region SR or between the conductive layer 182 and the drain region DR.

[0089] <Second Embodiment> In the first embodiment, an example was described in which a channel region CR, a source region SR, and a drain region DR were provided in the oxide semiconductor layer 130. In this embodiment, an example is described in which a low-resistance region HRR is provided in addition to those regions. In the description of this embodiment, elements identical to those in the first embodiment may be denoted by the same reference numerals in the drawings and their descriptions may be omitted.

[0090] (Pixel structure) Figure 21 is a schematic cross-sectional view showing the configuration of a pixel 13a including a semiconductor device according to one embodiment of the present invention. The basic structure of Figure 21 is the same as that of the pixel 13 shown in Figure 3, but the configuration of the oxide semiconductor layer 130a, which functions as the active layer of the semiconductor device, is different. Specifically, the oxide semiconductor layer 130a has low-resistance regions HRR between the channel region CR and the source region SR, and between the channel region CR and the drain region DR.

[0091] The low-resistance region (HRR) is a region with relatively lower resistance than the channel region (CR). However, the resistance of the low-resistance region (HRR) is higher than that of the source region (SR) and the drain region (DR). The low-resistance region (HRR) functions as a buffer region that suppresses the carrier movement speed from the channel region (CR) to the source region (SR) or drain region (DR). In other words, functionally, it is similar to the region generally called the LDD region.

[0092] (Method of manufacturing pixels) Figures 22 and 23 are schematic cross-sectional views showing a method for manufacturing a pixel 13a including a semiconductor device according to one embodiment of the present invention.

[0093] First, in the first embodiment, steps S1010 to S1060 shown in Figure 4 are performed to form a resist mask RM on the insulating layer 140. As shown in Figure 22, this embodiment differs from the first embodiment in that the resist mask RM is provided on the oxide semiconductor layer 130 so as to cover the conductive layer 150. In this case, the width of the resist mask RM covering the conductive layer 150 in the channel direction is set to be wider than the width of the conductive layer 150 in the channel direction. That is, the opening RM1 of the resist mask RM and the conductive layer 150 are separated by a predetermined distance (here L3) in the channel direction. There are no particular restrictions on the range of distance L3, but it is desirable to set it to 0.5 μm or more and 3.0 μm or less (preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.5 μm or more and 2.0 μm or less). In this case, the opening RM1 is formed so as to overlap with the region of the oxide semiconductor layer 130 that will later function as the source region SR and the drain region DR.

[0094] Next, as shown in Figure 22, impurities are implanted into the oxide semiconductor layer 130 using the resist mask RM as a mask. The impurity implantation process is the same as the process described in step S1070 of Figure 4. By performing the impurity implantation process, a channel region CR, a source region SR, and a drain region DR are formed in the oxide semiconductor layer 130. In this embodiment, the region directly beneath the resist mask RM covering the conductive layer 150, that is, the region shielded by the resist mask RM covering the conductive layer 150, becomes the channel region CR (the region without added impurities).

[0095] Next, as shown in Figure 23, after removing the resist mask RM, impurities are again injected into the oxide semiconductor layer 130 using the conductive layer 150 as a mask. That is, impurities are injected into the region of the channel region CR formed in the process shown in Figure 22 that does not overlap with the conductive layer 150. As a result, impurities are selectively injected into a portion of the channel region CR, forming a region with lower resistance than the channel region CR.

[0096] In this case, the process shown in Figure 23 uses a lower dose (amount added) of impurities than the process shown in Figure 22. As a result, a low-resistance region HRR is formed between the channel region CR and the source region SR, and between the channel region CR and the drain region DR, where the resistance is lower than that of the channel region CR and higher than that of the source region SR and the drain region DR. Thus, in this embodiment, the channel region CR and the low-resistance region HRR are formed in a self-aligned manner.

[0097] In this embodiment, as in the first embodiment, when impurities are implanted into the oxide semiconductor layer 130, a resist mask RM is placed around the oxide semiconductor layer 130, thereby suppressing the amount of hydrogen generated inside the insulating layer 120 or insulating layer 140. Therefore, according to this embodiment, it is possible to efficiently suppress the decrease in channel resistance due to hydrogen diffusion.

[0098] (Modified version of the second embodiment) As shown in Figure 23, this embodiment demonstrates an example in which the resist mask RM is removed and impurities are implanted using the conductive layer 150 as a mask when forming the low-resistance region HRR. However, this is not the only example, and a new resist mask RMa may be formed when forming the low-resistance region HRR.

[0099] Figure 24 is a schematic cross-sectional view showing a method for manufacturing a pixel 13a including a semiconductor device according to a modification of one embodiment of the present invention. In this modification, after the process shown in Figure 22, the resist mask RM is removed and then a resist mask RMa is formed again. In this modification, an example is shown in which the resist mask RMa is arranged around the oxide semiconductor layer 130, similar to the first embodiment. That is, the position of the inner wall of the opening RMa1 of the resist mask RMa and the position of the edge of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. However, the example is not limited to this example, and, similar to the modification of the first embodiment, in a plan view, the size of the outer shape (contour) of the edge of the opening RMa1 may be larger or smaller than the size of the outer shape (contour) of the edge of the oxide semiconductor layer 130.

[0100] According to this modified example, the exposed area of ​​the insulating layer 140 is reduced even in the impurity injection process for forming the low-resistance region HRR, thereby suppressing the amount of hydrogen generated inside the insulating layer 120 and the insulating layer 140. Therefore, according to this modified example, it is possible to suppress the decrease in channel resistance due to hydrogen diffusion even more efficiently.

[0101] The embodiments described above (including modifications) of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any modifications based on these embodiments, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0102] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0103] 10…Display device, 11…Substrate, 12…Display unit, 13, 13a…Pixel, 14-1…Gate drive circuit, 14-2…Gate drive circuit, 16…Terminal, 17…Terminal unit, 18…Flexible printed circuit, 19…Peripheral unit, 20…Touch sensor, 100…Substrate, 110…Conductive layer, 120…Insulating layer, 130, 130a…Oxide semiconductor layer, 140…Insulating layer, 150…Conductive layer, 160…Insulating layer, 161, 162…Contact hole, 181, 182…Conductive layer, 190…Insulating layer, 191…Contact hole, 200…Pixel electrode, 210…Bank, 212…Aperture, 220…Light-emitting layer, 230…Common electrode, 240…Sealing layer

Claims

1. An oxide semiconductor layer is formed on the first insulating layer. A second insulating layer is formed on the oxide semiconductor layer. A conductive layer is formed on the second insulating layer. A resist mask having openings that overlap with at least a portion of the oxide semiconductor layer is formed on the second insulating layer and the conductive layer. A method for manufacturing a semiconductor device, comprising using the resist mask to implant impurities into the oxide semiconductor layer via the second insulating layer.

2. A method for manufacturing a semiconductor device according to claim 1, wherein, in a plan view, the outer shape of the edge of the opening matches the outer shape of the edge of the oxide semiconductor layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, in a plan view, the outer shape of the edge of the oxide semiconductor layer includes the outer shape of the edge of the opening.

4. A method for manufacturing a semiconductor device according to claim 1, wherein, in a plan view, the outer shape of the edge of the opening encompasses the outer shape of the edge of the oxide semiconductor layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the distance from the edge of the opening to the edge of the oxide semiconductor layer is 0.3 μm or more and 1.2 μm or less.

6. The method for manufacturing a semiconductor device according to claim 1, wherein in the region superimposed with the oxide semiconductor layer, the opening and the conductive layer are separated in the channel direction.

7. A method for manufacturing a semiconductor device according to claim 6, further comprising implanting impurities into the oxide semiconductor layer after removing the resist mask.

8. An oxide semiconductor layer on the first insulating layer, A second insulating layer on the oxide semiconductor layer, A conductive layer on the second insulating layer, Includes, The oxide semiconductor layer includes a first region superimposed on the conductive layer and a second region not superimposed on the conductive layer. A semiconductor device wherein the concentration of a predetermined impurity in the region of the second insulating layer that overlaps with the second region is higher than the concentration of the impurity in the region of the second insulating layer that does not overlap with the oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein the concentration of the impurity in the region of the second insulating layer that overlaps with the second region is 100 times or more higher than the concentration of the impurity in the region of the second insulating layer that does not overlap with the oxide semiconductor layer.

10. The semiconductor device according to claim 8, wherein the concentration of the impurity in the region of the second insulating layer that overlaps with the second region is higher than the concentration of the impurity in the region of the second insulating layer that overlaps with the first region.

11. The semiconductor device according to claim 10, wherein the concentration of the impurity in the region of the second insulating layer that overlaps with the second region is 100 times or more higher than the concentration of the impurity in the region of the second insulating layer that overlaps with the first region.

12. An oxide semiconductor layer on the first insulating layer, A second insulating layer on the oxide semiconductor layer, A conductive layer on the second insulating layer, Includes, The oxide semiconductor layer includes a first region superimposed on the conductive layer and a second region not superimposed on the conductive layer. A semiconductor device wherein the concentration of a predetermined impurity in the region of the first insulating layer that overlaps with the second region is higher than the concentration of the impurity in the region of the first insulating layer that does not overlap with the oxide semiconductor layer.

13. The semiconductor device according to claim 12, wherein the concentration of the impurity in the region of the first insulating layer that overlaps with the second region is 100 times or more higher than the concentration of the impurity in the region of the first insulating layer that does not overlap with the oxide semiconductor layer.

14. The semiconductor device according to claim 12, wherein the concentration of the impurity in the region of the first insulating layer that overlaps with the second region is higher than the concentration of the impurity in the region of the first insulating layer that overlaps with the first region.

15. The semiconductor device according to claim 14, wherein the concentration of the impurity in the region of the first insulating layer that overlaps with the second region is 100 times or more higher than the concentration of the impurity in the region of the first insulating layer that overlaps with the first region.

16. A display device comprising a semiconductor device according to any one of claims 1 to 15.

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