Semiconductor device, display device, and method for manufacturing a semiconductor device.

Abstract

To suppress the decrease in channel resistance of semiconductor devices using oxide semiconductors. [Solution] The semiconductor device includes an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, a metal oxide layer having an opening that overlaps with at least a portion of the oxide semiconductor layer and in contact with the upper surface of the gate insulating layer in a region that does not overlap with the oxide semiconductor layer, and a gate electrode provided on the gate insulating layer in a region that overlaps with the oxide semiconductor layer.

Description

Technical Field

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[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor, a display device, and a method for manufacturing a semiconductor device.

Background Art

[0002] In recent years, development of semiconductor devices using oxide semiconductors has been underway instead of silicon semiconductors using amorphous silicon, low-temperature polysilicon, and single-crystalline silicon (see, for example, Patent Document 1). For example, a transistor that uses an oxide semiconductor layer including an oxide semiconductor as a channel can be manufactured with a simple structure and a low-temperature process, similar to a transistor including an amorphous silicon layer. A transistor including an oxide semiconductor layer is known to have a higher field-effect mobility than a transistor including an amorphous silicon layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a transistor that uses an oxide semiconductor layer as a channel, deterioration of electrical characteristics due to a decrease in channel resistance often becomes a problem. For example, when hydrogen diffuses excessively into the oxide semiconductor constituting the channel, there is a problem that the channel resistance decreases and the transistor operates in the depletion mode unintentionally.

[0005] [[ID=3·8]] One embodiment of the present invention has an object to suppress a decrease in channel resistance of a semiconductor device using an oxide semiconductor.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, a metal oxide layer having an opening that overlaps with at least a portion of the oxide semiconductor layer and in contact with the upper surface of the gate insulating layer in a region that does not overlap with the oxide semiconductor layer, and a gate electrode provided on the gate insulating layer in a region that overlaps with the oxide semiconductor layer.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming an oxide semiconductor layer on an insulating surface, forming a gate insulating layer on the oxide semiconductor layer, forming a metal oxide layer having an opening that overlaps with at least a portion of the oxide semiconductor layer and is in contact with the upper surface of the gate insulating layer, forming a gate electrode on the gate insulating layer, and adding an impurity to the oxide semiconductor layer via the gate insulating layer. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic plan view showing the configuration of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 2] This is a schematic circuit diagram showing the equivalent circuit of a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 4] This is a flowchart illustrating a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 9A] This is a schematic plan view showing a method for manufacturing pixels including a semiconductor device according to one embodiment of the present invention. [Figure 9B] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 10A] This is a schematic plan view showing a method for manufacturing pixels including a semiconductor device according to one embodiment of the present invention. [Figure 10B] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 10C] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 12] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 13] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 14] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 15] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 16] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 17] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to one embodiment of the present invention. [Figure 18A] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 18B] This is a schematic plan view showing a method for manufacturing pixels including a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 19A]It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to a modification of an embodiment of the present invention. [Figure 19B] It is a schematic plan view showing a method of manufacturing a pixel including a semiconductor device according to a modification of an embodiment of the present invention. [Figure 20] It is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 21] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 22] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 23] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 24] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 25] It is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 26] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 27] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 28] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 29] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to an embodiment of the present invention. [Figure 30] It is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device according to a modification of an embodiment of the present invention. [Figure 31] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to a modification of an embodiment of the present invention. [Figure 32] It is a schematic cross-sectional view showing a method of manufacturing a pixel including a semiconductor device according to a modification of an embodiment of the present invention. [Figure 33] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 34] This is a schematic cross-sectional view showing a method for manufacturing a pixel including a semiconductor device according to a modified example of one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, and shape of the components compared to the actual embodiments. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification, claims, and drawings (hereinafter referred to as "this specification, etc."), components similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the illustration. Also, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be arranged between the substrate and the oxide semiconductor layer. Upward or downward refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a plan view. On the other hand, when referring to a pixel electrode vertically above a semiconductor device, it means that the semiconductor device and the pixel electrode overlap in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0011] In this specification, multiple elements formed by processing a single film, such as etching, may be described as elements having different functions or roles. These multiple elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer. That is, when it is stated in this specification that "A and B are the same layer," it means that both element A and element B are elements formed by processing a single layer.

[0012] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other components.

[0013] In this specification, "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are included as forms of semiconductor devices. The semiconductor devices of the embodiments shown below can be used, for example, in display devices, integrated circuits (ICs) such as microprocessing units (MPUs), or memory circuits.

[0014] In this specification, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, although an organic EL display device including an organic EL layer will be used as an example to describe the embodiments described later, the structure in this embodiment can be applied to other display devices including the electro-optical layers described above.

[0015] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0016] The source and drain of a transistor may have their functions reversed depending on the voltage supplied to them. Therefore, in this specification, the terms "source" and "drain" may be interchangeable as needed.

[0017] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0018] <First Embodiment> (Display device configuration) The following describes a display device 10 according to one embodiment of the present invention. In this embodiment, an organic EL display device is exemplified as the display device 10. The organic EL display device is a display device in which each pixel includes an organic EL element as a light-emitting element and a semiconductor device for driving the light-emitting element.

[0019] Figure 1 is a schematic plan view showing the configuration of a display device 10 including a semiconductor device according to one embodiment of the present invention. As shown in Figure 1, the display device 10 includes a display unit 12 and a peripheral unit 19 provided on a substrate 11. The display unit 12 has a plurality of pixels 13 arranged in a matrix. Each of the plurality of pixels 13 has a semiconductor device composed of a plurality of transistors, which will be described later, and a light-emitting element. A touch sensor 20 is arranged on the display unit 12 and on the display unit 12.

[0020] The peripheral portion 19 is provided so as to surround the display unit 12. The peripheral portion 19 refers to the portion of the substrate 11 from the display unit 12 to the edge of the substrate 11. In other words, the peripheral portion 19 refers to the portion of the substrate 11 other than the portion on which the display unit 12 is provided (specifically, the portion outside the display unit 12). The peripheral portion 19 has gate drive circuits 14-1 and 14-2 and a terminal portion 17 including a plurality of terminals 16. The gate drive circuits 14-1 and 14-2 are provided so as to sandwich the display unit 12. A flexible printed circuit 18 equipped with a driver IC 15 is connected to the terminal portion 17. A plurality of wires (not shown) included in the flexible printed circuit 18 are connected to the driver IC 15 and the terminal portion 17. In the example shown in Figure 1, the source drive circuit is incorporated into the driver IC 15. However, the source drive circuit is not limited to this example and may be formed on the substrate 11 using transistors.

[0021] The driver IC 15 is connected to gate drive circuits 14-1 and 14-2 and to multiple video signal lines VL. Gate drive circuit 14-1 or gate drive circuit 14-2 is connected to the pixels 13 via selection control lines Sg. Of the multiple selection control lines Sg, for example, the selection control lines Sg for odd-numbered rows are connected to gate drive circuit 14-1, and the selection control lines Sg for even-numbered rows are connected to gate drive circuit 14-2. The video signal lines VL are connected to the pixels 13. The display unit 12 is supplied with a control signal SG (see Figure 2) from the driver IC 15 via the gate drive circuits 14-1 and 14-2 and the selection control lines Sg to select each pixel 13. The display unit 12 is also supplied with a video signal Vsig (see Figure 2) from the driver IC 15 via the video signal lines VL. These signals drive multiple transistors included in the pixels 13, enabling the display unit 12 to display an image corresponding to the video signal Vsig. The high-potential power line SLa and the low-potential power line SLb, connected to the pixel 13, are each connected to different terminals 16.

[0022] The substrate 11 can be a glass substrate, a quartz substrate, a ceramic substrate, a flexible plastic substrate, or a resin substrate. When a flexible plastic substrate or a resin substrate is used as the substrate 11, the substrate 11 can be bent between the display unit 12 and the terminal unit 17. This reduces the area of ​​the bezel portion of the display device 10.

[0023] (Pixel circuit configuration) Figure 2 is a schematic circuit diagram showing the circuit configuration of a pixel 13 including a semiconductor device according to one embodiment of the present invention. Each pixel 13 constituting the display device 10 is connected to a high-potential power line SLa, a low-potential power line SLb, a selection control line Sg, and a video signal line VL. The high-potential power line SLa is connected to a high-potential power supply Pvdd. The low-potential power line SLb is connected to a low-potential power supply Pvss. The selection control line Sg is connected to gate drive circuits 14-1 and 14-2. The video signal line VL is connected to a driver IC 15 that supplies the video signal Vsig.

[0024] Each pixel 13 has at least a drive transistor DRT, a selection transistor SST, and a light-emitting element OLED. A high-potential power supply Pvdd is connected to the anode of the light-emitting element OLED via the drive transistor DRT. A low-potential power supply Pvss is connected to the cathode of the light-emitting element OLED. In this embodiment, the anode of the light-emitting element OLED is connected to the pixel electrode 200 (see Figure 3), and the cathode is connected to the common electrode 230 (see Figure 3).

[0025] The drive transistor DRT is connected in series with the light-emitting element OLED between the high-potential power line SLa and the low-potential power line SLb. The drive transistor DRT functions as a current control element that controls the current flowing to the light-emitting element OLED according to the gate-source voltage. The selection transistor SST functions as a switching element that selects conduction or non-conductivity between two nodes and applies a voltage to the gate of the drive transistor DRT that corresponds to the luminescence brightness of the light-emitting element OLED. A retaining capacitor Cs is provided between the gate and source of the drive transistor DRT. The retaining capacitor Cs maintains the gate-source voltage of the drive transistor DRT.

[0026] The selection transistor SST has its gate connected to the selection control line Sg, one of its source or drain connected to the video signal line VL, and the other of its source or drain connected to the gate and retaining capacitance Cs of the drive transistor DRT. The drive transistor DRT has its drain connected to the high-potential power line SLa, and its source connected to the retaining capacitance Cs and the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is connected to the low-potential power line SLb. The drive transistor DRT outputs a drive current to the light-emitting element OLED in an amount corresponding to the video signal Vsig.

[0027] Although not shown in the diagram, pixel 13 may further include other transistors such as a correction transistor for correcting the threshold of the drive transistor DRT, and a reset transistor for resetting the voltage held in the holding capacitance Cs.

[0028] In this embodiment, oxide semiconductors are used as the semiconductors for the selection transistor SST and the drive transistor DRT. Transistors using oxide semiconductors have the advantage of low power consumption because they have a low off-leak current and can be driven at low frequencies. Therefore, by configuring pixels using oxide semiconductors, the power consumption of the display device 10 can be reduced. Furthermore, transistors using oxide semiconductors have the advantage of not exhibiting a kink effect and having good saturation characteristics compared to transistors using so-called low-temperature polysilicon.

[0029] (Pixel structure) Figure 3 is a schematic cross-sectional view showing the configuration of a pixel 13 including a semiconductor device according to one embodiment of the present invention. The pixel 13 shown in Figure 3 includes a drive transistor DRT that supplies current to the light-emitting element OLED as a semiconductor device. Although not shown in Figure 3, the pixel 13 also includes a selection transistor SST as shown in Figure 2. The pixel 13 shown in Figure 3 may include many more transistors in addition to the drive transistor DRT and the selection transistor SST.

[0030] The drive transistor DRT of this embodiment includes a conductive layer 110, an insulating layer 120, an oxide semiconductor layer 130, an insulating layer 140, a metal oxide layer 145, a conductive layer 150, an insulating layer 160, a conductive layer 181, and a conductive layer 182, which are provided on a substrate 100 having an insulating surface.

[0031] The substrate 100 is, for example, a glass substrate on which one or more insulating layers are formed, each layer being made of a material selected from insulating oxides such as silicon oxide (SiOx) or silicon oxide nitride (SiOxNy), or insulating nitrides such as silicon nitride (SiNx) or silicon oxide nitride (SiNxOy). Here, silicon oxide nitride (SiNxOy) is a silicon oxide containing oxygen in a smaller proportion than nitrogen (x>y). Silicon oxide nitride (SiOxNy) is a silicon nitride containing nitrogen (N) in a smaller proportion than oxygen (O) (x>y).

[0032] In this embodiment, a substrate 100 having an insulating surface is constructed by laminating a silicon nitride layer and a silicon oxide layer on a glass substrate in that order from bottom to top. The silicon nitride layer serves as a protective layer to prevent the intrusion of contaminants (e.g., alkaline substances) from the glass substrate. However, this is not limited to this example, and a quartz substrate, ceramic substrate, plastic substrate, or resin substrate may be used instead of the glass substrate. Furthermore, the lamination order of the silicon oxide layer, silicon nitride layer, silicon oxide-nitride layer, or silicon nitride-oxide layer is arbitrary.

[0033] The conductive layer 110 is provided on the substrate 100. The conductive layer 110 functions as the lower gate electrode in the drive transistor DRT. The conductive layer 110 can be made of materials such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material for the conductive layer 110. The conductive layer 110 also functions as a light-shielding layer that reduces the amount of light reaching the oxide semiconductor layer 130 from the lower layer.

[0034] The insulating layer 120 is provided on top of the conductive layer 110. The insulating layer 120 functions as the lower gate insulating layer in the drive transistor DRT. As the insulating layer 120, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be used. In this embodiment, as the insulating layer 120, an insulating layer is used in which a silicon nitride layer and a silicon oxide layer are stacked in order from bottom to top. As will be described later, since an oxide semiconductor layer 130 is provided on top of the insulating layer 120, it is preferable that the surface of the insulating layer 120 that is in contact with the oxide semiconductor layer 130 is a silicon oxide layer.

[0035] The thickness of the insulating layer 120 is not particularly limited. In this embodiment, the thickness of the insulating layer 120 is 200 nm or more and 600 nm or less (preferably 300 nm or more and 500 nm or less, and more preferably 350 nm or more and 450 nm or less). In this embodiment, a laminated structure consisting of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm is used as the insulating layer 120.

[0036] The oxide semiconductor layer 130 is provided on top of the insulating layer 120. The oxide semiconductor layer 130 functions as the active layer in the drive transistor DRT. As the material constituting the oxide semiconductor layer 130, an amorphous oxide semiconductor (for example, IGZO) can be used. The thickness of the oxide semiconductor layer 130 can be 10 nm or more and 100 nm or less (preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 40 nm or less).

[0037] In this embodiment, the oxide semiconductor layer 130 can be formed using a sputtering method. The composition of the oxide semiconductor layer 130 formed using the sputtering method depends on the composition of the sputtering target.

[0038] Furthermore, as shown in Figure 3, the oxide semiconductor layer 130 is divided into a channel region CR, a source region SR, and a drain region DR. The channel region CR is a region that overlaps with the conductive layer 150, which functions as a gate electrode, and forms a channel when a gate voltage is applied to the conductive layer 150. The source region SR and the drain region DR are regions with lower resistance than the channel region CR and function as conductive regions. In other words, the source region SR and the drain region DR have higher electrical conductivity than the channel region CR. To put it another way, the source region SR and the drain region DR have the properties of a conductor, while the channel region has the properties of a semiconductor. As will be described later, the source region SR and the drain region DR are formed by adding impurities to the oxide semiconductor layer 130 using methods such as ion implantation.

[0039] The insulating layer 140 is provided on top of the oxide semiconductor layer 130. The insulating layer 140 functions as the upper gate insulating layer in the drive transistor DRT. As the insulating layer 140, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be used. In this embodiment, a silicon oxide layer is used as the insulating layer 140. It is preferable that the insulating layer 140 has few defects and a composition close to the stoichiometric ratio. Specifically, it is preferable that no defects are observed when the insulating layer 140 is evaluated by the electron spin resonance (ESR) method. The thickness of the insulating layer 140 is not particularly limited. In this embodiment, the thickness of the insulating layer 140 is 50 nm or more and 300 nm or less (preferably 60 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less).

[0040] The metal oxide layer 145 is a layer composed of an oxide insulator containing metal, and is formed by a sputtering method as described later. In this embodiment, a metal oxide mainly composed of aluminum is used as the metal oxide layer 145. For example, inorganic insulating layers such as aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum oxide nitride (AlNxOy), and aluminum nitride (AlNx) are used as the metal oxide layer 145. The expression "metal oxide layer mainly composed of aluminum" means that the proportion of aluminum contained in the metal oxide layer 145 is 1% or more of the total metal oxide layer 145. The proportion of aluminum contained in the metal oxide layer 145 may be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide layer 145. The above ratio may be a mass ratio or a weight ratio. In this embodiment, the thickness of the metal oxide layer 145 is 20 nm or less (preferably 15 nm or less, more preferably 10 nm or less).

[0041] In this embodiment, the metal oxide layer 145 has an opening 145-1. As will be described later, the opening 145-1 is provided so as to overlap with at least a portion of the oxide semiconductor layer 130. In other words, the metal oxide layer 145 has the opening 145-1 provided so that, in a plan view, the entire or almost entire oxide semiconductor layer 130 is exposed (i.e., the metal oxide layer 145 and the oxide semiconductor layer 130 do not overlap). Therefore, the metal oxide layer 145 can also be called a metal oxide pattern.

[0042] The conductive layer 150 is provided on top of the insulating layer 140. The conductive layer 150 functions as the gate electrode on the upper side of the drive transistor DRT. The materials that make up the conductive layer 150 can be aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material that makes up the conductive layer 150. The conductive layer 150 also functions as a light-shielding layer that reduces the amount of light reaching the oxide semiconductor layer 130 from the upper side.

[0043] As described above, the conductive layer 150 functions as the upper gate electrode in the drive transistor DRT, but at the same time, it also functions as gate wiring. In other words, the conductive layer 150 functions as gate wiring, and the portion of the gate wiring that overlaps with the oxide semiconductor layer that functions as the active layer of the transistor functions as the gate electrode. Therefore, for the sake of explanation, the gate electrode and gate wiring may be described separately in this specification, but they may be a single integrated component.

[0044] The insulating layer 160 is provided on top of the conductive layer 150. The insulating layer 160 functions as an interlayer insulating layer in the drive transistor DRT. As the insulating layer 160, one or more layers selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon oxide nitride layer can be used. In this embodiment, a laminated structure including a silicon oxide layer and a silicon nitride layer is used as the insulating layer 160.

[0045] The conductive layers 181 and 182 are provided on the insulating layer 160. Conductive layer 181 is connected to the source region SR of the oxide semiconductor layer 130 via a contact hole 161 provided in the insulating layer 160 and functions as the source electrode in the drive transistor DRT. Conductive layer 182 is connected to the drain region DR of the oxide semiconductor layer 130 via a contact hole 162 provided in the insulating layer 160 and functions as the drain electrode in the drive transistor DRT. In other words, conductive layers 181 and 182 each function as terminal electrodes in the drive transistor DRT.

[0046] The materials that make up the conductive layers 181 and 182 can be aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a laminated structure including a titanium layer and an aluminum layer is used as the material that makes up the conductive layers 181 and 182.

[0047] As described above, the drive transistor DRT of this embodiment is a dual-gate transistor that includes a lower gate electrode (conductive layer 110) facing the oxide semiconductor layer 130 via an insulating layer 120, and an upper gate electrode (conductive layer 150) facing the oxide semiconductor layer 130 via an insulating layer 140. However, it is not limited to this example, and the drive transistor DRT may also be a top-gate transistor. For example, if the conductive layer 110 shown in Figure 3 is not used as a gate electrode, such as by applying a fixed voltage to the conductive layer 110, the drive transistor DRT functions as a top-gate transistor.

[0048] An insulating layer 190, made of resin material, is provided on the drive transistor DRT as a planarization layer. The pixel electrode 200 is connected to the conductive layer 181 (i.e., the source electrode of the drive transistor DRT) via a contact hole 191 provided in the insulating layer 190. In this embodiment, a laminated structure of a layer containing silver (Ag) and a layer containing a metal oxide (e.g., ITO) is used as the pixel electrode 200, but the invention is not limited to this example.

[0049] A bank 210 made of resin material is provided above the pixel electrode 200. The bank is also called a partition or rib. The bank 210 is provided so as to cover a portion of the pixel electrode 200. In other words, the bank 210 has an opening 212 at a position that overlaps with the pixel electrode 200. The portion of the pixel electrode 200 not covered by the bank 210 (exposed region) functions as the light-emitting region of the pixel 13. A light-emitting layer 220 made of organic EL (electroluminescent) material is provided so as to cover the exposed region of the pixel electrode 200.

[0050] Furthermore, a common electrode 230 is provided so as to cover the bank 210 and the light-emitting layer 220. Although not shown in Figure 3, the common electrode 230 is arranged to span multiple pixels 13. The pixel electrode 200, the light-emitting layer 220, and the common electrode 230 constitute a light-emitting OLED. The pixel electrode 200 functions as the anode of the light-emitting OLED. The common electrode 230 functions as the cathode of the light-emitting OLED.

[0051] A sealing layer 240 is provided on top of the light-emitting element OLED. The sealing layer 240 is a protective layer to prevent the intrusion of moisture and other external elements. In this embodiment, a laminated structure is used for the sealing layer 240, in which an inorganic insulating layer, an organic insulating layer, and another inorganic insulating layer are stacked in that order from the bottom. For example, a silicon nitride layer can be used as the inorganic insulating layer. For example, an organic resin layer (for example, a resin layer composed of polyimide or acrylic) can be used as the organic insulating layer.

[0052] As explained above, pixel 13 is equipped with a drive transistor DRT, and in relation to the manufacturing method described later, a characteristic impurity distribution exists around the drive transistor DRT. This point will be described in detail below along with the manufacturing method of the semiconductor device.

[0053] (Method of manufacturing pixels) Figure 4 is a flowchart illustrating a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. Figures 5 to 8, 9B, 10B, 10C, and 11 to 17 are schematic cross-sectional views showing a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. Figures 9A and 10A are schematic plan views showing a method for manufacturing a pixel 13 including a semiconductor device according to one embodiment of the present invention. As shown in Figure 4, the method for manufacturing a semiconductor device according to this embodiment includes steps S1010 to S1130. Steps S1010 to S1130 will be described in order below, but the order of the steps in the method for manufacturing a semiconductor device according to this embodiment may be changed. In addition, in the method for manufacturing a semiconductor device according to this embodiment, one or more steps may be omitted, or further steps may be included.

[0054] First, as shown in Figures 4 and 5, a conductive layer 110 (first conductive layer) having a predetermined pattern shape is formed on the substrate 100 (step S1010). The patterning of the conductive layer 110 is performed using photolithography. In this embodiment, the conductive layer 110 functions as a light-shielding layer. In addition, an insulating layer 120 (first insulating layer) is formed so as to cover the conductive layer 110. The insulating layer 120 is deposited using the chemical vapor deposition (CVD) method. In this embodiment, the insulating layer 120 is a laminated structure consisting of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm.

[0055] Next, as shown in Figures 4 and 6, an oxide semiconductor layer 130 having a predetermined pattern shape is formed on the insulating layer 120 (step S1020). The oxide semiconductor layer 130 is formed to overlap with the conductive layer 110. The oxide semiconductor layer 130 is formed by patterning an oxide semiconductor film, which has been deposited using the sputtering method, into a predetermined shape using photolithography. The oxide semiconductor film deposited using the sputtering method has an amorphous structure.

[0056] Amorphous oxide semiconductor films can be easily patterned using photolithography. When etching oxide semiconductor films, either wet etching or dry etching may be used. When using wet etching, an acidic etching solution can be used to etch the oxide semiconductor film. For example, oxalic acid solution, PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) solution, sulfuric acid solution, hydrogen peroxide solution, or hydrofluoric acid solution can be used as the etching solution.

[0057] Furthermore, the oxide semiconductor layer 130 having a predetermined pattern shape is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1020 will be referred to as "OS annealing". In OS annealing, the oxide semiconductor layer 130 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300°C to 500°C (preferably 350°C to 450°C). The holding time at the target temperature is 15 minutes to 120 minutes (preferably 30 minutes to 60 minutes).

[0058] Next, as shown in Figures 4 and 7, an insulating layer 140 (second insulating layer) is formed on the oxide semiconductor layer 130 (step S1030). In this embodiment, a silicon oxide layer with a thickness of 100 nm is used as the insulating layer 140.

[0059] Next, as shown in Figures 4 and 8, a metal oxide layer 145 is formed on the insulating layer 140 (step S1040). In this embodiment, an 8 nm thick aluminum oxide (AlOx) layer is formed as the metal oxide layer 145 by sputtering. When the metal oxide layer 145 is formed by sputtering, a large amount of oxygen is injected into the interior of the insulating layer 140. At this stage, the metal oxide layer 145 is an unprocessed metal oxide layer (a metal oxide layer in a deposited state) that has not undergone patterning treatment.

[0060] Furthermore, the insulating layer 140 is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1040 will be referred to as "oxidation annealing". Due to the formation of the oxide semiconductor layer 130 and the insulating layer 140, many oxygen vacancies are generated inside the oxide semiconductor layer 130. When oxidation annealing is performed, oxygen is supplied from the insulating layer 140 to the oxide semiconductor layer 130, and the oxygen vacancies in the oxide semiconductor layer 130 are repaired. In this embodiment, since oxygen is injected into the insulating layer 140 when the metal oxide layer 145 is formed, increasing the amount of oxygen inside the insulating layer 140, a sufficient amount of oxygen can be supplied to the oxide semiconductor layer 130 by oxidation annealing. Also, at that time, the metal oxide layer 145 functions as a barrier layer that prevents the movement of oxygen, making it possible to efficiently supply oxygen to the oxide semiconductor layer 130.

[0061] Next, as shown in Figures 4, 9A, and 9B, the metal oxide layer 145 is patterned to form an opening 145-1 (step S1050). In this embodiment, a resist mask (not shown) is formed on the metal oxide layer 145 by photolithography, and the metal oxide layer 145 is etched by a wet etching process using an aqueous hydrofluoric acid solution to form the opening 145-1. At this stage, the metal oxide layer 145 is a processed metal oxide layer (patterned metal oxide layer) that has undergone patterning.

[0062] As shown in Figure 9A, the metal oxide layer 145 is formed in a region that does not overlap with the oxide semiconductor layer 130. Specifically, the position of the inner wall of the opening 145-1 and the position of the edge of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. In other words, as shown in Figures 9A and 9B, in a plan view, the outer shape of the edge of the opening 145-1 in the metal oxide layer 145 coincides with the outer shape of the edge of the oxide semiconductor layer 130.

[0063] Here, "matching" includes not only cases where they match perfectly, but also cases where they fall within the range of error in the alignment when forming the opening 145-1. For example, even if the position of the outer shape of the edge of the opening 145-1 and the position of the outer shape of the edge of the oxide semiconductor layer 130 differ by a range of 1.5 μm (preferably 1.0 μm, more preferably 0.5 μm), the outer shape of the edge of the opening 145-1 and the outer shape of the edge of the oxide semiconductor layer 130 are considered to match.

[0064] Furthermore, strictly speaking, Figure 9B shows an example where the position of the inner wall of the opening 145-1 and the position of the edge of the upper surface of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. However, the position of the inner wall of the opening 145-1 and the position of the edge of the lower surface of the oxide semiconductor layer 130 may also coincide in a direction perpendicular to the substrate 100.

[0065] Next, as shown in Figures 4, 10A, 10B, and 10C, a conductive layer 150 (second conductive layer) is formed on the insulating layer 140 and the metal oxide layer 145 (step S1060). In this embodiment, the conductive layer 150 functions as gate wiring. In this embodiment, a metal film made of a molybdenum-tungsten alloy is formed using a sputtering method, and the conductive layer 150 is formed by patterning the metal film into a predetermined shape. In this embodiment, the thickness of the conductive layer 150 is 300 nm, but it is not limited to this example.

[0066] As shown in Figure 10A, the conductive layer 150 is formed so as to intersect with the oxide semiconductor layer 130. Specifically, the conductive layer 150 has a longitudinal direction that intersects with the longitudinal direction (channel direction) of the oxide semiconductor layer 130. In Figure 10A, the cross-sectional view obtained by cutting along the dashed line indicated by A-A' corresponds to Figure 10B, and the cross-sectional view obtained by cutting along the dashed line indicated by B-B' corresponds to Figure 10C.

[0067] As shown in Figure 10B, in the region where the oxide semiconductor layer 130 and the conductive layer 150 overlap, the oxide semiconductor layer 130 and the conductive layer 150 face each other via the insulating layer 140. The region where the oxide semiconductor layer 130 and the conductive layer 150 overlap is located inside the opening 145-1 provided in the metal oxide layer 145. Therefore, in the region where the oxide semiconductor layer 130 and the conductive layer 150 overlap, the conductive layer 150 and the insulating layer 140 are in contact.

[0068] Furthermore, as shown in Figure 10C, in regions where the oxide semiconductor layer 130 and the conductive layer 150 do not overlap, the metal oxide layer 145 is positioned between the insulating layer 140 and the conductive layer 150. In other words, in regions where the oxide semiconductor layer 130 and the conductive layer 150 do not overlap, the conductive layer 150 and the metal oxide layer 145 are in contact. In this way, since the periphery of the oxide semiconductor layer 130 is covered by the metal oxide layer 145, a large amount of oxygen remains in the insulating layer 140 located in the region covered by the metal oxide layer 145. As a result, as will be described later, the amount of hydrogen diffusing from the periphery of the oxide semiconductor layer 130 toward the oxide semiconductor layer 130 can be suppressed.

[0069] Next, as shown in Figures 4 and 11, impurities are implanted into the oxide semiconductor layer 130 via the insulating layer 140 (step S1070). The impurities can be implanted into the oxide semiconductor layer 130, for example, by ion implantation. Examples of impurities that can be used include argon (Ar), phosphorus (P), or boron (B). However, other elements may also be used, not limited to these examples.

[0070] In this embodiment, since the conductive layer 150 is formed on the oxide semiconductor layer 130, the conductive layer 150 functions as a mask, inhibiting the implantation of impurities into a portion of the oxide semiconductor layer 130. Therefore, in the oxide semiconductor layer 130, impurities are not implanted in the region overlapping with the conductive layer 150, and a channel region CR is formed in that region. In addition, in the oxide semiconductor layer 130, a source region SR and a drain region DR are formed in the region where impurities are implanted because the oxide semiconductor layer 130 does not overlap with the conductive layer 150. In the source region SR and drain region DR, oxygen vacancies are generated inside the oxide semiconductor layer 130 by the implantation of impurities, and hydrogen is trapped in these oxygen vacancies. As a result, the source region SR and drain region DR are conductive and have higher electrical conductivity than the channel region CR.

[0071] Here, the technical significance of arranging the metal oxide layer 145 in this embodiment will be explained. In this embodiment, impurities are added to the oxide semiconductor layer 130 by passing through the insulating layer 140. In this embodiment, since a silicon oxide layer is used as the insulating layer 140, Si-O bonds and Si-H bonds contained in the silicon oxide layer may be broken by collisions with impurities. As a result, oxygen and hydrogen are generated in the region of the insulating layer 140 through which the impurities passed during ion implantation. In particular, the generated hydrogen easily moves within the insulating layer 140 when heat is applied in a later process. Such hydrogen diffusion can be a factor that leads to, for example, a decrease in the resistance of the channel region CR (i.e., a decrease in channel resistance).

[0072] Therefore, in this embodiment, a metal oxide layer 145 is arranged to cover the periphery of the oxide semiconductor layer 130, thereby minimizing the amount of hydrogen diffusing into the interior of the insulating layer 140 around the oxide semiconductor layer 130.

[0073] In this embodiment, impurities that have passed through the insulating layer 140 are implanted into the oxide semiconductor layer 130. On the other hand, around the oxide semiconductor layer 130, impurities that have passed through the metal oxide layer 145 are implanted into the insulating layer 140 (or insulating layers 120 and 140). Therefore, regardless of whether they are superimposed on the oxide semiconductor layer 130 or not, hydrogen and oxygen are generated inside the insulating layer 140 due to collisions of impurity ions caused by ion implantation.

[0074] However, in the region surrounding the oxide semiconductor layer 130 (i.e., the region where the metal oxide layer 145 is located), the metal oxide layer 145 functions as a barrier layer that prevents oxygen movement, thereby suppressing the diffusion of oxygen that was originally present inside the insulating layer 140 and oxygen generated by ion implantation upwards (i.e., into the air). In other words, in the region where the metal oxide layer 145 is located, the oxygen present inside the insulating layer 140 remains inside the insulating layer 140 without diffusing into the air.

[0075] As described above, hydrogen is generated inside the insulating layer 140 by ion implantation, but the oxygen present inside the insulating layer 140 functions as a hydrogen trap that captures hydrogen. In other words, the oxygen present inside the insulating layer 140 plays a role in suppressing the diffusion of hydrogen generated by the subsequent heating process. Therefore, in the region surrounding the oxide semiconductor layer 130 (the region where the metal oxide layer 145 is not placed), the oxygen remaining inside the insulating layer 140 functions as a hydrogen trap, effectively suppressing hydrogen diffusion. Here, during ion implantation, the region where the oxide semiconductor layer 130 is not formed occupies an overwhelmingly larger area than the region where the oxide semiconductor layer 130 is formed. In other words, by placing the metal oxide layer 145 around the oxide semiconductor layer 130, the amount of hydrogen generated near the oxide semiconductor layer 130 can be significantly reduced, and the decrease in channel resistance due to hydrogen diffusion can be efficiently suppressed.

[0076] Furthermore, an opening 145-1 is provided above the region of the insulating layer 140 that overlaps with the oxide semiconductor layer 130, and the metal oxide layer 145 is not placed there. Therefore, oxygen can easily escape into the air from the insulating layer 140 located above the source region SR and drain region DR shown in Figure 11. As a result, hydrogen can easily diffuse in the insulating layer 140 located above the source region SR and drain region DR, and this hydrogen diffusion contributes largely to reducing the resistance of the source region SR and drain region DR.

[0077] As described above, in this embodiment, when impurities are added to the oxide semiconductor layer 130 to form the source region SR and drain region DR, by arranging the metal oxide layer 145 around the oxide semiconductor layer 130, a large amount of oxygen can be retained inside the insulating layer 140 located directly beneath the metal oxide layer 145. This makes it possible to efficiently suppress the diffusion of hydrogen inside the insulating layer 140 located directly beneath the metal oxide layer 145 with oxygen. As a result, according to this embodiment, the decrease in channel resistance due to hydrogen diffusion can be suppressed, and a highly reliable semiconductor device can be manufactured.

[0078] Next, as shown in Figures 4 and 12, a third insulating layer (insulating layer 160) is formed to cover the conductive layer 150 (step S1080). In this embodiment, the insulating layer 160 has a laminated structure in which a silicon oxide layer and a silicon nitride layer are stacked in order from the bottom layer by plasma CVD. Furthermore, contact holes 161 and 162 are formed in the portions of the insulating layers 140 and 160 that overlap with the source region SR and drain region DR of the oxide semiconductor layer 130, respectively.

[0079] Next, as shown in Figures 4 and 13, a third conductive layer (conductive layers 181 and 182) is formed on the insulating layer 160 (step S1090). Specifically, a three-layer metal layer consisting of a titanium layer, an aluminum layer, and a titanium layer in that order is formed by sputtering, and the conductive layers 181 and 182 are formed by patterning the metal layer into a predetermined shape. The conductive layers 181 and 182 are electrically connected to the oxide semiconductor layer 130 via contact holes 161 and 162, respectively. That is, conductive layer 181 is connected to the source region SR and functions as a source electrode, and conductive layer 182 is connected to the drain region DR and functions as a drain electrode.

[0080] Next, as shown in Figures 4 and 14, a fourth insulating layer (insulating layer 190) is formed to cover the conductive layers 181 and 182 (step S1100). The insulating layer 190 in this embodiment is formed by applying a resin material (for example, acrylic or polyimide) by a solution coating method. In this embodiment, a photosensitive acrylic material is used as the insulating layer 190. By performing exposure and photosensitization using a photosensitive resin material, an insulating layer 190 having contact holes 191 can be formed. In this embodiment, contact holes 191 are formed in the portion of the insulating layer 190 that overlaps with the conductive layer 181.

[0081] In this embodiment, an example is shown in which the insulating layer 190 is formed by a solution coating method, but it is not limited to this example, and it is also possible to form it by other methods such as printing. The insulating layer 190 functions as a planarization layer. Therefore, it is preferable that the thickness of the insulating layer 190 be 1 μm or more and 4 μm or less (preferably 2 μm or more and 3 μm or less).

[0082] Next, as shown in Figures 4 and 15, the pixel electrode 200 is formed on the insulating layer 190 (step S1110). Specifically, the pixel electrode 200 is formed by depositing a transparent conductive film (metal oxide film) on the insulating layer 190 by sputtering and patterning it into a predetermined pattern shape. In this embodiment, ITO (indium tin oxide), a metal oxide, is used as the material constituting the pixel electrode 200. The pixel electrode 200 is electrically connected to the conductive layer 181, which functions as a source electrode, via a contact hole 191.

[0083] Next, as shown in Figures 4 and 16, a bank 210 is formed on the pixel electrode 200 (step S1120). A resin material (for example, a photosensitive acrylic material) can be used as the material for the bank 210. Specifically, after applying the resin material by a solution coating method or the like, exposure and development are performed to form a bank 210 including an opening 212. As shown in Figure 16, the opening 212 provided in the bank 210 exposes most of the upper surface of the pixel electrode 200.

[0084] After forming the bank 210, an emissive layer 220 made of organic EL material is formed so as to overlap with the opening 212. In this embodiment, the emissive layer 220 is formed by vapor deposition using an organic EL material that emits red, green, or blue light. The emissive layer 220 is formed with different emission colors for each pixel 13. That is, a red-emitting organic EL material is used for pixels 13 that emit red light, a green-emitting organic EL material is used for pixels 13 that emit green light, and a blue-emitting organic EL material is used for pixels 13 that emit blue light. In addition to the emissive layer made of emissive material, the emissive layer 220 may also include an electron injection layer, an electron transport layer, an electron blocking layer, a hole injection layer, a hole transport layer, or a hole blocking layer as a functional layer made of functional material.

[0085] A common electrode 230 is formed on the light-emitting layer 220. In this embodiment, a layer containing magnesium silver is formed as the common electrode 230 by a vapor deposition method. The common electrode 230 may be provided across multiple pixels. With the formation of the common electrode 230, a light-emitting OLED composed of the pixel electrode 200, the light-emitting layer 220, and the common electrode 230 is formed.

[0086] Finally, as shown in Figures 4 and 17, a sealing layer 240 is formed to cover the light-emitting element OLED (step S1130). Although not shown in the figures, the sealing layer 240 has a laminated structure in which a silicon nitride layer, an organic resin layer (e.g., an acrylic layer), and a silicon nitride layer are stacked in that order from the bottom. However, this is not limited to this example, and a silicon oxide layer or an amorphous silicon layer may be provided between the silicon nitride layer and the organic resin layer. By providing these layers, the adhesion between the silicon nitride layer and the organic resin layer can be improved. Also, in this embodiment, since a touch sensor 20 (see Figure 1) is provided on the sealing layer 240, an overcoat layer may be provided on the sealing layer 240 for the purpose of planarization.

[0087] Through the process described above, a pixel 13 including a drive transistor DRT is completed as a semiconductor device. In this embodiment, oxygen generated inside the insulating layer 140 during ion implantation can be retained around the oxide semiconductor layer 130. As a result, the diffusion of hydrogen generated inside the insulating layer 140 during ion implantation by the subsequent heating process can be efficiently suppressed. Therefore, hydrogen diffusion into the channel region CR after ion implantation can be effectively suppressed, and a highly reliable semiconductor device with suppressed reduction in channel resistance can be manufactured.

[0088] (Modification 1 of the first embodiment) As shown in Figures 9A and 9B, this embodiment illustrates a configuration in which the position of the inner wall of the opening 145-1 in the metal oxide layer 145 and the position of the edge of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. However, the embodiment is not limited to this example, and the size of the opening 145-1 may be larger or smaller than the size of the oxide semiconductor layer 130.

[0089] Figure 18A is a schematic cross-sectional view showing a method for manufacturing a pixel 13 including a semiconductor device according to a modified example of one embodiment of the present invention. Figure 18B is a schematic plan view showing a method for manufacturing a pixel 13 including a semiconductor device according to a modified example of one embodiment of the present invention. In this modified example, the metal oxide layer 145 is arranged to overlap the edge of the oxide semiconductor layer 130 by a predetermined distance (here, L1). Specifically, as shown in Figure 18B, the metal oxide layer 145 is arranged along the outer circumference of the oxide semiconductor layer 130 so as to overlap it by a width of L1. There are no particular restrictions on the range of distance L1, but it is desirable to set it to 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less).

[0090] If the distance L1 is too large, there is a risk that the oxide semiconductor layer 130 will become highly resistive due to oxygen in the region where the metal oxide layer 145 and the oxide semiconductor layer 130 overlap. In other words, the effective area of ​​the source region SR and the drain region DR may be reduced. Furthermore, if the metal oxide layer 145 is present in the region where the source region SR and the source electrode (conductive layer 181) are connected, or in the region where the drain region DR and the drain electrode (conductive layer 182) are connected, etching defects may occur during contact hole formation. Thus, excessive superposition of the metal oxide layer 145 on the oxide semiconductor layer 130 can lead to connection defects between the source electrode or drain electrode and the oxide semiconductor layer 130.

[0091] Furthermore, if the distance L1 is too small, when a misalignment occurs during the formation of the opening 145-1 in the metal oxide layer 145, areas where the oxide semiconductor layer 130 and the metal oxide layer 145 overlap and areas where they do not overlap may occur, which can be a factor in variations in the characteristics of the semiconductor device.

[0092] As described above, in the case of Modification 1, the size of the opening 145-1 in the metal oxide layer 145 is smaller than the size of the oxide semiconductor layer 130. In other words, in a plan view, the outline (contour) of the edge of the oxide semiconductor layer 130 encompasses the outline (contour) of the edge of the opening 145-1. With this configuration, the region in the insulating layer 140 where oxygen remains can be made as wide as possible. Therefore, the amount of hydrogen diffusing from the periphery of the oxide semiconductor layer 130 toward the channel region CR can be significantly suppressed.

[0093] Next, Figure 19A is a schematic cross-sectional view showing a method for manufacturing a pixel 13 including a semiconductor device according to a modified example of one embodiment of the present invention. Figure 19B is a schematic plan view showing a method for manufacturing a pixel 13 including a semiconductor device according to a modified example of one embodiment of the present invention. In this modified example, the metal oxide layer 145 is arranged to be separated from the edge of the oxide semiconductor layer 130 by a predetermined distance (here, L2). Specifically, as shown in Figure 19B, the metal oxide layer 145 is arranged along the outer circumference of the oxide semiconductor layer 130 so as to be separated from the oxide semiconductor layer 130 by a width of L2. There are no particular restrictions on the range in which the distance L2 can be, but it is desirable to set it to 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less).

[0094] If the distance L2 is too large, the exposed area of ​​the insulating layer 140 will increase, which may lead to an increase in the amount of hydrogen reaching the channel region CR. Conversely, if the distance L2 is too small, if misalignment occurs when forming the opening 145-1 of the metal oxide layer 145, the oxide semiconductor layer 130 and the metal oxide layer 145 may overlap, which may reduce the effective area of ​​the source region SR or drain region DR. When the oxide semiconductor layer 130 and the metal oxide layer 145 overlap in this way, as described above, it can lead to poor connection between the source electrode or drain electrode and the oxide semiconductor layer 130.

[0095] As described above, in the case of Modification 2, the size of the opening 145-1 in the metal oxide layer 145 is larger than the size of the oxide semiconductor layer 130. In other words, in a plan view, the outer shape (contour) of the edge of the opening 145-1 encompasses the outer shape (contour) of the edge of the oxide semiconductor layer 130. With this configuration, the metal oxide layer 145 does not overlap the oxide semiconductor layer 130 (especially the source region SR and the drain region DR), thus preventing problems such as poor contact between the conductive layer 181 and the source region SR or between the conductive layer 182 and the drain region DR.

[0096] (Modification 2 of the first embodiment) In the first embodiment, an example was shown in which the metal oxide layer 145 formed in step S1040 shown in Figure 4 was patterned and left around the oxide semiconductor layer 130. However, the example is not limited to this, and the metal oxide layer may be formed after the conductive layer 150 is formed.

[0097] For example, the metal oxide layer 145 formed in step S1040 described above is completely removed after annealing. Then, after forming a conductive layer 150 on the insulating layer 140, a metal oxide layer having an opening that overlaps with the oxide semiconductor layer 130 can be formed. In this case, the metal oxide layer is positioned around the oxide semiconductor layer 130 and covers the top and sides of the conductive layer 150 around the oxide semiconductor layer 130 (i.e., the region that does not overlap with the oxide semiconductor layer 130).

[0098] <Second Embodiment> In the first embodiment, an example was described in which a channel region CR, a source region SR, and a drain region DR were provided in the oxide semiconductor layer 130. In this embodiment, an example is described in which a low-resistance region HRR is provided in addition to those regions. In the description of this embodiment, elements identical to those in the first embodiment may be denoted by the same reference numerals in the drawings and their descriptions may be omitted.

[0099] (Pixel structure) Figure 20 is a schematic cross-sectional view showing the configuration of a pixel 13a including a semiconductor device according to one embodiment of the present invention. The basic structure of Figure 20 is the same as that of the pixel 13 shown in Figure 3, but the configuration of the oxide semiconductor layer 130a, which functions as the active layer of the semiconductor device, is different. Specifically, the oxide semiconductor layer 130a has low-resistance regions HRR between the channel region CR and the source region SR, and between the channel region CR and the drain region DR.

[0100] The low-resistance region (HRR) is a region with relatively lower resistance than the channel region (CR). However, the resistance of the low-resistance region (HRR) is higher than that of the source region (SR) and the drain region (DR). The low-resistance region (HRR) functions as a buffer region that suppresses the carrier movement speed from the channel region (CR) to the source region (SR) or drain region (DR). In other words, functionally, it is similar to the region generally called the LDD region.

[0101] Furthermore, in this embodiment, a metal oxide layer 145a is provided so as to cover the conductive layer 150. Specifically, the metal oxide layer 145a is provided so as to cover the upper and side surfaces of the conductive layer 150, and a part of the upper surface of the insulating layer 140. Consequently, in the first embodiment, one opening 145-1 is provided in the metal oxide layer 145 in one transistor, whereas in this embodiment, two openings 145a-1 are provided in the metal oxide layer 145a in one transistor. As shown in Figure 20, the two openings 145a-1 are superimposed on the source region SR and drain region DR provided in the oxide semiconductor layer 130a, respectively. At this time, the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the upper surface of the insulating layer 140 is superimposed on the low-resistance region HRR of the oxide semiconductor layer 130a.

[0102] (Method of manufacturing pixels) Figures 21 to 24 are schematic cross-sectional views showing a method for manufacturing a pixel 13a including a semiconductor device according to one embodiment of the present invention.

[0103] First, in the first embodiment, steps S1010 to S1040 shown in Figure 4 are performed to complete the oxide annealing of the oxide semiconductor layer 130a. Then, the metal oxide layer 145 provided on the insulating layer 140 is completely removed, and a conductive layer 150 (second conductive layer) is formed in a position where it overlaps with the oxide semiconductor layer 130a. This results in the state shown in Figure 21.

[0104] Next, as shown in Figure 22, a metal oxide layer 145a is formed on the insulating layer 140 and the conductive layer 150. The metal oxide layer 145a may be formed using the same materials and deposition conditions as the metal oxide layer 145 described in the first embodiment. In this embodiment, an aluminum oxide (AlOx) layer with a thickness of 8 nm is formed as the metal oxide layer 145a by sputtering.

[0105] After forming the metal oxide layer 145a, the metal oxide layer 145a is patterned to form openings 145a-1. Specifically, a resist mask (not shown) is formed on the metal oxide layer 145a by photolithography, and the metal oxide layer 145a is etched by a wet etching process using hydrofluoric acid to form two openings 145a-1. At this time, the metal oxide layer 145a is left on top of the conductive layer 150 so as to cover the conductive layer 150.

[0106] As shown in Figure 22, a portion of the metal oxide layer 145a, which is arranged to cover the conductive layer 150, is in contact with the upper surface of the insulating layer 140. Specifically, a portion of the metal oxide layer 145a covering the conductive layer 150 is arranged to overlap with the insulating layer 140 by a predetermined distance (here, L3). In other words, in Figure 22, the opening 145a-1 is separated from the edge of the conductive layer 150 by a predetermined distance L3. There are no particular restrictions on the range of distance L3, but it is desirable to set it to 0.5 μm or more and 3.0 μm or less (preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.5 μm or more and 2.0 μm or less). The opening 145a-1 is formed to overlap with the region of the oxide semiconductor layer 130a that will later function as the source region SR and the drain region DR.

[0107] Next, as shown in Figure 23, impurities are implanted into the oxide semiconductor layer 130a. The impurity implantation process is the same as the process described in step S1070 of Figure 4. By performing the impurity implantation process, a channel region CR, a source region SR, and a drain region DR are formed in the oxide semiconductor layer 130a. In this embodiment, the region directly below the conductive layer 150 becomes the channel region CR (region without added impurities). Also, the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140 does not function as a mask in the impurity implantation process. Therefore, impurities are added to the oxide semiconductor layer 130a located directly below the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140.

[0108] Subsequently, by forming the insulating layer 160, the conductive layer 181, and the conductive layer 182 according to steps S1080 and S1090 shown in Figure 4 of the first embodiment, the state shown in Figure 24 is obtained.

[0109] During the process of forming the insulating layer 160, conductive layer 181, and conductive layer 182, the oxide semiconductor layer 130 and insulating layer 140 are heated. In this embodiment, a large amount of oxygen, whose diffusion is suppressed by the metal oxide layer 145a, remains directly beneath the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140. Therefore, the heating during the process of forming the insulating layer 160, conductive layer 181, and conductive layer 182 causes the oxygen remaining inside the insulating layer 140 to diffuse into the oxide semiconductor layer 130. As a result, the oxygen vacancies formed in the oxide semiconductor layer 130 by the impurity injection process are repaired again by oxygen, and the resistance of the oxide semiconductor layer 130 increases. That is, the oxide semiconductor layer 130 located directly beneath the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140 increases in resistance.

[0110] As described above, in this embodiment, a low-resistance region HRR is formed between the channel region CR and the source region SR, and between the channel region CR and the drain region DR, where the resistance is lower than that of the channel region CR and higher than that of the source region SR and the drain region DR. In this way, the channel region CR and the low-resistance region HRR are formed in a self-aligned manner. In this embodiment, the width of the low-resistance region HRR in the channel direction is L3.

[0111] In this embodiment, as in the first embodiment, when impurities are implanted into the oxide semiconductor layer 130, the metal oxide layer 145a is placed around the oxide semiconductor layer 130, thereby suppressing the diffusion of hydrogen during the subsequent heating process. Therefore, according to this embodiment, it is possible to efficiently suppress the decrease in channel resistance due to hydrogen diffusion.

[0112] <Third Embodiment> This embodiment describes an example of manufacturing a semiconductor device using a method different from that of the first embodiment. Specifically, in this embodiment, a metal oxide layer 145b is left between the insulating layer 140 and the conductive layer 150. In describing this embodiment, elements identical to those in the first embodiment may be denoted by the same reference numerals in the drawings and their descriptions may be omitted.

[0113] Figure 25 is a schematic cross-sectional view showing the configuration of a pixel 13b including a semiconductor device according to one embodiment of the present invention. The basic structure of Figure 25 is the same as that of the pixel 13 shown in Figure 3, but differs in that a metal oxide layer 145b is interposed between the insulating layer 140 and the conductive layer 150.

[0114] Figures 26 to 29 are schematic cross-sectional views showing a method for manufacturing a pixel 13b including a semiconductor device according to one embodiment of the present invention.

[0115] First, in the first embodiment, steps S1010 to S1040 shown in Figure 4 are performed to complete the oxide annealing of the oxide semiconductor layer 130. Then, a conductive layer 150 (second conductive layer) is formed on the metal oxide layer 145b at a position where it overlaps with the oxide semiconductor layer 130. This results in the state shown in Figure 26.

[0116] In this embodiment, a molybdenum-tungsten alloy is used as the constituent material for the conductive layer 150, and aluminum oxide is used as the constituent material for the metal oxide layer 145b. In this case, by using a dry etching process using a fluorine-based gas for the patterning process to form the conductive layer 150, a selectivity ratio between the conductive layer 150 and the metal oxide layer 145b can be ensured.

[0117] Next, as shown in Figure 27, a resist mask RM is formed on the metal oxide layer 145b. The resist mask RM has an opening RM1 in a position that overlaps with the oxide semiconductor layer 130. In other words, the resist mask RM is formed in a region that does not overlap with the oxide semiconductor layer 130. Specifically, the position of the inner wall of the opening RM1 and the position of the edge of the oxide semiconductor layer 130 coincide in a direction perpendicular to the substrate 100. That is, in a plan view, the outer shape of the edge of the opening RM1 coincides with the outer shape of the edge of the oxide semiconductor layer 130.

[0118] Next, as shown in Figure 28, the metal oxide layer 145b is etched using the resist mask RM and the conductive layer 150 as masks to form two openings 145b-1. At this time, the etching process is performed by wet etching using hydrofluoric acid. By using hydrofluoric acid as the etchant, not only the resist mask RM but also the conductive layer 150 can be used as a mask. Furthermore, in this embodiment, since the thickness of the metal oxide layer 145b is 10 nm or less, etching is completed in a very short time. Therefore, by controlling the etching time, over-etching of the insulating layer 140 that is exposed after etching of the metal oxide layer 145b can be minimized.

[0119] Next, as shown in Figure 29, after removing the resist mask RM, impurities are added to the oxide semiconductor layer 130 using ion implantation. This forms a channel region CR, a source region SR, and a drain region DR in the oxide semiconductor layer 130.

[0120] The processes from the impurity injection process shown in Figure 29 onward are the same as in the first embodiment, so redundant explanations are omitted. Also, in this embodiment, the role of the metal oxide layer 145b arranged around the oxide semiconductor layer 130 is the same as in the first embodiment, so its explanation is omitted. According to this embodiment, the amount of hydrogen generated near the oxide semiconductor layer 130 can be significantly reduced, and the decrease in channel resistance due to hydrogen diffusion can be efficiently suppressed. As a result, the decrease in channel resistance due to hydrogen diffusion can be suppressed, and highly reliable semiconductor devices can be manufactured.

[0121] (Modified version of the third embodiment) Figure 30 is a schematic cross-sectional view showing the configuration of a pixel 13c including a semiconductor device according to a modified example of one embodiment of the present invention. While the basic structure of Figure 30 is similar to that of the pixel 13 shown in Figure 25, the configuration of the oxide semiconductor layer 130c, which functions as the active layer of the semiconductor device, is different. Specifically, the oxide semiconductor layer 130c includes low-resistance regions HRR between the channel region CR and the source region SR, and between the channel region CR and the drain region DR.

[0122] Figures 31 to 34 are schematic cross-sectional views showing a method for manufacturing a pixel 13c, including a semiconductor device according to a modified example of one embodiment of the present invention.

[0123] First, after going through the state shown in Figure 26 above, a resist mask RM is formed on the metal oxide layer 145c as shown in Figure 31. The resist mask RM is formed not only in the region that does not overlap with the oxide semiconductor layer 130, but also on the conductive layer 150. Specifically, in Figure 31, in addition to the resist mask RM provided at the position shown in Figure 27, a resist mask RM is provided that covers the top and side surfaces of the conductive layer 150, and a part of the top surface of the insulating layer 140. As a result, in Figure 31, two openings RM1 are provided in the resist mask RM of one transistor.

[0124] At this time, a portion of the resist mask RM covering the conductive layer 150 is positioned to overlap with the insulating layer 140 by a predetermined distance (here, L3). In other words, in Figure 31, the opening RM1 is separated from the edge of the conductive layer 150 by a predetermined distance L3. There are no particular restrictions on the range of distance L3, but it is desirable to set it to 0.5 μm or more and 3.0 μm or less (preferably 1.0 μm or more and 2.0 μm or less, and more preferably 1.5 μm or more and 2.0 μm or less). The opening RM1 is formed to overlap with the region of the oxide semiconductor layer 130a that will later function as the source region SR and the drain region DR.

[0125] Next, as shown in Figure 32, the metal oxide layer 145c is etched using the resist mask RM as a mask to form two openings 145c-1. The etching is performed by wet etching using hydrofluoric acid. However, this is not limited to this example; either wet etching or dry etching may be used as long as it is possible to etch the metal oxide layer 145c. However, it is desirable to minimize over-etching of the insulating layer 140 that is exposed after etching the metal oxide layer 145c.

[0126] As shown in Figure 32, a metal oxide layer 145c remains between the insulating layer 140 and the conductive layer 150 due to the process. As shown in Figure 32, the width of the metal oxide layer 145c positioned between the insulating layer 140 and the conductive layer 150 in the channel direction is twice the width of the conductive layer 150 in the channel direction by a predetermined distance L3. In other words, the portion of the metal oxide layer 145c located between the insulating layer 140 and the conductive layer 150 that does not overlap with the conductive layer 150 (hereinafter referred to as the "non-overlapping portion of the metal oxide layer 145c") protrudes from the conductive layer 150 in the channel direction and covers the insulating layer 140.

[0127] Next, after removing the resist mask RM, impurities are implanted into the oxide semiconductor layer 130c, as shown in Figure 33. The impurity implantation process is the same as the process described in step S1070 of Figure 4. By performing the impurity implantation process, a channel region CR, a source region SR, and a drain region DR are formed in the oxide semiconductor layer 130c. In this modified example, the region directly beneath the conductive layer 150 becomes the channel region CR (the region without added impurities). Also, the non-overlapping portion of the metal oxide layer 145c does not function as a mask in the impurity implantation process. Therefore, impurities are added to the oxide semiconductor layer 130c located directly beneath the non-overlapping portion of the metal oxide layer 145c.

[0128] Subsequently, by forming the third insulating layer 160, the conductive layer 181, and the conductive layer 182 according to steps S1080 and S1090 shown in Figure 4 of the first embodiment, the state shown in Figure 34 is obtained.

[0129] During the process of forming the third insulating layer 160, conductive layer 181, and conductive layer 182, the oxide semiconductor layer 130 and insulating layer 140 are heated. In this embodiment, a large amount of oxygen, whose diffusion is suppressed by the metal oxide layer 145c, remains directly beneath the non-overlapping portion of the metal oxide layer 145c. Therefore, the heating during the process of forming the third insulating layer 160, conductive layer 181, and conductive layer 182 causes the oxygen remaining inside the insulating layer 140 to diffuse into the oxide semiconductor layer 130. As a result, the oxygen vacancies formed in the oxide semiconductor layer 130 by the impurity injection process are repaired again by oxygen, and the resistance of the oxide semiconductor layer 130 increases. That is, the oxide semiconductor layer 130 located directly beneath the non-overlapping portion of the metal oxide layer 145c has increased resistance.

[0130] As described above, in this embodiment, a low-resistance region HRR is formed between the channel region CR and the source region SR, and between the channel region CR and the drain region DR, where the resistance is lower than that of the channel region CR and higher than that of the source region SR and the drain region DR. In this embodiment, the width of the low-resistance region HRR in the channel direction is L3.

[0131] In this embodiment, as in the first embodiment, when impurities are implanted into the oxide semiconductor layer 130c, the metal oxide layer 145c is placed around the oxide semiconductor layer 130c, thereby suppressing hydrogen diffusion during the subsequent heating process. Therefore, according to this embodiment, it is possible to efficiently suppress the decrease in channel resistance due to hydrogen diffusion.

[0132] The embodiments described above (including modifications) of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any modifications based on these embodiments, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0133] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0134] 10…Display device, 11…Substrate, 12…Display unit, 13, 13a…Pixel, 14-1…Gate drive circuit, 14-2…Gate drive circuit, 16…Terminal, 17…Terminal unit, 18…Flexible printed circuit, 19…Peripheral unit, 20…Touch sensor, 100…Substrate, 110…Conductive layer, 120…Insulating layer, 130, 130a…Oxide semiconductor layer, 140…Insulating layer, 145, 145a, 1 45b, 145c…metal oxide layer, 145-1, 145a-1, 145b-1, 145c-1…opening, 150…conductive layer, 160…insulating layer, 161, 162…contact hole, 181, 182…conductive layer, 190…insulating layer, 191…contact hole, 200…pixel electrode, 210…bank, 212…opening, 220…light-emitting layer, 230…common electrode, 240…sealing layer

Claims

1. Oxide semiconductor layer, A gate insulating layer provided on the oxide semiconductor layer, A metal oxide layer having an opening that overlaps with at least a portion of the oxide semiconductor layer, and in a region that does not overlap with the oxide semiconductor layer, in contact with the upper surface of the gate insulating layer, A gate electrode provided on the gate insulating layer in the region overlapping with the oxide semiconductor layer, Semiconductor equipment, including

2. The semiconductor device according to claim 1, wherein, in a plan view, the outer shape of the edge of the opening matches the outer shape of the edge of the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein, in a plan view, the outer shape of the edge of the oxide semiconductor layer includes the outer shape of the edge of the opening.

4. The semiconductor device according to claim 3, wherein the metal oxide layer is superimposed on a portion of the oxide semiconductor layer along the edge of the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein, in a plan view, the outer shape of the edge of the opening encompasses the outer shape of the edge of the oxide semiconductor layer.

6. The semiconductor device according to claim 5, wherein the distance from the edge of the opening to the edge of the oxide semiconductor layer is 0.3 μm or more and 1.2 μm or less.

7. The semiconductor device according to claim 1, wherein the gate electrode is in contact with the metal oxide layer in a region that does not overlap with the oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein the opening has a first opening that overlaps with the source region of the oxide semiconductor layer and a second opening that overlaps with the drain region of the oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein a portion of the metal oxide layer covers the upper and side surfaces of the gate electrode and is in contact with the gate insulating layer in the region where it overlaps with the oxide semiconductor layer.

10. The semiconductor device according to claim 8, wherein a portion of the metal oxide layer is disposed between the gate insulating layer and the gate electrode in a region where it overlaps with the oxide semiconductor layer.

11. The semiconductor device according to claim 1, wherein the metal oxide layer comprises aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx).

12. The semiconductor device according to claim 1, wherein the thickness of the metal oxide layer is 20 nm or less.

13. A display device comprising a semiconductor device according to any one of claims 1 to 12.

14. By forming an oxide semiconductor layer on an insulating surface, A gate insulating layer is formed on the oxide semiconductor layer. A metal oxide layer is formed having an opening that overlaps with at least a portion of the oxide semiconductor layer and is in contact with the upper surface of the gate insulating layer. A gate electrode is formed on the gate insulating layer, Adding impurities to the oxide semiconductor layer via the gate insulating layer, A method for manufacturing a semiconductor device, including the method described above.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the metal oxide layer is formed by a sputtering method.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the metal oxide layer comprises aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx).

17. The method for manufacturing a semiconductor device according to claim 14, wherein the thickness of the metal oxide layer is 20 nm or less.

18. The method for manufacturing a semiconductor device according to claim 14, wherein, in a plan view, the outer shape of the edge of the opening matches the outer shape of the edge of the oxide semiconductor layer.

19. The method for manufacturing a semiconductor device according to claim 14, wherein, in a plan view, the outer shape of the edge of the oxide semiconductor layer includes the outer shape of the edge of the opening.

20. The method for manufacturing a semiconductor device according to claim 14, wherein, in a plan view, the outer shape of the edge of the opening encompasses the outer shape of the edge of the oxide semiconductor layer.

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