memory devices

Abstract

To improve the reliability of memory devices. [Solution] The memory device of the embodiment includes a cell array including a first wiring extending in a first direction, second and third wirings extending in a second direction, a first cell between the first and second wirings, and a second cell between the first and third wirings; a first switch circuit connected to the first wiring and provided at one end of the cell array in the first direction; a second switch circuit connected to the second and third wirings and provided at one end of the cell array in the second direction; and first and second global lines connected to the second switch circuit, wherein the second wiring is positioned between the first switch circuit and the third wiring in the first direction, the second wiring is connected to the first global line via the second switch circuit, the third wiring is connected to the second global line via the second switch circuit, and the length of the second global line is shorter than the length of the first global line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] Memory devices using variable resistance elements (for example, magneto resistive effect elements) as memory elements are known. In order to improve the characteristics of memory devices, various technologies related to memory devices have been researched and developed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the reliability of the memory device.

Means for Solving the Problems

[0005] The memory device of the embodiment includes a memory cell array comprising: a first local wiring extending in a first direction; a second local wiring extending in a second direction intersecting the first direction; a third local wiring extending in the second direction; a first memory cell provided between the first local wiring and the second local wiring; and a second memory cell provided between the first local wiring and the third local wiring; a first switch circuit connected to the first local wiring and provided on one end of the memory cell array in the first direction; and a circuit connected to the second and third local wiring and on one end of the memory cell array in the second direction. The device comprises a second switch circuit provided at the end, a first circuit for performing a write or read operation of the memory cell array, and first and second global wirings connected between the second switch circuit and the first circuit, wherein the second local wiring is positioned between the first switch circuit and the third local wiring in the first direction, the second local wiring is connected to the first global wiring via the second switch circuit, the third local wiring is connected to the second global wiring via the second switch circuit, and the length of the second global wiring is shorter than the length of the first global wiring. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example configuration of a memory cell array of a memory device according to the first embodiment. [Figure 3] A bird's-eye view showing an example configuration of a memory cell array in a memory device according to the first embodiment. [Figure 4] A cross-sectional view showing an example configuration of a memory cell array in a memory device according to the first embodiment. [Figure 5] A cross-sectional view showing an example configuration of a memory cell array in a memory device according to the first embodiment. [Figure 6] A schematic diagram showing an example of the memory cell configuration of the memory device of the first embodiment. [Figure 7] A plan view showing an example configuration of a memory device according to the first embodiment. [Figure 8] A cross-sectional view showing an example configuration of a memory device according to the first embodiment. [Figure 9] A cross-sectional view showing an example configuration of a memory device according to the first embodiment. [Figure 10] A plan view showing an example configuration of a memory device according to the first embodiment. [Figure 11] A cross-sectional view showing an example configuration of a memory device according to the first embodiment. [Figure 12] A cross-sectional view showing an example configuration of a memory device according to the first embodiment. [Figure 13] A cross-sectional view showing an example configuration of a memory device according to the second embodiment. [Figure 14] A cross-sectional view showing an example configuration of a memory device according to the second embodiment. [Figure 15] A cross-sectional view showing an example configuration of a memory device according to the third embodiment. [Figure 16] A cross-sectional view showing an example configuration of a memory device according to the third embodiment. [Figure 17] A diagram showing a modified example of the memory device of the embodiment. [Figure 18] A diagram showing a modified example of the memory device of the embodiment. [Modes for carrying out the invention]

[0007] This embodiment will be described in detail below with reference to the drawings. In the following description, elements having the same function and configuration will be denoted by the same reference numerals. In each of the following embodiments, for multiple identical components (e.g., circuits, wiring, various voltages and signals), a distinguishing number or letter may be added to the end of the reference numeral. If components that have a distinguishing number or letter at the end of their reference numeral do not need to be distinguished from one another, the reference numeral or letter at the end is omitted.

[0008] (Embodiment) (1) First Embodiment Referring to FIGS. 1 to 12, the memory device 100 of the first embodiment will be described.

[0009] (a) Configuration Example Referring to FIGS. 1 to 12, the configuration example of the memory device of this embodiment will be described.

[0010] (a-1) Overall Configuration FIG. 1 is a diagram showing a configuration example of the memory device 100 of this embodiment.

[0011] As shown in FIG. 1, the memory device 100 of this embodiment is connected to a device outside the memory device 100 (hereinafter referred to as an external device) 900.

[0012] The external device 900 sends a command CMD, an address ADR, and a control signal CNT to the memory device 100. Data DT is transferred between the memory device 100 and the external device 900. The external device 900 sends data (hereinafter referred to as write data) to be written into the memory device 100 to the memory device 100 during a write operation. The external device 900 receives data (hereinafter referred to as read data) read from the memory device 100 from the memory device 100 during a read operation.

[0013] The memory device 100 of this embodiment includes a memory cell array 110, a column control circuit 120, a row control circuit 130, a write circuit 140, a read circuit 150, a voltage generation circuit 160, an input / output circuit 170, and a control circuit 180.

[0014] The memory cell array 110 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0015] Multiple memory cells MC are associated with multiple rows and multiple columns in the memory cell array 110. Each memory cell MC is connected to one of multiple word lines WL. Each memory cell MC is connected to one of multiple bit lines BL.

[0016] The column control circuit 120 controls the columns of the memory cell array 110. The column control circuit 120 is connected to the memory cell array 110 via bit lines (local wiring) BL. The column control circuit 120 receives the column address of the memory cell array 110 in address ADR (or the decoded result of the column address). Based on the decoded result of the column address, the column control circuit 120 controls multiple bit line BLs. In this way, the column control circuit 120 sets each of the multiple bit line BLs (multiple columns) to either a selected state or a deselected state. In the following, bit line BLs set to the selected state are called selected bit line BLs, and bit line BLs other than selected bit line BLs are called deselected bit line BLs. The column control circuit 120 includes one or more column switch circuits 121. Each column switch circuit 121 controls the connection between the selected bit line BL and the global wiring described later.

[0017] The row control circuit 130 controls the rows of the memory cell array 110. The row control circuit 130 is connected to the memory cell array 110 via word lines (local wiring) WL. The row control circuit 130 receives the row address of the memory cell array 110 in the address ADR (or the decoded result of the row address). Based on the decoded result of the row address, the row control circuit 130 controls multiple word lines WL. In this way, the row control circuit 130 sets each of the multiple word lines WL (multiple rows) to either a selected state or a deselected state. In the following, word lines WL set to the selected state are called selected word lines WL, and word lines WL other than selected word lines WL are called deselected word lines WL. The row control circuit 130 includes one or more row switch circuits 131. Each row switch circuit 131 controls the connection between the selected word line WL and the global wiring described later.

[0018] The write circuit 140 writes data to the memory cell MC. The write circuit 140 is connected to the column control circuit 120 and the row control circuit 130 via global wiring GBL and GWL. The write circuit 140 supplies a voltage (or current) for writing data to the selection word line WL and the selection bit line BL, respectively, via global wiring GBL and GWL. This supplies a certain write voltage (or write current) to the selected memory cell MC. The write circuit 140 can supply one of a plurality of write voltages to the selected memory cell MC, depending on the data to be written. For example, each of the plurality of write voltages has a polarity (bias direction) corresponding to the data to be written. For example, the write circuit 140 includes a write driver (not shown) and a write sink (not shown), etc.

[0019] The read circuit 150 reads data from the memory cell MC. The read circuit 150 is connected to the column control circuit 120 and the row control circuit 130 via global wiring GBL and GWL. The read circuit 150 amplifies the signal output from the selected memory cell MC to the selected bit line BL. Based on the amplified signal, the read circuit 150 determines the data in the memory cell MC. For example, the read circuit 150 includes a preamplifier (not shown), a sense amplifier (not shown), a read driver (not shown), and a read sink (not shown).

[0020] The voltage generation circuit 160 uses the power supply voltage provided by the external device 900 to generate voltages for various operations of the memory cell array 110. For example, the voltage generation circuit 160 generates various voltages used for writing operations. The voltage generation circuit 160 outputs the generated voltages to the writing circuit 140. For example, the voltage generation circuit 160 generates various voltages used for reading operations. The voltage generation circuit 160 outputs the generated voltages to the reading circuit 150.

[0021] The input / output circuit 170 functions as an interface circuit for various signals ADR, CMD, CNT, and DT between the memory device 100 and the external device 900. The input / output circuit 170 transfers the address ADR from the external device 900 to the control circuit 180. The input / output circuit 170 transfers the command CMD from the external device 900 to the control circuit 180. The input / output circuit 170 transfers various control signals CNT between the external device 900 and the control circuit 180. The input / output circuit 170 transfers the write data DT from the external device 900 to the write circuit 140. The input / output circuit 170 transfers the data DT from the read circuit 150 to the external device 900 as read data.

[0022] The control circuit (also called a sequencer, state machine, or internal controller) 180 decodes the command CMD. Based on the decoded command CMD and the control signal CNT, the control circuit 180 controls the operation of the column control circuit 120, row control circuit 130, write circuit 140, read circuit 150, voltage generation circuit 160, and input / output circuit 170 within the memory device 100. The control circuit 180 decodes the address ADR. The control circuit 180 sends the decoded address ADR to the column control circuit 120 and row control circuit 130, etc. For example, the control circuit 180 includes a register circuit (not shown) for temporarily storing the command CMD and address ADR. Note that the register circuit, the circuit for decoding the command CMD (command decoder), and the circuit for decoding the address ADR (address decoder) may be provided outside the control circuit 180 within the memory device 100.

[0023] (a-2) Memory cell array Referring to Figures 2 to 5, an example of the configuration of the memory cell array 110 in the memory device 100 of this embodiment will be described.

[0024] Figure 2 is an equivalent circuit diagram showing an example configuration of the memory cell array 110 of the memory device 100 in this embodiment.

[0025] As shown in Figure 2, multiple memory cells MC are arranged in a matrix within the memory cell array 110. Each memory cell MC has multiple bit lines BL (BL <0> BL <1> ,···,BL <n>) one of the corresponding words, and multiple word lines WL (WL <0> WL <1> ,···,WL <m>It is connected to one of the corresponding ones. M and N are integers greater than or equal to 1.

[0026] Each memory cell MC includes a memory element 1 and a switching element 2.

[0027] The memory element 1 is, for example, a variable resistance element. The resistance state of the memory element 1 changes to one of several resistance states (e.g., low resistance state and high resistance state) depending on the supplied voltage (or current). The memory element 1 can store data by associating its resistance state with data (e.g., "0" data and "1" data).

[0028] The switching element (also called a selector element or simply a selector) 2 functions as a selector element for the memory cell MC. The switching element 2 has the function of controlling the supply of voltage (or current) to the memory element 1 when writing data to the corresponding memory element 1 and when reading data from the corresponding memory element 1.

[0029] For example, if a certain voltage applied to a memory cell MC is lower than the threshold voltage of the switching element 2 within that memory cell MC, the switching element 2 is set to the off state (high resistance state, non-conductive state). In this case, the switching element 2 cuts off the voltage (or current) to the memory element 1. If a certain voltage applied to a memory cell MC is equal to or greater than the threshold voltage of the switching element 2 within that memory cell MC, the switching element 2 is set to the on state (low resistance state, conductive state). In this case, the switching element 2 supplies voltage (or current) to the memory element 1.

[0030] The switching element 2 can switch whether or not to allow current to flow into the memory cell MC, regardless of the direction of current flow within the memory cell MC, depending on the magnitude of the voltage applied to the memory cell MC.

[0031] For example, switching element 2 is a two-terminal element. In the example in Figure 2, one end of switching element 2 is connected to the word line WL. The other end of switching element 2 is connected to one end of memory element 1. The other end of memory element 1 is connected to the bit line BL.

[0032] Figures 3 to 5 are diagrams illustrating an example configuration of the memory cell array 110 of the memory device 100 of this embodiment. Figure 3 is a bird's-eye view illustrating an example configuration of the memory cell array 110. Figure 4 is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array 110 along a first direction (axis). Figure 5 is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array 110 along a second direction (axis). In the example of Figures 3 to 5, the first direction corresponds to the X direction, and the second direction corresponds to the Y direction.

[0033] As shown in Figures 3 to 5, the memory cell array 110 is located above the upper surface of the substrate 90. The X direction is parallel to the upper surface of the substrate 90. The Y direction is parallel to the upper surface of the substrate 90 and intersects the X direction. Hereafter, the plane parallel to the upper surface of the substrate 90 will be called the XY plane. The direction (axis) perpendicular to the XY plane will be called the Z direction (Z axis). The plane parallel to the plane formed by the X direction and the Z direction will be called the XZ plane. The plane parallel to the plane formed by the Y direction and the Z direction will be called the YZ plane.

[0034] Multiple wirings (conductive layers) 50 are provided above the upper surface of the substrate 90 in the Z direction, via an insulating layer 80. The multiple wirings 50 are aligned along the X direction. Each wiring 50 extends along the Y direction. The multiple wirings 50 function, for example, as word lines WL.

[0035] Multiple wirings (conductive layers) 51 are provided above multiple wirings 50 in the Z direction. Multiple wirings 51 are aligned along the Y direction. Each wiring 51 extends along the X direction. Multiple wirings 51 function, for example, as bit lines BL.

[0036] Multiple memory cells MC are provided between multiple wirings 50 and multiple wirings 51. The multiple memory cells MC are arranged in a matrix in the XY plane.

[0037] Multiple memory cells MCs aligned in the Y direction are provided above a single wiring 50. Two memory cells MCs aligned in the Y direction are adjacent with a predetermined spacing between them. Each of the multiple memory cells MCs aligned in the Y direction is connected to a common wiring 50 (word line WL) via a corresponding contact 52. Multiple contacts 52 are provided on a single wiring 50.

[0038] Multiple memory cells MCs aligned in the X direction are located below a single wiring 51. Two memory cells MCs aligned in the X direction are adjacent to each other with a predetermined spacing. Each of the multiple memory cells MCs aligned in the X direction is connected to a common wiring 51 (bit line BL) via a corresponding contact 53. Multiple contacts 53 are located below the single wiring 51.

[0039] For example, if the memory cell array 110 has the circuit configuration shown in Figure 2, the switching element 2 is located below the memory element 1 in the Z direction. The switching element 2 is located between the memory element 1 and the wiring 50 (word line WL). The memory element 1 is located between the wiring 51 (bit line BL) and the switching element 2.

[0040] Thus, each memory cell MC is a stack of memory elements 1 and switching elements 2. With these memory cell MCs, the memory cell array 110 has a stacked configuration.

[0041] Depending on the process (e.g., etching method) used to form the memory cell array 110, the memory cell MC may have a tapered cross-sectional shape.

[0042] An insulating layer 60 is provided above the substrate 90. The insulating layer 60 covers the memory cell MC, wiring 50, 51, and contacts 52, 53. An insulating layer 62 is provided on the insulating layer 60 and wiring 51.

[0043] Figures 4 and 5 show an example in which an insulating layer 80 is provided between a plurality of wirings 50 and a substrate 90. If the substrate 90 is a semiconductor substrate, one or more field-effect transistors TR may be provided on the semiconductor region on the upper surface of the substrate 90. The field-effect transistor TR is covered by the insulating layer 80. The field-effect transistor TR is provided on a semiconductor region surrounded by an element isolation insulating layer 99. The field-effect transistor TR includes a gate electrode 91, a gate insulating film 92, and source / drain layers 93a and 93b. The source / drain layers (diffusion layers) 93a and 93b are provided within the semiconductor region. The gate electrode 91 is located on the semiconductor region between the source / drain layers 93a and 93b via the gate insulating film 92. A contact plug CP is provided on the gate electrode 91 and on the source / drain layers 93a and 93b.

[0044] Within the insulating layer 80, multiple conductive layers M0, M1, M2, M3, contact plugs CP, and via plugs VP (VP0, VP1, VP2, VP3) are provided, forming a multilayer wiring structure. The field-effect transistors TR on the substrate 90 are components of circuits such as the column control circuit 120 and the row control circuit 130. The field-effect transistors TR are connected to the memory cell array 110 via the conductive layers M0, M1, M2, M3 and contact plugs CP and via plugs VP0, VP1, VP2, VP3 within the insulating layer 80. In this way, circuits for controlling the operation of the memory cell array 110 can be provided below the memory cell array 110 in the Z direction.

[0045] The circuit configuration and structure of the stacked memory cell array 110 are not limited to the examples shown in Figures 2 to 5. Depending on the connection relationship between the memory element 1 and the switching element 2 to the bit line BL and the word line WL, the circuit configuration and structure of the memory cell array 110 can be appropriately modified. For example, the structure of the memory cell array 110 having the circuit configuration of Figure 2 is not limited to the examples in Figures 3 to 5. For example, the switching element 2 may be provided above the memory element 1 in the Z direction. In this case, wiring 50 is used as the bit line BL, and wiring 51 is used as the word line WL.

[0046] (a-3) Memory cell Figure 6 is a cross-sectional view showing an example of the configuration of a memory cell MC in the memory device 100 of this embodiment.

[0047] As shown in Figure 6, in a stacked memory cell MC, the memory element 1 and the switching element 2 are aligned in the Z direction. In this example, the memory element 1 is provided on the switching element 2 in the Z direction.

[0048] For example, the variable resistor element as memory element 1 is a magnetoresistive element. In this case, the memory device 100 of this embodiment is a magnetic memory such as MRAM (Magnetoresistive Random Access Memory).

[0049] <Example of magnetoresistive element configuration> For example, the magnetoresistive element 1 includes at least two magnetic layers 11 and 13 and a non-magnetic layer 12. The non-magnetic layer 12 is located between the two magnetic layers 11 and 13 in the Z direction. In the example in Figure 6, the layers 11, 12, and 13 are arranged in the Z direction from the word line WL (wiring 50) side to the bit line BL (wiring 51) side, in the order of magnetic layer 11, non-magnetic layer 12, and magnetic layer 13.

[0050] The two magnetic layers 11 and 13 and the non-magnetic layer 12 form a magnetic tunnel junction. Hereinafter, the magnetoresistive element 1 including the magnetic tunnel junction will be called an MTJ (Magnetic Tunnel Junction) element 1. The non-magnetic layer 12 in the MTJ element 1 will be called a tunnel barrier layer.

[0051] The magnetic layers 11 and 13 are ferromagnetic layers containing, for example, cobalt (Co), iron (Fe), and / or boron (B). The magnetic layers 11 and 13 may be single-layer films (e.g., alloy films) or multilayer films (e.g., artificial lattice films). The tunnel barrier layer 12 is an insulating layer containing, for example, magnesium oxide. The tunnel barrier layer 12 may be a single-layer film or a multilayer film.

[0052] When the MTJ element 1 is a perpendicular magnetization type magnetoresistive element, each magnetic layer 11, 13 has perpendicular magnetic anisotropy. The easy magnetization axis direction of each magnetic layer 11, 13 is perpendicular to the layer plane (film plane) of the magnetic layer 11, 13. Each magnetic layer 11, 13 has magnetization perpendicular to the layer plane of the magnetic layer 11, 13. The direction of magnetization of each magnetic layer 11, 13 is parallel to the alignment direction (Z direction) of the magnetic layers 11, 13.

[0053] Of the two magnetic layers 11 and 13, the magnetization direction of one magnetic layer is variable, while the magnetization direction of the other magnetic layer is constant. The MTJ element 1 can have multiple resistance states (resistance values) depending on the relative relationship (magnetization arrangement) between the magnetization direction of one magnetic layer and the magnetization direction of the other magnetic layer.

[0054] For example, the magnetization direction of magnetic layer 13 is variable. The magnetization direction of magnetic layer 11 is constant (fixed). In the following, the magnetic layer 13, whose magnetization direction is variable, is called the memory layer. In the following, the magnetic layer 11, whose magnetization direction is constant (fixed), is called the reference layer. The memory layer 13 may also be called the free layer, magnetization-free layer, or magnetization-variable layer. The reference layer 11 may also be called the pinned layer, pinned layer, magnetization-invariant layer, or magnetization-fixed layer.

[0055] In this embodiment, "the magnetization direction of the reference layer (magnetic layer) is constant" or "the magnetization direction of the reference layer (magnetic layer) is fixed" means that when a current or voltage is supplied to the MTJ element 1 to change the magnetization direction of the memory layer 13, the magnetization direction of the reference layer 11 does not change before and after the supply of the current or voltage due to the supplied current or voltage.

[0056] When the magnetization direction of the memory layer 13 is the same as the magnetization direction of the reference layer 11 (i.e., the magnetization arrangement state of the MTJ element 1 is a parallel arrangement state), the resistance state of the MTJ element 1 is the first resistance state. When the magnetization direction of the memory layer 13 is different from the magnetization direction of the reference layer 11 (i.e., the magnetization arrangement state of the MTJ element 1 is an antiparallel arrangement state), the resistance state of the MTJ element 1 is a second resistance state, which is different from the first resistance state. The resistance value of the MTJ element 1 in the second resistance state (antiparallel arrangement state) is higher than the resistance value of the MTJ element 1 in the first resistance state (parallel arrangement state).

[0057] In the following, with respect to the magnetization alignment state of MTJ element 1, the parallel alignment state is also referred to as the P state, and the antiparallel alignment state is also referred to as the AP state.

[0058] For example, the MTJ element 1 is connected to two electrodes 31 and 32. The magnetic layers 11 and 13 and the tunnel barrier layer 12 are provided between the two electrodes 31 and 32 in the Z direction. The reference layer 11 is provided between the electrode (called the intermediate electrode) 31 and the tunnel barrier layer 12. The memory layer 13 is provided between the electrode (called the upper electrode) 32 and the tunnel barrier layer 12.

[0059] For example, a shift cancellation layer 14 may be provided within the MTJ element 1. In this case, the shift cancellation layer 14 is provided between the reference layer 11 and the intermediate electrode 31. The shift cancellation layer 14 is a magnetic layer that mitigates the effect of the leakage magnetic field of the reference layer 11. When the MTJ element 1 includes a shift cancellation layer 14, a non-magnetic layer 15 is provided between the shift cancellation layer 14 and the reference layer 11. The non-magnetic layer 15 is a metallic layer, such as a ruthenium (Ru) layer. The shift cancellation layer 14 is antiferromagnetically coupled to the reference layer 11 via the non-magnetic layer 15. As a result, the laminate including the reference layer 11 and the shift cancellation layer 14 forms a SAF (Synthetic antiferromagnetic) structure. In the SAF structure, the magnetization direction of the shift cancellation layer 14 is opposite to the magnetization direction of the reference layer 11. The SAF structure allows the magnetization direction of the reference layer 11 to be more stably fixed. Furthermore, the collection of the two magnetic layers 11 and 14 and the non-magnetic layer 15 that form the SAF structure is sometimes referred to as the reference layer.

[0060] For example, the MTJ element 1 may include at least one of a base layer (not shown) and a cap layer (not shown). The base layer is provided between the magnetic layer (here, a shift-cancellation layer) 14 and the intermediate electrode 31. The base layer is a non-magnetic layer (e.g., a conductive layer). The base layer is a layer for improving the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 14 in contact with the base layer. The cap layer is provided between the magnetic layer (here, a memory layer) 13 and the upper electrode 32. The cap layer is a non-magnetic layer (e.g., a conductive layer). The cap layer is a layer for improving the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 13 in contact with the cap layer. Note that the base layer and the cap layer may each be considered as components of the electrodes 31 and 32.

[0061] <Example of switching element configuration> As shown in Figure 6, when the switching element 2 is a two-terminal element, the switching element 2 includes at least one variable resistance layer (also called a switching layer or selector layer) 20. The variable resistance layer 20 is located between two electrodes 30, 31 in the Z direction. The variable resistance layer 20 can take on multiple resistance states.

[0062] The electrode (referred to as the lower electrode) 30 is located below the variable resistance layer 20 in the Z direction, and the intermediate electrode 31 is located above the variable resistance layer 20 in the Z direction. For example, the lower electrode 30 is located between the wiring 50 and the variable resistance layer 20. The electrode 31 is located between the variable resistance layer 20 and the MTJ element 1.

[0063] The variable resistance layer 20 is connected to the wiring 50 via the lower electrode 30 and contact 52. The variable resistance layer 20 is connected to the MTJ element 1 via the intermediate electrode 31.

[0064] Depending on the voltage applied to the switching element 2 (memory cell MC), the resistance state of the variable resistance layer 20 becomes either a high-resistance state (non-conductive state) or a low-resistance state (conductive state). When the resistance state of the variable resistance layer 20 is high-resistance, the switching element 2 is off. When the resistance state of the variable resistance layer 20 is low-resistance, the switching element 2 is on.

[0065] When the memory cell MC is set to the selected state, the switching element 2 is turned on, and the resistance state of the variable resistance layer 20 is low. When the memory cell MC is set to the unselected state, the switching element 2 is turned off, and the resistance state of the variable resistance layer 20 is high.

[0066] Furthermore, depending on the material of the variable resistance layer 20, the change in the resistance state of the variable resistance layer 20 may also depend on the current (for example, the magnitude of the current) flowing through the switching element 2 (memory cell MC).

[0067] For example, the lower electrode 30 and the upper electrode 32 are conductive layers made of titanium (Ti), tungsten (W), titanium nitride (TiN), or tungsten nitride (WN). The intermediate electrode 31 is a conductive layer made of carbon (C) or carbon nitride (CN).

[0068] A memory cell array 110 having the structure shown in Figures 3 to 6 can be formed using well-known techniques.

[0069] (a-4) Configuration of global word lines and global bit lines Figures 7 to 12 illustrate the configuration of the global wiring within the memory cell array 110 of the MRAM 100 in this embodiment.

[0070] Figure 7 is a plan view showing an example of the configuration of global word lines in the MRAM100 of this embodiment.

[0071] As shown in Figure 7, the memory cell array 110 has a rectangular layout when viewed from the Z direction.

[0072] M book word line WL <1> WL <2> ,···,WL <x>···,WL <m-1>,WL <m>These are arranged in the X direction with predetermined intervals within the memory cell array 110. N bit lines BL <1> BL <2> ,···,BL <y>···,BL <n-1>,BL <n>These are arranged in the Y direction with predetermined intervals within the memory cell array 110. The bit lines BL are positioned above the word lines WL in the Z direction. The lengths of the multiple word lines WL are the same. The lengths of the multiple bit lines BL are the same.

[0073] For example, a memory cell MC is located at the coordinates (x,y) within the memory cell array 110. The memory cell MC is located along the word line WL. <x>and bit line BL <y>It is located at the intersection of the two lines. x is an integer between 1 and M (inclusive). y is an integer between 1 and N (inclusive).

[0074] For example, the value of "M" is equal to the value of "N". The spacing between memory cells MC in the X direction is equal to the spacing between memory cells MC in the Y direction. The memory cell array 110 has a square layout (planar structure) when viewed from the Z direction.

[0075] When multiple memory cells (MCs) are arranged at predetermined intervals in the X direction, the wiring resistance between two adjacent memory cells (MCs) in the X direction has a resistance value of "Rs_x". When the address of a word line (WL) changes by one, the wiring resistance applied to the memory cells (MCs) changes by "Rs_x". When multiple memory cells (MCs) are arranged at predetermined intervals in the Y direction, the wiring resistance between two adjacent memory cells (MCs) in the Y direction has a resistance value of "Rs_y". When the address of a bit line (BL) changes by one, the wiring resistance applied to the memory cells (MCs) changes by "Rs_y".

[0076] For example, in this embodiment, the value of "Rs_x" is equal to the value of "Rs_y". In the following, the resistance between memory cells MC will also be denoted as "Rs".

[0077] As shown in Figure 7, in the MRAM of this embodiment, the row control circuit 130 includes a row switch circuit 131-1. The row switch circuit 131-1 is provided on one end of the memory cell array 110 in the Y direction. Hereinafter, within the memory cell array 110, the region closer to the row switch circuit 131-1 will be called the near region (near side), and the region further from the row switch circuit 131-1 will be called the far region (far side).

[0078] The low switch circuit 131-1 is connected to multiple word lines WL. The low switch circuit 131-1 is connected to multiple global word lines GWL (GWL <1> GWL <xx>, SEE Each global word line GWL is connected to the write circuit 140 and the read circuit 150.

[0079] The row switch circuit 131-1 includes multiple row switch SWRs. A row switch SWR is, for example, a field-effect transistor TR. One end of each row switch SWR is electrically connected to a corresponding word line WL from among multiple word lines WL. The other end of each row switch SWR is electrically connected to a corresponding global word line GWL from among multiple global word lines GWL.

[0080] In the row switch circuit 131-1, each row switch SWR is set to either the ON state or the OFF state depending on the supplied address ADR. Depending on the ON / OFF state of the multiple row switches SWR in the row switch circuit 131-1, one word line WL is electrically connected to the global word line GWL via the ON row switch SWR.

[0081] The distance between the memory cell MC and the column switch SWC changes depending on the X-direction (row) coordinate of the memory cell MC within the memory cell array 110.

[0082] As a result, when the MRAM 100 is in operation, the magnitude of the wiring resistance of the bit line BL applied to the memory cell MC within the memory cell array 110 changes depending on the X-direction (row) coordinate of the memory cell MC.

[0083] In this embodiment, the multiple global word lines GWL have different lengths from each other. This allows the MRAM 100 in this embodiment to mitigate the effects caused by differences in the wiring resistance of the bit lines BL corresponding to the coordinates of the memory cells MC.

[0084] A bit line BL <y>Multiple memory cells MCa, MCb, and MCc are connected to it.

[0085] Memory cell MCa is a word line WL <1> It is connected to the word line WL. <x>It is connected to the word line WL. <m>It connects to the network.

[0086] The Y-coordinates (column) of memory cells MCa, MCb, and MCc are the same. The distance between each memory cell MCa, MCb, and MCc and its corresponding low switch SWR is the same. Therefore, the wiring resistance of the word line WL applied to each memory cell MCa, MCb, and MCc (hereinafter referred to as the word line resistance) is the same (y × Rs_y).

[0087] The X-coordinates (rows) of memory cells MCa, MCb, and MCc are different. Therefore, the distances between each of the memory cells MCa, MCb, and MCc and the column switch circuit 121 (column switch SWC) are different. As a result, the wiring resistance of the bit line BL applied to each memory cell MCa, MCb, and MCc (hereinafter referred to as bit line resistance) are different. The bit line resistance between the near memory cell Ma and the column switch SMC is "1 × Rs_x". The bit line resistance between the memory cell MCb and the column switch SWC is "x × Rs_x". The bit line resistance between the far memory cell MCc and the column switch SWC is "M × Rs_x". The bit line resistance (1 × Rs_x) between the memory cell MCa and the column switch SWC is lower than the bit line resistances x × Rs_x and M × Rs_x. The bit line resistance x × Rs_x between the memory cell MCb and the column switch SWC is higher than the wiring resistance 1 × Rs_x and lower than the wiring resistance M × Rs_x. The bit line resistance M × Rs_x between the memory cell MCc and the column switch SWC is higher than both the bit line resistance 1 × Rs_x and the bit line resistance x × Rs_x.

[0088] Thus, for multiple memory cells MC connected to a common bit line BL, the magnitude of the bit line resistance applied to a selected memory cell MC varies depending on the X coordinate of the memory cell MC.

[0089] Each global word line (GWL) is associated with a set of multiple word lines (hereinafter referred to as a word line group) WG1, WGxx, WGi. Each word line group WG1, WGxx, WGi contains a predetermined number of word lines (WL).

[0090] Global Word Line (GWL) <1> This refers to the word line WL in the region of the memory cell array 110 on the side where the column switch circuit 121-1 is located in the X direction (one end of the memory cell array 110 in the X direction). <1> It is associated with the word line group WG1, which includes the global word line GWL. <1> It is connected to multiple word lines WL within word line group WG1 via multiple low switches SWR.

[0091] Global Word Line (GWL) This refers to the word lines in the region opposite to the side of the memory cell array 110 in the X direction where the column switch circuit 121-1 is located (the other end side of the memory cell array 110 in the X direction). <m>It is associated with the word line group WGi, which includes the global word line GWL. It is connected to multiple word lines WL within word line group WGi via multiple low switches SWR.

[0092] Global Word Line (GWL) <xx>This refers to the word line WL within the region (central region) between one end and the other end of the memory cell array 110 in the X direction. <x>It is associated with the word line group WGxx, which includes the global word line GWL. <xx>It is connected to multiple word lines WL within word line group WGxxW via multiple low switches SWR.

[0093] As described above, the global word line GWL and the global bit line GBL are provided between the substrate 90 and the memory cell array 110 in the Z direction. Multiple global word lines GWL are provided within the multilayer wiring structure on the substrate 90.

[0094] Figures 8 and 9 are schematic cross-sectional views showing examples of the structure of multiple global word lines (GWLs) in the MRAM 100 of this embodiment.

[0095] Figure 8 shows the global word line GWL among several global word lines GWLs. <1> The structure is shown. Figure 9 shows the global word line GWL among several global word lines GWLs. This shows the structure.

[0096] As shown in Figures 8 and 9, the low switch SWR (field-effect transistor TR) is provided on the semiconductor substrate 90. One end of the low switch SWR is connected to the word line WL via a plurality of conductive layers M0, M1, M2, M3, a contact plug CP, and via plugs VP0, VP1, VP2, VP3. The other end of the low switch SWR is connected to one end of the global word line GWL via a plurality of conductive layers M0, M1, M2, a contact plug CP, and via plugs VP0, VP1.

[0097] The field-effect transistor TR of the global switch GXSW is provided on the semiconductor substrate 90. One end of the global switch GXSW is connected to the other end of the global word line GWL. The other end of the global switch GXSW is connected to wiring DX via a plurality of conductive layers M0, 71, a contact plug CP, and a via plug VP0. Wiring DX is connected to a write circuit 140 or a read circuit 150.

[0098] Multiple global word lines (GWLs) are located below the memory cell array 110 in the Z direction. The global word lines (GWLs) are connected between the transistor TR of the low switch SWR and the transistor TR of the global switch GXSW. For example, the global word lines (GWLs) are located within the layer (wiring level) of the conductive layer M2. As shown in Figure 8, the global word lines (GWLs) <1> It includes a conductive layer 70N. As shown in Figure 9, the global word line GWL It includes a conductive layer 70F.

[0099] For example, the cross-sectional area SGWL of the global word line GWL is larger than the cross-sectional area SWL of the word line WL and the cross-sectional area SBL of the bit line BL. Therefore, it is desirable that the resistivity of the material used for the global word line GWL is higher than that of the material used for the bit line GL. The material of the conductive layers 70N and 70F of the global word line GWL is different from the material of the conductive layers M0, M1, M2, and M3. It is desirable that the material of the conductive layers 70N and 70F is a material with relatively high resistivity. For example, the material of the conductive layers 70N and 70F is selected from tantalum (Ta), titanium (Ti), tungsten (W) oxides, tungsten nitrides, silicon (Si) oxides, and silicon nitrides. The material of the conductive layers M0, M1, M2, and M3 is, for example, copper (Cu).

[0100] To adjust the length of the global word line GWL, the positions of the low switch SWR and the global switch GXSW on the semiconductor substrate 70 can be changed as appropriate.

[0101] The width of the global word line GWL (dimension in the X direction) is greater than the width of the word line WL (dimension in the X direction).

[0102] As shown in Figures 7 to 9, the global word line GWL extends primarily in the Y direction.

[0103] Global Word Line (GWL) <1> It has a length (wiring length) of LY1. Global word wire GWL <xx>It has length LYxx. Global word line GWL It has length LYi. Length LY1 is longer than lengths LYxx,LYi. Length LYxx is shorter than length LY1 and longer than length LYi. Length LYi is shorter than lengths LY1,LYxx. For example, length LY1 is equal to the Y-direction dimension of the memory cell array 110 (the length of the set of memory cells arranged in the Y-direction).

[0104] Thus, memory cells MCa that are close to the column switch circuit 121-1 have long wiring lengths, and global word lines GWL <1> Memory cells MCc that are connected to the column switch circuit 121-1 and have a long distance from it have a short wiring length, and the global word line GWL It connects to the network.

[0105] The resistance of a wire is proportional to its length. Therefore, global word wire GWL <1> The wiring resistance is the global word wire GWL. <xx>Wiring resistance, and global word wire GWL Higher than the wiring resistance. Global word wire GWL <xx>The wiring resistance is the global word wire GWL. <1> Lower than the wiring resistance of the global word wire GWL Higher than the wiring resistance. Global word wire GWL The wiring resistance is the global word wire GWL. <1> Wiring resistance, and global word wire GWL <xx>It is lower than the wiring resistance.

[0106] When the resistance value per unit length of the global word wire GWL is indicated by "RGWL", the global word wire GWL <1> The wiring resistance is "LY1×RGWL", and the global word wire GWL <xx>The wiring resistance is "LYxx×RGWL", and the global word wire GWL The wiring resistance is "LYi×RGWL".

[0107] For example, the difference between the bit line resistance of memory cell MCa and the bit line resistance of memory cell MCc is "(M-1) × Rs_x". Also, global word line GWL <1> Resistance value and global word wire GWL The difference in resistance is "(LY1-LYi)×RGWL".

[0108] When offsetting the difference in bit line resistance, it is desirable that the magnitude of (LY1-LYi)×RGWL is close to the magnitude of (M-1)×Rs_x. If the magnitude of (LY1-LYi)×RGWL is equal to the magnitude of (M-1)×Rs_x, the effect of the difference in bit line resistance becomes virtually zero.

[0109] If the unit length Ly of the global word line GWL is the same as the pitch between memory cells MC, then it is desirable that "N × RGWL × Ly" is equal to "M × Rs_x". If N is equal to M, then the resistivity of the unit length of the global word line GWL may be equal to the resistivity of the unit length of the bit line.

[0110] As described above, the difference in bit line resistance corresponding to the X-coordinate of the memory cell MC is reduced by the difference in wiring resistance of the global word line GWL.

[0111] Figure 10 is a plan view showing an example of the configuration of the global bit line GBL in the MRAM 100 of this embodiment.

[0112] In the MRAM 100, the column control circuit 120 includes a column switch circuit 121-1. The column switch circuit 121-1 is located on one end of the memory cell array 110 in the X direction. Hereinafter, within the memory cell array 110, the region closer to the column switch circuit 121-1 will be called the near region (near side), and the region further from the column switch circuit 121-1 will be called the far region (far side).

[0113] The column switch circuit 121-1 is connected to multiple bit lines BL. The column switch circuit 121-1 is connected to multiple global bit lines GBL (GBL <1> GBL <yy>,GBL <j>Each global bit line GBL is connected to the write circuit 140 and the read circuit 150.

[0114] The column switch circuit 121-1 includes a plurality of column switches SWC. A column switch SWC is, for example, a field-effect transistor TR. One end of each column switch SWC is electrically connected to a corresponding bit line BL from a plurality of bit lines BL. The other end of each column switch SWC is electrically connected to a corresponding global bit line GBL from a plurality of global bit lines GBL.

[0115] In the column switch circuit 121-1, each column switch SWC is set to either the ON state or the OFF state according to the supplied address ADR. Depending on the ON / OFF state of the multiple column switches SWC in the column switch circuit 121-1, one bit line BL is electrically connected to the corresponding global bit line GBL via the ON state column switch SWC.

[0116] The distance between the memory cell MC and the low switch SWR changes depending on the Y-coordinate (column) of the memory cell MC within the memory cell array 110.

[0117] As a result, during the operation of the MRAM 100, the magnitude of the wiring resistance of the word line WL applied to the memory cell MC within the memory cell array 110 changes depending on the Y-coordinate of the memory cell MC.

[0118] In this embodiment, the multiple global bit lines GBL have different lengths from each other. This allows the MRAM 100 in this embodiment to mitigate the effects caused by differences in the wiring resistance of the word lines WL due to the coordinates of the memory cells MC.

[0119] As shown in Figure 10, a word line WL <x>Multiple memory cells, MCd, MCe, and MCf, are connected to it.

[0120] Memory cell MCd is bit line BL <1> It is connected to the bit line BL. <y>It is connected to the bit line BL. The memory cell MCf is connected to the bit line BL. <n>It connects to the network.

[0121] The X-coordinates (rows) of memory cells MCd, MCe, and MCf are the same. Therefore, the bit line resistance applied to each memory cell MCd, MCe, and MCf is the same (x × Rs_x).

[0122] The Y-coordinates of memory cells MCd, MCe, and MCf are different. Therefore, the distances between each of the memory cells MCd, MCe, and MCf and the row switch circuit 131 (row switch SWR) are different. As a result, the word line resistance applied to each memory cell MCd, MCe, and MCf is different. The word line resistance between the near memory cell MCd and the row switch SWR is "1 × Rs_y". The word line resistance between the memory cell MCe and the row switch SWR is "y × Rs_y". The word line resistance between the far memory cell MCf and the row switch SWR is "N × Rs_y". The word line resistance 1 × Rs_y between the memory cell MCd and the row switch SWR is lower than the word line resistances y × Rs_y and N × Rs_y. The word line resistance y × Rs_y between the memory cell MCe and the row switch SWR is higher than the word line resistance 1 × Rs_y and lower than the word line resistance N × Rs_y. The word line resistance N×Rs_y between the memory cell MCf and the low switch SWR is higher than the word line resistance 1×Rs_y and the word line resistance N×Rs_y.

[0123] Thus, for multiple memory cells MC connected to a common word line WL, the magnitude of the word line resistance applied to a selected memory cell MC varies depending on the Y coordinate of the memory cell MC.

[0124] Furthermore, it is desirable that the resistivity (Ω / nm) per unit length of the global word line GWL be approximately the same as the resistivity (Ω / nm) per unit length of the bit line BL.

[0125] As shown in Figure 10, each global bit line GBL is associated with a set of multiple bit lines (hereinafter referred to as a bit line group) BG1, BGyy, BGj. Each bit line group BG1, BGyy, BGj contains a predetermined number of bit lines BL.

[0126] Global Bit Line (GBL) <1> This is associated with bit line group BG1, which includes bit line BL1 in the region of the memory cell array 110 in the Y direction, on the side where the low switch circuit 131-1 is located (one end of the memory cell array 110 in the Y direction). <1> It is connected to multiple bit lines BL within bit line group BG1 via each of the multiple column switches SWC.

[0127] Global Bit Line (GBL) <j>This refers to the bit line BL in the region opposite to the side of the memory cell array 110 in the Y direction where the low switch circuit 131-1 is located (the other end side in the Y direction of the memory cell array 110). <n>It is associated with the bit line group BGj, which includes the global bit line GBL. <j>It is connected to multiple bit lines BL within bit line group BGj via each of the multiple column switches SWC.

[0128] Global Bit Line (GBL) <yy>This refers to the bit line BL in the region (central region) between one end and the other end of the memory cell array 110 in the Y direction. <y>It is associated with the bit line group BGyy, which includes the global bit line GBL. <yy>It is connected to multiple word lines WL within bit line group BGyy via each of the multiple column switches SWC.

[0129] As described above, the global bit line GBL is provided between the substrate 90 and the memory cell array 110 in the Z direction. Multiple global bit line GBLs are provided within the multilayer wiring structure on the substrate 90.

[0130] Figures 11 and 12 are schematic cross-sectional views showing examples of the structure of multiple global bit lines (GBLs) in the MRAM 100 of this embodiment.

[0131] Figure 11 shows the global bit line GBLs among multiple global bit line GBLs. <1> This shows the structure. Figure 12 shows the global bit line GBL among multiple global bit line GBLs. <j>This shows the structure.

[0132] As shown in Figures 11 and 12, the column switch SWC (field-effect transistor TR) is provided on the semiconductor substrate 90. One end of the column switch SWC is connected to the bit line BL via a plurality of conductive layers M0, M1, M2, M3, a contact plug CP, and via plugs VP0, VP1, VP2, VP3, VPA. The other end of the column switch SWC is connected to one end of the global bit line GBL via a plurality of conductive layers M0, M1, M2, a contact plug CP, and via plugs VP0, VP1.

[0133] The field-effect transistor TR of the global switch GYSW is provided on the semiconductor substrate 90. One end of the global switch GYSW is connected to the other end of the global bit line GBL. The other end of the current path of the global switch GYSW is connected to wiring DY via a plurality of conductive layers M0, 73, a contact plug CP, and a via plug VP0. Wiring DY is connected to the write circuit 140 or the read circuit 150.

[0134] Multiple global bit lines (GBLs) are located below the memory cell array 110 in the Z direction. The global bit lines (GBLs) are connected between the transistor TR of the column switch SWC and the transistor TR of the global switch GYSW. In the multilayer wiring structure, the layer in which the global bit lines (GBLs) are located is different from the layer in which the global word lines (GWLs) are located. For example, the global bit lines (GBLs) are located within the conductive layer M3. The layer in which the global bit lines (GBLs) are located may be a lower layer than the layer in which the global word lines (GWLs) are located (for example, the conductive layer M0 or the conductive layer M1). The layer in which the global bit lines (GBLs) are located may be the same as the layer in which the global word lines (GWLs) are located.

[0135] As shown in Figure 11, the global bit line GBL <1> This includes a conductive layer 72N. As shown in Figure 12, the global bit line GBL <j>It includes a conductive layer 72F.

[0136] For example, the cross-sectional area SGBL of the global bit line GBL is larger than the cross-sectional area SWL of the word line WL and the cross-sectional area SBL of the bit line BL. Therefore, it is desirable that the resistivity of the material used for the global bit line GBL is higher than that of the material used for the bit line BL. It is desirable that the material of the conductive layers 72N and 72F be a material with relatively high resistivity. For example, the material of the conductive layers 72N and 72F is selected from one of the following: tantalum (Ta), titanium (Ti), tungsten (W) oxides, tungsten nitrides, silicon (Si) oxides, and silicon nitrides.

[0137] To adjust the length of the global bit line GBL, the positions of the column switch SWC and the global switch GYSW on the semiconductor substrate 70 can be changed as appropriate.

[0138] The width of the global bit line GBL (dimension in the Y direction) is greater than the width of the bit line BL (dimension in the Y direction).

[0139] As shown in Figures 10 to 12, the global bit line GBL extends primarily in the X direction.

[0140] Global Bit Line (GBL) <1> It has a length (wiring length) LX1. Global bit wire GBL <yy>It has a length LXyy. Global bit line GBL <j>It has length LYj. Length LX1 is longer than lengths LXyy and LXj. Length LXyy is shorter than length LX1 and longer than length LXj. Length LXj is shorter than lengths LX1 and LXyy.

[0141] Thus, memory cells MCd that are close to the low switch circuit 131-1 have long wiring lengths on the global bit lines GBL. <1> The memory cell MCf, which is connected to the low switch circuit 131-1 and has a long distance from it, has a global bit line GBL with a short wiring length. <j>It connects to the network.

[0142] Global Bit Line (GBL) <1> The wiring resistance is the global bit wire GBL <yy>Wiring resistance, and global bit wire GBL <j>Higher than the wiring resistance. Global bit wire GBL <yy>The wiring resistance is the global bit wire GBL <1> Lower than the wiring resistance of the global bit wire GBL <j>Higher than the wiring resistance. Global bit wire GBL <j>The wiring resistance is the global bit wire GBL <1> Wiring resistance, and global bit wire GBL <yy>It is lower than the wiring resistance.

[0143] When the resistance value per unit length of a global bit line GBL is indicated by "RGBL", the global bit line GBL <1> The wiring resistance is "LX1×RGBL", and the global bit line GBL <yy>The wiring resistance is "LXyy × RGBL", and the global bit line GBL The wiring resistance is "LXj × RGBL".

[0144] For example, the difference between the word line resistance of memory cell MCd and the word line resistance of memory cell MCf is "(N-1) × Rs_y". Also, global bit line GBL <1> Resistance value and global bit line GBL <j>The difference in resistance is "(LX1-LXj)×RGBL".

[0145] When offsetting the difference in word line resistance, it is desirable that the magnitude of (LX1-LXj)×RGBL is close to the magnitude of (N-1)×Rs_y. If the magnitude of (LX1-LXj)×RGBL is equal to the magnitude of (N-1)×Rs_y, the effect of the difference in bit line resistance becomes virtually zero.

[0146] If the unit length Lx of the global bit line GBL is the same as the pitch between memory cells MC, then it is desirable that "M × RGBL × Lx" is equal to "N × Rs_y". If N is equal to M, then the resistivity of the unit length of the global bit line GBL may be equal to the resistivity of the unit length of the word line WL.

[0147] As described above, the difference in word line resistance corresponding to the Y-coordinate of the memory cell MC is reduced by the difference in wiring resistance of the global bit line GBL.

[0148] (b) Example of operation An example of the operation of the MRAM100 in this embodiment will be described.

[0149] In this embodiment, the MRAM 100 receives a command CMD, an address ADR, and various control signals CNT from an external device 900. If the command CMD to be executed is a write operation, the MRAM 100 further receives write data DT from the external device 900.

[0150] MRAM100 initiates the commanded operation (write operation or read operation) based on the command CMD, address ADR, and various control signals CNT.

[0151] The control circuit 180 performs various controls according to the operation to be executed based on the command CMD and various control signals CNT. The control circuit 180 decodes the address ADR.

[0152] The column control circuit 120 and the row control circuit 130 activate the column switch circuit 121-1 and the row switch circuit 131-1 based on the decoding result of the address ADR.

[0153] The activated column switch circuit 121-1 and the activated row switch circuit 131-1 access the memory cell (selection cell) MC indicated by address ADR. The voltage and current used for the operation to be performed are supplied to the selection cell MC via the global bit line GBL, bit line BL, global word line GWL, and word line WL.

[0154] The low switch SWR connected to the selected word line WL, and the column switch SWC connected to the selected bit line BL, are turned ON.

[0155] Word line WL <1> and bit line BL <1> When operating on memory cells MCs in the vicinity of the row switch circuit 131-1 and the column switch circuit 121-1, such as memory cells MC connected to the row switch circuit 131-1, the word line resistance and bit line resistance applied to the memory cells MC are relatively small.

[0156] In this embodiment, as shown in Figures 7 and 10, the global word line GWL has a long wiring length LY1. <1> However, via the low switch SWR, the selected word line WL (for example, word line WL) <1> Global bit wire GBL with long wiring length LX1 is connected to (). <1> However, via the column switch SWC, the selected bit line BL (for example, bit line BL) <1> It connects to ).

[0157] Word line WL <m>and bit line BL <n>When operating on a memory cell MC that is far from the row switch circuit 131-1 and the column switch circuit 121-1, such as a memory cell MC connected to the row switch circuit 131-1, the word line resistance and bit line resistance applied to the memory cell MC are relatively large.

[0158] In this embodiment, as shown in Figures 7 and 10, the global word line GWL has a short wiring length LYi. However, via the low switch SWR, the selected word line WL (for example, word line WL) <m>Global bit wire GBL, which is connected to a short wiring length LYj. <j>However, via the column switch SWC, the selected bit line BL (for example, bit line BL) <n>It connects to ).

[0159] Thus, the MRAM 100 of this embodiment connects one of a plurality of global word lines GWL having different wiring lengths LY and one of a global bit line GBL having a different wiring length LX to the memory cell to be operated on, depending on the magnitude of the word line resistance and bit line resistance applied to the memory cell in the memory cell array 110.

[0160] As a result, in the MRAM 100 of this embodiment, the difference in wiring resistance corresponding to the coordinate of the memory cell MC is reduced.

[0161] (c) Summary In a memory cell array with a crosspoint structure, the magnitude of the wiring resistance applied to a memory cell varies depending on the coordinate of the memory cell. Due to differences in the wiring resistance of memory cells, the read margin of multiple memory cells in the memory cell array may deteriorate.

[0162] The MRAM 100 of this embodiment includes a plurality of global word lines GWL having different wiring lengths LY, and a plurality of global bit lines GBL having different wiring lengths LX.

[0163] Depending on the coordinates of the memory cell MC, the global word line GWL and the global bit line GBL connected to the memory cell MC will differ.

[0164] If a memory cell MC at a coordinate close to the low switch circuit 131-1 is selected, the selected memory cell MC is connected to the global bit line GBL with a long wiring length LX1 via the bit line BL. <1> It is connected to the global bit line GBL with a short wiring length LXj via the bit line BL. If a memory cell MC at a coordinate far from the low switch circuit 131-1 is selected, the selected memory cell MC is connected to the global bit line GBL with a short wiring length LXj via the bit line BL. <j>It connects to the network.

[0165] If a memory cell MC with coordinates close to the column switch circuit 121-1 is selected, the selected memory cell MC is connected to the global word line GWL with a long wiring length LY1 via the word line WL. <1> It is connected to the global word line WL with a short wiring length LYi when a memory cell MC at a coordinate far from the column switch circuit 121-1 is selected. It connects to the network.

[0166] As a result, the MRAM 100 of this embodiment can reduce the difference in wiring resistance applied to the memory cell MC due to the coordinates of the memory cell MC.

[0167] As a result, the MRAM 100 of this embodiment can suppress the degradation of the read margin.

[0168] As described above, the memory device 100 of this embodiment can improve the reliability of the operation of the memory cell MC.

[0169] (2) Second embodiment A memory device of the second embodiment will be described with reference to Figures 13 and 14.

[0170] Figures 13 and 14 are plan views showing examples of the structure of global wiring GWL and GBL in the memory device (MRAM) 100 of this embodiment.

[0171] As shown in Figures 13 and 14, each of the multiple global wirings GWL and GBL may have different widths WX (WX1, WXxx, WXi) and WY (WY1, WYyy, WYj) in addition to wiring lengths LY and LX.

[0172] As shown in Figure 13, the global word line GWL <1> It has a width (wiring width) WX1 in the X direction. Global word line GWL <xx>It has a wiring width WXxx in the X direction. Global word line GWL The wiring has a wiring width WXi in the X direction. Each of the wiring widths WX1, WXxx, and WXi is different from the others.

[0173] Wiring width WX1 is smaller than wiring widths WXxx and WXj. Wiring width WXxx is smaller than wiring width WXj and larger than wiring width WX1. Wiring width WXj is larger than wiring widths WX1 and WXxx.

[0174] The wiring resistance of the global word wire GWL changes depending on the wiring width WX. If the wiring thickness and length remain unchanged, the wiring resistance of the global word wire GWL decreases as the wiring width WX increases.

[0175] This allows the global word line GWL The wiring resistance is the global word wire GWL. <1> This becomes even smaller than the wiring resistance.

[0176] As shown in Figure 14, Global Bit Line GBL <1> It has a wiring width WY1 in the Y direction. Global bit line GBL <yy>It has a wiring width WYyy in the Y direction. Global bit line GBL <j>The wiring has a wiring width WYj in the Y direction. Each of the wiring widths WY1, WYyy, and WYj is different from the others.

[0177] Wiring width WY1 is smaller than wiring widths WYyy and WYj. Wiring width WYyy is smaller than wiring width WYj and larger than wiring width WY1. Wiring width WYj is larger than wiring widths WY1 and WYyy.

[0178] The wiring resistance of the global bit line GBL changes depending on the wiring width WY. If the wiring thickness and length remain unchanged, the resistance of the global bit line GBL decreases as the wiring width WY increases.

[0179] This allows for global bit lines (GBL) <j>The wiring resistance is even lower than that of the global bit line GBL.

[0180] Here, the resistivity of the global word line GWL is denoted by "ρGWL", and the resistivity of the bit line BL is denoted by "ρBL". <1> The cross-sectional area is indicated by "SGWL1", and the global word line GWL The cross-sectional area is denoted by "SGWLi". The unit length of the bit wire BL is denoted by "Lb".

[0181] Bit Line BL <y>and word line WL <1> The bit line resistor and bit line BL of the memory cell MCa connected to it. <y>and word line WL <m>The difference between the bit line resistance of the connected memory cell MCc and the bit line resistance is given by the following equation (f1).

[0182] (M-1)×ρBL×Lb / SBL ···(f1)

[0183] Global Word Line (GWL) <1> Wiring resistance and global word wire GWL The difference from the wiring resistance is given by the following equation (f2).

[0184] ρGWL×LY1 / SGWL1-ρGWL×LYi / SGWLi ···(f2)

[0185] As described above, by having a value in equation (f2) that approximates the value in equation (f1), the difference between the bit line resistance of the memory cell MCa and the bit line resistance of the memory cell MCc is reduced.

[0186] It is desirable that the following equation (f3) be satisfied in order to reduce the effect of differences in bit line resistance within the memory cell array 110.

[0187] ρGWL×LY1 / SGWL1-ρGWL×LYi / SGWLi =(M-1)×ρBL×Lb / SBL ···(f3)

[0188] Furthermore, the resistivity of the global bit line GBL is denoted as "ρGBL", and the resistivity of the word line WL is denoted as "ρWL". <1> The cross-sectional area is shown in SGBL1, and the global bit line GBL <j>The cross-sectional area is denoted by SGBLj. The unit length of the word line WL is denoted by "Lw".

[0189] Word line WL <x>and bit line BL <1> Word line resistor and word line WL of memory cell MCD connected to it <x>and bit line BL <n>The difference between the word line resistance of the connected memory cell MCf and the following equation (f4) is given by:

[0190] (N-1)×ρWL×Lw / SWL ···(f4)

[0191] Global Bit Line (GBL) <1> Wiring resistance and global bit wire GBL <j>The difference from the wiring resistance is given by the following equation (f5).

[0192] ρGBL×LX1 / SGBL1-ρGBL×LXj / SGBLj ···(f5)

[0193] As described above, by having a value in equation (f5) that approximates the value in equation (f4), the difference between the word line resistance of memory cell MCd and the word line resistance of memory cell MCf is reduced.

[0194] It is desirable that the following equation (f6) be satisfied in order to reduce the effect of differences in word line resistance within the memory cell array 110.

[0195] ρGBL×LX1 / SGBL1-ρGBL×LXj / SGBLj =(N-1)×ρWL×Lw / SWL ···(f6)

[0196] In general, in semiconductor processes, it is difficult to vary the film thickness of conductive layers (wirings) within the same layer for each conductive layer. Therefore, as in this embodiment, it is effective to change the resistance value of global wiring GWL and GBL by controlling the wiring width of global wiring GWL and GBL. However, the film thickness of global word lines GWL may be varied for each global word line GWL. Similarly, the film thickness of global bit lines GBL may be varied for each global bit line GBL.

[0197] As described above, in this embodiment, the wiring resistance of the global wiring is controlled by the wiring width in addition to the wiring length. For example, the length of the global wiring GWL,GBL may be limited depending on the chip layout and the size of the memory cell array.

[0198] Therefore, the MRAM 100 of this embodiment can flexibly accommodate constraints on the layout within the chip.

[0199] As described above, the memory device 100 of this embodiment can obtain the same effects as the embodiment described above.

[0200] (3) Third Embodiment A memory device of the second embodiment will be described with reference to Figures 15 and 16.

[0201] Figures 15 and 16 are plan views showing examples of the structure of global wiring GWL and GBL in the memory device (MRAM) 100 of this embodiment.

[0202] As shown in Figures 15 and 16, the MRAM 100 may include two column switch circuits 121-1, 121-2 and two row switch circuits 131-1, 131-2.

[0203] One column switch circuit 121-1 is located on one end of the memory cell array 110 in the X direction. The other column switch circuit 121-2 is located on the other end of the memory cell array 110 in the X direction.

[0204] When the memory cell array 110 is positioned between two column switch circuits 121-1 and 121-2, the regions on one end and the other end of the memory cell array 110 in the X direction become the near region relative to the column switch circuit 121, and the central region of the memory cell array 110 becomes the far region relative to the column switch circuit 121.

[0205] For example, when operating on a memory cell MC, one of the two column switch circuits 121-1 and 121-2, the one closer to the selected memory cell MC, column switch circuit 121, is activated.

[0206] In this case, as shown in Figure 15, the global word line GWL corresponds to the central word line group WGxx in the X direction of the memory cell array 110. <xx>The wiring length LYxx corresponds to the global word line GWL, which is the word line group WG1 on one end of the memory cell array 110 in the X direction. <1> The wiring length LY1 and the global word line GWL corresponding to the word line group WGi on the other end of the memory cell array 110 in the X direction. The wiring length is shorter than LY1. For example, the global word wire GWL. The wiring length LY1 is the global word wire GWL. <1> The wiring length is equal to LY1.

[0207] Furthermore, Global Word Line (GWL) <xx>The wiring width is the global word wire GWL. <1> GWL The wiring width may differ. For example, the global word wire GWL. <xx>The wiring width is the global word wire GWL. <1> GWL It is wider than the wiring width.

[0208] One row switch circuit 131-1 is located at one end of the memory cell array 110 in the Y direction. The other row switch circuit 131-2 is located at the other end of the memory cell array 110 in the Y direction.

[0209] For example, when operating on a memory cell MC, one of the two column switch circuits 121-1 and 121-2, the one closer to the selected memory cell MC, column switch circuit 121, is activated.

[0210] When the memory cell array 110 is positioned between two row switch circuits 131-1 and 131-2, the regions on one end and the other end of the memory cell array 110 in the Y direction become the near region relative to the row switch circuit 131, and the central region of the memory cell array 110 becomes the far region relative to the row switch circuit 131.

[0211] In this case, as shown in Figure 16, the global bit line GBL corresponds to the central bit line group BGyy in the Y direction of the memory cell array 110. <yy>The wiring length LXyy corresponds to the global bit line GBL, which is the bit line group BG1 on one end of the memory cell array 110 in the X direction. <1> The wiring length LX1 and the global bit line GBL corresponding to the bit line group BGj on the other end of the X direction of the current charge array 110. <j>The wiring length is shorter than LX1. For example, global bit wire GBL <j>The wiring length LY1 is the global bit line GBL <1> The wiring length is equal to LY1.

[0212] Furthermore, global bit line GBL <yy>The wiring width is global bit wire GBL <1> GBL <j>The wiring width may differ. For example, global bit wire GBL <yy>The wiring width is global bit wire GBL <1> GBL <j>It is wider than the wiring width.

[0213] Even in this embodiment, where the MRAM 100 has a configuration in which switch circuits 121 and 131 are provided at both ends of the memory cell array 110, the selected memory cell MC can be connected to a corresponding global word line GWL of different wiring lengths LY and a corresponding global bit line GBL of different wiring lengths LX, depending on the coordinate of the memory cell MC.

[0214] Therefore, the memory device 100 of this embodiment can achieve substantially the same effects as the memory device of the above-described embodiment.

[0215] (4) Variations A modified example of the memory device of the embodiment will be described with reference to Figures 17 and 18.

[0216] Figures 17 and 18 are plan views showing the planar shape of the global wiring (global bit line or global word line) GL in a modified example of the memory device of the embodiment.

[0217] As shown in Figure 17, with respect to global bit lines GBL or global word lines GWL, global wiring GL having high wiring resistance (long wiring length) may have a meandering planar shape when viewed from a direction perpendicular to the semiconductor substrate 90 (Z direction).

[0218] The global wiring GL includes a plurality of portions 74 extending in direction A (direction X or Y) and a plurality of portions 75 extending in direction B (direction Y or X) intersecting direction A. The portions 74 and 75 are arranged alternately in direction A.

[0219] This increases the effective length of the global wiring (GL).

[0220] As shown in Figure 18, the global wiring GL having a high resistance may have a folded shape when viewed from the Z direction.

[0221] The global wiring GL includes two portions 76 extending in direction A and a portion 77 extending in direction B.

[0222] Part 77 connects one part 76 to the other part 76 at one end of the two parts 76 in direction A.

[0223] This increases the effective length of the global wiring (GL).

[0224] As a result of Figures 17 and 18, the resistance of the global wiring GL increases.

[0225] In this way, by controlling the planar shape of the global wiring GL, the resistance values ​​of multiple global wiring GLs may be adjusted.

[0226] The memory device 100 of this modified example can achieve substantially the same effects as the memory device of the embodiment described above.

[0227] (5) Others In the above-described embodiment, MRAM is exemplified as the memory device 100 of this embodiment. However, the memory device 100 of this embodiment may be a memory device other than MRAM.

[0228] For example, the memory device 100 of this embodiment may be a memory device using a transition metal oxide element having variable resistance characteristics as a memory element (for example, a resistive random access memory such as ReRAM (Resistive Random Access Memory)), a memory device using a phase change element as a memory element (for example, a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a memory device using a ferroelectric element as a memory element (for example, a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)).

[0229] Even if the memory device 100 in this embodiment is a memory device other than MRAM, the effects described in the above-described embodiment can be obtained.

[0230] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0231] 100: Memory device, 110: Memory cell array, 120: Column control circuit, 121-1, 121-2: Column switch circuit, 130: Row control circuit, 131-1, 131-2: Row switch circuit, MC, MCa: Memory cell, 1: Memory element, 2: Switching element.< / j> < / yy> < / j> < / yy> < / j> < / j> < / yy> < / xx> < / xx> < / xx> < / j> < / n> < / x> < / x> < / j> < / m> < / y> < / y> < / j> < / j> < / yy> < / xx> < / j> < / n> < / j> < / m> < / n> < / m> < / j> < / yy> < / yy> < / j> < / j> < / yy> < / j> < / yy> < / j> < / j> < / yy> < / j> < / j> < / yy> < / y> < / yy> < / j> < / n> < / j> < / n> < / y> < / x> < / j> < / yy> < / xx> < / xx> < / xx> < / xx> < / xx> < / xx> < / x> < / xx> < / m> < / m> < / x> < / y> < / xx> < / y> < / x> < / n> < / y> < / m> < / x> < / m> < / n>

Claims

1. A memory cell array comprising: a first local wiring extending in a first direction; a second local wiring extending in a second direction intersecting the first direction; a third local wiring extending in the second direction; a first memory cell provided between the first local wiring and the second local wiring; and a second memory cell provided between the first local wiring and the third local wiring. A first switch circuit connected to the first local wiring and provided on one end of the memory cell array in the first direction, A second switch circuit connected to the second and third local wirings and provided on one end of the memory cell array in the second direction, A first circuit that performs a write operation or read operation of the memory cell array, The first and second global wirings connected between the second switch circuit and the first circuit, It is equipped with, The second local wiring is positioned between the first switch circuit and the third local wiring in the first direction. The second local wiring is connected to the first global wiring via the second switch circuit. The third local wiring is connected to the second global wiring via the second switch circuit. The length of the second global wiring is shorter than the length of the first global wiring. Memory device.

2. The length of the first local wiring between the second memory cell and the first switch circuit is longer than the length of the first local wiring between the first memory cell and the first switch circuit. The memory device according to claim 1.

3. The system further comprises a third global wiring connected between the second switch circuit and the first circuit, The memory cell array is A fourth local wiring extending in the second direction and provided between the second local wiring and the third local wiring in the first direction, A third memory cell is provided between the first local wiring and the fourth local wiring, Includes, The fourth local wiring is connected to the third global wiring via the second switch circuit. The length of the third global wiring is shorter than the length of the first global wiring and longer than the length of the second global wiring. The memory device according to claim 1.

4. The width of the second global wiring is greater than the width of the first global wiring. The memory device according to claim 1.

5. Fourth and fifth global wirings connected between the first switch circuit and the first circuit, Furthermore, it is equipped with, The memory cell array is A fifth local wiring extending in the first direction and positioned between the first local wiring and the second switch circuit in the second direction, A fourth memory cell is provided between the second local wiring and the fifth local wiring, It further includes, The first local wiring is connected to the fourth global wiring via the first switch circuit. The fifth local wiring is connected to the fifth global wiring via the first switch circuit. The length of the fourth global wiring is shorter than the length of the fifth global wiring. The memory device according to claim 1.

6. The memory cell array is provided above the substrate, The first and second global wirings are provided between the memory cell array and the substrate in a third direction perpendicular to the surface of the substrate. The memory device according to claim 1.

7. The first local wiring is the first bit line, The second local wiring is the first word line, The third local wiring is the second word line, The first switch circuit is a low switch circuit, The first global wiring is the first global word line, The aforementioned second global wiring is the second global word line, The memory device according to claim 1.

8. The first local wiring is the first word line, The second local wiring is the first bit line, The third local wiring is the second bit line, The first switch circuit described above is a column switch circuit, The first global wiring is the first global bit line, The aforementioned second global wiring is a second global bit line, The memory device according to claim 1.

9. The resistivity of the first and second global wirings is higher than the resistivity of the first to third local wirings. The memory device according to claim 1.

10. The first and second global wirings have the following relationship with respect to the first local wiring: ρGWL×LY1 / SGWL1-ρGWL×LYi / SGWLi =(M-1)×ρBL×Lb / SBL...(f0) Here, ρGWL corresponds to the resistivity of the first and second global wirings, LY1 corresponds to the wiring length of the first global wiring, LYi corresponds to the wiring length of the second global wiring, SGWL1 corresponds to the cross-sectional area of ​​the first global wiring, SGWLi corresponds to the cross-sectional area of ​​the second global wiring, M corresponds to the number of pitches in the first direction within the memory cell array, ρBL corresponds to the resistivity of the first local wiring, Lb corresponds to the unit length of the first local wiring, and SBL corresponds to the cross-sectional area of ​​the first local wiring. The memory device according to claim 1.

11. A memory cell array comprising: a first local wiring extending in a first direction; a second local wiring extending in a second direction intersecting the first direction; a third local wiring extending in the second direction; a fourth local wiring extending in the second direction; a first memory cell provided between the first local wiring and the second local wiring; a second memory cell provided between the first local wiring and the third local wiring; and a third memory cell provided between the first local wiring and the fourth local wiring; A first switch circuit connected to the first local wiring and provided on one end of the memory cell array in the first direction, A second switch circuit connected to the first local wiring and provided on the other end side in the first direction of the memory cell array, A third switch circuit connected to the second, third, and fourth local wirings and provided on one end of the memory cell array in the second direction, A fourth switch circuit connected to the second, third, and fourth local wirings and provided on the other end side in the second direction of the memory cell array, A first circuit that performs a write operation or read operation of the memory cell array, The first, second, and third global wirings connected between the third switch circuit and the first circuit, It is equipped with, The fourth local wiring is positioned between the second local wiring and the third local wiring in the first direction. The first global wiring is connected to the second local wiring via at least one of the third and fourth switch circuits. The second global wiring is connected to the third local wiring via at least one of the third and fourth switch circuits. The third global wiring is connected to the fourth local wiring via at least one of the third and fourth switch circuits. The length of the third global wiring is shorter than the length of the first global wiring and the length of the second global wiring. Memory device.

12. The length of the first global wiring is equal to the length of the second global wiring. The memory device according to claim 11.

13. The length of the first local wiring between the second memory cell and the first switch circuit is longer than the length of the first local wiring between the first memory cell and the first switch circuit. The memory device according to claim 11.

14. The width of the third global wiring is greater than the width of the first global wiring. The memory device according to claim 11.

15. Fourth and fifth global wirings connected between the first switch circuit and the first circuit, Furthermore, it is equipped with, The memory cell array is A fifth local wiring extending in the first direction and positioned between the first local wiring and the third switch circuit in the second direction, A fourth memory cell is provided between the second local wiring and the fifth local wiring, It further includes, The first local wiring is connected to the fourth global wiring via the first switch circuit. The fifth local wiring is connected to the fifth global wiring via the first switch circuit. The length of the fourth global wiring is shorter than the length of the fifth global wiring. The memory device according to claim 11.

16. The memory cell array is provided above the substrate, The first and second global wirings are provided between the memory cell array and the substrate in a third direction perpendicular to the surface of the substrate. The memory device according to claim 11.

17. The first local wiring is the first bit line, The second local wiring is the first word line, The third local wiring is the second word line, The fourth local wiring is the third word line, The first switch circuit is a first low switch circuit, The aforementioned second switch circuit is a second low switch circuit, The third switch circuit is the first column switch circuit, The fourth switch circuit is a second column switch circuit, The first global wiring is the first global word line, The aforementioned second global wiring is the second global word line, The third global wiring is the third global word line. The memory device according to claim 11.

18. The first local wiring is the first word line, The second local wiring is the first bit line, The third local wiring is the second bit line, The fourth local wiring is the third bit line, The first switch circuit is a first column switch circuit, The aforementioned second switch circuit is a second column switch circuit, The third switch circuit is the first low switch circuit, The fourth switch circuit is a second low switch circuit, The first global wiring is the first global bit line, The aforementioned second global wiring is a second global bit line, The third global wiring is the third global bit line. The memory device according to claim 11.

19. The resistivity of the first to third global wiring is higher than the resistivity of the first to third local wiring. The memory device according to claim 11.

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