Address routing reduction strategies for non-volatile memory decoders

Abstract

To program an MRAM memory cell, a bipolar decoder is provided that supplies current (when the line is driven positively) and sinks current (when the line is drawn negatively), taking into account the bipolar nature of the memory cell, in order to pass current from the corresponding bit line of the memory cell to the corresponding word line or from the word line to the bit line. [Solution] In a non-volatile memory device, the bipolar decoder uses an NMOS device for the negative selector switch and a PMOS switch for the positive selector switch. To reduce layout area and routing, the negative and positive selector switches are grouped separately such that a subset of positive selector switches is located between a subset of negative selector switches, and vice versa. Connections for the decoder switches are routed to a central hookup area for connection to the control lines of the crosspoint array.

Description

[Technical Field]

[0001] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory can store and retain information even when not connected to a power source (e.g., a battery).

[0002] An example of non-volatile memory is magnetoresistive random-access memory (MRAM), which uses magnetization to represent stored data, in contrast to some other memory technologies that use electric charge to store data. Generally, MRAM consists of a number of magnetic memory cells formed on a semiconductor substrate, each memory cell representing (at least) one bit of data. Bits of data are written to the memory cell by changing the direction of magnetization of the magnetic elements within the memory cell, and bits are read out by measuring the resistance of the memory cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). As used herein, the direction of magnetization is the direction in which the magnetic moment is oriented.

[0003] Some non-volatile memory arrays are arranged in a crosspoint configuration where word lines extend perpendicularly to bit lines, and memory cells are formed at their intersections. Some crosspoint memory arrays have two or more stories or levels of memory cells.

[0004] Read / write circuits may be used to read data from and write data to non-volatile memory cells. Data may be read by sensing current or voltage at a sensing node while current flows through a selected memory cell. Sensing amplifiers may be provided to perform sensing. Sensing amplifiers and / or other read / write circuits may occupy a considerable area on the memory die. Efficient design may reduce the area occupied by sensing amplifiers and / or other circuits. [Brief explanation of the drawing]

[0005] Elements with similar numbering refer to common components in different drawings. [Figure 1] This is a block diagram of one embodiment of a memory system connected to a host. [Figure 2] This is a block diagram of one embodiment of a memory package. [Figure 3] This is a block diagram of one embodiment of a memory die. [Figure 4] This is a block diagram of one embodiment of an integrated memory assembly. [Figure 5] An example of a sense amplifier is shown. [Figure 6] An example of a memory access operation (read operation) is shown. [Figure 7A] A perspective view shows one embodiment of a memory array that forms a crosspoint architecture. [Figure 7B] Figure 7A shows a side view and a top view of the cross point structure, respectively. [Figure 7C] Figure 7A shows a side view and a top view of the cross point structure, respectively. [Figure 7D] A perspective view shows one embodiment of a two-level memory array that forms a crosspoint architecture. [Figure 8] This shows one embodiment of the structure of an MRAM memory cell. [Figure 9]A particular embodiment of an MRAM memory cell design implemented in a cross-point array is shown in more detail. [Figure 10A] Writing of an MRAM memory cell by use of a spin torque transfer (STT) mechanism is shown. [Figure 10B] Writing of an MRAM memory cell by use of a spin torque transfer (STT) mechanism is shown. [Figure 11] An embodiment including a threshold switching selector within an MRAM memory array having a cross-point architecture is shown. [Figure 12A] Reading of an MRAM cell is shown. [Figure 12B] Reading of an MRAM cell is shown. [Figure 13A] The flow of current in the read operation of different stories in a multi-story non-volatile memory structure is shown. [Figure 13B] The flow of current in the read operation of different stories in a multi-story non-volatile memory structure is shown. [Figure 14A] An example including different sense amplifiers for different stories is shown. [Figure 14B] An example including different sense amplifiers for different stories is shown. [Figure 15A] Aspects of the present technology including a sense amplifier and a control circuit configured to enable the sense amplifier to read non-volatile memory cells of different stories are shown. [Figure 15B] Aspects of the present technology including a sense amplifier and a control circuit configured to enable the sense amplifier to read non-volatile memory cells of different stories are shown. [Figure 15C] Aspects of the present technology including a sense amplifier and a control circuit configured to enable the sense amplifier to read non-volatile memory cells of different stories are shown. [Figure 16] An example of a memory die including a common sense amplifier is shown. [Figure 17] A part of a data storage system according to an example of the present technology is shown. [Figure 18A] An example of a method is shown which involves connecting a sensing amplifier to the bit line and word line according to the story in which the non-volatile memory cells are located. [Figure 18B] This example demonstrates using the same sensing amplifier to sense non-volatile memory cells in different stories. [Figure 19A] An embodiment of a bipolar decoder is presented, and the two figures show different parts of the circuit, both constituting an embodiment of the circuit. [Figure 19B] An embodiment of a bipolar decoder is presented, and the two figures show different parts of the circuit, both constituting an embodiment of the circuit. [Figure 20] An embodiment of a triple-well transistor, which can be used in the decoder switch shown in Figures 19A and 19B, is shown. [Figure 21] Figures 19A and 19B show one embodiment of the decoder floor plan. [Figure 22] One embodiment is shown for hooking up the positions of array vias that connect the decoder circuit to the word lines and bit lines of the associated crosspoint array. [Figure 23] One embodiment is shown for hooking up the positions of array vias that connect the decoder circuit to the word lines and bit lines of the associated crosspoint array. [Figure 24] Figure 21 is a side view of one embodiment of a different decoder block, showing how they connect to the metal layer in Figure 22. [Figure 25] The decoder in Figure 21 is repeated, but a portion of the routing from Figure 24 is shown in the top view. [Figure 26] This is a detail of the lower left quadrant of Figure 25, which illustrates routing. [Figure 27] This is a flowchart of one embodiment for forming a memory device including the decoder structure shown in Figures 19A to 26. [Figure 28] This shows one embodiment of the module decoder floor plan. [Figure 29]One embodiment for routing control signals across module decoders is shown. [Figure 30] This is a flowchart of one embodiment for forming the decoder arrangement shown in Figures 28 and 29. [Modes for carrying out the invention]

[0006] In a memory array with a crosspoint architecture, a first set of conductive wires (e.g., word wires or WLs) extends across the surface of the substrate, and a second set of conductive wires (e.g., bit wires or BLs) extends on the substrate perpendicular to the first set of conductive wires. Memory cells are located at the crosspoint junctions of the two sets of conductive wires. Embodiments of memory cells may include programmable resistive elements, such as MRAM elements, which can be connected in series with a selector switch (selector) in the crosspoint memory structure.

[0007] In some memory structures, including crosspoint MRAM memory structures, memory cells may be formed in two or more stories (e.g., a first story formed between the first word line layer and the bit line layer, and a second story formed between the bit line layer and the second word line layer). Accessing memory cells in such structures can be difficult. For example, if the current direction is the same in both layers (e.g., current flows upward through the memory cell), the current flows from the word line to the bit line in the first story and from the bit line to the word line in the second story. This may require dedicated circuitry for each story (e.g., a sense amplifier).

[0008] To program an MRAM memory cell (i.e., to change its state from logic 1 to logic 0, or vice versa), current must flow from the corresponding bit line of the memory cell to its corresponding word line, or vice versa. To achieve this, the bit line and word line decoders must be able to supply current (when driving the line positively) and sink current (when drawing the line negatively), taking into account the bipolar nature of the memory cell. Consequently, the decoder must be bipolar. NMOS devices are used for the negative selector switches, and PMOS switches are used for the positive selector switches. To reduce layout area and routing, in embodiments of bipolar decoders, the negative and positive selector switches are grouped separately such that a subset of positive selector switches is positioned between a subset of negative selector switches, and vice versa. Connections for the decoder switches are routed to a central hookup area for connection to the control lines of the crosspoint array.

[0009] Routing for such decoders is very complex and can consume a considerable area of ​​the die, especially in the case of bipolar decoders that need to selectively provide both positive and negative bias levels. Therefore, reducing the routing area is beneficial to the memory device, particularly if the area required for the decoding structure can be fitted into the footprint of the memory array. The following additional aspects present techniques for reducing address path routing. Bit-line decoders and word-line decoders are divided into subsets covering different bit-line and word-line ranges of the crosspoint array. Inverters are positioned along the opposing edges of the subdecoders and within the bit-line and word-line subdecoders to drive local selection switches. The inverters are aligned on the die such that a single set of bit-line enable signals may be shared by multiple bit-line subdecoders and a single set of word-line enable signals may be shared by multiple word-line subdecoders.

[0010] Figure 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. The memory system 100 can implement the techniques presented herein for managing the error rate. Many different types of memory systems can be used with the techniques proposed herein. Exemplary memory systems include solid-state drives ("SSDs"), memory cards containing dual in-line memory modules (DIMMs) for DRAM replacement, and embedded memory devices. However, other types of memory systems may also be used.

[0011] The memory system 100 in Figure 1 comprises a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 comprises a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, the FEP circuit 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, the integrated controller ASIC can combine both front-end and back-end functions. The ASICs for the BEP circuits 112 and the FEP circuits 110, respectively, are implemented on the same semiconductor so that the controller 102 is manufactured as a system-on-a-chip ("SoC"). Both the FEP circuits 110 and the BEP circuits 112 include their own processors. In one embodiment, the FEP circuit 110 and BEP circuits 112 operate in a master-slave configuration, with the FEP circuit 110 being the master and each BEP circuit 112 being a slave. For example, the FEP circuit 110 implements a flash translation layer (FTL) or media management layer (MML) that performs memory management (e.g., garbage collection, wear leveling), logic address to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuits 112 manage memory operations on the memory package / die as required by the FEP circuit 110. For example, the BEP circuits 112 can perform read, erase, and programming processes. Furthermore, the BEP circuits 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), and control the toggle-mode interface to the memory package. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages.

[0012] In one embodiment, the non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Thus, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die within the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as resistive random-access memory (ReRAM, MRAM, FeRAM, or RRAM, etc.) or storage class memory (SCM) based on phase-change memory (PCM). In other embodiments, BEP or FEP may be included on the memory die.

[0013] The controller 102 communicates with the host 120, for example, via an interface 130 that implements protocols such as NVM Express (NVMe) or Compute Express Link (CXL) over PCI Express (PCIe), or using a JEDEC standard double data rate or low-power double data rate (DDR or LPDDR) interface such as DDR5 or LPDDR5. To cooperate with the memory system 100, the host 120 includes a host processor 122 connected along a bus 128, host memory 124, and a PCIe interface 126. The host memory 124 is the host's physical memory and can be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage device. The host 120 is external to and isolated from the memory system 100. In one embodiment, the memory system 100 is integrated into the host 120.

[0014] Figure 2 is a block diagram of one embodiment of a memory package 104 including a plurality of memory dies 292 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 is connected to a toggle mode interface 296 for communicating with the TM interface of a BEP circuit. In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one embodiment, each memory package includes eight or sixteen memory dies. However, other numbers of memory dies may also be implemented. In another embodiment, the toggle interface is instead a JEDEC standard DDR or LPDDR with or without variations such as a relaxed time set or a smaller page size. The technology described herein is not limited to any particular number of memory dies.

[0015] Figure 3 is a block diagram showing an example of a memory system 500 that can implement the technology described herein. The memory system 500 includes a memory array 502 which may include any of the memory cells described below. The array terminal lines of the memory array 502 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations may also be implemented. The memory system 500 includes a row control circuit 520 connected to each word line of the memory array 502 via line 508. The row control circuit 520 receives row address signals and one or more various control signals from the system control logic 560 and may typically include circuits such as a row decoder 522 and a word line (WL) driver 524 for both read and write operations.

[0016] The memory system 500 also includes a column control circuit 510, the input / output 506 of which is connected to each bit line of the memory array 502. Although only a single block is shown for the memory array 502, the memory die may include multiple arrays or “tiles” that can be accessed individually. The column control circuit 510 receives column address signals and one or more different control signals from the system control logic 560 and may typically include circuits such as a column decoder 512, a bit line (BL) driver 514, and a read / write (R / W) circuit 516, which may include, for example, a sensing amplifier for reading.

[0017] The system control logic 560 receives data and commands from the host and provides output data and status to the host. In other embodiments, the system control logic 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host. In some embodiments, the system control logic 560 may include a state machine that provides die-level control of memory operation. In one embodiment, the state machine is programmable by software. In other embodiments, the state machine does not use software and is fully implemented in hardware (e.g., electrical circuitry). In another embodiment, the state machine is replaced by a microcontroller, which may be on or off the memory chip. The system control logic 560 may also include a power control module that controls the power and voltage supplied to the rows and columns of the memory array 502 during memory operation and may include charge pump and regulator circuits for generating regulated voltages. The system control logic 560 may include one or more state machines, registers, and other control logic for controlling the operation of the memory system 500.

[0018] In some embodiments, all elements of the memory system 500, including the system control logic 560, may be formed as part of a single die (for example, the memory die 292 in Figure 2). In other embodiments, some or all of the system control logic 560 may be formed on different dies.

[0019] For the purposes of this specification, the phrase "one or more control circuits" may include other control circuits represented by the controller, state machine, microcontroller, and / or system control logic 560, and / or other similar circuits used to control non-volatile memory.

[0020] In one embodiment, the memory structure 502 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed on a single substrate such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions located on a silicon (or other type) substrate. In another embodiment, the memory structure 502 includes a two-dimensional memory array of non-volatile memory cells.

[0021] The exact type of memory array architecture or memory cell included in memory structure 502 is not limited to any specific example. Many different types of memory array architectures or memory technologies can be used to form memory structure 502. Examples of suitable technologies for memory cells in memory structure 502 include NAND flash memory, ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, and phase-change memory (e.g., PCM). Examples of suitable technologies for memory cell architectures in memory structure 502 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, and vertical bit-line arrays.

[0022] An example of a ReRAM crosspoint memory includes a reversible resistive switching element arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. Conductive bridge memory elements are sometimes called programmable metallization cells. Conductive bridge memory elements can be used as state change elements based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature rises, the mobility of ions also increases, reducing the programming threshold of the conductive bridge memory cell. Thus, conductive bridge memory elements can have a wide programming threshold with respect to temperature.

[0023] Another example is magnetoresistive random-access memory (MRAM), which stores data using magnetic memory elements. The element is formed from two ferromagnetic layers, each capable of holding a magnetization separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity, and the magnetization of the other layer can be changed to match the magnetization of an external magnetic field for memory storage. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is positioned perpendicular to each other, parallel to the cell, one above the cell and one below the cell, between a pair of write lines. As current passes through them, an induced magnetic field is generated. Embodiments of MRAM-based memory are described in more detail below.

[0024] Phase-change memory (PCM) utilizes the inherent behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the coordination state of germanium atoms using programming current pulses. Note that the use of “pulse” as herein does not require a square wave and includes (continuous or discontinuous) oscillations or bursts of sound, current, voltage, light, or other waves. The memory elements within each selectable memory cell or bit may include further series elements, such as an obonic threshold switch or a selector such as a metal-insulating substrate.

[0025] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather cover many related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0026] The elements in Figure 3 can be grouped into two parts: the memory structure 502 (including the memory cells) and the peripheral circuitry, which includes all other elements. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die of the memory system 500 allocated to the memory structure 502. However, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose very strict limitations on these peripheral elements. For example, the need to fit the sensing amplifier circuitry within the available area can be a significant constraint on the sensing amplifier design architecture. With respect to the system control logic 560, the reduction in area availability can limit the available functions that can be implemented on-chip. Therefore, the fundamental trade-off in the design of the memory die for the memory system 500 is the amount of area allocated to the memory structure 502 versus the amount of area allocated to the peripheral circuitry.

[0027] Another area where the memory structure 502 and peripheral circuits often conflict lies in the processing involved in forming these areas, as these areas often involve different processing techniques and involve trade-offs in having different techniques on a single die. For example, if the memory structure 502 is NAND flash, it is an NMOS structure, but the peripheral circuits are often CMOS-based. For example, elements such as sensing amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 560 often use PMOS devices. The processing operations for manufacturing CMOS dies differ in many ways from the processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0028] To overcome these limitations, the embodiments described below allow the elements of Figure 3 to be separated onto separately formed dies, which are then joined together. More specifically, the memory structure 502 can be formed on one die, and some or all of the peripheral circuit elements, including one or more control circuits, can be formed on separate dies. For example, the memory die may be formed solely from memory elements such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or arrays of memory cells of other memory types. Some or all of the peripheral circuits, even if they include elements such as decoders and sensing amplifiers, can be moved to separate dies. This allows each memory die to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements moved onto separate peripheral circuit dies that can be optimized for CMOS processing. This allows for more space for peripheral elements and can incorporate additional capabilities that could not be easily incorporated when limited to the margins of the same die holding the memory cell array. The two dies can then be joined together in a joined multi-die memory circuit, with the array on one die connected to the peripheral elements on the memory circuit of the other die. While the following focuses on a joined memory circuit with one memory die and one peripheral die, other embodiments may utilize more dies, such as two memory dies and one peripheral die.

[0029] Figure 4 shows an alternative arrangement to the arrangement in Figure 3, which may be implemented using wafer-to-wafer bonding to provide bonded die pairs for the integrated memory assembly 600. Figure 4 shows an example of peripheral circuits, including control circuits, coupled to a memory structure 602 formed within the memory die 601 or formed within the control die 611. Similar to 502 in Figure 3, the memory die 601 may contain multiple independently accessible arrays or “tiles”. Common components are labeled as in Figure 3 (e.g., 502 is here 602, 510 is here 610, etc.). It can be seen that the system control logic 660, row control circuit 620, and column control circuit 610 (which may be formed by a CMOS process) are located within the control die 611. Additional elements, such as functions from the controller 102, can also be moved to the control die 611. The system control logic 660, row control circuit 620, and column control circuit 610 may be formed by a common process (e.g., a CMOS process), and as a result, additional elements and functions more typically found on the memory controller 102 may require little or no additional process steps (i.e., the same process steps used to manufacture the controller 102 may also be used to manufacture the system control logic 660, row control circuit 620, and column control circuit 610). Therefore, moving such circuitry from a die such as the memory die of the memory system 500 may reduce the number of steps required to manufacture such a die, while adding such circuitry to a die such as the control die 611 may require no additional process steps at all.

[0030] Figure 4 shows a column control circuit 610 on a control die 611 coupled to a memory structure 602 on a memory die 601 via an electrical path 606. For example, the electrical path 606 may provide electrical connections between the column decoder 612, driver circuit 614, and R / W circuit 616 and the bit lines of the memory structure 602. The electrical path may extend from the column control circuit 610 in the control die 611 through pads on the control die 611 bonded to corresponding pads on the memory die 601 connected to the bit lines of the memory structure 602. Each bit line of the memory structure 602 may have a corresponding electrical path in the electrical path 606, which includes a pair of bonding pads connected to the column control circuit 610. Similarly, a row control circuit 620, including a row decoder 622, array driver 624, and block selector 626, is coupled to the memory structure 602 via an electrical path 608. Each electrical path 608 may correspond to a word line, dummy word line, or selector gate line. An additional electrical path may be provided between the control die 611 and the memory die 601.

[0031] In relation to Figure 3, the on-die control circuit in Figure 4 can include additional features within its logic elements, including both more general capabilities and some CPU capabilities than those typically found in the memory controller 102, but it can also include application-specific features.

[0032] Hereinafter, the system control logic 560 / 660, column control circuits 510 / 610, row control circuits 520 / 620, and / or controller 102 (or equivalent circuits) may be considered as part of one or more control circuits that perform the functions described herein, in combination with all or a subset of the other circuits shown in Figure 3, or on the control die 611 in Figure 4. A control circuit may consist of hardware only, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, integrated circuit, or other types of circuitry.

[0033] In the following description, the memory arrays 502 / 602 in Figures 3 and 4 are described primarily in the context of a crosspoint architecture, but much of the description can be applied more generally. The following description mainly focuses on embodiments based on a crosspoint architecture using MRAM memory cells, but much of the description can be applied more generally to non-volatile memory cells.

[0034] Figure 5 shows an example of a sensing amplifier 570 (for example, in a read / write circuit 516 or 616). Figure 5 shows a sensing node 572 which can be connected to a selected non-volatile memory cell (for example, via a selected bit line which can be selected by a column decoder 512 or 612). A current mirror 574 connected to a supply voltage VNN controls the current flowing through the selected non-volatile memory cell during sensing. The sensing amplifier 570 includes a comparator 576 that receives a voltage from the sensing node 572 and compares it to a reference voltage (Vref) from a reference voltage source 578. For example, the comparator 576 may generate a digital output (logic 1 or 0) depending on whether the voltage at the sensing node 572 is higher or lower than the reference voltage. The digital output from the comparator 576 is latched to a data latch 580 and output as sensing data.

[0035] Figure 6 illustrates a read operation for a selected memory cell 680 located at the intersection of a selected word line 682 and a selected bit line 684 (for example, in structure 502 / 602). The word line driver 542 generates a first supply voltage VPP (e.g., a positive voltage), which is then applied to the word line 682 selected by the row decoder 522. The column decoder 512 selects the bit line 684 and connects it to a sensing node 572, where a voltage is sensed by the sensing amplifier 570 as current flows through a current mirror that receives a second supply voltage VNN (e.g., a negative voltage) from the bit line driver 514. The sensing amplifier 570 can sense the state of the selected memory cell 680 from the voltage at the sensing node 572 while a predetermined current flows through the selected memory cell 680 from the current mirror 574.

[0036] Figure 7A is a perspective view showing one embodiment of a portion of a memory array forming a crosspoint architecture. The memory array 502 / 602 in Figure 7A is an example of an implementation of the memory array 502 in Figure 3 or the memory array 602 in Figure 4, and the memory die can include multiple such array structures. The bit lines BL1-BL5 are arranged in a first direction (e.g., the “bit line direction” as expressed to extend within a page) with respect to the substrate (not shown) beneath the die, and the word lines WL1-WL5 are arranged in a second direction (e.g., the “word line direction” as expressed to extend within a page) perpendicular to the first direction (across a page). Figure 7A is an example of a horizontal crosspoint structure in which both the word lines WL1-WL5 and BL1-BL5 extend horizontally with respect to the substrate, and two of these memory cells, indicated by 701, carry current (I cell The lines (as shown in the diagram) are oriented to flow vertically. In a memory array with additional layers of memory cells, as described below with respect to Figure 7D, there are corresponding additional layers of bit lines and word lines.

[0037] As shown in Figure 7A, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 may include rewritable memory cells, such as those that can be implemented using ReRAM, MRAM, PCM, FeRAM, or other materials having programmable resistance. The current in the memory cell at the first memory level is indicated by arrow I cell Although it is shown as flowing upwards, as illustrated by [the diagram], current can flow in any direction, as will be explained in more detail below.

[0038] Figures 7B and 7C show the side and top views, respectively, of the crosspoint structure in Figure 7A. The side view in Figure 7B shows one lower wire or word line WL1 and upper wires or bit lines BL1~BL n This shows that PCM, FeRAM, ReRAM, or other technologies may be used, but each crosspoint between the upper and lower wires contains an MRAM memory cell. Figure 7C shows M lower wires WL1~WL Mand N upper wires BL1 to BL N is a top view showing a cross-point structure for. In the binary embodiment, the MRAM cells at each cross-point can be programmed to one of two resistance states, namely, high and low. Further details regarding embodiments for MRAM memory cell designs and techniques for their programming are given below.

[0039] The cross-point array of FIG. 7A has one layer (one story) of word lines and bit lines and shows an embodiment in which MRAM or other memory cells are located at the intersections of two sets of conductive lines. To increase the storage density of the memory die, a plurality of layers (stories) of such memory cells and conductive lines can be formed. An example of two layers (two stories) is shown in FIG. 7D.

[0040] FIG. 7D shows in perspective view an embodiment of a portion of a two-level (two-story) memory array forming a cross-point architecture. Similar to FIG. 7A, FIG. 7D shows the first layer 718 (first story) of memory cells 701 of array 502 / 602 connected at the cross-points of the first layer of word lines WL 1,1 ~WL 1,4 and bit lines BL1 to BL5. The second layer (second story) of memory cells 720 is above the bit lines BL1 to BL5 and is formed between these bit lines and a second set of word lines WL 2,1 ~WL 2,4 FIG. 7D shows two layers (stories) 718 and 720 of memory cells, but this structure can be extended upward via additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array of FIG. 7D can be biased for read or program operations such that current within each layer flows from the word line layer to the bit line layer or vice versa.

[0041] The use of a crosspoint architecture enables arrays with a small footprint, and several such arrays can be formed on a single die. Memory cells formed at each intersection may be resistive memory cells in which data values ​​are encoded as different resistance levels. Depending on the embodiment, the memory cells may be binary values ​​having either a low-resistance state or a high-resistance state, or they may be multilevel cells (MLCs) that may have additional resistance between the low-resistance and high-resistance states. The crosspoint array described herein may be used as memory die 292 in Figure 4 to replace local memory 106, or both.

[0042] Figure 8 shows one embodiment of the structure of an MRAM memory cell. The voltage applied across the memory cell between the corresponding word line and bit line of the memory cell is the voltage source V app Represented as 813, the memory cell includes a lower electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by an isolation or tunneling layer of magnesium oxide (MgO) 805 in this example, and an upper electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 803 and the free layer 807. If the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low-resistance state (LRS), and if they have opposite orientations, the memory cell is in an antiparallel (AP) high-resistance state (HRS). Embodiments of the MLC include additional intermediate states. The orientation of the reference layer 803 is fixed and is upward in the example in Figure 15. The reference layer 803 is also known as the fixed layer or pinned layer.

[0043] Data is written to the MRAM memory cell by programming the free layer 807 to have the same or opposite orientation. The reference layer 803 is formed to maintain its orientation when the free layer 807 is programmed. The reference layer 803 may have a more complex design, including a composite antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the figures and descriptions, and only the fixed magnetic layers, which are primarily responsible for the tunnel magnetoresistance within the cell, are considered.

[0044] Figure 9 shows in more detail one embodiment of an MRAM memory cell design that can be implemented in a crosspoint array. When arranged in a crosspoint array, the upper and lower electrodes of the MRAM memory cell are two of the adjacent layers of wires in the array, for example, the upper and lower wires of a 2-level or 2-deck array. In the embodiment shown here, the lower electrode is the word line 901 of the memory cell and the upper electrode is the bit line 911, although in some embodiments these can be reversed by reversing the orientation of the memory elements. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are also separated by an isolated MgO barrier 905. In the embodiment shown in Figure 9, an MgO cap 908 is also formed on the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. Liners 921 and 923 are located on either side of the memory cell structure; although they may be part of the same structure, they appear separate in the cross-sectional view of Figure 9. On either side of liners 921 and 923 are portions of filler material 925 and 927, which are used to fill other empty areas of the crosspoint structure.

[0045] With respect to the free layer 907, embodiments include a CoFe or CoFeB alloy having a thickness of about 1-2 nm, the Ir layer can be scattered within the free layer in close proximity to the MgO barrier 905, and the free layer 907 can be doped with Ta, W, or Mo. Embodiments of the base layer 903 may include a CoFeB and CoPt multilayer bilayer bonded to an Ir or Ru spacer 902. The MgO cap 908 is optional but can be used to increase the anisotropy of the free layer 907. The conductive spacer can be a conductive metal such as Ta, W, Ru, CN, TiN, and TaN, among others.

[0046] To sense the data state stored in MRAM, V app A voltage represented by is applied across the memory cell to determine its resistance state. To read the MRAM memory cell, the voltage difference V app A bias can be applied in either direction. However, MRAM memory cells are directional, and therefore, in some situations, reading in one direction is preferred over other directions. For example, the optimal current amplitude for writing a bit to AP (high resistance state, HRS) may be 50% or more greater than the optimal current amplitude for writing to P (low resistance state), and therefore, when reading to AP (2AP), the bit error rate (read failure) is less likely to occur. Some of these situations and the resulting read directionality are described below. The directionality of the bias comes into play in particular in some embodiments for programming MRAM memory cells.

[0047] The following description primarily concerns perpendicular spin-transfer torque MRAM memory cells, which include a switchable magnetization direction in which the free layers 807 / 907 in Figures 8 and 9 are perpendicular to the plane of the free layer. Spin-transfer torque ("STT") is an effect that can be used to correct the orientation of magnetic layers within a magnetic tunnel junction using a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum inherent to the carrier. Currents are generally unpolarized (e.g., consisting of 50% spin-up electrons and 50% spin-down electrons). A spin-polarized current is one in which there are more electrons of either spin (e.g., a majority of spin-up electrons or a majority of spin-down electrons). A spin-polarized current can be generated by passing a current through a thick magnetic layer (reference layer). When this spin-polarized current is directed to a second magnetic layer (free layer), the angular momentum is transferred to this second magnetic layer, changing the direction of magnetization in the second magnetic layer. This is called spin-transfer torque. Figures 10A and 10B illustrate the use of spin-transfer torque for programming or writing to MRAM memory. Spin-transfer torque magnetic random-access memory (STT MRAM) has the advantages of lower power consumption and better scalability than MRAM variants such as toggle MRAM. Compared to other MRAM implementations, STT switching technology requires relatively low power, virtually eliminates the problem of adjacent bit interference, and has better scaling for higher memory cell density (reduced MRAM cell size). The latter issue is also advantageous for STT MRAM, where the magnetization of the free layer and reference layer is oriented perpendicular to the film plane rather than in-plane.

[0048] Since the STT phenomenon is more easily explained in terms of electron behavior, Figures 10A and 10B and their explanations are given in terms of electron current, and the direction of the write current is defined as the direction of electron flow. Therefore, the term write current in reference to Figures 10A and 10B refers to electron current. Since electrons are negatively charged, electron current is in the opposite direction to conventionally defined current, and as a result, electron current flows from low voltage levels to high voltage levels instead of the conventional current flow from high voltage levels to low voltage levels.

[0049] Figures 10A and 10B illustrate writing and reading of an MRAM memory cell using an STT mechanism and show a simplified schematic diagram of an example of an STT-switchable MRAM memory cell 1000 in which both the reference layer magnetization and the free layer magnetization are perpendicular. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002 comprising an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier 1014 (TB) as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is a free layer FL whose magnetization direction can be switched. The lower ferromagnetic layer 1012 is a reference (or fixed) layer RL whose magnetization direction cannot be switched. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across memory cell 1000 is relatively high. The data ("0" or "1") of memory cell 1000 is read by measuring the resistance of memory cell 1000. In this regard, the conductors 1006 / 1008 attached to memory cell 1000 are used to read the MRAM data. By design, both parallel and antiparallel configurations remain stable in a quiescent state and / or during read operations (with sufficiently low read currents).

[0050] For both the reference layer RL 1012 and the free layer FL 1010, the direction of magnetization is perpendicular (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figures 10A and 10B show the magnetization direction of the reference layer RL 1012 as upward, and the magnetization direction of the free layer FL 1010 as switchable between upward and downward, which is also perpendicular to the plane.

[0051] In one embodiment, the tunnel barrier 1014 is made of magnesium oxide (MgO), but other materials can also be used. The free layer 1010 is a ferromagnetic metal having the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys can be used to form the free layer 1010. In one embodiment, the free layer 1010 includes an alloy of cobalt, iron, and boron. The base layer 1012 can be many different types of materials, including (but not limited to) multiple layers of cobalt and platinum and / or cobalt and iron alloys.

[0052] To "set" the MRAM memory cell bit values ​​(i.e., select the direction of free layer magnetization), an electronic write current 1050 is applied from conductor 1008 to conductor 1006, as shown in Figure 10A. To generate the electronic write current 1050, the upper conductor 1006 is placed at a higher voltage level than the lower conductor 1008 due to the negative charge of electrons. Since the reference layer 1012 is a ferromagnetic metal, electrons in the electronic write current 1050 are spin-polarized as they pass through the reference layer 1012. When spin-polarized electrons tunnel across the tunnel barrier 1014, the conservation of angular momentum may impart a spin transfer torque to both the free layer 1010 and the reference layer 1012, but this torque is (by design) insufficient to influence the magnetization direction of the reference layer 1012. In contrast, this spin-transfer torque is (by design) sufficient to switch the magnetization orientation within the free layer 1010 to be parallel (P) to the magnetization orientation of the reference layer 1012, if the initial magnetization orientation of the free layer 1010 was antiparallel (AP) with respect to the reference layer 1012, a process called antiparallel-parallel (AP2P) writing. The parallel magnetization remains stable before and after such an electronic writing current is turned off.

[0053] In contrast, if the magnetizations of the free layer 1010 and the reference layer 1012 are initially parallel, the direction of the magnetization of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electronic writing current in the opposite direction to that described above. For example, the electronic writing current 1052 is applied from conductor 1006 to conductor 1008 by applying a higher voltage level to the lower conductor 1008, as shown in Figure 10B. This writes the free layer 1010 from a P state to an AP state, and is called parallel-antiparallel (P2AP) writing. Thus, by the same STT physics, the direction of the magnetization of the free layer 1010 can be deterministically set to one of two stable orientations by a wise choice of the direction (polarity) of the electronic writing current.

[0054] The data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit, but sometimes other rules apply. A read current can be applied across the memory cell (e.g., across the magnetic tunnel junction 1002) by applying an electronic read current from conductor 1008 to conductor 1006, flowing as shown at 1050 in Figure 10A ("AP2P direction"). Alternatively, the electronic read current can be applied from conductor 1006 to conductor 1008 and flow as shown at 1052 in Figure 10B ("P2AP direction"). If the electronic write current is too high during a read operation, it can disrupt the data stored in the memory cell and change its state. For example, if the electronic read current uses the P2AP direction in Figure 10B, a current or voltage level that is too high can switch any memory cell from a low-resistance P state to a high-resistance AP state. As a result, while MRAM memory cells can be read in either direction, the directional nature of the write operation can make one read direction preferable to the other, as in various embodiments such as the P2AP direction, more current is required to write bits in that direction.

[0055] The explanations for Figures 10A and 10B relate to the electron current in relation to the read current and write current, but the following explanations will relate to conventional currents unless otherwise specified.

[0056] Regardless of whether a selected memory cell in the array structure shown in Figures 7A to 7D is being read or written, the bit and word lines corresponding to the selected memory cell are biased to apply a voltage across the selected memory cell and induce an electron flow, as shown with respect to Figure 10A or Figure 10B. This can also apply a voltage across the unselected memory cells in the array and induce a current in the unselected memory cells. This wasted power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high-resistance and low-resistance states, but this still increases current and power consumption and imposes additional design constraints on the design of the memory cells and array.

[0057] One approach to address this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, a selector transistor can be placed in series with each resistive memory cell element in Figures 7A-7D, so that memory cell 701 is, in this case, a combination of a selector and a programmable resistor. However, the use of transistors requires the introduction of additional control lines in order to turn on the corresponding transistor of the selected memory cell. Furthermore, transistors often do not scale as well as resistive memory elements, and as a result, the use of transistor-based selectors can become a limiting factor as memory arrays move to smaller sizes.

[0058] An alternative approach to selector elements is the use of a threshold switching selector device in series with a programmable resistor element. A threshold switching selector has high resistance (off or non-conducting) when biased to a voltage lower than its threshold voltage, and low resistance (on or conducting) when biased to a voltage higher than its threshold voltage. The threshold switching selector remains on until its current drops below the holding current or its voltage drops below the holding voltage. Once this occurs, the threshold switching selector returns to the off state. Therefore, to program a memory cell at a crosspoint, the associated threshold switching selector must be turned on, and sufficient voltage or current must be applied to set or reset the memory cell. Similarly, to read a memory cell, the threshold switching selector must be activated by being turned on before the resistance state of the memory cell can be determined. An example of a set of threshold switching selectors is the ovonic threshold switching material of an ovonic threshold switch (OTS).

[0059] Figure 11 shows one embodiment of incorporating a threshold switching selector into an MRAM memory array having a crosspoint architecture. The example in Figure 11 shows two MRAM cells in a two-layer (two-story) crosspoint array as shown in Figure 7D, in a side view. Figure 11 shows the lower first conductive wire (within the first or lower word line layer) of word line 1 1100, the upper first conductive wire (within the second or upper word line layer) of word line 2 1120, and the intermediate conductive wire (within the bit line layer) of bit line 1110. In Figure 11, all of these lines are shown extending from left to right across the page for ease of presentation. In a crosspoint array, they are represented more precisely as in the perspective view of Figure 7D, where the word lines or first conductive wires or wires extend in one direction parallel to the surface of the underlying substrate, and the bit lines or second conductive wires or wires extend in a second direction parallel to the surface of the substrate, substantially perpendicular to the first direction. MRAM memory cells are also represented in a simplified form showing only the reference layer, free layer, and intermediate tunnel barrier; however, actual implementations will typically include the additional structures described above with respect to Figure 9.

[0060] The MRAM device 1102, which includes a free layer 1101, a tunnel barrier 1103, and a reference layer 1105, is formed on top of the threshold switching selector 1109. This series combination of the MRAM device 1102 and the threshold switching selector 1109 together forms a story 0 cell between the bit line 1110 and the word line 1100. The series combination of the MRAM device 1102 and the threshold switching selector 1109 operates primarily as described above with respect to Figures 10A and 10B, except for some voltage drop across the threshold switching selector 1109 when the threshold switching selector 1109 is turned on. However, firstly, the threshold switching selector 1109 has a threshold voltage V th It must be turned on by applying a voltage exceeding a certain value, and then the bias current or voltage must be maintained at a sufficiently high level above the holding current or holding voltage of the threshold switching selector 1109 so that it remains on during subsequent read or write operations.

[0061] In story 1, the MRAM device 1112 includes a free layer 1111 and a tunnel barrier 1113, and the reference layer 1115 is formed on top of the threshold switching selector 1119. The series combination of the MRAM device 1112 and the threshold switching selector 1119 together forms a story 1 cell between the bit line 1110 and the word line 2 1120. The story 1 cell operates similarly to the story 0 cell, except that the lower conductor corresponds here to the bit line 1110, and the upper conductor corresponds here to the word line, word line 2 1120.

[0062] In the embodiment shown in Figure 11, the threshold switching selector 1109 / 1119 (selector) is formed beneath the MRAM devices 1102 / 1112, so that the selector 1109 contacts the first word line 1100 of the first word line layer, and the MRAM device 1102 is formed between the selector 1109 and the bit line 1110. In alternative embodiments, the threshold switching selector can be formed above the MRAM devices for one or both layers. As described with respect to Figures 10A and 10B, the MRAM memory cells are directional. In Figure 11, the MRAM devices 1102 and 1112 have the same orientation, and the free layers 1101 / 1111 are above the reference layers 1105 / 1115 (for a substrate not shown). Forming stories between conductive lines having the same structure can have several advantages with respect to processing, in particular, because each of the two stories, as well as subsequent stories in embodiments with more stories, can be formed according to the same processing sequence when forming a multi-story non-volatile memory structure.

[0063] Reading data from or writing data to an MRAM memory cell involves supplying current to the memory cell. In embodiments where a threshold switching selector is arranged in series with the MRAM device, the threshold switching selector must be turned on by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM device before current can pass through the MRAM device.

[0064] Figure 12A shows a schematic diagram of an example of reading a non-volatile memory cell 1220, which includes an MRAM cell 1222 connected in series with selector 1224. The MRAM cell 1222 has a resistor R corresponding to the resistance of the MRAM cell 1222 in the parallel and antiparallel states. P and R AP It is schematically shown as two resistors having V. MRAM However, depending on whether MRAM cell 1222 is in a parallel state or an antiparallel state, it can have two different values ​​(for example, V MRAM =Iread* R P or V MRAM = Iread * R AP ) The constant current Iread is maintained through the MRAM cell 1222 during reading (e.g., by a current mirror such as current mirror 574). The selector 1224 is schematically represented as a voltage source that provides a constant voltage difference Voffset when it is in the ON state (e.g., exceeding a threshold voltage). The sense amplifier 570 is connected to sense the voltage at the sense node 572 (e.g., the voltage varies according to the resistance of the MRAM cell 1222 and the resulting voltage V MRAM which is different).

[0065] FIG. 12B shows the voltage distributions that can be compared by the comparator (e.g., comparator 576) of the sense amplifier 570 in the sensing operation. The first voltage distribution marked "P" (e.g., at the sense node 572) corresponds to the parallel or "P" state of the MRAM cell. The second voltage distribution marked "AP" corresponds to the anti-parallel or "AP" state of the MRAM cell. There is a reference voltage Vref (e.g., from the Vref source 578) between these distributions. By comparing the voltage at the sense node 572 with the reference voltage Vref, a determination can be made as to which state the MRAM cell is in (e.g., a sensed voltage < Vref indicates the P state and a sensed voltage > Vref indicates the AP state).

[0066] In a non-volatile memory cell including a selector connected in series with the MRAM cell, a conventional current may flow from the selector side to the MRAM side. In a multi-story non-volatile memory structure as shown in FIG. 11, this can cause some differences when accessing non-volatile memory cells in different stories.

[0067] Figures 13A and 13B illustrate the differences in accessing non-volatile memory cells in different stories. In the first story (story 0 in Figure 13A), current flows from the word line side to the bit line side. For example, Figure 13A shows the word line selected via the WL driver 624 (variable resistor R) so that the current Iread flows from the word line side to the bit line side. WL A positive voltage VPP is applied to the selected bit line (which is schematically shown as a variable resistor R), and the selected bit line (variable resistor R) is also shown. BL The negative voltage VNN applied to (r shown schematically as) is shown. In contrast, in the second story (story 1 in Figure 13B), the current flows from the bit line side to the word line side. For example, Figure 13B shows the bit line (R selected via the BL driver 614) such that the current Iread flows from the bit line side to the word line side. BL The positive voltage VPP applied to ) and the selected word line (R WL The negative voltage VNN applied to ) and the result are shown.

[0068] To read memory cells from different stories within a multi-story MRAM memory structure (for example, as shown in Figure 11), the read / write circuit may include separate sensing amplifiers for reading memory cells within each story. For example, Figures 14A and 14B show an example where two different sensing amplifiers are used to read non-volatile memory from different stories.

[0069] Figure 14A shows an example of a read operation directed towards a non-volatile memory cell in the first story (story 0 readout), for example, in the story 0 cell in Figure 11. The positive voltage VPP is controlled by switch 1470 (e.g., the switch on the WL decoder) and the selected word line (e.g., the variable resistor R). WL The selected non-volatile memory cell 1472 is connected via the first word line 1100 (as schematically shown). The selected bit line (e.g., R BLA bit line (1110, shown schematically) connects a selected non-volatile memory cell 1472 to a current mirror 574 via a switch 1474 (e.g., a switch on the BL decoder) which is connected to a negative voltage VNN and configured to maintain the read current Iread during read operations. A low-voltage sensing amplifier 1478 is connected to sense the voltage between the selected bit line and the current mirror 574 (for example, the low-voltage sensing amplifier 1478 may be configured to sense low voltages including negative voltages in the range of, for example, -2.5 volts to -3.0 volts).

[0070] Figure 14B shows an example of a second story (story 1 readout), for example, a readout operation directed to a non-volatile memory cell in story 1 cell in Figure 11. The positive voltage VPP is applied to switch 1480 and the selected bit line (e.g., R BL The selected non-volatile memory cell 1482 is connected via the bit line 1110 (which is schematically shown as R). WL A word line (1120, schematically shown as such) connects a selected non-volatile memory cell 1482 to a negative voltage VNN via a switch 1484. A high-voltage sensing amplifier 1483 is connected to sense the voltage between the selected bit line and the current mirror 574 (for example, the high-voltage sensing amplifier 1483 may be configured to sense high voltages including positive voltages in the range of, for example, 2.5 volts to 3.0 volts).

[0071] Embodiments of this technology include using a single sensing amplifier to perform sensing during read operations directed to memory cells of two different stories (for example, as shown in Figure 11), wherein the current flow is different for reading the memory cells of the different stories (for example, the first story, from the word line to the bit line in story 0, and the second story, from the bit line to the word line in story 1).

[0072] Figure 15A shows an example of a control circuit connected to a non-volatile memory cell 1552 (for example, a non-volatile memory cell in any story within an MRAM memory structure as shown in Figure 11). The non-volatile memory cell 1552 is connected to bit line switches 1554 and word line switches 1556, respectively, via bit line R BL and word line R WL The bit line switch 1554 includes a first set of switches 1558 connected between the first voltage VPP (e.g., positive voltage) and the bit line, and a second set of switches 1560 connected between the bit line and the sense amplifier 1478. The word line switch 1556 includes a third set of switches 1562 connected between the first voltage VPP and the word line, and a fourth set of switches 1564 connected between the word line and the sense amplifier 1478. Each switch may correspond to a different switching scale and transistor type. For example, the first letter shown next to each transistor / switch may indicate the scale (e.g., L = local, G = global, and P = plane). The second letter indicates whether it is connected to a line extending in the x or y direction (e.g., Y is the bit line, X is the word line). The third letter indicates the type of transistor (for example, P indicates PMOS and N indicates NMOS, so that the first switch 1558 and the third switch 1562 are formed by PMOS transistors, and the second switch 1560 and the fourth switch 1564 are formed by NMOS transistors). Figure 15A also shows a bank control circuit 1566 and a module control circuit 1568 that can control the signals used to turn the bit line switch 1554 and the word line switch 1556 on / off. For example, the control gates of the first, second, third, and fourth sets of transistors may be connected to the module control circuit 1568 and / or the bank control circuit 1566 (control lines are omitted for clarity). The sensing amplifier 1478 is connected on top of the current mirror 574 connected to a second voltage VNN (e.g., a negative voltage).

[0073] Figure 15B shows an example of a read operation directed to a first non-volatile memory cell 1552 in a first story (e.g., story 0 cell in Figure 11). In this example, a first voltage VPP (e.g., positive voltage) is connected to the first non-volatile memory cell 1552 via a selected word line by turning on a third switch 1562. A sensing amplifier 1478 and a first voltage VNN (e.g., negative voltage) are connected to the first non-volatile memory cell 1552 via a bit line by turning on a second switch 1560. The first switch 1558 and the fourth switch 1564 are turned off for this read operation. In this configuration, the read current Iread flows through switch 1562, the selected bit line, the first non-volatile memory cell 1552, the selected bit line, switch 1560, and the current mirror 574, as indicated by the dotted arrow. The sensing amplifier 1478 senses a voltage above the current mirror 574 to determine the state of the first non-volatile memory cell 1552.

[0074] Figure 15C shows an example of a read operation directed to a second non-volatile memory cell 1592 in a second story (e.g., cell 1 in story 11). In this example, a first voltage VPP (e.g., positive voltage) is connected to the second non-volatile memory cell 1592 via a selected bit line by turning on a first switch 1558. A sensing amplifier 1478 and a first voltage VNN (e.g., negative voltage) are connected to the second non-volatile memory cell 1592 via a word line by turning on a fourth switch 1564. Switches 1560 and 1562 are turned off for this read operation. In this configuration, the read current Iread flows through switch 1558, the selected bit line, the second non-volatile memory cell 1592, the selected word line, switch 1564, and the current mirror 574, as indicated by the dotted arrow. The sensing amplifier 1478 senses a voltage above the current mirror 574 to determine the state of the second non-volatile memory cell 1592.

[0075] The bank control circuit 1566 and / or module control circuit 1568 (in combination with other control circuits, for example, system control logic 560 / 660) may control the first, second, third, and fourth switches 1558, 1560, 1562, and 1564 such that when reading memory cells from a first story (e.g., story 0), the connection is configured as shown in Figure 15B, and when reading memory cells from a second story (e.g., story 1), the connection is configured as shown in Figure 15C. For example, a control circuit (e.g., bank control circuit 1566, module control circuit 1568, and / or system control logic 560 / 660) can receive the address of a selected non-volatile memory cell and determine the story in which the selected non-volatile memory cell is located from a plurality of stories, including a first story between a first word line layer and a bit line layer (e.g., story 0 between word line 1 1100 and bit line 1110 in Figure 11) and a second story between the bit line layer and a second word line layer (e.g., story 1 between bit line 1110 and word line 2 1120). The control circuit can then apply appropriate voltages to the first, second, third, and fourth switches to perform configuration according to the story in which the non-volatile memory cell is located. The bank control circuit 1566, module control circuit 1568, bit line switch 1554, and word line switch 1556 (either alone or in combination with additional switches such as system control logic 560 / 660) can be considered examples of means for reading non-volatile memory cells located in a plurality of stories, including a first story between a first word line layer and a bit line layer (e.g., story 0 in Figure 11) and a second story between a bit line layer and a second word line layer (e.g., story 1 in Figure 11), and include connecting a sense amplifier to a first selected non-volatile memory cell in the first story via a bit line in the bit line layer (see, for example, Figure 15B), and connecting a sense amplifier to a second selected non-volatile memory cell in the second story via a second word line in the second word line layer (see, for example, Figure 15C).Although the examples in Figures 15B and 15C refer to read operations, any memory access operation (e.g., write operations) can be similarly applied to memory cells in different stories using aspects of this technology.

[0076] Figure 16 shows a simplified schematic diagram of a memory die 1600 implementing an embodiment of the present technology. For example, Figure 16 shows a bit line switch 1554 connected to the bit lines of the memory array 502 via an input / output 506, and a word line switch 1556 connected to the word lines of the memory array 502 via an input / output line 508. The bit line switch 1554 and the word line switch 1556 are connected to a common control circuit 1602, which includes a common sensing amplifier 1604 and a common driver 1606. For example, each sensing amplifier of the common sensing amplifier 1604 may be connected to either a bit line (via the bit line switch 1554) or a word line (via the word line switch 1556), and in this way may be used to sense nonvolatile memory cells of different stories. Similarly, each driver of the common driver 1606 may be connected to either a bit line (via the bit line switch 1554) or a word line (via the word line switch 1556), and in this way may be used to drive appropriate voltages (e.g., VPP and VNN) on the bit line or word line. In this way, the common driver 1606 may be used for read operations directed to memory cells in different stories. Other components of the memory die 1600 may be similar to those of the memory system 500 and will not be described further here. The integrated memory assembly may be implemented using WL switches, bit line switches, and common circuits that may be connected to either (for example, the integrated memory assembly 600 may be configured to include a word line switch 1665, a bit line switch 1554, and a common control circuit 1602).

[0077] Figure 17 shows an exemplary implementation of an aspect of the technology in a data storage system including a core formed from N banks, each bank having n modules. Figure 17 also shows an example of a control circuit that may be used to control a switch connecting a common sense amplifier and / or driver to word lines and bit lines.

[0078] The digital media control circuit 1780 receives address 1782 (e.g., a logic address in a read command directed to one or more nonvolatile memory cells). The digital media control circuit 1780 can use address 1782 to generate location information 1786 (e.g., a physical address) in an appropriate format. For example, location information 1786 may include the bank, module, story, and coordinates (e.g., bit lines and word lines) where the selected nonvolatile memory cell to be read is located (e.g., the memory structure has stories or layers with different characteristics as shown in Figure 11).

[0079] The digital media control circuit 1780 transmits location information 1786 to the bank control circuit 1566. The bank control circuit can use the location information 1786 to determine which story (e.g., the first story, story 0, or the second story, story 1) the nonvolatile memory cell is located in. The bank control circuit 1566 sends signal 1792 to the module control circuit 1568. The module control circuit 1568 generates signals to enable / disable the bit line switches 1554 (e.g., switches 1558 in the first set and switches 1560 in the second set) and the word line switches 1556 (e.g., switches 1562 in the third set and switches 1564 in the fourth set). For example, in the case of a read operation directed to a non-volatile memory cell in the first story, the module control circuit 1568 may generate signals to configure a switch as shown in Figure 15B, and in the case of a read operation directed to a non-volatile memory cell in the second story, the module control circuit 1568 may generate signals to configure a switch as shown in Figure 15C. Figure 17 shows a specific arrangement of components, but the technology is not limited to any specific arrangement and can be implemented using a wide range of components.

[0080] Figure 18A shows an example of a method that includes receiving a first address of a first selected nonvolatile memory cell at the intersection of a first word line and a first bit line in a nonvolatile memory cell structure 1820 (e.g., the lower cell in Figure 11), determining that the first selected nonvolatile memory cell is in a first story 1822 (e.g., story 0), and, in response to determining that the first selected nonvolatile memory cell is in a first story, connecting a sensing amplifier to the first bit line (e.g., as shown in Figure 15B) to read out the first selected nonvolatile memory cell 1824. The method further includes receiving the second address of a second selected nonvolatile memory cell at the intersection of a first bit line and a second word line in a nonvolatile memory cell structure 1826 (e.g., the upper cell in Figure 11), determining that the second selected nonvolatile memory cell is in a second story (e.g., story 1) 1828, and, in response to determining that the second selected nonvolatile memory cell is in a second story, connecting a sensing amplifier to the second word line (e.g., as shown in Figure 15C) to read out the second selected nonvolatile memory cell 1830.

[0081] Figure 18B shows method steps that may be performed alone or in combination with the steps shown in Figure 18A. These steps include reading a first non-volatile memory cell by passing a first current through a first word line, a first non-volatile memory cell, a first bit line, and a current mirror 1840 (e.g., Iread in Figure 15B); sensing the first non-volatile memory cell with a sensing amplifier and passing a first current 1842 by comparing a sensing voltage between the first bit line and the current mirror with a reference voltage; reading a second non-volatile memory cell by passing a first current through a first bit line, a second non-volatile memory cell, a second word line, and a current mirror 1844 (e.g., Iread in Figure 15C); and sensing a second non-volatile memory cell with a sensing amplifier, which includes comparing a sensing voltage between the second word line and the current mirror with a reference voltage while passing a first current 1846.

[0082] The embodiments of the memory device presented above utilize a crosspoint architecture in which each MRAM cell is constructed in the cross-sectional area between a vertical bit line (on one level) and a horizontal word line (constructed above or below). To conserve die size, embodiments may utilize an architecture that allows CMOS selection transistors to be located below the memory array. Accessing a given memory cell requires charging one of several (e.g., 256, 512, 1024, or 2048) bit lines and word lines through a set of selection transistors in a decoder (multiplexer) circuit, such as within the row control circuits 520 / 620 and column control circuits 510 / 610 in Figure 3 or 4. As described above, embodiments of the MRAM crosspoint array utilize both positive and negative bias levels. The following description presents embodiments of such bipolar decoder circuits. The exemplary embodiments used in this description relate to a crosspoint MRAM memory in which the decoder circuit is located beneath the memory cells on the same die as the memory cells, but can be applied more generally to other embodiments such as those based on other programmable resistive elements such as ReRAM, FeRAM, RRAM, or PCM memory cells, and embodiments in which the decoder circuit is formed around the memory array or on a separate control die, as in the embodiment of Figure 4.

[0083] Next, the decoder circuit and its requirements are described. A decoder is a multiplexing circuit that provides a unique connection (and current delivery capability) to each of the lines it drives. In an exemplary embodiment, a bit-line decoder drives one of 1024 bit lines, and a word-line decoder drives one of 1024 word lines. In a crosspoint structure, the decoder may be the same in both cases. In the inactive state, a deselector transistor drives the bit line and word line to ground (0V). To program the MRAM cell (i.e., to change its state from logic 1 to logic 0, or vice versa), current must flow from the bit line to the word line, or vice versa. As a result, the decoder must be able to source current (when driving a line positively) and sink current (when driving a line negatively). The cell is bipolar. Therefore, the decoder must be bipolar.

[0084] Figures 19A and 19B present one embodiment of a bipolar decoder, where the two figures show different parts of the circuit and together constitute one embodiment of the circuit. The decoder includes a positive decoding path (above the upper dashed horizontal line), a ground decoding path (between the dashed horizontal lines), and a negative decoding path (below the lower dashed line). Figures 19A and 19B relate to a bit-line decoder, but a word-line decoder can be configured similarly. In the exemplary embodiment shown, hierarchical decoding is used first at the "pane" (i.e., crosspoint array section) level, then at the global level, and finally at the local level. Considering pane selection, the local control signal 1911 is connected to a positive pane selection PMOS switch PPS 1913 and a positive pane deselection NMOS switch PPD 1915 to supply a bias level pos_MUX to the pos_pane supply line when a pane is selected (low local value), which is supplied to 32 global selections (in this example). The positive bias level pos_MUX depends on the operation being performed. Global Positive Selection Switch GPS <0> 1903-0~GPS <31> 1903-31 is connected to the pos_pane and receives their enable signal pos_global_enb (where 1903 is a PMOS, so "b" represents a bar or inverter) via a set of inverters / drivers from the level shifter 1901 from the termination circuit 1900, and supplies the corresponding pos_global signal to the 32 local select switches (in this example as well). The pos_global line is connected to the global positive deselect switch GPD. <0> 1905-0~GPS <31> It is connected to ground via 1905-31 and receives local control signal 1907.

[0085] Each positive global supply line pos_global for each global select / deselect switch GPS 1903 / GPD 1905 is connected to the corresponding set of bit lines via a local positive select switch. For example, as shown in Figures 19A and 19B, GPS <0> The pos_global line from 1903-0 is connected to the respective local positive selection switch LPS. <0> 1925-0~LPS <31> Local bit line LBL via 1925-31 <0> ~LBL <31> Connected to GPS <31> The pos_global line from 1903-31 is connected to the respective local positive selection switch LPS. <0> 1927-0~LPS <31> Local bit line LBL via 1927-31 <991> ~LBL <1023> It is connected to, and other bit lines not shown are connected in the same way. The control signal for the local positive select switch (pos_local_enable) is again provided from the level shifter 1921 in the termination circuit 1900 through a set of drivers in the termination circuit 1900. An additional driver / inverter 1923 is for each of the 32 local positive control signals for the local positive select switch pos_local_enb to drive the PMOS select gate, and as will be further described below, the additional driver / inverter 1923 is located near the actual switch. The positive and negative local deselector signals are part of the ground decoding path of the termination circuit 1900. For the positive decoding side, the level shifter 1941 provides the positive deselector enable signal (pos_desel_en) via a set of drivers / inverters to the GPS <0> For the bit lines supplied by 1903-0, PMOS LPD <0> 1947-0~LPD <31> Provided to the 1947-31 local positive deselection switch, GPS <31> For the bit lines supplied by 1903-31, PMOS LPD <0> 1949-0~LPD <31> Provides local positive deselector switch for 1949-31.When a bit line is deselected, regardless of whether positive or negative is used for the selected bit line, the deselected bit line is set to ground, so an additional set of driver / inverter 1945s are again placed around the array to generate an inverted desel_enb from pos_desel_en and from the negative deselection enable signal neg_desel_en from the level shifter 1943. Thus, in this exemplary embodiment, there is one pane selection (PPS) fed into 32 global selections (GPS). Each global selection is fed into 32 local selections (LPS), resulting in 1024 unique bit line connections. In the off / idle state, the deselections (PPD, GPD, LPD) drive grounding to each level in the decoding path.

[0086] Considering the remainder of the negative portion of the decoder, the negative decoding path mirrors the positive decoding path and is laid out similarly, but the selection here is between ground and the negative voltage neg_MUX for selected operation, the negative voltage is selected through an NMOS device, and the deselection connection to ground is done through a PMOS device. More specifically, pane level selection connects the line neg_pane to ground via NPD 1993 or to neg_MUX by NPS 1995 based on the local control signal 1991. Global decoding to provide the neg_global signal, if selected, is performed by switching the NMOS GNS based on the control signal neg_global_en from level shifter 1981. <0> 1985-0~GNS <31> Executed by 1985-31, and when deselected, the PMOS switch GND based on local control signal 1987. <0> 1983-0~GND <31> This is performed by 1983-31. For local decoding of local bit lines, deselection is as described above for the positive decoding side. To decode the selected local bit line, the control signal neg_local_enb is provided by level shifter 1961 through a set of driver / inverters, which include an extra relative driver / inverter since the switch here is NMOS. The neg_local_en signal is then generated again by driver / inverter 1963, which is located closer to the decoding switch. Next, the negative local enable signal is used by GNS <0> Switch LNS for local switches supplied by 1985-0 <0> 1965-0~LNS <31> It was supplied to the control gates of 1965-31 and GNS <0> Switch LNS for local switches supplied by 1985-31 <0> 1967-0~LNS <31> The same applies to the 1967-31 control gate and other switches not shown.

[0087] Figure 20 shows one embodiment of a triple-well transistor that can be used in the decoder switch of Figures 19A and 19B. A triple-well transistor is used because the negative decoding path side passes a negative voltage (e.g., -2.5 V). In Figure 20, PMOS 2030 is located between a pair of triple-well NMOS 2010 and 2050 on a deep N-well 2003 in a P substrate 2001. The PMOS switch 2030 includes a control gate 2031 that has a p+ region on either side of the N-well 2033 and n+ taps on both sides of the p+ region. The N-well 2033 of the PMOS 2030 and the deep N-well 2003 of the triple-well NMOS are short-circuited. The triple-well NMOS 2010 / 2050 have their respective control gates 2011 / 2051 on the isolated P-well regions 2013 / 2053. There are n+ regions on both sides of the NMOS control gates, and p+ taps on both sides of those. Within the P-substrate 2001, and above the deep N-well 2003 outside the triple-well NMOS 2010 and triple-well NMOS 2080, are the respective N-wells 2080 and 2090, each having n+ taps. This arrangement can be used in both the bit-line decoding circuits in Figures 19A and 19B, as well as in word-line selection circuits which may have a similar structure.

[0088] Figure 21 is an embodiment of the decoder floor plan shown in Figures 19A and 19B. This example shows a bit-line decoder, but a similar arrangement can be used for a word-line decoder or decoder layer, as will be described below with respect to Figure 23. In this example, the decoder drives 1024 lines, with 512 lines driven from the left and the other 512 lines driven from the right. Instead of grouping all NMOS and PMOS devices together as shown in Figure 20, different device types are separated to accommodate an exemplary embodiment of the array-via hookup strategy.

[0089] More specifically, as shown in the diagram, the global selection decoder is located in the center, and half of the local selection decoders are located on either side. Each set of these decoders is divided into an NMOS, negative selection region (dotted region) and a PMOS, positive selection region. In this example, half of the NMOS local negative selection (LNS) switches are in the center and are again divided in half, into a left portion 2101A with 256 switches and a right portion 2101B with 256 switches, and the corresponding set of 16 global negative selection (GNS) 2121 is located between the two sides. On either side of the LNS arrays 2101A and 2101B on the edge of the switch array are the local driver / inverter 2141A and 2141B, corresponding to element 1923 8 in Figure 19A, enabling clearly defined control signal levels.

[0090] Half of the PMOS local positive selection (LPS) switches are located above the central LNS region, and the other half is located below, which is then divided in half again, resulting in the left portion 2107A and the right portion 2107B of 256 switches above, and the left portion 2109A and the right portion 2109B of 256 switches below. The corresponding sets of 16 global positive selection (GPS) switches 2127 and 2129 are located between the two sides. On both sides of the LPS arrays 2107A / 2107B and 2109A / 2109B on the edge of the switch array are the corresponding local driver / inverter 2147A / 2147B and 2149A / 2149B corresponding to element 1963 8 in Figure 19A.

[0091] The remaining half of the NMOS LNS switch is again divided in half, and again into a left half and a right half, with 128 NMOS LNS switches 2115A / 2115B on top, with the corresponding GNS switch 2135 in between and the corresponding edge driver / inverter 2155A / 2155B on either side, and 128 NMOS LNS switches 2117A / 2117B on top, with the corresponding GNS switch 2137 in between and the corresponding edge driver / inverter 2157A / 2157B on either side. The PMOS Local Positive Deselection (LPD) is then divided into four groups, further divided into left and partial divisions, and placed between the LNS block and the LPS block, and again the corresponding edge position drivers are placed on both sides, with 2103A / B and 2143A / B above the central LNS block, 2105A / B and 2145A / B below the central LNS block, 2111A / B and 2151A / B above the upper LPS block, and 2113A / B and 2153A / B below the lower LPS block. Figure 21 and the related figures below are examples, but other embodiments can switch the arrangement of NMOS LNS blocks and PMOS LPS blocks (along with the corresponding GNS / GPS and driver blocks), and the number of drivers within each block, which is a trade-off between block layout size and routing optimization.

[0092] Figures 22 and 23 illustrate one embodiment for hooking up the positions of array vias connecting a decoder circuit to the word lines and bit lines of the associated crosspoint array (or pane). Figures 22 and 23 are two-story crosspoint arrays, as in the embodiment of Figure 7D. In Figure 22, the word line layer WL1 2203 is above the bit line layer 2205, and the bit line layer 2205 is above the word line layer 2201 of story 0. Figure 22 is oriented so that the bit lines of layer 2205 enter the page and the word lines of layers 2201 and 2203 extend from left to right. Three memory cells are shown in each story, the leftmost of which is labeled memory cell 1 2111 and selector OTS 1 in story 1, and memory cell 0 2117 and selector OTS0 in story 0. The bit lines of layer BL 2205 and the word lines of layers WL0 2201 and WL1 2203 must be connected to corresponding sets of decoders, such as the decoders for the bit lines shown in Figures 19A, 19B, and 20, and similar sets of decoders for each of the word line layers. Because the bit lines and word lines have different orientations, the corresponding decoders must also be oriented differently. The corresponding sets of vias connect the bit line layer and the word line layer to a set of metal layer contacts m5 connected to the decoder circuit as shown in Figure 24, providing bias levels to the word lines and bit lines.

[0093] Figure 23 shows one embodiment for the orientation of three decoders for word line layer 0 2301, bit line layer 2305, and word line layer 1 2303. Although Figure 23 shows these decoders side by side, in exemplary embodiments they may be arranged one above the other. For example, in one set embodiment, the decoders are below an array represented by dashed block 2323, and the vias in Figure 22 connect the decoders below. In one embodiment, such as Figure 4, the decoder layers are on a control die 611, which is then connected by m5 contacts. Decoder layers 2301, 2305, and 2303 may be arranged in the same order as the word line layers and bit line layers, with the bit line layer 2303 in the center, or in other ways, depending on the embodiment. The orientation of the word lines (WL) in word line layer 0 decoder 2301 and layer a 2303 decoder extends from left to right, as in Figure 22, and the decoders are connected in the central dotted area (represented by black dots) where the m5 connectors are located. The orientation of the bit lines (BL) within the bit line layer decoder 2305 extends vertically, corresponding to the top view in Figure 22, and the decoder is connected in the central dotted area (represented by black dots) where the m5 connector is located.

[0094] To provide all the bias conditions for memory operation, each bit line and word line must be connected to a positive local selection (LPS), negative local selection (LNS), and local deselection (LPD) from the corresponding decoder. The minimum design rule does not allow a single interconnection layer, and consequently, two layers (metal layers 4 and 5, m4 and m5) are used to connect the selection transistors to the array vias. To accommodate this, NMOS and PMOS transistors are separated. Figure 24 is a side view of these connections.

[0095] Figure 24 is a side view of one embodiment of a different decoder block in Figure 21, showing how they connect to the m5 metal layer in Figure 22. With respect to Figure 21, Figure 24 is a side view, although it is also oriented from top to bottom. NMOS LNS block 2401 can correspond to blocks 2115A and 2115B in Figure 21. PMOS LPD block 2403 can correspond to blocks 2111A and 2111B. PMOS LPS block 2405 can correspond to blocks 2107A and 2107B, and PMOS LPD block 2407 can correspond to blocks 2103A and 2103B. NMOS LNS blocks 2409 and 2411 can both correspond to 2101A and 2101B, and as shown below with respect to Figure 25, NMOS LNS selection blocks 2101A and 2101B are below the hookup region, and their routing extends in different directions. Similarly, PMOS LPD block 2413 can correspond to blocks 2105A and 2105B. PMOS LPS block 2415 can correspond to blocks 2109A and 2109B. PMOS LPD block 2417 can correspond to blocks 2113A and 2113B, and NMOS LNS block 2419 can correspond to blocks 2117A and 2117B.

[0096] The upper half of the blocks in Figure 24 can correspond to even bit lines, and the lower half of the blocks can correspond to odd bit lines. Each decoder block is routed to the m4 metal layer through connections with brighter dots, and then routed to the m5 metal layer through connections with darker dots, which then connects to array vias as shown in Figures 22 and 23. (Regarding the naming of m4 and m5, in one set of embodiments, a smaller number of metal layers are used to form the decoder, and the routing layers are labeled here as m4 and m5.) For routing, the decoder blocks are grouped in different layers, with halves of blocks 2401, 2403, and 2405 grouped in section 2421 of the m5 layer and then grouped to the upper set of array vias. The other halves of 2405, 2407, and 2409 are grouped in section 2425 of the m4 layer and then grouped to the second set of array vias. Half of 2411, 2413, and 2415 are grouped into section 2417 of the m4 layer, and then into a third set of array vias, while the other half of 2415, 2417, and 2419 are grouped into section 2423 of the m5 layer, and then into the lower set of array vias. A top view of this routing is shown in Figure 25.

[0097] Figure 25 replicates the decoder of Figure 21, but with some of the routing from Figure 24 shown in the top view added. Hookup regions 2501A and 2501B correspond to the hookup regions of bit line layer 2305 in Figure 23. Hookup regions 2501A and 2501B span the width of their respective NMOS LNS regions 2101A and 2101B, and these switches are gaps on the GNS region 2121 as they supply local switches rather than being directly connected to memory array vias. Sections of the m4 and m5 metal layers are shown as 2503, which cover the entire local selection decoding switch, but only a portion is shown as 2503 for clarity. By centralizing the hookup regions 2501A and 2501B, the amount of routing can be minimized, thereby simplifying the structure and reducing RC delay along the lines because the lines are shorter compared to having hookups on the edges.

[0098] Figure 26 is a detail of the lower left quadrant of Figure 25 to show the routing, showing only the lower parts (as shown in the figure) of local selection blocks 2117A, 2113A, 2109A, 2105A, and 2101A. In the hookup region, the array vias are arranged so that the m5 layer is attached to the array via, as shown in Figure 24. The m4 and m5 lines extend downward across local selection blocks 2117A, 2113A, 2109A, and 2105A. As is clearer in Figure 25 and more so in Figure 26, the black rectangle along the line 2503 is the connection of local selection blocks 2109A (upper half), 2105A, and 2101A, which is connected along m4 as shown in Figure 24, then connected to one of the m5 connection regions, and then connected to the array via. The dotted rectangle along line 2503 is connected along m5 as shown in Figure 24, and then the connections of local selection blocks 2109A (lower half), 2113A, and 2117A are connected to array vias.

[0099] Figure 27 is a flowchart of one embodiment for forming a memory device including the decoder structure shown in Figures 19A to 26. The flow begins in step 2701 by forming a bipolar decoder circuit for a first set of control lines of a crosspoint memory array (i.e., a first of either the bit lines or the word lines), and the memory cells are connected between the first set of control lines and a second set of control lines (i.e., the other of the bit lines and the word lines). Examples of crosspoint array structures may be those described above with respect to Figures 7A to 7D. The bipolar decoder has both a positive voltage selector switch and a negative voltage selector switch, including a local positive selector switch and a local negative selector switch, which can be laid out as in the embodiment of Figure 21. Both the local positive selector switch and the local negative selector switch may be formed on the die in steps 2703 and 2705 as part of the same CMOS manufacturing method, and they are typically formed as part of the same manufacturing process.

[0100] In step 2703, the positive voltage selector switches are configured to supply positive voltage levels to a first set of control lines, as described with respect to Figures 19A and 19B for an example of a bit line decoder. Formed on the die and shown in Figure 21, the positive voltage selector switches have a first subset of PMOS LPS switches 2107A and 2107B, and a second subset of PMOS LPS switches 2109A and 2109B. Between and on either side of the LPS switch subsets are a subset of negative selector switches. These are formed in step 2705, which can be performed concurrently with step 2703, and supply negative voltage levels to the first set of control lines. Although not included in the flow chart of Figure 27, exemplary embodiments also form a set of PMOS LPD deselector switches between the set of positive selector switches and the set of negative selector switches, as shown in the embodiment of Figure 21.

[0101] In step 2707, routing is performed for connecting the switches. In the embodiments of Figures 22 to 26, these are metal wire layers m4 and m5 that connect each of the local selection switches to the m5 layer connections in hookup regions 2501A and 2501B. In step 2711, the connections in the hookup regions are connected to the crosspoint array, and in particular to the array vias in the above example. Depending on the embodiment, step 2711 may include forming the array on top of the decoder structure, or, in one embodiment such as Figure 4, bonding the memory die to the control die on which the decoder is formed.

[0102] Referring back to the bipolar decoder embodiment in Figures 19A and 19B, in this example there are a total of 144 unique input control signals for each decoder. pos_global_enb<31:0> neg_global_enb<31:0> pos_local_en<31:0> neg_local_enb<31:0> pos_desel_en<7:0> neg_desel_en<7:0> Each of these control signals for each decoder requires its own routing lines, which can consequently consume a significant amount of memory used by the control circuit. Therefore, decoding the entire memory die requires a large amount of routing, and it would be beneficial to reduce the amount of routing. The following presents embodiments for reducing such routing requirements.

[0103] To take a specific embodiment of the structure of the crosspoint array, it can be arranged such that the smallest accessible unit is a “module”. In this example, a module may consist of eight panes, which were the highest level of decoding in the embodiments of Figures 19A and 19B. For the above decoding values, this provides a module containing 4K bit lines and 4K (2K upper story, 2K lower story) word lines. Figure 28 shows one embodiment of the decoder arrangement of the module.

[0104] Figure 28 shows one embodiment of the module's decoder floor plan. The module includes eight panes 2821–2828, whose footprint is represented by white squares. Decoding of 4K bit lines is handled by four bit line decoders 2801, 2803, 2805, and 2807, represented by light dots. Decoding for 4K word lines is handled by two lower story decoders 2811 and 2813 and two upper story decoders 2815 and 2817. As described with respect to Figure 23, the hookup area of ​​each decoder is represented by darker dots. In the arrangement of Figure 28, the bit lines extend vertically and beyond the bit line decoders, and the word lines of both stories extend from left to right and again beyond the word line decoders. This arrangement translates to 1,024 unique gate controls per module, which, under typical manufacturing capabilities, requires a larger metal footprint for the desired module size. In one embodiment, the control circuit is formed on or beneath the same die as the crosspoint structure, or in another embodiment, it is formed on a separate control die bonded to the memory die. In such cases, the height and width of the module are better defined by the number of bit lines / word lines (the footprint of the memory array) rather than by the underlying CMOS or interconnect structure.

[0105] Referring back to Figure 25, edge drivers / inverters such as 2155A / 2155B are positioned along both sides of the decoder. Under the arrangement in Figure 28, this allows the inner edge driver / inverter of bit-line decoder 2801 to be aligned with the outer edge driver / inverter of bit-line decoder 2803, the outer edge driver / inverter of bit-line decoder 2805 to be aligned with the inner edge driver / inverter of bit-line decoder 2807, and the inner edge drivers / inverters of word-line decoders 2811, 2813, 2815, and 2817 to be aligned. This arrangement allows a single decoding line to be shared by multiple sub-decoders. Figure 29 presents one embodiment for reducing the overall number of metals by driving multiple decoders for a given input signal.

[0106] Figure 29 shows one embodiment for routing control signals across the decoders of a module. Figure 29 shows only the local positive enable selection and local positive deselection signals for the decoders in Figures 19A and 19B, but negative selection signals are arranged similarly. Figure 29 repeats the elements of Figure 28, such as bit-line decoders 2801, 2903, 2805, and 2807, and word-line decoders 2811, 2813, 2815, and 2817. Control signals are sent across the module where the global selection gate is driven directly, but local selection uses inverters / drivers embedded within the decoder to improve signal integrity, such as inverter 2901 driving line 2903 of bit-line decoder 2801. Referring back to Figure 19A, these embedded inverters could correspond to inverters 1923, 1945, and 1963. By arranging these inverters along the outer edge of the decoder, control signals can be easily shared across multiple decoders.

[0107] For example, the right edge of bitline decoder 2801 and the left edge of bitline decoder 2803. This allows the vertical bitline signals pos_LBL_en<31:16> and pos_LBLd_en<7:4> to extend across the inverters of the two decoders along these edges, and as a result they can be used for the inverters / drives of both decoders, so that both marked with X (2921 and 2923) use a single line. Similarly, inverters along the right edge of 2803 and the left edge of 2805, also marked with X, can share local decoded signals, as can those along the right edge of 2805 and the left edge of 2807. Since neither the left edge of decoder 2801 nor the right edge of decoder 2807 overlaps with each other or with other bitline decoders, each needs to receive the same decoded signals separately. Since each bitline decoder shares a set of local decoded signals with another bitline decoder, these pairs need to be distinguished by additional decoded signals, such as a global selection signal or pane selection signal. For example, global bitline selection lines can run perpendicular to local selection lines. If global bitline selection lines extend horizontally across the decoders, they can be used to distinguish between the upper pair of bitline decoders 2801 and 2805 and the lower pair of bitline decoders 2803 and 2807.

[0108] Figure 30 is a flowchart of one embodiment for forming the decoder arrangement of Figures 28 and 29. Step 3000 is to form bit line and word line decoder circuits for the bit line and word line of the crosspoint memory array on the die. The decoding formation in step 3000 includes forming sub-decoders for the bit line in steps 3001 and 3003 and sub-decoders for the word line in steps 3005 and 3007, which can be manufactured according to various CMOS processing operation flows.

[0109] Steps 3001 and 3003 form first and second bit-line sub-decoders, respectively, which decode the corresponding first and second ranges of bit lines. Referring to Figures 28 and 29, these may be decoder 2801 covering bit lines BL0 to BL1023 and decoder 2803 covering bit lines BL1024 to BL2047. Steps 3001 and 3003 include forming selection switches and inverters such as 2921 and 2923 connected to drive these switches. The drivers are located on the left and right edges of sub-decoders 2801 and 2803, and (in this example) the drivers along the left edge of sub-decoder 2801 and the right edge of sub-decoder 2803 are aligned vertically. This allows, in step 3009, selection enable lines to extend vertically over the aligned inverters and connect to them, enabling selection of the inverter / driver in each of the sub-decoders with a single line.

[0110] Steps 3005 and 3007 form first and second word line sub-decoders, respectively, which decode the corresponding first and second ranges of the word line. Referring to Figures 28 and 29, these may be decoder 2811, which covers bit lines WL0 to WL1023, and decoder 2813, which covers bit lines WL1024 to BL2079. Steps 3005 and 3007 include forming selection switches and inverters such as 2911 and 2913 connected to drive these switches. The drivers are located on the upper and lower edges of sub-decoders 2811 and 2813, and (in this example) the drivers along the upper edge of sub-decoder 2811 and the lower edge of sub-decoder 2813 are aligned in the left-right direction. This makes it possible in step 3011 for selection enable lines to extend in the left-right direction over the aligned inverters and connect to them, so that a single line can select the inverter / driver in each of the sub-decoders.

[0111] In one embodiment, as shown in Figure 3, where the control circuit for the memory array 502 is formed on the same die 500, a crosspoint array can be formed on the control circuit including the decoder in step 3020. In one embodiment, such as Figure 4, where the control circuit for the memory array 602 is formed on the memory die 601 and the control circuit is formed on the control die 611, a die having the crosspoint array can be joined to the control die including the decoder in step 3020.

[0112] According to a first set of embodiments, the non-volatile memory device comprises a control circuit configured to be connected to an array comprising a first plurality of non-volatile memory cells, wherein each of the first plurality of memory cells has a crosspoint structure connected between one of a plurality of first control lines extending in a first direction and one of a plurality of first second control lines extending in a second direction. The control circuit comprises a first control line decoder disposed on a die and connected to the array, configured to selectively bias the first control lines, the first control line decoder comprising a first first control line subdecoder comprising a first set of first control line selection switches configured to bias a first range of the first control lines, and a plurality of inverters connected along both edges of the first first control line subdecoder in a second direction to drive the first set of first control line selection switches. The first control line subdecoder also comprises a second first control line subdecoder comprising: a second set of first control line selector switches configured to bias a second range of the first control lines; and a plurality of inverters connected along both edges of the second first control line subdecoder in a second direction to drive the second set of first control line selector switches, wherein the inverter along one of the edges of the first first control line subdecoder is aligned in a first direction on the die with the inverter along one of the edges of the second first control line subdecoder.

[0113] According to another set of embodiments, the method involves forming decoder circuits on a first die for bit lines and word lines of a crosspoint memory array of non-volatile memory cells connected between one of the bit lines and one of the word lines, comprising: forming a first bit line subdecoder having a selection switch configured to bias a first range of bit lines, and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias a first range of bit lines; and forming a second bit line subdecoder having a selection switch configured to bias a second range of bit lines, and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias a second range of bit lines, wherein the inverters along one of the edges of the first bit line subdecoder The invention includes forming a first word line subdecoder having a selection switch configured to bias a first range of word lines and a plurality of inverters along opposing edges in a second direction connected to drive the selection switch configured to bias a first range of word lines, wherein the inverter along one of the edges of the first word line subdecoder is aligned in a first direction with an inverter along one of the edges of the second word line subdecoder.

[0114] In another set of embodiments, the memory device comprises a non-volatile memory cell structure including a plurality of non-volatile memory cells arranged in a crosspoint configuration, each memory cell having a programmable resistive element connected between one of a plurality of bit lines and one of a plurality of word lines, and one or more control circuits connected to the memory cell structure. The one or more control circuits include a bit line decoder, a first bit line subdecoder having a selection switch connected to bias a first range of bit lines and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias a first range of bit lines, and a second bit line subdecoder having a selection switch connected to bias a second range of bit lines and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias a second range of bit lines, wherein the inverter along one of the edges of the first bit line subdecoder is aligned in a second direction with the inverter along one of the edges of the second bit line subdecoder, and A word line decoder comprising: a first word line subdecoder having a selection switch connected to bias a first range of word lines and a plurality of inverters along opposing edges in a second direction connected to drive the selection switch configured to bias a first range of word lines; and a second word line subdecoder having a selection switch connected to bias a second range of word lines and a plurality of inverters along opposing edges in a second direction connected to drive the selection switch configured to bias a second range of word lines, wherein the inverter along one of the edges of the first word line subdecoder is aligned in the first direction with the inverter along one of the edges of the second word line subdecoder.

[0115] For the purposes of this specification, references to “embodiments,” “one embodiment,” “several embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0116] For the purposes of this specification, connections may be direct or indirect (e.g., through one or more other parts). Where it is referred that one element is connected or coupled to another, that element may be directly connected to the other element or indirectly connected to the other element through an intervening element. When it is said that one element is directly connected to another, there is no intervening element between that element and the other element. Two devices are “communicating” if they are connected directly or indirectly so that electronic signals can be communicated between them.

[0117] For the purposes of this specification, the term "based on" may be read as "based at least in part on."

[0118] For the purposes of this specification, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, may not imply an ordering of objects, but rather may be used for identifying purposes to distinguish different objects.

[0119] In this specification, the term “set” of objects may refer to one or more “sets” of objects.

[0120] The detailed description above is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosed form to the exact form. Many modifications and variations are possible in light of the above teachings. The embodiments described have been selected to best illustrate the principles of the proposed art and its practical application, thereby enabling other persons skilled in the art to best utilize it in various embodiments and with various modifications suitable for the specific use to be intended. The scope is intended to be defined by the claims appended herein.

Claims

1. Non-volatile memory device, A control circuit configured to connect to an array comprising a first plurality of nonvolatile memory cells, wherein each of the first plurality of memory cells has a crosspoint structure in which it is connected between one of a plurality of first control lines extending in a first direction and one of a plurality of first second control lines extending in a second direction, and the control circuit comprises, The system includes a first control line decoder, which is positioned on the die, connected to the array, and configured to selectively bias the first control line, wherein the first control line decoder is A first control line subdecoder, A first set of first control line selection switches configured to bias a first range of the first control line, A first control line subdecoder comprising: a plurality of inverters connected to drive a first set of first control line selection switches along both edges of the first control line subdecoder in the second direction; A second first control line subdecoder, A second set of first control line selection switches configured to bias a second range of the first control line, A non-volatile memory device comprising: a second first control line subdecoder, comprising: a plurality of inverters connected along both edges of the second first control line subdecoder in the second direction to drive a second set of first control line selection switches, wherein the inverter along one of the edges of the first first control line subdecoder comprises a plurality of inverters aligned in the first direction on the die with the inverter along one of the edges of the second first control line subdecoder; and a second first control line subdecoder.

2. The non-volatile memory device according to claim 1, wherein the first control line decoder is a bipolar decoder.

3. The aforementioned control circuit is The non-volatile memory device according to claim 1, further comprising a first plurality of first control enable signal lines extending in the first direction on the aligned inverters of the first first control line sub-decoder and the second first first control line sub-decoder.

4. The first plurality of first control enable signal lines are local enable lines, the first set of first control line selection switches and the second set of first control line selection switches are local selection switches, the first first control line subdecoder further comprises the first set of global first control line selection switches, the second first control line subdecoder further comprises the second set of global first control line selection switches, and the control circuit is A first set of global enable signals extending in the second direction along the first control line subdecoder, The non-volatile memory device according to claim 3, further comprising: a second set of global enable signals extending in the second direction on the second first control line sub-decoder.

5. The non-volatile memory device according to claim 1, further comprising the array, wherein the array is arranged on the die on the first control line decoder.

6. The control circuit is formed on a control die, and the non-volatile memory device is The non-volatile memory device according to claim 1, further comprising a memory die including the array, wherein the memory die is separated from the control die and bonded to the control die.

7. The non-volatile memory device according to claim 1, further comprising the array, wherein the memory cell is a magnetoresistive random access memory (MRAM) memory cell.

8. The non-volatile memory device according to claim 1, further comprising the array, wherein the memory cell is a phase-change memory (PCM) memory cell.

9. The first control line is a bit line, the second control line is a word line, and the control circuit is, The system further comprises a word line decoder disposed on the die, connected to the array, and configured to selectively bias the word line, wherein the word line decoder The first word line subdecoder, A first set of word line selection switches configured to bias a first range of the word lines, A first word line subdecoder comprising: a plurality of inverters connected to drive a first set of word line selection switches along both edges of the first word line subdecoder in the first direction; The second word line subdecoder, A second set of word line selection switches configured to bias a second range of the word lines, A non-volatile memory device according to claim 1, comprising: a second word line subdecoder comprising: a plurality of inverters connected to drive a second set of word line selection switches along both edges of the second word line subdecoder in the first direction, wherein the inverter along one of the edges of the first word line subdecoder comprises a plurality of inverters aligned in the second direction on the die with the inverter along one of the edges of the second word line subdecoder.

10. The first bit line subdecoder is adjacent to the first word line subdecoder on the die in the first direction and adjacent to the second word line subdecoder on the die in the second direction. The second bit line subdecoder is adjacent to the first word line subdecoder on the die in the second direction and adjacent to the second word line subdecoder on the die in the first direction. The non-volatile memory device according to claim 9.

11. It is a method, The method involves forming decoder circuits for the bit lines and word lines of a crosspoint memory array of nonvolatile memory cells, each connected between one of the bit lines and one of the word lines, on a first die, A first bit line subdecoder is formed, comprising a selection switch configured to bias a first range of the bit line, and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias the first range of the bit line, A second bit line subdecoder is formed, comprising a selection switch configured to bias a second range of the bit line, and having a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias the second range of the bit line, wherein the inverter along one of the edges of the first bit line subdecoder is aligned in a second direction with the inverter along one of the edges of the second bit line subdecoder. A first word line subdecoder is formed, comprising a selection switch configured to bias a first range of the word line, and a plurality of inverters along the opposing edges in the second direction connected to drive the selection switch configured to bias the first range of the word line, A method comprising forming a second word line subdecoder having a selection switch configured to bias a second range of the word line, and a plurality of inverters along opposing edges in a second direction connected to drive the selection switch configured to bias a second range of the word line, wherein the inverter along one of the edges of the first word line subdecoder is aligned in the first direction with the inverter along one of the edges of the second word line subdecoder.

12. Forming the decoder circuit means The first bit line subdecoder is formed adjacent to the first word line subdecoder on the first die in the first direction, and adjacent to the second word line subdecoder on the first die in the second direction. The method according to claim 11, further comprising forming a second bit line subdecoder adjacent to the first word line subdecoder on the first die in the second direction and adjacent to the second word line subdecoder on the first die in the first direction.

13. Forming the crosspoint memory array on the decoder circuit on the first die, The method according to claim 11, further comprising:

14. Forming the crosspoint memory array on the second die, The first die and the second die are joined together, The method according to claim 11, further comprising:

15. Forming the decoder circuit means To form a plurality of bit line local enable signals extending in the second direction, connected to the aligned inverters of the first bit line subdecoder and the second bit line subdecoder, The method according to claim 11, further comprising forming a plurality of local word line enable signals extending in the first direction, connected on the aligned inverters of the first word line subdecoder and the second word line subdecoder.

16. A memory device, A non-volatile memory cell structure comprising a plurality of non-volatile memory cells arranged in a crosspoint configuration, wherein each memory cell has a programmable resistive element connected between one of a plurality of bit lines and one of a plurality of word lines, The memory cell structure comprises one or more control circuits connected to the memory cell structure, and the control circuits are A bitline decoder, A first bit line subdecoder comprising a selection switch connected to bias a first range of the bit line, and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias the first range of the bit line, A bit line decoder comprising: a second bit line subdecoder having a selection switch connected to bias a second range of the bit line, and a plurality of inverters along opposing edges in a first direction connected to drive the selection switch configured to bias the second range of the bit line, wherein the inverter along one of the edges of the first bit line subdecoder is aligned in a second direction with the inverter along one of the edges of the second bit line subdecoder; It is a word line decoder, A first word line subdecoder having a selection switch connected to bias a first range of the word line, and a plurality of inverters along the opposing edges in the second direction connected to drive the selection switch configured to bias the first range of the word line, A second word line subdecoder comprising a selection switch connected to bias a second range of the word line, and a plurality of inverters along opposing edges in a second direction connected to drive the selection switch configured to bias the second range of the word line, wherein the inverter along one of the edges of the first word line subdecoder is aligned in the first direction with the inverter along one of the edges of the second word line subdecoder, A memory device comprising a word line decoder, including a word line decoder.

17. The memory device according to claim 16, wherein the programmable resistor element is a magnetoresistive random access memory (MRAM) device.

18. The memory device according to claim 16, wherein the programmable resistor element is a phase-change memory device.

19. The first bit line subdecoder is adjacent to the first word line subdecoder on the first die in the first direction and adjacent to the second word line subdecoder on the first die in the second direction. The second bit line subdecoder is adjacent to the first word line subdecoder on the first die in the second direction, and adjacent to the second word line subdecoder on the first die in the first direction. The memory device according to claim 16.

20. The one or more control circuits described above are A plurality of bit line local enable signals extending in the second direction, connected to the aligned inverters of the first bit line subdecoder and the second bit line subdecoder, The memory device according to claim 16, further comprising: a plurality of local word line enable signals extending in the first direction, connected to the aligned inverters of the first word line subdecoder and the second word line subdecoder.

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