Burst mode of flyback power converters

Abstract

This invention provides a flyback power converter that improves burst mode operation. [Solution] The efficiency of the power converter is improved by setting an upper limit on the number of pulses delivered in a given burst packet and limiting power delivery by providing a fixed delay. To reduce switching losses, pulses are delivered between signal dips at the switching terminals of the switching elements. A frequency clamp circuit is also provided to ensure that the switching frequency does not exceed a predetermined threshold frequency. A device designed to implement improved burst operation includes a burst control circuit, a pulse control circuit, a delay control circuit, and a latch.

Description

Cross-reference of related applications

[0001] This application claims the interests of U.S. Provisional Patent Application No. 63 / 685,077, filed on 20 August 2024, which is incorporated herein by reference in its entirety. [Patent Document 1] U.S. Provisional Patent Application Number 63 / 685,077 [Technical Field]

[0002] This document relates to power converters, and more particularly to the burst mode of flyback power converters. [Background technology]

[0003] A flyback power converter is a switch-mode power supply that converts an AC or DC input voltage into one or more regulated DC output voltages. A flyback converter topology generally includes an input capacitor, a primary-side switching element (e.g., a metal-oxide-semiconductor field-effect transistor, i.e., a MOSFET), a coupled inductor called a flyback transformer, an output diode or rectifier, and an output capacitor. The transformer allows for energy storage, energy transfer, and galvanic isolation between the input and any output. The turns ratio of the primary and secondary windings of the transformer can be set so that the output voltage is lower or higher than the input voltage. In operation, when the primary-side switching element is closed (on time), the primary winding of the transformer is connected to the input voltage, increasing the primary current and thus storing energy in the transformer gap or core. During this on time, the output diode is reverse-biased and turned off, and the output capacitor supplies the load current. When the primary switching element is open (off time), the transformer's energy is transferred to the secondary side, and current flows through the output diode, which is forward-biased during this time, thereby replenishing the output capacitor and supplying load current. During this process, the transformer core is demagnetized, so the secondary current decreases. Some flyback converters use auxiliary transformer windings for trough sensing and overvoltage protection, as well as to generate an undervoltage bias power supply. Flyback power converters still have several significant problems. [Overview of the project]

[0004] In one example, the device includes a burst control circuit configured to receive a feedback voltage from a power converter and generate a burst enable signal; a pulse control circuit configured to receive the burst enable signal and a voltage signal from the current terminal of the switching element of the power converter; a delay control circuit configured to initiate a delay time; and a latch. The pulse control circuit is further configured to determine the timing between pulses delivered to the control terminal of the switching element and to assert the pulse enable signal. The delay time is initiated by the delay control circuit in response to the number of delivered pulses reaching a maximum pulse threshold. The latch is designed to receive the pulse enable signal and the pulse reset signal and to output pulses to the control terminal of the switching element.

[0005] In another example, the control circuit includes a valley count circuit configured to count the number of valleys detected in a received voltage signal, a frequency clamp circuit configured to determine whether the burst frequency corresponding to the time of the currently detected valley is lower than a threshold frequency, and one or more logic gates. The valley count circuit also asserts a valley enable signal when it has counted one or more valleys in the received voltage signal. The frequency clamp circuit also asserts a clamp signal in response to the burst frequency being lower than a threshold frequency. One or more logic gates are designed to receive at least the valley enable signal and the clamp signal and assert a pulse enable signal at the output terminal of one or more logic gates.

[0006] In another example, the device includes a burst control circuit configured to receive a feedback voltage from a power converter and generate a burst enable signal, a control circuit configured to receive the burst enable signal and a voltage signal from the current terminal of the switching element of the power converter, and a digital storage element. The control circuit is further configured to determine the timing between pulses delivered to the control terminal of the switching element, assert a pulse enable signal to deliver pulses, count the number of delivered pulses, and determine whether the number of delivered pulses is less than a maximum pulse threshold. The digital storage element receives the pulse enable signal and is configured to output pulses to the control terminal of the switching element.

[0007] In another example, a method includes delivering a first pulse to a control terminal of a switching element in a first time period, detecting a first dip in a switching signal sampled at the current terminal of the switching element in a second time period, and determining whether a first burst frequency associated with the time difference between the first time and the second time period is lower than a threshold frequency. In response that the first burst frequency is lower than the threshold frequency, the method includes delivering a second pulse to the control terminal of the switching element in a second time period. In response that the first burst frequency is higher than the threshold frequency, the method includes detecting a second dip in the switching signal in a third time period, determining whether a second burst frequency associated with the time difference between the first time and the third time period is lower than a threshold frequency, and delivering a second pulse to the control terminal of the switching element in a third time period in response that the second burst frequency is lower than the threshold frequency. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram of a flyback power converter system, including a control circuit configured to provide burst mode operation in one example, is shown.

[0009] [Figure 2] The block diagram of a flyback power converter control circuit configured to provide burst mode operation in one example is illustrated.

[0010] [Figure 3] The schematic diagram of the burst control circuit of the control circuit of FIG. 2 in one example is illustrated.

[0011] [Figure 4] The schematic diagram of the pulse control circuit of the control circuit of FIG. 2 in one example is illustrated.

[0012] [Figure 5] The schematic diagram of the frequency clamp circuit of the pulse control circuit of FIG. 4 in one example is illustrated.

[0013] [Figure 6] The schematic diagram of the delay control circuit of the control circuit of FIG. 2 in one example is illustrated.

[0014] [Figure 7] In one example, a graph of the signals generated by the system of FIG. 1 during burst mode operation is illustrated.

[0015] [Figure 8] The flowchart of a method for burst mode in a flyback power converter in one example is illustrated.

[0016] [Figure 9] The block diagram of a system including a flyback power converter in one example is illustrated.

Embodiments for Carrying Out the Invention

[0017] This specification describes a technique for providing burst-mode operation of a flyback power converter. This technique provides a burst mode in which voltage pulses are delivered to switching elements with reduced or relatively low power loss (e.g., increased switching efficiency). The efficiency of the power converter can be improved by defining an upper limit on the number of pulses delivered in a given burst packet and by limiting power delivery by introducing a fixed delay. To further reduce switching loss, pulses may be delivered between signal dips at the switching terminals of the switching elements. However, switching in, for example, a first signal dip may result in an excessively high switching frequency, which can cause electromagnetic interference (EMI) in the system. Therefore, a frequency clamp circuit is also provided to ensure that the switching frequency does not exceed a predetermined threshold. In one example, a device designed to implement the improved burst operation described above includes a burst control circuit, a pulse control circuit, a delay control circuit, and a latch. The burst control circuit may be configured to determine when to enter and exit burst mode operation, at least based on a feedback voltage from a connected load. A pulse control circuit may be configured to determine the timing of pulses delivered to the switching elements of a power converter. A delay control circuit may be configured to provide a predetermined delay after a set number of pulses have been delivered in order to improve the efficiency of power delivery. A latch may be designed to output a pulse-width modulation (PWM) signal based on an input received from at least a pulse control circuit. Numerous configurations will become apparent in light of this disclosure.

[0018] overview As mentioned above, flyback power converters still have several significant problems. Various electrical and power standards increasingly demand more efficient power systems. For example, the current European Union Ecodesign Requirements (EUER) standard for Universal Serial Bus (USB) power delivery requires that the input power be no more than 300mW for an output power of 210mW. Achieving this benchmark is challenging. More specifically, when operating in standby mode or minimum load to no load, the flyback power converter topology uses burst mode to help reduce power loss by delivering a series of voltage pulses to the gate terminals of the switching elements. During this burst mode, hysteresis control may be implemented to cope with load demand. When the load demands power, the switching elements turn on (close), and the switching frequency is typically above the audible frequency range (e.g., above 20kHz to around 25kHz). However, during this burst mode operation, relatively large switching losses can occur because the switch turns on at the DC input voltage rather than during the ring-down dips that appear in the signal at the switching terminals. Switching in signal dips can help mitigate some of these switching losses, but consistently meeting the standards set by the EUER can still be challenging. Furthermore, the standards for a given application may be stricter than those of the EUER, exacerbating the problem.

[0019] Accordingly, this specification describes techniques for providing a flyback power converter with more efficient burst-mode operation. In one example, this technique may be implemented by a controller having one or more circuits configured to provide a PWM signal to control the on-time of a switching element (e.g., a MOSFET). The signal generated at the switching terminal of the switching element (e.g., the drain terminal of a MOSFET) may include a ringing (or resonant) portion during the period when the switching element is off (also referred to as the off-time). During burst mode, the troughs in the signal between the ringing portions of the signal may be identified and used to trigger the generation of additional pulses to turn the switching element back on. According to some embodiments, the number of consecutive pulses thus delivered for a given burst packet to reduce switching losses may be limited to a predetermined number. According to some embodiments, after delivering a predetermined number of pulses, a fixed delay is introduced to limit power delivery. According to some embodiments, the switching frequency during burst mode is clamped below a threshold to limit the switching frequency. Thus, if the switching frequency becomes too high due to switching in the first trough of the signal, switching is attempted again in the next trough of the signal, and this continues until the switching frequency falls below a threshold.

[0020] According to several embodiments, a flyback power converter controller includes a burst control circuit, a pulse control circuit, a delay control circuit, and a latch or other equivalent storage element. The burst control circuit compares the feedback voltage received from the connected load with any number of comparators, along with different threshold voltage levels. These comparisons may be used to determine when to enter and exit burst operating mode. The pulse control circuit may include a valley sensing circuit, a valley counter, and a frequency clamp circuit to determine when to send a pulse enable signal to the latch in conjunction with digital logic. The delay control circuit may be designed to count the number of pulses and, when that number reaches a maximum value, to assert a delay signal to prevent further pulses from being supplied to the switching element over a fixed delay period.

[0021] Power converter architecture Figure 1 illustrates a block diagram of a flyback power converter system 100, including a control circuit configured to provide burst-mode operation in one example. As shown, the system 100 includes an integrated circuit (IC) 101, a flyback transformer 109, an output diode DOUT, an output capacitor COUT, a feedback circuit 111, an electromagnetic interference (EMI) filter 113, and a rectifier 115. In this example, the flyback power converter system 100 converts an AC input voltage (VAC) to a DC input voltage (VIN), which is then converted by the system 100 to a regulated DC output voltage (VOUT). In other examples, the DC input voltage VIN may be supplied directly rather than being obtained from the AC input voltage VAC.

[0022] As further illustrated, IC101 includes a control circuit 103, a driver 105, a switching element 107, and a sensing circuit 108. Each component of IC101 may be mounted on or part thereof an integrated circuit die in an integrated circuit package (to some examples, e.g., leaded ceramic flat pack, dual inline, ball grid array, pin grid array, land grid array, leaded chip carrier, leadless quad flat), on or part thereof a printed circuit board (to some examples, e.g., single-sided, double-sided, multilayer, flex), or on or part thereof any other suitable board on which circuit elements may even be formed and / or mounted. In some examples, the control circuit 103 may represent a separate controller, which may be part of its own die or board.

[0023] The flyback transformer 109, DOUT, COUT, feedback circuit 111, EMI filter 113, and rectifier 115 are shown as being outside IC 101 in this example, but in other examples, one or more of these components or circuits may be integrated within IC 101. A powered electronic system may also be coupled between the VOUT and ground terminal of system 100. The electronic system, here represented as load current (ILOAD), can be configured to suit any number of applications (e.g., automotive systems, computing systems, communication systems, gaming systems, home appliances and consumer electronic systems, mobile electronic systems such as smartphones, or any other applications that utilize regulated power). Other examples of the flyback power converter system 100 may include additional components not shown and / or in different configurations, and any such system may benefit from the technology described herein.

[0024] The EMI filter 113 removes unwanted noise injected into the line voltage, and the rectifier 115 rectifies the AC input. Any suitable EMI filter and rectifier circuit elements may be used. In other examples, VIN may be applied directly rather than being obtained from the AC power supply as shown. In such cases, system 100 may not include the EMI filter 113 and rectifier 115. The transformer 109 enables energy storage, energy transfer, and galvanic isolation between the input voltage VIN and the output voltage VOUT. The turns ratio of the primary winding 109p and the secondary winding 109s may be set so that VOUT can be lower or higher than VIN. Any suitable flyback transformer may be used.

[0025] The switching element 107 can be any suitable switching element technology, such as a gallium nitride field-effect transistor (GaN FET), another power FET, or a power bipolar junction transistor (BJT). In this example, the switching element 107 is coupled to the switching terminal (SW) and ground terminal of IC 101 via its current terminals (e.g., source / drain terminals for FETs, emitter / collector terminals for BJTs), and the sensing circuit 108 is coupled between the switching element 107 and ground. The control terminal of the switching element 107 (e.g., gate terminal for FETs, base terminal for BJTs) is coupled to the output of the driver 105. When the switching element 107 is closed (on time), the primary winding 109p is connected to the input voltage VIN, increasing the primary current and thus storing energy in the core of the transformer 109. During this on time, the diode DOUT is reverse-biased and turned off, and the capacitor COUT supplies the load current. When the switching element 107 is open (off time), the energy stored in the core of the transformer 109 is transferred to the secondary winding 109s (which is forward-biased at this time), causing current to flow through the diode DOUT, thereby replenishing the capacitor COUT and supplying the load current ILOAD. During this process, the core of the transformer 109 is demagnetized, so the secondary current decreases. The opening and closing of the switching element 107, including valley switching and burst mode operation, is controlled by the control circuit 103, as will be further explained below with reference to Figure 2.

[0026] The sensing circuit 108 detects the primary side peak current I PK It senses the current information (this is the actual primary side peak current I PK A scaled version of the peak current I is provided to the control circuit 103. PK This depends on the ILOAD and the state of the input line. The control circuit 103 controls the primary side peak current I PKAny suitable current sensing circuit element that allows the control circuit 103 to receive or otherwise determine the current may be used, for example, a resistor-based current sensing circuit including a sensing FET or BJT which is a scaled-down replica of the switching element 107. The feedback circuit 111 senses the output voltage and provides a feedback voltage VFB signal to the control circuit 103. The VFB signal may be, for example, a representation of the output power. Any suitable feedback circuit element that allows the control circuit 103 to receive or otherwise determine the current may be used, for example, a resistor divider and / or optocoupler feedback circuit which may be used in a flyback topology.

[0027] As further illustrated, the input voltage VIN is applied to one terminal of the primary winding of transformer 109, and the other terminal of the primary winding is coupled to the switching terminal (SW), so that IC 101 receives the switching terminal voltage (VSW) signal. System ground (GND) is coupled to the ground terminal of IC 101, and the VFB signal generated by the feedback circuit 111 is coupled to the feedback (FB) terminal of IC 101. Furthermore, the power supply voltage VDD may be generated on IC 101 or received via another terminal of IC 101 and may be used to supply power to its internal circuit elements as needed. Other examples may include different configurations and / or other components, and any such configuration may benefit from the techniques described herein.

[0028] Burst Mode Controller Architecture Figure 2 illustrates block diagrams of at least some of the control circuits 103 according to several embodiments. Each block may be implemented using any combination of logic gates and / or analog circuit elements to perform the functions described herein. Examples of specific circuit blocks are also provided with reference to Figures 3 to 6. According to some embodiments, the control circuit 103 includes at least a burst control circuit 202, a pulse control circuit 204, a delay control circuit 206, and a latch 208.

[0029] The burst control circuit 202 may be designed to receive a feedback voltage signal VFB and determine, at least based on the value of the feedback voltage VFB, when to enter or exit burst mode operation. The burst control circuit 202 may use any number of comparator circuits to compare the feedback voltage VFB with different threshold levels to determine whether to assert the BURST_EN signal (e.g., indicating that burst mode is enabled) or assert the BURST_EXIT signal (e.g., indicating that burst mode has ended). Further details of the burst control circuit 202 will be understood by referring to Figure 3.

[0030] According to several embodiments, the pulse control circuit 204 may be designed to receive various signals, at least a switching terminal voltage signal (VSW), and to determine when to assert the PULSE_EN signal, which indicates when to send a signal pulse to the control terminal of the switching element 107. The pulse control circuit 204 may include various circuits for performing various functions related to controlling the timing between pulses sent in a given burst packet. Thus, the pulse control circuit 204 may include at least several circuit elements related to identifying one or more valleys in the switching terminal voltage signal (VSW), and at least several circuit elements related to determining the switching frequency and clamping the switching frequency so that it does not exceed a predetermined threshold frequency. Further details of the pulse control circuit 204 will be understood by referring to Figures 4 and 5.

[0031] In some embodiments, the delay control circuit 206 may be designed to receive an output PWM signal (DRV_PWM) and determine the time to assert a delay signal (DELAY_SIG) to prevent any further pulses during the delay period. In one example, the delay control circuit 206 includes a counter for counting the number of consecutive pulses delivered (e.g., based on DRV_PWM) and a delay timer for determining the length of time to wait before resetting the counter. The state of the delay signal DELAY_SIG may be held at a given value (e.g., logical HIGH) for the entire delay period and may switch to another value (e.g., logical LOW) at the end of the delay period. Further details of the delay control circuit 206 will be understood by referring to Figure 6.

[0032] In some embodiments, the latch 208 is configured to output a PWM signal (DRV_PWM) to drive the on-time of the switching element 107. The rising edge of a given pulse is asserted when PULSE_EN switches to HIGH, and the falling edge of this given pulse is asserted when the latch is reset (for example, when the R input receives a logic HIGH signal). In some embodiments, the falling edge of a given pulse is determined by the primary side peak current I, which can be determined using a comparator 210. PK The threshold current value (I PK_REF This occurs when the voltage rises above ). In some embodiments, the asserted delay signal DELAY_SIG from the delay control circuit 206 can also hold the reset terminal R of the latch 208 in logic HIGH, so that output Q is forced LOW for the remainder of the delay period, regardless of the state of PULSE_EN. In some examples, additional digital logic, represented here by NOT and AND gates, can be used to ensure that the delay signal DELAY_SIG does not reset the latch during the delivery of voltage pulses. While latch 208 is provided for delivering pulse-width modulated signals, it should be understood that any digital storage elements, such as cascaded flip-flops, can be used as well.

[0033] Figure 3 illustrates a more detailed schematic of a burst control circuit 202 according to an embodiment. The burst control circuit 202 includes a first comparator 302 and a second comparator 304 that each receive a feedback voltage VFB. In one example, the first comparator 302 receives VFB at its positive input terminal, and the second comparator 304 also receives VFB at its positive input terminal. According to some embodiments, the negative input terminals of the first comparator 302 and the second comparator 304 are configured to receive a reference voltage for comparison with the feedback voltage VFB. For example, the first comparator 302 is designed to receive either a first reference voltage V BST_OFF or a second reference voltage V BST_ON depending on the state of switch S1, and the second comparator is designed to receive either a first reference voltage V BST_OFF or a third reference voltage V BST_EX depending on the state of switch S2. The value of each reference voltage can be determined in advance to set the voltage levels at which the system enters burst mode operation and exits burst mode operation. In the illustrated example, the same first reference voltage V BST_OFF [[ID=ON]]can be received at both negative terminals of the first comparator 302 and the second comparator 304, but in other examples, different voltage levels are used for these reference voltages of these two comparators.

[0034] According to some embodiments, the first reference voltage V BST_OFF represents the voltage at which the system stops providing pulses but does not exit burst mode, the second reference voltage V BST_ON represents the voltage at which the system starts providing pulses during burst mode, and the third reference voltage V BST_EX represents the voltage at which the system ends burst mode. In one example, the first reference voltage V BST_OFF is less than the second reference voltage V BST_ON and the second reference voltage V BST_ON is less than the third reference voltage V BST_EX . In one example, the first reference voltage VBST_OFF is about 0.25V, and the second reference voltage VBST_ON It is approximately 0.30V, and the third reference voltage V BST_EX The voltage is approximately 0.5V.

[0035] Here, the operation of the burst control circuit 202 will be explained using examples of the various reference voltage values ​​mentioned above. When the feedback voltage VFB is 0.25V (for example, the first reference voltage V BST_OFF When the value is less than (V), the output of the first comparator 302 is logic LOW, and thereby the switch S1 is set to the second reference voltage (V BST_ON ) is connected to the negative input terminal of the first comparator 302. Similarly, the output of the second comparator 304 is also logic LOW, thereby switching switch S2 to the third reference voltage (V BST_EX Connect the second comparator 304 to the negative input terminal. VFB is 0.3V (for example, the second reference voltage V BST_ON As long as the value is less than [value], neither the BURST_EN signal nor the BURST_EXIT signal will be asserted.

[0036] When VFB rises above 0.3V (for example, due to the load demanding power), the output of the first comparator 302 changes to logic HIGH, thereby causing switch S1 to the first reference voltage (V BST_OFF Connect the VFB to the negative input terminal of the first comparator 302. The value of VFB is still the third reference voltage V BST_EX The value is not greater than the value of the third reference voltage (VFB), and therefore the second comparator 304 continues to output a logic LOW. At this point, BURST_EN is asserted, and a voltage pulse can be sent to the switching element. VFB is still at the 0.5V level (for example, the third reference voltage VFB). BST_EX Since the VFB has not risen to the value of (V), BURST_EXIT remains at a logic LOW level. As long as VFB remains between 0.25V and 0.5V, the system remains in burst mode with the BURST_EN signal asserted. However, when VFB rises above 0.5V, the output of the second comparator 304 changes to logic HIGH, which means that the first reference voltage (V) is passed to switch S2. BST_OFFThe BURST_EXIT signal is asserted by connecting the BURST_EN signal to the negative input terminal of the second comparator 304. As a result, the AND gate receives a logic LOW signal from the inverted output of the second comparator 304, and the BURST_EN signal is simultaneously deasserted. On the other hand, when VFB falls below 0.25V, the output of the first comparator 302 changes to logic LOW, and as a result, switch S1 is set to the second reference voltage (V BST_ON Connect the ) to the negative input terminal of the first comparator 302. Then, when the feedback voltage VFB rises above 0.3V, the burst pulse can be re-enabled.

[0037] Figure 4 illustrates a more detailed schematic of a pulse control circuit 204 according to one embodiment. Using one or more logic gates (represented here as a single AND gate 408), it can receive various signals and output a pulse enable signal PULSE_EN. In some examples, the pulse enable signal PULSE_EN switches to HIGH when a pulse is delivered to the switching element 107. The pulse control circuit 204 may further include a valley sensing circuit 402, a valley counter 404, and a frequency clamp circuit 406.

[0038] In some embodiments, the valley detection circuit 402 receives a switching voltage signal VSW at a switching terminal SW and identifies the presence of one or more signal valleys in this signal. Simply put, following the switching element 107 turning off, VSW exhibits a ring-down period. Therefore, several consecutive signal valleys exist during the ring-down period. The valley detection circuit 402 is configured to identify that VSW is in a valley and assert an output signal (VALLEY_SIG) to indicate the presence of a valley in VSW. In this way, the system may assert the next pulse during a valley in the switching voltage VSW. In some embodiments, the valley detection circuit 402 uses a high-voltage capacitor and a resistive voltage divider to duplicate the VSW signal in a lower voltage domain and detect the low point of the signal. Further details regarding the exemplary operation of the valley detection circuit 402 are described in U.S. Patent Application No. 19 / 016,101, which is incorporated herein by reference in its entirety. Other embodiments may provide VALLEY_SIG using different trough-sensing circuit elements, such as a circuit element that senses troughs using the auxiliary windings of the flyback transformer 109, or a dedicated trough-sensing circuit element included in the control circuit 103. In some examples, the trough-sensing circuit 402 may also use another power converter signal, such as a primary voltage signal which may or may not be a high-voltage signal depending on the application, to sense the troughs of the VSW signal and to identify the sensed troughs. In any case, signal scaling may be used to convert a given signal to a lower voltage domain if desired. [Patent Document 2] U.S. Patent Application No. 19 / 016,101

[0039] In some embodiments, a valley counter 404 is provided to count the number of valleys in the VSW that pass before a pulse is finally asserted. Switching may occur in the first valley of the VSW signal, but as mentioned above, this may result in an excessively high switching frequency, and therefore, switching may instead be performed using higher-order valleys in the VSW signal. In some embodiments, the valley counter 404 includes any suitable counter circuit to keep track of the number of valleys identified in the VSW signal (for example, based on the VALLEY_SIG signal received from the valley sensing circuit 402). In some embodiments, the valley counter 404 provides an output to a latch or any other digital storage element so that a voltage pulse is asserted during a given counted valley. In some embodiments, the latch may be reset during any period when the PWM signal (DRV_PWM) is not asserted.

[0040] As described above, the switching frequency (relating to, for example, the timing between pulses sent to the switching element 107), also known as the burst frequency, can be clamped to ensure that it does not exceed a threshold switching frequency. In some embodiments, a frequency clamping circuit 406 is used that receives a PWM signal (DRV_PWM) and outputs a CLAMP_SIG signal based on the switching frequency of the PWM signal to prevent the generation of new pulses if the switching frequency is too high. The frequency clamping circuit 406 may more generally be called a frequency detection circuit.

[0041] In some embodiments, the AND gate 408 represents any number of AND gates or any type of logic gate. The AND gate 408 can generally receive outputs from the valley sensing circuit 402, the valley counter 404, and the frequency clamp circuit 406, respectively. The BURST_EN signal can also be used as an input to the AND gate 408; therefore, if the BURST_EN signal is not asserted, no pulse can be generated. In some embodiments, the switch at the output of the AND gate 408 is controlled by the BURST_EXIT signal. Thus, asserting the BURST_EXIT signal disconnects all pulse control logic from the driver at the control terminal of the switching element 107. In other examples, BURST_EXIT is used to switch off any other part of the circuit that produces a similar result to exiting burst control.

[0042] Figure 5 illustrates a more detailed schematic of a frequency clamp circuit 406 according to one embodiment. As described above, the frequency clamp circuit 406 receives a PWM signal DRV_PWM and determines whether the switching frequency of the PWM signal is higher than a threshold frequency. The threshold frequency can be a predetermined frequency based on the application. For example, the threshold frequency may be 250 kHz, so that pulses cannot be delivered at switching frequencies higher than 250 kHz. Any other threshold frequency value can also be used. Generally, the frequency clamp circuit 406 includes a first stage 502 that converts the square wave into shorter pulses at the rising edge of the square wave DRV_PWM signal, a second stage 504 that controls the charging and discharging of capacitor C, and a third stage which may be represented by a comparator 506 to compare the voltage across capacitor C with a threshold voltage corresponding to the threshold frequency.

[0043] In some embodiments, the first stage 502 of the frequency clamp circuit 406 includes an AND gate having a first input terminal for receiving the PWM signal after it has passed through an inverter and a delay 508, and a second input terminal for receiving the PWM signal after it has passed through a successive inverter. The delay 508 may represent a fixed delay time implemented using a cascaded number of inverters or other similar signal delay techniques. In some examples, the delay 508 represents a delay of about 20 ns to about 50 ns, for example, about 30 ns. In some embodiments, by introducing a short delay to the received signal, the AND gate receives two HIGH inputs for a short time corresponding to the length of the delay 508, and therefore the output of the AND gate pulses HIGH following the rising edge of the square wave signal DRV_PWM.

[0044] In some embodiments, the output of the AND gate is received at the control terminal of the switching element 510 in the second stage 504. When the switching element 510 is turned on, the capacitor C discharges (e.g., VC becomes 0 or near 0). When the switching element 510 is turned off, the current source I begins to charge C at a constant rate. Thus, VC rises at a constant rate. In some embodiments, the state of CLAMP_SIG depends on the comparison of VC and VREF. As long as VC is less than VREF, CLAMP_SIG remains logic LOW, thereby preventing the pulse control circuit 204 from generating further pulses. If the switching speed is too fast (e.g., faster than the threshold frequency), the switching elements 510 each turn on faster, and therefore the capacitor C discharges before VC rises above VREF. However, when the switching frequency of DRV_PWM falls below the threshold frequency, capacitor C can charge long enough for VC to rise and exceed VREF, and therefore CLAMP_SIG may be asserted, and the PULSE_EN signal may be asserted.

[0045] Figure 6 illustrates a more detailed schematic of a delay control circuit 206 according to one embodiment. The delay control circuit 206 includes at least a counter 602 configured to count the number of consecutive pulses delivered to the switching element 107. In some examples, the counter 602 counts pulses by counting the rising edges of the received PWM signal DRV_PWM.

[0046] In some embodiments, counter 602 asserts DELAY_SIG in response to the count reaching a predetermined number of pulses. In some examples, counter 602 counts up to three pulses before asserting DELAY_SIG. Counter 602 may count up to any number of pulses, such as up to eight pulses, before asserting DELAY_SIG. Once counter 602 has counted up to the maximum number of pulses, the operation of counter 602 may be paused from the time the asserted DELAY_SIG signal passes through the delay block 604 until counter 602 is reset. In some embodiments, the delay imposed on the signal in the delay block 604 is predetermined and may depend on a given application. In some examples, the signal delay imposed by the delay block 604 is approximately 40 μs to approximately 120 μs, for example, around 70 μs. The delay block 604 may be implemented using cascaded inverters or any other signal delay configuration. While DELAY_SIG is asserted (after the maximum number of pulses has been counted), the reset terminal of latch 208 (see Figure 2) remains ON, and no further pulses are sent to the switching element 107.

[0047] Figure 7 illustrates graphs of signals generated by the system in Figure 1 due to the burst control mode implemented by the control circuit 103 in Figure 2, according to several embodiments. Referencing any of the figures above may be helpful for further understanding, and the relevant explanations above apply equally here. The first (top) graph in Figure 7 shows the signals at the control terminal of the switching element 107, generally illustrating the various pulses when the switching element 107 is turned on (also referred to herein as on-time). The second graph from the top shows the VSW signal at the switching terminal (e.g., the drain of the switching element 107). The bottom graph shows the feedback voltage VFB along with different thresholds where the burst operation changes. All three graphs are illustrated along the same time axis.

[0048] During the first time period (t1), the feedback voltage VFB starts high enough so that the system does not enter burst mode. According to some embodiments, VFB decreases over time and eventually reaches a first voltage threshold V BST_OFF It becomes less than. According to some embodiments, at this point, the system starts sending pulses during burst mode, and the VFB turns upward to a second voltage threshold V BST_ON It waits for it to exceed the second voltage threshold V. As seen during the second time period (t2), VFB begins to rise as the load starts to demand more power, and eventually VFB reaches the second voltage threshold V BST_ONThe frequency rises above this threshold. When this occurs, a first pulse is sent, as observed by the square wave pulse received at the gate terminal of the switching element. At the end of this pulse, the switching element turns off, and the voltage at the switching terminal begins to ring down as the energy stored in the transformer is transferred to the load. According to some embodiments, the next pulse is sent during one of the troughs in the voltage signal at the switching terminal. In the illustrated example, the next pulse is sent at the first trough of the voltage signal at the switching terminal. However, as mentioned above, if the switching at the first trough causes the switching frequency to become too high (e.g., above a predetermined threshold frequency), the system attempts to send the next pulse at the next trough instead, and this continues until the switching frequency falls below the threshold frequency.

[0049] During a third time period (t3), any number of additional pulses are supplied to the gate terminal of the switching element. According to some embodiments, the number of pulses delivered consecutively is predetermined and stops when a maximum threshold is reached. In the illustrated example, three pulses are delivered by the end of the third time period t3, after which the system stops delivering pulses.

[0050] In some embodiments, a fixed delay is implemented by the system during a fourth time period t4, during which no additional pulses can be sent. As described above, this fixed delay period can range from approximately 40 μs to approximately 120 μs. During the delay period, the voltage signal at the switching terminal continues to ring down, and in some cases, it may reach a steady voltage level by the end of the fixed delay period. In some embodiments, the VFB may decrease slowly during the fixed delay period. In the illustrated example, the VFB decreases during the delay period from the first voltage threshold V BST_OFF It drops below VFB. Therefore, the system stops attempting to generate pulses, and VFB rises again to the second voltage threshold VFB. BST_ONNo new pulses are generated until the threshold is exceeded. As can be observed during the fifth time period t5, the fixed delay period has ended, but the system has risen at least again to the second voltage threshold V. BST_ON It will continue to wait before sending the next pulse until it exceeds a certain threshold.

[0051] In one embodiment, during a sixth time period (t6), another burst packet of three consecutive pulses is provided. In this example, each pulse is sent during the first signal trough, but as described above, pulses may also be sent between later troughs depending on the switching frequency. Also, in some examples, more than three pulses may be sent. Following the delivery of a predetermined number of pulses during a seventh time period (t7), a fixed delay is implemented again. However, in this example, the VFB has a first voltage threshold V during the delay period. BST_OFF Note that it did not drop below a certain value. Therefore, according to some embodiments, at the beginning of the eighth time period (t8), the next pulse is sent immediately without any additional delay. During the eighth time period t8, the load demand is met by the power converter, so the VFB begins to rise. During burst operation, the VFB rises above a third voltage threshold V BST_EX The voltage rises above this threshold, causing the system to immediately exit burst mode. According to some embodiments, upon exiting burst mode, the VFB rises above the first voltage threshold V BST_OFF The system will not restart burst mode until VFB falls below the second voltage threshold V BST_ON The system will not send the first pulse until it rises above that level.

[0052] methodology Figure 8 illustrates a flowchart of method 800 for burst-mode operation of a flyback power converter in one example. This method can be implemented, for example, by the system 100 shown in Figure 1, which has the control circuit 103 of Figure 2.

[0053] Method 800 begins with operation 802, in which a first voltage pulse is delivered to the gate of a switching element in a power converter. The voltage pulse may be a pulse-width modulated signal, which is part of a burst packet having any predetermined number of pulses. According to some embodiments, during the delivery of the pulse, the switching element is biased to ON, and the inductor of the flyback power converter is charged with the current flowing through the primary winding of the transformer.

[0054] Method 800 continues with operation 804 in which a first trough in the signal at a switching terminal (e.g., the drain terminal of a switching element) is detected. The first trough may be detected within a ring-down of the signal at the switching terminal. When the voltage pulse is removed from the gate of the switching element, the switching element turns off and the transformer's energy is transferred to the load. After this, as the parasitic capacitance at the switching terminal and the inductance of the transformer's primary coil begin to resonate, the signal at the switching terminal begins to ring down. As described above, analog trough sensing logic may be used to determine the presence of a local minimum (e.g., a trough) in the ring-down of the switching terminal signal.

[0055] Method 800 continues with operation 806, in which a determination is made regarding the burst frequency (e.g., the switching frequency of the switching element) in the currently detected signal trough. If the current burst frequency is higher than the maximum threshold frequency (e.g., the maximum frequency of 250 kHz), operation 808 detects the next trough in the signal at the switching terminal. Once the next trough is detected, Method 800 returns to operation 806 to re-examine whether the current burst frequency is higher than the maximum threshold frequency. If it is found that the burst frequency is lower than the maximum threshold frequency, Method 800 proceeds to operation 810, in which the next voltage pulse is provided to the gate of the switching element. The next pulse may be substantially similar to the first voltage pulse provided in operation 802.

[0056] Method 800 continues with operation 812, in which a determination is made as to whether the maximum number of pulses has been reached. As described above, a counter is used to continue tracking the number of voltage pulses delivered for a given burst packet. A predetermined maximum pulse threshold can be set to any number from 3 pulses to a maximum of 10 pulses, or to additional pulses. In the signal graph of Figure 7, the maximum pulse threshold is set to 3 pulses, and therefore each burst packet terminates after delivering 3 pulses. If the maximum pulse threshold has not yet been reached, Method 800 returns to operation 804 to deliver the next voltage pulse to the gate of the switching element.

[0057] If the maximum pulse threshold is reached, method 800 proceeds to operation 814, in which the system delays by a predetermined amount of time. According to some embodiments, the delay period may vary depending on the application and may range from about 40 μs to about 120 μs, for example, about 70 μs. According to some embodiments, no voltage pulses are supplied to the gate of the switching element during the delay period. However, the burst mode remains enabled during this delay period, and the system can continue to send other burst packets following the delay period.

[0058] Following the delay period in operation 814, method 800 continues in operation 816, in which a determination is made regarding the feedback voltage VFB. BST_ON If smaller, method 800 follows operation 818, in which the system waits for the feedback voltage to rise above a second voltage threshold VBST_ON. For example, the system may wait until VFB rises above 0.3V. According to some embodiments, VFB rises above the second voltage threshold V BST_ON If it is determined that the value exceeds the second voltage threshold V, or if the VFB has already exceeded the second voltage threshold V at the end of operation 814, BST_ON If it exceeds the limit, method 800 returns to operation 802 to send the first pulse of the next burst packet. Method 800 then performs the same operation as described above to send the pulse of the next burst packet.

[0059] According to several embodiments, Method 800 continues to send burst packets to operate the switching elements of the power converter until the burst mode ends. VFB is a third voltage threshold V BST_EX When the voltage rises above (for example, around 0.5V), the burst mode ends. According to several embodiments, the VFB in operation 820 exceeds a third voltage threshold V BST_EX The determination of whether it exceeds the third voltage threshold V can be made at any time during the execution of method 800. Thus, operation 820 can function as an interrupt to the flow of method 800 and is therefore illustrated separately from the main flow of method 800. BST_EX Whenever the voltage rises above the threshold, method 800 proceeds from operation 820 to operation 822, where the system exits burst mode. In some examples, the decision in operation 820 does not function as an interrupt that can occur at any time, but rather occurs at a specific time in method 800. As described above, when the VFB falls below the first voltage threshold VBST_OFF, and then the second voltage threshold V BST_ON If it rises beyond that point, it can re-enter burst mode (for example, starting from operation 802).

[0060] Power system Figure 9 illustrates a block diagram of a system 900 including a flyback power converter configured with an improved burst mode according to several embodiments of the present disclosure. As shown, the system 900 includes a snubber 910, a flyback transformer 911, an EMI filter 915, a rectifier 917, an AC sensing circuit 918, a synchronous rectifier transistor QSR, a synchronous rectifier (SR) controller 920, an output capacitor COUT, an output transistor QOUT, a port 922, a USB-PD controller 924 or a feedback circuit 913 including an error amplifier and optocoupler, and an IC 101 including a control circuit 103. In this example, the system 900 converts an AC input voltage (VAC) to a DC input voltage (VIN), which is then converted by the flyback power converter to a regulated DC output voltage (VOUT). VOUT is coupled to port 922, to which a load may be coupled. In other examples, the DC input voltage VIN may be supplied directly rather than being derived from the AC input voltage VAC.

[0061] The EMI filter 915 removes unwanted noise injected into the line voltage, the rectifier 917 rectifies the AC input, and the AC sensing circuit 918 causes IC 101 to detect whether VAC is present. Any suitable EMI filtering, rectifier, and sensing circuit elements may be used. In other examples, VIN may be applied directly rather than being obtained from an AC power source as shown. In such cases, system 900 may not include VAC, EMI filter 915, rectifier 917, and AC sensing circuit 918. Transformer 911 enables energy storage, energy transfer, and galvanic isolation between input VIN and output VOUT. Any suitable flyback transformer may be used. Snubber 910 provides a clamp voltage and can be implemented using any suitable snubber circuit. QSR and SR controllers 920 collectively provide a synchronous rectifier (instead of DOUT in Figure 1), and the synchronous rectifier may be used to improve the efficiency of the flyback topology.

[0062] The capacitor COUT operates in the same manner as described above with reference to Figure 1. In this example, port 922 is a Type-C USB port, and controller 924 is a USB-PD controller. Other universal proprietary port technologies may be used. QOUT may be used to disconnect the load in response to control from controller 924, for example, when an overvoltage or high current condition is detected. In some examples, an optocoupler provides IC 101 with a feedback voltage VFB used by the control circuit 103. The optocoupler provides isolation between the low-voltage environment at the load and the high-voltage environment at IC 101 by using light to transmit the voltage at the load to the VFB at IC 101. However, instead of an optocoupler, any other electrical isolation circuit, such as any type of galvanic insulator, or one or more capacitors may be used.

[0063] In this description, the term “to connect” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, if the intervening component C does not alter the functional relationship between device A and device B, device A is connected to device B via the intervening component C, and therefore device B is controlled by device A by the control signal generated by device A.

[0064] A device “configured” to perform a certain task or function may be configured by the manufacturer at the time of manufacture to perform that function (e.g., by programming and / or wiring connections), and / or may be configured (or reconfigurable) by the user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be done by firmware and / or software programming of the device, by constructing and / or laying out hardware components and interconnecting devices, or a combination thereof.

[0065] As used herein, the terms “terminal,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean interconnections or terminations between device elements, circuit elements, integrated circuits, devices or other electronic equipment, or semiconductor components.

[0066] A circuit or device described herein as including certain components may instead be adapted to be coupled with such components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may also be adapted, either during or after manufacturing, for example by an end user and / or a third party, to be coupled with at least some of the passive elements and / or sources to form the described structure.

[0067] While this specification describes the use of specific transistors, other transistors (or equivalent devices) may be used instead. For example, a p-channel field-effect transistor (PFET) may be used instead of an n-channel field-effect transistor (NFET) with little or no modification to the circuit. Other types of transistors (such as bipolar junction transistors (BJTs)) may also be used. Furthermore, the device may be mounted in or on a silicon substrate (Si), silicon carbide substrate (SiC), gallium nitride substrate (GaN), or gallium arsenide substrate (GaAs), among other examples.

[0068] In this specification, a field-effect transistor (FET) being "on" means that a conduction channel exists in the FET and that drain current can flow through the FET. In this specification, a field-effect transistor being "off" means that a conduction channel does not exist and that drain current does not flow through the FET. However, an off FET may conduct current through the transistor's body diode.

[0069] The circuits described herein are reconfigurable to include additional or different components, thereby providing functionality at least partially similar to the functionality available before the replacement of the components. Components indicated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance amount represented by the indicated resistor, unless otherwise stated. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors each coupled in parallel between the same terminals. In another example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors each coupled in series between the same two terminals as a single resistor or capacitor.

[0070] In the foregoing, the term "grounding" includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable or appropriate to the teachings of this application. In this description, unless otherwise stated, "about," "near," or "substantially" preceding a parameter means within ±10 percent of that parameter.

[0071] Further examples Example 1 is a device comprising a burst control circuit configured to receive the feedback voltage of a power converter and generate a burst enable signal, a pulse control circuit configured to receive the burst enable signal and the voltage signal from the current terminal of the switching element of the power converter, a delay control circuit configured to initiate a delay time, and a latch. The pulse control circuit is further configured to determine the timing between pulses delivered to the control terminal of the switching element and to assert the pulse enable signal. The delay time is initiated by the delay control circuit in response to the number of delivered pulses reaching a maximum pulse threshold. The latch is designed to receive the pulse enable signal and the pulse reset signal and to output pulses to the control terminal of the switching element.

[0072] Example 2 includes the device of Example 1, wherein the burst control circuit includes a first comparator configured to receive a feedback voltage at a first input and a first threshold voltage at a second input, and a second comparator configured to receive a feedback voltage at a first input and a second threshold voltage at a second input.

[0073] Example 3 includes the device of Example 2 and further includes a first set of switches configured to change the value of a first threshold voltage, and a second set of switches configured to change the value of a second threshold voltage.

[0074] Example 4 includes one of the devices from Examples 1 to 3, and the pulse control circuit includes a valley sensing circuit configured to detect valleys in a voltage signal.

[0075] Example 5 includes the device of Example 4, wherein the pulse control circuit includes a frequency detection circuit configured to determine whether the burst frequency at the time corresponding to a detected trough in the voltage signal is lower than a threshold frequency.

[0076] Example 6 includes the device of Example 5, wherein the valley sensing circuit is configured to detect the next valley in the voltage signal in at least partially in response to the burst frequency being higher than the threshold frequency.

[0077] Example 7 includes one of the devices from Examples 4 to 6, wherein the pulse control circuit is configured to assert a pulse enable signal in at least partially in response to a valley sensing circuit that detects a valley in the voltage signal.

[0078] Example 8 includes one of the devices from Examples 1 to 7, with a delay time of approximately 40 microseconds to approximately 120 microseconds.

[0079] Example 9 includes one of the devices from Examples 1 to 8, and the delay control circuit includes a counter configured to count the number of pulses delivered to the control terminal of the switching element.

[0080] Example 10 is a system comprising one of the devices from Examples 1 to 9, a transformer having an input voltage terminal, an output voltage terminal, a switching terminal to which a voltage signal is provided, a feedback terminal to which a feedback voltage is provided, a primary winding and a secondary winding, the primary winding coupled between the input voltage terminal and the switching terminal, and a feedback circuit coupled between the output voltage terminal and the feedback terminal.

[0081] Example 11 includes the device from Example 10, and the feedback circuit includes an optocoupler circuit.

[0082] Example 12 includes the device from Example 10 or Example 11, and the load coupled to the output voltage terminal includes a Universal Serial Bus (USB) port.

[0083] Example 13 is a control circuit comprising a valley count circuit configured to count the number of valleys detected in a received voltage signal, a frequency clamp circuit configured to determine whether the burst frequency corresponding to the time of the currently detected valley is lower than a threshold frequency, and one or more logic gates. The valley count circuit also asserts a valley enable signal when it has counted one or more valleys in the received voltage signal. The frequency clamp circuit also asserts a clamp signal in response to the burst frequency being lower than a threshold frequency. One or more logic gates are designed to receive at least the valley enable signal and the clamp signal and assert a pulse enable signal at the output terminal of one or more logic gates.

[0084] Example 14 includes the control circuit of Example 13, and further includes a valley sensing circuit configured to receive a voltage signal at the current terminal of a switching element of a power converter, detect a valley in the received voltage signal, and assert a valley detection signal in response to the detection of a valley in the received voltage signal.

[0085] Example 15 includes the control circuit of Example 14, wherein one or more logic gates are further configured to receive a valley detection signal.

[0086] Example 16 includes one of the control circuits from Examples 13 to 15, and one or more logic gates include at least one AND gate.

[0087] Example 17 includes one of the control circuits from Examples 13 to 16, wherein one or more logic gates are further configured to receive a burst enable signal, and a pulse enable signal is asserted in response to each of the valley enable signal, clamp signal, and burst enable signal being asserted.

[0088] Example 18 includes a control circuit from any one of Examples 13 to 17, further including a switch configured to disconnect output terminals from one or more logic gates in response to a burst termination signal being asserted.

[0089] Example 19 is a device comprising a burst control circuit configured to receive a feedback voltage from a power converter and generate a burst enable signal; one of the control circuits from Examples 13 to 18; a delay control circuit configured to initiate a delay time during which no pulses can be delivered; and a latch configured to receive a pulse enable signal and a pulse reset signal. The delay time is initiated in response to the number of delivered pulses reaching a maximum pulse threshold. The latch is configured to output pulses to the control terminals of the switching element.

[0090] Example 20 is a method for delivering a burst packet. This method includes delivering a first pulse to the control terminal of a switching element in a first time period, detecting a first dip in the switching signal sampled at the current terminal of the switching element in a second time period, and determining whether a first burst frequency associated with the time difference between the first time and the second time period is lower than a threshold frequency. In response that the first burst frequency is lower than the threshold frequency, this method includes delivering a second pulse to the control terminal of the switching element in a second time period. In response that the first burst frequency is higher than the threshold frequency, this method includes detecting a second dip in the switching signal in a third time period, determining whether a second burst frequency associated with the time difference between the first time and the third time period is lower than a threshold frequency, and delivering a second pulse to the control terminal of the switching element in a third time period in response that the second burst frequency is lower than the threshold frequency.

[0091] Example 21 includes the method of Example 20, further comprising detecting a third trough in the switching signal at a fourth time in response to a second burst frequency being higher than a threshold frequency, determining whether the third burst frequency associated with the time difference between the first time and the fourth time is lower than a threshold frequency, and delivering a second pulse to the control terminal of the switching element at a fourth time in response to the third burst frequency being lower than a threshold frequency.

[0092] Example 22 includes the method of Example 20 or Example 21, further comprising determining whether the number of delivered pulses has reached a predetermined maximum pulse threshold.

[0093] Example 23 includes the method of Example 22, further comprising waiting for a predetermined delay time in response to determining that the number of delivered pulses has reached a predetermined maximum pulse threshold.

[0094] Example 24 includes the method of Example 23, where the predetermined delay time is approximately 40 microseconds to approximately 120 microseconds.

[0095] Example 25 includes one of the methods in Examples 22 to 24, and further includes delivering another pulse to the control terminal of the switching element in response to determining that the number of delivered pulses has not reached a predetermined maximum pulse threshold.

[0096] Example 26 includes one of the methods of Examples 20 to 25, further comprising receiving a feedback voltage, comparing the feedback voltage to a first threshold voltage in a first comparator, and comparing the feedback voltage to a second threshold voltage different from the first threshold voltage in a second comparator.

[0097] Example 27 includes the method of Example 26, further comprising enabling burst operation associated with the delivery of first and second pulses in response to a feedback voltage greater than a first threshold voltage, and disabling burst operation in response to a feedback voltage greater than a second threshold voltage.

[0098] Example 28 is a device comprising a burst control circuit configured to receive the feedback voltage of a power converter and generate a burst enable signal, a control circuit configured to receive the burst enable signal and the voltage signal at the current terminal of the switching element of the power converter, and a digital storage element. The control circuit is further configured to determine the timing between pulses delivered to the control terminal of the switching element, assert a pulse enable signal to deliver pulses, count the number of pulses delivered, and determine whether the number of delivered pulses is less than a maximum pulse threshold. The digital storage element receives the pulse enable signal and is configured to output pulses to the control terminal of the switching element.

[0099] Example 29 includes the device of Example 28, further including a delay circuit configured to initiate a delay time during which no pulses can be sent to the control terminals of the switching element, the delay time being initiated in response to the number of delivered pulses reaching a maximum pulse threshold.

[0100] Example 30 includes the device from Example 29, with a delay time of approximately 40 microseconds to approximately 120 microseconds.

[0101] Example 31 includes one of the devices from Examples 28 to 30, wherein the burst control circuit includes a first comparator configured to receive a feedback voltage at a first input and a first threshold voltage at a second input, and a second comparator configured to receive a feedback voltage at a first input and a second threshold voltage at a second input.

[0102] Example 32 includes the device of Example 31 and further includes a first set of switches configured to change the value of a first threshold voltage, and a second set of switches configured to change the value of a second threshold voltage.

[0103] Example 33 includes one of the devices from Examples 28 to 32, and the control circuit includes a valley sensing circuit configured to detect valleys in a voltage signal.

[0104] Example 34 includes the device of Example 33, wherein the control circuit includes a frequency detection circuit configured to determine whether the burst frequency of time corresponding to a detected trough in the voltage signal is lower than a threshold frequency.

[0105] Example 35 includes the device of Example 34, wherein the valley sensing circuit is configured to detect the next valley in the voltage signal in at least partially in response to the burst frequency being greater than the threshold frequency.

[0106] Example 36 includes one of the devices from Examples 33 to 35, wherein the control circuit is configured to assert a pulse enable signal in at least partially in response to a valley sensing circuit that detects a valley in the voltage signal.

[0107] Example 37 includes one of the devices from Examples 28 to 36, where the digital storage element is a latch.

[0108] Example 38 is a system comprising one of the devices from Examples 28 to 37, a transformer having an input voltage terminal, an output voltage terminal, a switching terminal to which a voltage signal is provided, a feedback terminal to which a feedback voltage is provided, a primary winding and a secondary winding, the primary winding coupled between the input voltage terminal and the switching terminal, and a feedback circuit coupled between the output voltage terminal and the feedback terminal.

[0109] Example 39 includes the system from Example 38, and the feedback circuit includes an optocoupler circuit.

[0110] Example 40 includes the system of Example 38 or Example 39, wherein the load coupled to the output voltage terminal includes a Universal Serial Bus (USB) port.

[0111] Modifications to the described embodiments are permitted within the scope of the claims, and other embodiments are also possible.

Claims

1. It is a device, A burst control circuit configured to receive the feedback voltage of the power converter and generate a burst enable signal, A pulse control circuit configured to receive the burst enable signal and the voltage signal of the current terminal of the switching element of the power converter, further configured to determine the timing between pulses delivered to the control terminal of the switching element and assert the pulse enable signal, A delay control circuit configured to initiate a delay time, wherein the delay time is initiated in response to the number of delivered pulses reaching a maximum pulse threshold, A latch configured to receive the pulse enable signal and the pulse reset signal, the latch configured to output a pulse to the control terminal of the switching element, A device that includes this.

2. The device according to claim 1, wherein the burst control circuit is A first comparator configured to receive the feedback voltage at the first input and a first threshold voltage at the second input, A second comparator configured to receive the feedback voltage at the first input and a second threshold voltage at the second input, A device that includes this.

3. The device according to claim 2, A plurality of first switches configured to change the value of the first threshold voltage, A plurality of second switches configured to change the value of the second threshold voltage, Devices that further include this.

4. A device according to claim 1, wherein the pulse control circuit includes a valley sensing circuit configured to detect valleys in the voltage signal.

5. The device according to claim 4, wherein the pulse control circuit includes a frequency detection circuit configured to determine whether the burst frequency of the time corresponding to the detected trough of the voltage signal is lower than a threshold frequency.

6. The device according to claim 5, wherein the trough sensing circuit is configured to detect the next trough in the voltage signal in at least partially in response to the burst frequency being higher than the threshold frequency.

7. A device according to claim 4, wherein the pulse control circuit is configured to assert the pulse enable signal in at least partially in response to the valley sensing circuit that detects the valley of the voltage signal.

8. A device according to claim 1, wherein the delay control circuit includes a counter configured to count the number of pulses delivered to the control terminal of the switching element.

9. A control circuit, A valley counting circuit is configured to count the number of valleys detected in a received voltage signal, and to assert a valley enable signal when one or more valleys are counted in the received voltage signal. A frequency clamp circuit is configured to determine whether the burst frequency corresponding to the currently detected trough time is lower than a threshold frequency, and to assert a clamp signal in response to the burst frequency being lower than the threshold frequency. One or more logic gates configured to receive at least the valley enable signal and the clamp signal, the one or more logic gates configured to assert a pulse enable signal at the output terminal of the one or more logic gates, A control circuit, including one.

10. A control circuit according to claim 9, The voltage signal is received at the current terminal of the switching element of the power converter. The valley of the received voltage signal is detected, A control circuit further comprising a valley sensing circuit configured to assert a valley detection signal in response to the detection of the valley in the received voltage signal.

11. A control circuit according to claim 9, wherein one or more logic gates are further configured to receive a burst enable signal, and the pulse enable signal is asserted in response to each of the valley enable signal, the clamp signal, and the burst enable signal being asserted.

12. A control circuit according to claim 9, further comprising a switch configured to disconnect the output terminals from one or more logic gates in response to a burst termination signal being asserted.

13. It is a device, A burst control circuit configured to receive the feedback voltage of the power converter and generate a burst enable signal, A control circuit configured to receive the burst enable signal and the voltage signal of the current terminal of the switching element of the power converter, wherein the control circuit The timing between pulses delivered to the control terminal of the switching element is determined. Assert the pulse enable signal to deliver pulses. The control circuit is configured to count the number of delivered pulses and to determine whether the number of delivered pulses is less than a maximum pulse threshold, A digital storage element configured to receive the pulse enable signal and output a pulse to the control terminal of the switching element, A device that includes this.

14. The device according to claim 13, further comprising a delay circuit configured to initiate a delay period during which no pulses can be sent to the control terminal of the switching element, wherein the delay period is initiated in response to the number of delivered pulses reaching the maximum pulse threshold.

15. The device according to claim 13, wherein the burst control circuit is A first comparator configured to receive the feedback voltage at the first input and a first threshold voltage at the second input, A second comparator configured to receive the feedback voltage at the first input and a second threshold voltage at the second input, A device that includes this.

16. The device according to claim 15, A plurality of first switches configured to change the value of the first threshold voltage, A plurality of second switches configured to change the value of the second threshold voltage, Devices that further include this.

17. The device according to claim 13, wherein the control circuit includes a valley sensing circuit configured to detect a valley in the voltage signal.

18. A device according to claim 17, wherein the control circuit includes a frequency detection circuit configured to determine whether the burst frequency of the time corresponding to the detected trough of the voltage signal is lower than a threshold frequency.

19. The device according to claim 18, wherein the trough sensing circuit is configured to detect the next trough in the voltage signal in at least partially in response to the burst frequency being higher than the threshold frequency.

20. A device according to claim 17, wherein the control circuit is configured to assert the pulse enable signal in at least partially in response to the valley sensing circuit that detects the valley of the voltage signal.

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