Switching power supply LLC interleaving current sharing control system and method

Abstract

The invention provides a switching power supply LLC interleaving current sharing control system and method. The system comprises a switching power supply conversion circuit, a controller and a logic operation circuit. Wherein the controller is used for obtaining driving signals of a plurality of switch tubes in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch according to an output voltage set value and an output current and voltage sampling value of the interlaced full-bridge LLC resonant converter module; the driving signal is used for controlling the working state of the switching tube so as to realize current sharing of the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch. According to the current value sampled by the two branches, the current-sharing pulse which only affects the turn-off signal of the switching tube can be generated, in the current-sharing adjusting process, the deviation of 90 degrees of MOS tube driving at the same position of the two resonant full bridges can be maintained without complex setting of a controller or addition of an additional complex circuit, and the current-sharing effect of the two resonant full bridges is improved. And a good effect of small interleaving parallel output ripple is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply control, in particular to a switching power supply LLC interleaved parallel current sharing control system and method. BACKGROUND

[0002] At present, with the rapid development of the communication field, higher requirements are put forward for the high efficiency of the AC-DC (alternating current to direct current) high-frequency switching power supply or the extremely simple AC-DC outdoor power supply inside the base station, and high efficiency and high power density are the goals of the continuous optimization of power supply products. LLC resonant converter (inductor-inductor-capacitor resonant converter) has the advantages of easy realization of soft switching, i.e. zero voltage switching (ZVS) or zero current switching (ZCS), high conversion efficiency, and is widely used in the field of switching power supply.

[0003] At present, most of the switching power supplies of the base station are 48V grade, which belongs to the occasion of low voltage and large current. In order to reduce the output current ripple, two LLC resonant converters usually work in an interleaved parallel manner. This technology not only brings higher power density, but also significantly reduces the output current ripple. However, when using interleaved control with the same switching frequency, due to the parameter deviation of the resonant elements (including resonant inductance, resonant capacitance and transformer excitation inductance) of the two paths in the manufacturing process, there will be a large difference in voltage gain under the same switching frequency, resulting in uneven current of the two-phase output current, the larger current side bears a larger pressure, the heat is serious, the output voltage ripple is large, which greatly affects the stability and reliability of the system.

[0004] The existing technical solutions can realize the current sharing control of the multi-path resonant converter of the switching power supply. Some solutions need to increase additional power devices, causing cost increase and equipment size increase, and cannot achieve high power density. Some solutions control the current of each branch separately, which can well realize current sharing control. However, since it is variable frequency control, the switching frequencies of each path are different, which cannot realize interleaved control, resulting in large output ripple.

[0005] Therefore, how to realize the current sharing control of the multi-path resonant converter of the switching power supply while avoiding the problems of cost increase, equipment size increase and large output ripple has become a problem to be solved. SUMMARY

[0006] The technical problem to be solved by the present application is to solve the above-mentioned problems of the prior art, and to provide a switching power supply LLC interleaved parallel current sharing control system and method to solve the problems existing in the prior art.

[0007] In a first aspect, this application provides a switching power supply LLC interleaved parallel current sharing control system, the system comprising: a switching power supply conversion circuit, a controller, and a logic operation circuit; The switching power supply conversion circuit includes a filter module, a power factor correction (PFC) module, an interleaved full-bridge LLC resonant converter module, and a rectifier module connected in sequence. The interleaved full-bridge LLC resonant converter module includes a first full-bridge resonant converter branch and a second full-bridge resonant converter branch, and multiple switching transistors are provided in both the first full-bridge resonant converter branch and the second full-bridge resonant converter branch. The controller is connected to the switching power supply conversion circuit and the logic operation circuit respectively; The controller is used to acquire the output voltage setpoint and output current voltage sample value of the interleaved full-bridge LLC resonant converter module. Based on the output voltage setpoint and output current voltage sample value, the controller obtains the drive signals of multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through the logic operation circuit. The drive signals are used to control the working state of the switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch to achieve current sharing between the first full-bridge resonant converter branch and the second full-bridge resonant converter branch.

[0008] In some embodiments, the controller obtains drive signals for multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through the logic operation circuit based on the output voltage setpoint and the output current voltage sample value, including: The controller obtains the original drive signals of multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch based on the output voltage setting value and the output current voltage sampling value. Based on the output current sample value in the output current voltage sample value, it is determined whether current sharing control is required; the output current sample value includes the first output current of the first full-bridge resonant converter branch and the second output current of the second full-bridge resonant converter branch. If current sharing control is required, the current sharing adjustment signal is obtained based on the output current sampling value; Based on the original driving signal and the current sharing adjustment signal, the final driving signal of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch is obtained through the logic operation circuit. The final driving signal is used to control the working state of the switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch to achieve current sharing between the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch.

[0009] In some embodiments, the controller obtains the original drive signals for multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch based on the output voltage setpoint and the output current-voltage sampled values, including: The reference current value Iref is determined based on the output voltage setting value Voutref and the output voltage sampling value Vo in the output current and voltage sampling values. Based on the first output current Io1, the second output current Io2, and the reference current value Iref, the original driving signals of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch are obtained.

[0010] In some embodiments, determining the reference current value Iref based on the output voltage setting value Voutref and the output voltage sampling value Vo in the output current voltage sampling value includes: The output voltage sample value Vo is low-pass filtered to obtain the feedback value Voutfb used for output voltage loop control; The feedback value Voutfb is compared with the output voltage setpoint Voutref to obtain the voltage error Verror. The voltage error value Verror is input into the voltage loop PI controller for calculation, resulting in the Vctrl signal; After the Vctrl signal is amplitude-limited, the first current-limiting setpoint Iref1 is obtained, and the second current-limiting setpoint Iref2 corresponding to the interleaved full-bridge LLC resonant converter module is determined. The smaller of the first current limiting setpoint Iref1 and the second current limiting setpoint Iref2 is determined as the reference current value Iref.

[0011] In some embodiments, the original driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained based on the first output current Io1, the second output current Io2, and the reference current value Iref, including: The first output current Io1 and the second output current Io2 are filtered respectively to obtain the first output current sample value Io1fb and the second output current sample value Io2fb. The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current and Iofb. The output current Iofb is compared with the reference current value Iref to obtain the current error Ierror; The current error value Ierror is input into the current loop PI controller for calculation, resulting in the Ictrl signal; The Ictrl signal is converted and limited to obtain the switching frequency fs of the LLC resonant converter; The original driving signals PWM1 and PWM2 of the first full-bridge resonant converter branch, and the original driving signals PWM3 and PWM4 of the second full-bridge resonant converter branch are obtained based on the switching frequency fs.

[0012] In some embodiments, determining whether current sharing control is needed based on the output current sample value in the output current voltage sample value includes: The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current and Iofb. If the output current and Iofb are greater than the first preset current threshold Iset1, then it is determined that current sharing control is required. If the output current and Iofb are less than the second preset current threshold Iset2, it is determined that current sharing control is not required, wherein the first preset current threshold Iset1 is greater than the second preset current threshold Iset2.

[0013] In some embodiments, the current sharing adjustment signal is obtained based on the output current sampling value, including: Determine the output current and half of Iofb as the current sharing loop setpoint Ishareref; The larger of the first output current sampling value Io1fb and the second output current sampling value Io2fb is determined to be the current sharing value Isfb; The current sharing loop setpoint Ishareref and the current sharing current value Isfb are compared to obtain the current sharing error Iseeror; The current sharing error value Iseror is input into the current sharing loop PI controller for calculation, and the current sharing adjustment signal Isctrl is obtained.

[0014] In some embodiments, the first full-bridge resonant conversion branch includes first branch MOSFETs Q7 and Q9, and first branch MOSFETs Q8 and Q10; the second full-bridge resonant conversion branch includes second branch MOSFETs Q11 and Q13, and second branch MOSFETs Q12 and Q14. The logic operation circuit includes AND gates U1, U2, U3 and U4, and NOT gates U5 and U6; Based on the original driving signal and the current sharing adjustment signal, the final driving signals for multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch are obtained through the logic operation circuit, including: The Share_PWM wave for current sharing regulation is output according to the current sharing regulation signal Isctrl, including the Share_PWM1 signal corresponding to the first full-bridge resonant transformation branch and the Share_PWM2 signal corresponding to the second full-bridge resonant transformation branch. The Share_PWM1 signal is processed by the NOT gate U5 to obtain the Share_PWM1_CTR signal, and the Share_PWM2 signal is processed by the NOT gate U6 to obtain the Share_PWM2_CTR signal. The Share_PWM1_CTR signal and the original drive signal PWM1 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM1_CTR of MOS transistors Q7 and Q10 in the first full-bridge resonant converter branch. The Share_PWM1_CTR signal and the original drive signal PWM2 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM2_CTR of MOS transistors Q8 and Q9 in the first full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM3 of the second full-bridge resonant converter branch are processed by the logic AND gate U3 to obtain the final drive signal PWM3_CTR of MOS transistors Q11 and Q14 in the second full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM4 of the second full-bridge resonant converter branch are processed by the logic AND gate U4 to obtain the final drive signal PWM4_CTR of MOS transistors Q12 and Q13 in the second full-bridge resonant converter branch.

[0015] Secondly, this application provides a switching power supply LLC interleaved parallel current sharing control method, applied to the aforementioned switching power supply LLC interleaved parallel current sharing control system, the method comprising: Obtain the output voltage setpoint and output current / voltage sample values ​​of the interleaved full-bridge LLC resonant converter module. Based on the output voltage setting value and the output current and voltage sampling value, the driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained through the logic operation circuit. The driving signals are used to control the working state of the switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch to achieve current sharing between the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch.

[0016] In some embodiments, obtaining the drive signals for multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through a logic operation circuit based on the output voltage setting value and the output current voltage sampling value includes: Based on the output voltage setting value and the output current voltage sampling value, the original driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained. Based on the output current sampling value in the output current voltage sampling value, it is determined whether current sharing control is required; the output current sampling value includes the first output current Io1 of the first full-bridge resonant converter branch and the second output current Io2 of the second full-bridge resonant converter branch. If current sharing control is required, the current sharing adjustment signal is obtained based on the output current sampling value; Based on the original driving signal and the current sharing adjustment signal, the final driving signal of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch is obtained through the logic operation circuit. The final driving signal is used to control the working state of the switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch to achieve current sharing between the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch.

[0017] This application provides a switching power supply LLC interleaved parallel current sharing control system and method. The system includes: a switching power supply conversion circuit, a controller, and a logic operation circuit; wherein, the switching power supply conversion circuit includes a filter module, a power factor correction (PFC) module, an interleaved full-bridge LLC resonant converter module, and a rectifier module connected in sequence; wherein, the interleaved full-bridge LLC resonant converter module includes a first full-bridge resonant converter branch and a second full-bridge resonant converter branch, and both the first and second full-bridge resonant converter branches are provided with multiple switching transistors; the controller is connected to the switching transistors respectively. The power conversion circuit and the logic operation circuit are connected. The controller is used to acquire the output voltage setpoint and output current voltage sample value of the interleaved full-bridge LLC resonant converter module. Based on the output voltage setpoint and output current voltage sample value, the logic operation circuit obtains the drive signals of multiple switching transistors in the first and second full-bridge resonant converter branches. The drive signals are used to control the operating state of the switching transistors in the first and second full-bridge resonant converter branches to achieve current sharing between the first and second full-bridge resonant converter branches. This application can generate a current sharing pulse that only affects the switching transistor turn-off signal based on the sampled current values ​​of the two branches. During the current sharing adjustment process, it is not necessary to make complex settings to the controller or add additional complex circuits to maintain a 90° deviation in the driving of the MOS transistors at the same position of the two resonant full-bridges, achieving a good effect of low ripple in the interleaved parallel output. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1A schematic diagram of the LLC interleaved parallel current sharing control system for a switching power supply provided in an embodiment of this application; Figure 2 A circuit diagram of a switching power supply conversion circuit provided in an embodiment of this application; Figure 3 A schematic diagram of the two-channel interleaved LLC resonant converter provided in the embodiments of this application; Figure 4 A schematic diagram of the logic operation circuit provided in the embodiments of this application; Figure 5 This is a schematic diagram of the flow sharing control logic provided in an embodiment of this application; Figure 6 A schematic diagram of the PWM waveform for current sharing control in the current-biased branch of the LLC resonant converter provided in this embodiment of the application; Figure 7 This is a schematic diagram of the PWM waveform for current sharing control in the low-current branch of an LLC resonant converter provided in an embodiment of this application. Figure 8 A schematic diagram of the alternating parallel current sharing control method for switching power supply LLC provided in an embodiment of this application; Figure 9 This is a schematic diagram of data processing in the alternating parallel current sharing control method for switching power supplies LLC provided in the embodiments of this application.

[0020] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solution of this application, the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0022] It is understood that the specific embodiments and accompanying drawings described herein are merely for explaining this application and are not intended to limit this application.

[0023] It is understood that, without conflict, the various embodiments and features in the embodiments of this application can be combined with each other.

[0024] It is understood that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, while parts unrelated to this application are not shown in the drawings.

[0025] It is understood that each unit or module involved in the embodiments of this application may correspond to only one entity structure, or may be composed of multiple entity structures, or multiple units or modules may be integrated into one entity structure.

[0026] It is understood that the terms "first," "second," etc., used in the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0027] It is understood that, without conflict, the functions and steps marked in the flowcharts and block diagrams of this application may occur in a different order than those marked in the accompanying drawings.

[0028] It is understood that the flowcharts and block diagrams of this application illustrate the possible architecture, functions, and operations of systems, apparatuses, devices, and methods according to various embodiments of this application. Each block in a flowchart or block diagram may represent a unit, module, program segment, or code, containing executable instructions for implementing the specified function. Furthermore, each block or combination of blocks in the block diagrams and flowcharts may be implemented using a hardware-based system to implement the specified function, or using a combination of hardware and computer instructions.

[0029] It is understood that the units and modules involved in the embodiments of this application can be implemented by software or by hardware. For example, the units and modules can be located in the processor.

[0030] It is understood that the specific values ​​of each parameter in this application are merely illustrative examples, and in practical applications, the parameters can be optimized and adjusted based on specific requirements.

[0031] To address the current sharing problem in parallel LLC converters, existing technologies have proposed many methods for achieving parallel current sharing. The most direct method is based on frequency conversion control. By sampling the output current and independently adjusting the switching frequency of each parallel module, the LLC can achieve good current sharing. However, because the switching frequencies of the LLC converters in each phase are different, interleaved parallel connection cannot be achieved, resulting in large output voltage ripple.

[0032] Another current sharing control approach involves adjusting the equivalent resonant capacitor value. This method effectively compensates for the tolerances of the resonant components in each module, achieving excellent current sharing performance. However, this method requires external power switches and resonant capacitors, which increases the cost and size of the converter.

[0033] Based on the shortcomings of existing technologies, the purpose of this application is to achieve current sharing control in a multi-channel interleaved resonant converter without increasing the rated power devices to reduce the power density of the switching power supply, nor requiring complex configuration of the DSP controller's output logic or a high-configuration controller. The goal is to achieve current sharing control during the operation of the resonant converter without compromising the low ripple of the interleaved parallel output voltage and current.

[0034] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic diagram of the LLC interleaved parallel current sharing control system for a switching power supply provided in an embodiment of this application, as shown below. Figure 1 As shown, this application provides a switching power supply LLC interleaved parallel current sharing control system, the system including: a switching power supply conversion circuit, a controller, and a logic operation circuit; The switching power supply conversion circuit includes a filter module, a power factor correction (PFC) module, an interleaved full-bridge LLC resonant converter module, and a rectifier module connected in sequence; wherein the PFC module forms an AC-DC conversion module, and the interleaved full-bridge LLC resonant converter module and the rectifier module form a DC-DC conversion module.

[0036] Specifically, the filtering module is an EMI filtering (Electromagnetic Interference Filtering) module.

[0037] The interleaved full-bridge LLC resonant converter module includes a first full-bridge resonant converter branch and a second full-bridge resonant converter branch, and multiple switching transistors are provided in both the first full-bridge resonant converter branch and the second full-bridge resonant converter branch. The controller is connected to the switching power supply conversion circuit and the logic operation circuit respectively; The controller is used to acquire the output voltage setpoint and output current voltage sample value of the interleaved full-bridge LLC resonant converter module. Based on the output voltage setpoint and output current voltage sample value, the controller obtains the drive signals of multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through the logic operation circuit. The drive signals are used to control the working state of the switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch to achieve current sharing between the first full-bridge resonant converter branch and the second full-bridge resonant converter branch.

[0038] The controller can be, for example, a DSP (Digital Signal Processing) controller or other types of controllers.

[0039] Figure 2 The circuit diagram of the switching power supply conversion circuit provided in the embodiments of this application is as follows: Figure 2As shown below, the detailed circuit structure of the switching power supply conversion circuit will be explained.

[0040] refer to Figure 2 In some embodiments, the PFC module is a two-interleaved parallel totem pole PFC module, which is used to convert AC power into 400V high voltage DC power and realize the input power factor correction function. It mainly includes two PFC inductors L1 and L2, four high-frequency transistors Q1, Q2, Q3 and Q4, and two power frequency transistors Q5 and Q6.

[0041] Specifically, the two interleaved parallel totem pole PFC modules are connected to AC mains power at the front end. The four high-frequency transistors Q1, Q2, Q3, and Q4 are fast totem pole transistors, and the two power frequency transistors Q5 and Q6 are slow totem pole transistors. The totem poles operate in an interleaved parallel manner. The two interleaved parallel totem pole PFC modules rectify and convert the AC voltage into DC high voltage, and simultaneously achieve a high input power factor during the conversion process.

[0042] In some embodiments, the switching power supply conversion circuit further includes a bus capacitor Cbus, which is used to smooth the rectified DC voltage, reduce voltage fluctuations, lower voltage ripple, improve power quality, and provide instantaneous current to meet load demands when the load changes. The AC-DC conversion module and the DC-DC (DC to DC) conversion module are connected via the bus capacitor Cbus. Specifically, two interleaved parallel totem-pole PFC modules are connected to the interleaved full-bridge LLC resonant converter module via the bus capacitor Cbus.

[0043] In some embodiments, the interleaved full-bridge LLC resonant converter module (hereinafter referred to as LLC resonant converter) includes a first full-bridge resonant converter branch H1 (hereinafter referred to as full-bridge H1 branch) and a second full-bridge resonant converter branch H2 (hereinafter referred to as full-bridge H2 branch), and multiple switching transistors are provided in both the first full-bridge resonant converter branch and the second full-bridge resonant converter branch.

[0044] The full-bridge H1 branch includes four MOSFETs (Q7, Q8, Q9, and Q10), a resonant inductor (Lr1), a resonant capacitor (Cr1), and a transformer (T1) (inductor Lm1 in the diagram represents the internal structure of transformer T1).

[0045] Specifically, the H1 branch of the full-bridge circuit includes the first branch's upper MOSFETs Q7 and Q9, and the first branch's lower MOSFETs Q8 and Q10. The source (S) of Q7 and the drain (D) of Q8 are connected, with the connection point connected to one side of the resonant inductor Lr1. The other side of the resonant inductor Lr1 is connected to the resonant capacitor Cr1, and the other side of the resonant capacitor Cr1 is connected to one end of the primary winding of transformer T1. The other end of the primary winding of transformer T1 is connected to the source (S) of Q9 and the drain (D) of Q10. The driving waveforms of Q7, Q8, Q9, and Q10 are obtained by logical operations on the original PWM (Pulse Width Modulation) and current-sharing PWM waves generated by the DSP controller. Among them, the driving waveforms of Q7 and Q10 are consistent, and the driving waveforms of Q8 and Q9 are consistent.

[0046] The full-bridge H2 branch includes four MOSFETs (Q11, Q12, Q13, and Q14), a resonant inductor Lr2, a resonant capacitor Cr2, and a transformer T2 (inductor Lm2 in the diagram represents the internal structure of transformer T2). The LLC resonant converter can achieve a constant output voltage by controlling the switching frequency (frequency regulation).

[0047] Specifically, the H2 branch of the full-bridge circuit includes the upper MOSFETs Q11 and Q13 in the second branch, and the lower MOSFETs Q12 and Q14 in the second branch. The source (S) of Q11 and the drain (D) of Q12 are connected, with the connection point connected to one side of the resonant inductor Lr2. The other side of the resonant inductor Lr2 is connected to the resonant capacitor Cr2, and the other side of the resonant capacitor Cr2 is connected to one end of the primary winding of transformer T2. The other end of the primary winding of transformer T2 is led out to the source (S) of Q13 and the drain (D) of Q14. The driving waveforms of Q11, Q12, Q13, and Q14 are obtained by logical operations on the original PWM and current-sharing PWM waves generated by the DSP controller. Among them, the driving waveforms of MOSFETs Q11 and Q14 are consistent, and the driving waveforms of MOSFETs Q12 and Q13 are consistent.

[0048] Figure 3 A schematic diagram of the two-channel interleaved LLC resonant converter provided in the embodiments of this application is shown below. Figure 3As shown, the driving PWM waveforms of MOS at the same position in the two full-bridge resonant converters are identical, with a phase difference of 90°. Taking MOS Q7 and Q11 at the same position in H1 and H2 full-bridges as examples, the driving waveforms of Q7 and Q11 are 90° out of phase. The waveforms of other MOS at the same position in H1 and H2 full-bridges are also identical, with a phase difference of 90°. The output current Io1 of the H1 full-bridge resonant converter and the output current Io2 of the H2 full-bridge resonant converter are interleaved to synthesize the total output current Io. It can be seen that after interleaving, the ripple of the output current Io is much smaller. The control method of interleaving and paralleling two LLCs can greatly reduce the ripple of the secondary output current of the converter, reduce the number of filter capacitors, and help improve the power density of the converter.

[0049] In some embodiments, the rectifier module is a two-bridge rectifier module, including diodes D1, D2, D3, and D4 corresponding to the first rectifier bridge, and diodes D5, D6, D7, and D8 corresponding to the second rectifier bridge. The rectifier bridge is mainly used to convert AC voltage into stable DC voltage, ensuring the efficiency and stability of the resonant converter. By controlling the operating frequency, zero current turn-off (ZCS) can be achieved.

[0050] Specifically, the anode of diode D1 and the cathode of diode D2 are connected together, and their common point is introduced to one end of the secondary side of transformer T1. The anode of diode D3 and the cathode of diode D4 are connected together, and their common point is introduced to one end of the secondary side of transformer T1. The anodes of D2 and D4 are connected together and introduced to the sampling resistor Rs1 to collect the output current of the H1 branch of the full bridge of the LLC resonant converter.

[0051] The anode of diode D5 and the cathode of diode D6 are connected together, and their common point is introduced to one end of the secondary side of transformer T2. The anode of diode D7 and the cathode of diode D8 are connected together, and their common point is introduced to one end of the secondary side of transformer T2. The anodes of D6 and D8 are connected together and introduced to the sampling resistor Rs2 to collect the output current of the H2 branch of the full bridge of the LLC resonant converter.

[0052] In some embodiments, the switching power supply conversion circuit further includes branch sampling resistors Rs1 and Rs2, wherein Rs1 is used to collect the output current of the full-bridge H1 branch of the LLC resonant converter, and Rs2 is used to collect the output current of the full-bridge H2 branch of the LLC resonant converter.

[0053] In some embodiments, the switching power supply conversion circuit further includes an output capacitor Co.

[0054] The above embodiments are structural descriptions of the LLC interleaved parallel current sharing control system for switching power supplies in this application. The working principle of the controller in this application will be explained below.

[0055] In some embodiments, the controller obtains the drive signals of multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through the logic operation circuit based on the output voltage setting value and the output current voltage sampling value, including the following processing steps (1) to (4): (1) The controller obtains the original driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch based on the output voltage setting value and the output current voltage sampling value; (2) Determine whether current sharing control is required based on the output current sampling value in the output current voltage sampling value; the output current sampling value includes the first output current Io1 of the first full-bridge resonant conversion branch and the second output current Io2 of the second full-bridge resonant conversion branch. (3) If current sharing control is required, the current sharing adjustment signal is obtained based on the output current sampling value; (4) Based on the original driving signal and the current sharing adjustment signal, the final driving signal of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch is obtained through the logic operation circuit. The final driving signal is used to control the working state of the switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch to realize current sharing between the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch.

[0056] In some embodiments, the above processing step (1) includes the following processing steps (1.1) to (1.2): (1.1) Determine the reference current value Iref based on the output voltage setting value Voutref and the output voltage sampling value Vo in the output current and voltage sampling values; (1.2) Based on the first output current Io1, the second output current Io2 and the reference current value Iref, the original driving signals of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch are obtained.

[0057] In some embodiments, the above processing step (1.1) includes the following processing steps: The output voltage sample value Vo is low-pass filtered to obtain the feedback value Voutfb used for output voltage loop control; The feedback value Voutfb is compared with the output voltage setpoint Voutref to obtain the voltage error Verror. The voltage error value Verror is input into the voltage loop PI controller for calculation, resulting in the Vctrl signal; After the Vctrl signal is amplitude-limited, the first current-limiting setpoint Iref1 is obtained, and the second current-limiting setpoint Iref2 corresponding to the interleaved full-bridge LLC resonant converter module is determined. Specifically, Iref2 can be obtained according to the current-limiting or power-limiting characteristics of the LLC resonant converter.

[0058] The smaller of the first current limiting setpoint Iref1 and the second current limiting setpoint Iref2 is determined as the reference current value Iref. Specifically, the magnitudes of Iref1 and Iref2 are compared, and the smaller value is assigned to Iref.

[0059] In some embodiments, the above processing step (1.2) includes the following processing steps: The first output current Io1 and the second output current Io2 are filtered respectively to obtain the first output current sample value Io1fb and the second output current sample value Io2fb. The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current Iofb, that is, Iofb=Io1fb+Io2fb; The output current Iofb is compared with the reference current value Iref to obtain the current error Ierror; The current error value Ierror is input into the current loop PI controller for calculation, resulting in the Ictrl signal; The Ictrl signal is converted and limited to obtain the switching frequency fs of the LLC resonant converter; The original drive signals PWM1~PWM2 of the first full-bridge resonant converter branch and the original drive signals PWM3~PWM4 of the second full-bridge resonant converter branch are obtained based on the switching frequency fs. PWM1~PWM2 and PWM3~PWM4 are 90° apart at corresponding positions on the LLC resonant converter, have the same switching frequency, and operate in an interleaved parallel configuration.

[0060] In some embodiments, the above processing step (2) includes the following processing steps: The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current and Iofb. If the output current and Iofb are greater than the first preset current threshold Iset1, then it is determined that current sharing control is required. If the output current and Iofb are less than the second preset current threshold Iset2, it is determined that current sharing control is not required. That is, when the output load current is small, current sharing adjustment is not required. The first preset current threshold Iset1 is greater than the second preset current threshold Iset2.

[0061] In some embodiments, the above processing step (3) includes the following processing steps: The output current and half of Iofb are determined as the current sharing loop setpoint Ishareref, i.e., Ishareref = 0.5. Iofb; The larger of the first output current sampling value Io1fb and the second output current sampling value Io2fb is determined to be the current sharing value Isfb. Specifically, the magnitudes of Io1fb and Io2fb are compared, and the larger value is assigned to Isfb. The current sharing loop setpoint Ishareref and the current sharing current value Isfb are compared to obtain the current sharing error Iseeror; The current sharing error, Iseeror, is input to the current sharing loop PI controller for calculation, resulting in the current sharing adjustment signal Isctrl for the branch with the larger current. Furthermore, Isctrl for the branch with the smaller current is directly set to 0.

[0062] Figure 4 A schematic diagram of the logic operation circuit provided in the embodiments of this application, such as... Figure 4 As shown, in some embodiments, the logic operation circuit includes two NOT gates and four AND gates, namely: AND gate U1, AND gate U2, AND gate U3 and AND gate U4, and NOT gate U5 and NOT gate U6.

[0063] The NOT gate performs an "invert" operation and is a single-input, single-output gate circuit, whose output is always the opposite of the input.

[0064] Among them, the logic AND gate performs the "AND" operation. It is a multi-input, single-output gate circuit. The output is high level (1) only when all inputs are high level (1) at the same time; otherwise, the output is low level (0).

[0065] In some embodiments, the above processing step (4) includes the following processing steps: The Share_PWM wave for current sharing regulation is output according to the current sharing regulation signal Isctrl, including the Share_PWM1 signal corresponding to the first full-bridge resonant transformation branch and the Share_PWM2 signal corresponding to the second full-bridge resonant transformation branch. The Share_PWM1 signal is processed by the NOT gate U5 to obtain the Share_PWM1_CTR signal, and the Share_PWM2 signal is processed by the NOT gate U6 to obtain the Share_PWM2_CTR signal. The Share_PWM1_CTR signal and the original drive signal PWM1 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM1_CTR of MOS transistors Q7 and Q10 in the first full-bridge resonant converter branch. The Share_PWM1_CTR signal and the original drive signal PWM2 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM2_CTR of MOS transistors Q8 and Q9 in the first full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM3 of the second full-bridge resonant converter branch are processed by the logic AND gate U3 to obtain the final drive signal PWM3_CTR of MOS transistors Q11 and Q14 in the second full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM4 of the second full-bridge resonant converter branch are processed by the logic AND gate U4 to obtain the final drive signal PWM4_CTR of MOS transistors Q12 and Q13 in the second full-bridge resonant converter branch.

[0066] Figure 5 This is a schematic diagram of the current sharing control logic provided in the embodiments of this application, such as... Figure 5 As shown, the DSP controller triggers another EPWM module within its controller to output a carrier wave with a frequency of 2fs based on the frequency fs of the LLC resonant converter. Based on the carrier frequency, the counter period value PRD at this switching frequency can be calculated. According to the adjustment value Isctrl of the current sharing loop PI controller for the branch with larger current, the PWM wave is set high when the count value is PRD+Isctrl during the EPWM module's count decline period, and low when the count value is close to 2PRD-1. This generates the Share_PWM wave for current sharing control in this resonant branch. This Share_PWM wave corresponds to the falling edge of the original drive PWM of the LLC resonant converter. That is, the Share_PWM_CTR generated after the Share_PWM is processed by a logic NOT gate only affects the falling edge of the original PWM of the LLC resonant converter. In the process of implementing current sharing regulation, it ensures that the rising edge, i.e., the PWM turn-on moment, maintains a 90° phase difference with the other LLC resonant converter.

[0067] Figure 6 This is a schematic diagram of the PWM waveform for current sharing control in the overcurrent branch of the LLC resonant converter provided in this application embodiment, as shown below. Figure 6As shown, taking the H2 resonant converter as the branch with a large output current, the DSP controller generates the original drive waveforms PWM3 and PWM4 of the H2 resonant bridge MOSFETs based on the voltage and current dual closed-loop output values. It also generates the current sharing adjustment pulse Share_PWM2 based on the current sharing control loop output values. Share_PWM2 is processed by a logic NOT gate to obtain Share_PWM2_CTR. Share_PWM2_CTR and the original PWM3 and PWM4 are then logically ANDed to generate PWM3_CTR and PWM4_CTR signals with smaller positive pulse widths than PWM3 and PWM4, which serve as the H2 full-bridge drive signals. These signals only affect the falling edge of the original PWM3 and PWM4, keeping the rising edge unchanged. In other words, the final drive waveform of the H2 resonant converter is changed through current sharing control, reducing the effective pulse width. This achieves current sharing control without affecting the phase difference of the two resonant full-bridge drives, maintaining a small interleaved ripple effect.

[0068] Figure 7 This is a schematic diagram of the PWM wave for current sharing control in the low-current branch of the LLC resonant converter provided in this application embodiment, as shown below. Figure 7 As shown, taking the H1 resonant converter as the branch with the smaller output current, when the output current is the smaller of the two branches, its current sharing pulse width is 0, that is, the current sharing pulse Share_PWM1 is at a low level. After Share_PWM1 passes through the NOT gate, the output Share_PWM1_CTR is at a high level. Since Share_PWM1_CTR is at a high level throughout the switching cycle, the PWM1_CTR output by the original H1 full-bridge driver PWM1 and Share_PWM1_CTR after passing through the AND gate U1 is the same as the original driver PWM1; the PWM2_CTR output by the original H1 full-bridge driver PWM2 and Share_PWM1_CTR after passing through the AND gate U2 is the same as the original driver PWM2. That is, during the current sharing process, the side with the smaller output current does not adjust the control pulse width, keeping its output unchanged.

[0069] In this application, the DSP controller prioritizes reducing the duty cycle of the LLC converter with the larger current based on the current sharing control of each LLC full bridge, while the duty cycle of the LLC converter with the smaller current is not adjusted.

[0070] Specifically, for the branch with smaller output current, the current sharing SHARE_PWM wave is at a low level. Then, after passing through the NOT gate, the low-level signal becomes the high-level SHARE_PWM_CTR. SHARE_PWM_CTR is logically ANDed with the original PWM wave of the LLC resonant converter. The output wave is the same as the original PWM wave, that is, no current sharing adjustment is performed on the branch with smaller current. In addition, the pulse width of the current sharing SHARE_PWM wave for the branch with larger output current will be adjusted according to the current sharing situation of the two branches. When adjusting the pulse width of the current sharing SHARE_PWM wave for the larger branch, only the turn-off time is adjusted, and the turn-on time is not adjusted, so as to ensure that it is turned on at the same time as the original PWM wave of the branch with larger output current.

[0071] The DSP controller outputs a PWM signal for current sharing adjustment. For branches with higher current, the turn-on time of the current sharing PWM wave is consistent with the turn-on time of the full-bridge MOS transistors in that branch's resonant converter, and the turn-off time is adjusted by pre-turning off the duty cycle according to the current sharing adjustment. For branches with lower current, the current sharing PWM wave is a constant high level. Then, a logical AND operation is performed between the current sharing PWM wave and the original drive PWM wave of the LLC full-bridge MOS transistors. The waveform after the logical operation is the final MOS drive waveform of the LLC full-bridge. The final drive signal of the MOS transistors is used to control the operating state of the switching transistors in the two full-bridge LLC resonant converters and to achieve current sharing control.

[0072] In this application, based on the frequency of the LLC resonant converter, one PWM channel of the DSP controller is set to output a carrier wave with a frequency twice that of the resonant converter. The width of the current sharing pulse width can be determined based on the Isctrl value of the current sharing loop. A high level is set at the position corresponding to the falling moment of the carrier wave, and a low level is set at the end of the switching cycle. This generates a synchronization pulse corresponding to the falling edge of the LLC resonant converter's PWM drive. For the SHARE_PWM wave of the current sharing control, SHARE_PWM is passed through a logic NOT gate to generate a SHARE_PWM_CTR signal. The generated current sharing SHARE_PWM_CTR wave is then logically ANDed with the original PWM waves of the two full-bridge LLC resonant converters. After the logical AND operation, the final drive PWM_CTR waveforms of the two full-bridge LLC resonant converters are obtained. During the duty cycle adjustment process, the phase of the two full-bridge converters is strictly maintained at 90° to ensure a low-ripple, interleaved effect.

[0073] Figure 8 This is a schematic diagram of the alternating parallel current sharing control method for switching power supplies LLC provided in the embodiments of this application, as shown below. Figure 8 As shown, this application provides a switching power supply LLC interleaved parallel current sharing control method, applied to the switching power supply LLC interleaved parallel current sharing control system in the above embodiments. The method includes: S1. Obtain the output voltage setpoint and output current / voltage sample values ​​of the interleaved full-bridge LLC resonant converter module. S2. Based on the output voltage setting value and the output current and voltage sampling value, the driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained through the logic operation circuit. The driving signals are used to control the working state of the switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch to achieve current sharing between the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch.

[0074] In some embodiments, obtaining the drive signals for multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through a logic operation circuit based on the output voltage setting value and the output current voltage sampling value includes: Based on the output voltage setting value and the output current voltage sampling value, the original driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained. Based on the output current sampling value in the output current voltage sampling value, it is determined whether current sharing control is required; the output current sampling value includes the first output current Io1 of the first full-bridge resonant converter branch and the second output current Io2 of the second full-bridge resonant converter branch. If current sharing control is required, the current sharing adjustment signal is obtained based on the output current sampling value; Based on the original driving signal and the current sharing adjustment signal, the final driving signal of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch is obtained through the logic operation circuit. The final driving signal is used to control the working state of the switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch to achieve current sharing between the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch.

[0075] Figure 9 This is a schematic diagram of data processing in the LLC interleaved parallel current sharing control method for switching power supplies provided in the embodiments of this application, as shown below. Figure 9 As shown, the specific processing steps for obtaining the final drive signals of multiple switching transistors in the first and second full-bridge resonant transformation branches in this application include: (1) Determine the reference current value Iref based on the output voltage setting value Voutref and the output voltage sampling value Vo in the output current and voltage sampling values; specifically including: The output voltage sample value Vo is low-pass filtered to obtain the feedback value Voutfb used for output voltage loop control; The feedback value Voutfb is compared with the output voltage setpoint Voutref to obtain the voltage error Verror. The voltage error value Verror is input into the voltage loop PI controller for calculation, resulting in the Vctrl signal; After the Vctrl signal is amplitude-limited, the first current-limiting setpoint Iref1 is obtained, and the second current-limiting setpoint Iref2 corresponding to the interleaved full-bridge LLC resonant converter module is determined. The smaller of the first current limiting setpoint Iref1 and the second current limiting setpoint Iref2 is determined as the reference current value Iref.

[0076] (2) Based on the first output current Io1, the second output current Io2, and the reference current value Iref, the original driving signals of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch are obtained, specifically including: The first output current Io1 and the second output current Io2 are filtered respectively to obtain the first output current sample value Io1fb and the second output current sample value Io2fb. The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current and Iofb. The output current Iofb is compared with the reference current value Iref to obtain the current error Ierror; The current error value Ierror is input into the current loop PI controller for calculation, resulting in the Ictrl signal; The Ictrl signal is converted and limited to obtain the switching frequency fs of the LLC resonant converter; The original driving signals PWM1 and PWM2 of the first full-bridge resonant converter branch, and the original driving signals PWM3 and PWM4 of the second full-bridge resonant converter branch are obtained based on the switching frequency fs.

[0077] (3) Summing the first output current sample value Io1fb and the second output current sample value Io2fb yields the output current and Iofb; If the output current and Iofb are greater than the first preset current threshold Iset1, then it is determined that current sharing control is required. If the output current and Iofb are less than the second preset current threshold Iset2, it is determined that current sharing control is not required, wherein the first preset current threshold Iset1 is greater than the second preset current threshold Iset2.

[0078] (4) Determine that half of the output current and Iofb is the current sharing loop setpoint Ishareref; The larger of the first output current sampling value Io1fb and the second output current sampling value Io2fb is determined to be the current sharing value Isfb; The current sharing loop setpoint Ishareref and the current sharing current value Isfb are compared to obtain the current sharing error Iseeror; The current sharing error value Iseror is input into the current sharing loop PI controller for calculation, and the current sharing adjustment signal Isctrl is obtained.

[0079] (5) Output the Share_PWM wave of current sharing adjustment according to the current sharing adjustment signal Isctrl, including the Share_PWM1 signal corresponding to the first full-bridge resonant transformation branch and the Share_PWM2 signal corresponding to the second full-bridge resonant transformation branch. The Share_PWM1 signal is processed by the NOT gate U5 to obtain the Share_PWM1_CTR signal, and the Share_PWM2 signal is processed by the NOT gate U6 to obtain the Share_PWM2_CTR signal. The Share_PWM1_CTR signal and the original drive signal PWM1 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM1_CTR of MOS transistors Q7 and Q10 in the first full-bridge resonant converter branch. The Share_PWM1_CTR signal and the original drive signal PWM2 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM2_CTR of MOS transistors Q8 and Q9 in the first full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM3 of the second full-bridge resonant converter branch are processed by the logic AND gate U3 to obtain the final drive signal PWM3_CTR of MOS transistors Q11 and Q14 in the second full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM4 of the second full-bridge resonant converter branch are processed by the logic AND gate U4 to obtain the final drive signal PWM4_CTR of MOS transistors Q12 and Q13 in the second full-bridge resonant converter branch.

[0080] In some embodiments, this application provides a switching power supply LLC interleaved parallel current sharing control device, which includes a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to execute the switching power supply LLC interleaved parallel current sharing control method in the above embodiments of this application.

[0081] The memory is connected to the processor. The memory can be flash memory, read-only memory or other types of memory. The processor can be a central processing unit or a microcontroller.

[0082] In some embodiments, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the switching power supply LLC interleaved parallel current sharing control method in the above embodiments of this application.

[0083] The computer-readable storage medium includes volatile or non-volatile, removable or non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, computer program modules or other data. Computer-readable storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other memory technologies, CD-ROM (Compact Disc Read-Only Memory), DVD or other optical disc storage, cartridges, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer.

[0084] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of this application, and this application is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this application, and these modifications and improvements are also considered to be within the scope of protection of this application.

Claims

1. A switching power supply LLC interleaved parallel current sharing control system, characterized in that, The system includes: a switching power supply conversion circuit, a controller, and a logic operation circuit; The switching power supply conversion circuit includes a filter module, a power factor correction (PFC) module, an interleaved full-bridge LLC resonant converter module, and a rectifier module connected in sequence. The interleaved full-bridge LLC resonant converter module includes a first full-bridge resonant converter branch and a second full-bridge resonant converter branch, and multiple switching transistors are provided in both the first full-bridge resonant converter branch and the second full-bridge resonant converter branch. The controller is connected to the switching power supply conversion circuit and the logic operation circuit respectively; The controller is used to acquire the output voltage setpoint and output current voltage sample value of the interleaved full-bridge LLC resonant converter module. Based on the output voltage setpoint and output current voltage sample value, the controller obtains the drive signals of multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through the logic operation circuit. The drive signals are used to control the working state of the switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch to achieve current sharing between the first full-bridge resonant converter branch and the second full-bridge resonant converter branch.

2. The LLC interleaved parallel current sharing control system for switching power supplies according to claim 1, characterized in that, The controller, based on the output voltage setpoint and the output current voltage sample value, obtains the drive signals for multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch through the logic operation circuit, including: The controller obtains the original drive signals of multiple switching transistors in the first full-bridge resonant converter branch and the second full-bridge resonant converter branch based on the output voltage setting value and the output current voltage sampling value. Based on the output current sample value in the output current voltage sample value, it is determined whether current sharing control is required; the output current sample value includes the first output current of the first full-bridge resonant converter branch and the second output current of the second full-bridge resonant converter branch. If current sharing control is required, the current sharing adjustment signal is obtained based on the output current sampling value; Based on the original driving signal and the current sharing adjustment signal, the final driving signal of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch is obtained through the logic operation circuit. The final driving signal is used to control the working state of the switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch to achieve current sharing between the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch.

3. The LLC interleaved parallel current sharing control system for switching power supplies according to claim 2, characterized in that, The controller obtains the original drive signals for multiple switching transistors in the first and second full-bridge resonant conversion branches based on the output voltage setpoint and the output current and voltage sample values, including: The reference current value Iref is determined based on the output voltage setting value Voutref and the output voltage sampling value Vo in the output current and voltage sampling values. Based on the first output current Io1, the second output current Io2, and the reference current value Iref, the original driving signals of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch are obtained.

4. The LLC interleaved parallel current sharing control system for switching power supplies according to claim 3, characterized in that, The reference current value Iref is determined based on the output voltage setting value Voutref and the output voltage sampling value Vo from the output current and voltage sampling values, including: The output voltage sample value Vo is low-pass filtered to obtain the feedback value Voutfb used for output voltage loop control; The feedback value Voutfb is compared with the output voltage setpoint Voutref to obtain the voltage error Verror. The voltage error value Verror is input into the voltage loop PI controller for calculation, resulting in the Vctrl signal; After the Vctrl signal is amplitude-limited, the first current-limiting setpoint Iref1 is obtained, and the second current-limiting setpoint Iref2 corresponding to the interleaved full-bridge LLC resonant converter module is determined. The smaller of the first current limiting setpoint Iref1 and the second current limiting setpoint Iref2 is determined as the reference current value Iref.

5. The LLC interleaved parallel current sharing control system for switching power supplies according to claim 3, characterized in that, Based on the first output current Io1, the second output current Io2, and the reference current value Iref, the original driving signals for multiple switching transistors in the first and second full-bridge resonant transformation branches are obtained, including: The first output current Io1 and the second output current Io2 are filtered respectively to obtain the first output current sample value Io1fb and the second output current sample value Io2fb. The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current and Iofb. The output current Iofb is compared with the reference current value Iref to obtain the current error Ierror; The current error value Ierror is input into the current loop PI controller for calculation, resulting in the Ictrl signal; The Ictrl signal is converted and limited to obtain the switching frequency fs of the LLC resonant converter; The original driving signals PWM1 and PWM2 of the first full-bridge resonant converter branch, and the original driving signals PWM3 and PWM4 of the second full-bridge resonant converter branch are obtained based on the switching frequency fs.

6. The LLC interleaved parallel current sharing control system for switching power supplies according to claim 5, characterized in that, Based on the output current sample value in the output current voltage sample value, determine whether current sharing control is required, including: The first output current sample value Io1fb and the second output current sample value Io2fb are summed to obtain the output current and Iofb. If the output current and Iofb are greater than the first preset current threshold Iset1, then it is determined that current sharing control is required. If the output current and Iofb are less than the second preset current threshold Iset2, it is determined that current sharing control is not required, wherein the first preset current threshold Iset1 is greater than the second preset current threshold Iset2.

7. The LLC interleaved parallel current sharing control system for switching power supplies according to claim 6, characterized in that, The current sharing adjustment signal is obtained based on the output current sampling value, including: Determine the output current and half of Iofb as the current sharing loop setpoint Ishareref; The larger of the first output current sampling value Io1fb and the second output current sampling value Io2fb is determined to be the current sharing value Isfb; The current sharing loop setpoint Ishareref and the current sharing current value Isfb are compared to obtain the current sharing error Iseeror; The current sharing error value Iseror is input into the current sharing loop PI controller for calculation, and the current sharing adjustment signal Isctrl is obtained.

8. The switching power supply LLC interleaved parallel current sharing control system according to claim 7, characterized in that, The first full-bridge resonant converter branch includes the first branch MOSFETs Q7 and Q9 (upper MOSFETs) and Q8 and Q10 (lower MOSFETs); the second full-bridge resonant converter branch includes the second branch MOSFETs Q11 and Q13 (upper MOSFETs) and Q12 and Q14 (lower MOSFETs). The logic operation circuit includes AND gates U1, U2, U3 and U4, and NOT gates U5 and U6; Based on the original driving signal and the current sharing adjustment signal, the final driving signals for multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch are obtained through the logic operation circuit, including: The Share_PWM wave for current sharing regulation is output according to the current sharing regulation signal Isctrl, including the Share_PWM1 signal corresponding to the first full-bridge resonant transformation branch and the Share_PWM2 signal corresponding to the second full-bridge resonant transformation branch. The Share_PWM1 signal is processed by the NOT gate U5 to obtain the Share_PWM1_CTR signal, and the Share_PWM2 signal is processed by the NOT gate U6 to obtain the Share_PWM2_CTR signal. The Share_PWM1_CTR signal and the original drive signal PWM1 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM1_CTR of MOS transistors Q7 and Q10 in the first full-bridge resonant converter branch. The Share_PWM1_CTR signal and the original drive signal PWM2 of the first full-bridge resonant converter branch are processed by the logic AND gate U1 to obtain the final drive signal PWM2_CTR of MOS transistors Q8 and Q9 in the first full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM3 of the second full-bridge resonant converter branch are processed by the logic AND gate U3 to obtain the final drive signal PWM3_CTR of MOS transistors Q11 and Q14 in the second full-bridge resonant converter branch. The Share_PWM2_CTR signal and the original drive signal PWM4 of the second full-bridge resonant converter branch are processed by the logic AND gate U4 to obtain the final drive signal PWM4_CTR of MOS transistors Q12 and Q13 in the second full-bridge resonant converter branch.

9. A method for controlling the interleaved parallel current sharing of LLC switching power supplies, characterized in that, The method, applied to the switching power supply LLC interleaved parallel current sharing control system as described in any one of claims 1 to 8, comprises: Obtain the output voltage setpoint and output current / voltage sample values ​​of the interleaved full-bridge LLC resonant converter module. Based on the output voltage setting value and the output current and voltage sampling value, the driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained through the logic operation circuit. The driving signals are used to control the working state of the switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch to achieve current sharing between the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch.

10. The method for interleaved parallel current sharing control of LLC switching power supply according to claim 9, characterized in that, The step of obtaining drive signals for multiple switching transistors in the first and second full-bridge resonant converter branches through logic operation circuits based on the output voltage setpoint and the output current and voltage sampled values ​​includes: Based on the output voltage setting value and the output current voltage sampling value, the original driving signals of multiple switching transistors in the first full-bridge resonant conversion branch and the second full-bridge resonant conversion branch are obtained. Based on the output current sampling value in the output current voltage sampling value, it is determined whether current sharing control is required; the output current sampling value includes the first output current Io1 of the first full-bridge resonant converter branch and the second output current Io2 of the second full-bridge resonant converter branch. If current sharing control is required, the current sharing adjustment signal is obtained based on the output current sampling value; Based on the original driving signal and the current sharing adjustment signal, the final driving signal of multiple switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch is obtained through the logic operation circuit. The final driving signal is used to control the working state of the switching transistors in the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch to achieve current sharing between the first full-bridge resonant transformation branch and the second full-bridge resonant transformation branch.

Images