Semiconductor equipment

Abstract

To provide a semiconductor device that can suppress the degradation of its characteristics due to temperature cycling. [Solution] The semiconductor device comprises a frame having an inner wall surface, a semiconductor element housed in the frame, and an epoxy resin material provided inside the frame, sealing the semiconductor element and containing a filler. The epoxy resin material has a base portion with a flat surface on its surface, and a raised portion that rises from the base portion along the inner wall surface and has a curved surface on its surface. The curved surface is located between the flat surface and the inner wall surface, and a gap exists between the raised portion and the inner wall surface that connects to the curved surface.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor device used in a power module, a semiconductor element is housed in a frame body, and the semiconductor element is sealed with a sealing resin material. An epoxy resin material is known as a sealing resin material for such applications.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device using an epoxy resin material as a sealing resin material, due to the repeated on and off of the semiconductor element, the epoxy resin material undergoes a temperature cycle, and damage such as cracks may occur in the epoxy resin material. When damage such as cracks occurs in the epoxy resin material, the characteristics of the semiconductor device may deteriorate.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing deterioration of characteristics associated with temperature cycles.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure comprises a frame having an inner wall surface, a semiconductor element housed in the frame, and an epoxy resin material provided within the frame, sealing the semiconductor element and containing a filler, wherein the epoxy resin material has a base portion having a flat surface on its surface, and a raised portion that rises from the base portion along the inner wall surface and has a curved surface on its surface, the curved surface being located between the flat surface and the inner wall surface, and a gap connecting to the curved surface existing between the raised portion and the inner wall surface. [Effects of the Invention]

[0007] According to this disclosure, it is possible to suppress the degradation of properties associated with temperature cycling. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a cross-sectional view showing an enlarged view of region R1 in Figure 2. [Figure 4] Figure 4 shows an SEM image including the base and raised portion. [Figure 5] Figure 5 shows an SEM image of region R2 in Figure 4. [Figure 6] Figure 6 shows an SEM image of region R3 in Figure 5. [Figure 7] Figure 7 shows an SEM image of region R4 in Figure 4. [Figure 8] Figure 8 shows an SEM image of region R5 in Figure 7. [Modes for carrying out the invention]

[0009] The implementation methods are described below.

[0010] [Description of Embodiments in this Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated. In the following description, an XYZ orthogonal coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the posture of the semiconductor device. Also, depending on the viewpoint, the +Z side may be referred to as the upper side, the upper portion, or above, and the -Z side may be referred to as the lower side, the lower portion, or below. In the present disclosure, "plan view" means viewing an object from above, and "plan shape" means the shape of an object viewed from above.

[0011] 〔1〕 A semiconductor device according to an aspect of the present disclosure includes a frame body having an inner wall surface, a semiconductor element housed in the frame body, and an epoxy resin material provided in the frame body for sealing the semiconductor element and containing a filler. The epoxy resin material has a base portion having a flat surface on the surface and a raised portion that rises from the base portion along the inner wall surface and has a curved surface on the surface. The curved surface is between the flat surface and the inner wall surface, and there is a gap connecting to the curved surface between the raised portion and the inner wall surface.

[0012] When the semiconductor element repeatedly turns on and off, the epoxy resin material repeatedly expands and contracts thermally. Such repeated thermal expansion and contraction, that is, a temperature cycle, causes thermal stress to act on the epoxy resin material. However, the thermal stress concentrates on the raised portion, and it is difficult for the thermal stress to act on the base portion. Also, due to the presence of a gap between the raised portion and the inner wall surface, the raised portion is likely to contract thermally without being restricted by the frame body. Therefore, damage such as cracks in the epoxy resin material is unlikely to occur, and deterioration of characteristics associated with the temperature cycle can be suppressed.

[0013] 〔2〕 In 〔1〕, the curved surface may be curved so as to rise as it approaches the inner wall surface. In this case, thermal stress is likely to concentrate on the tip of the raised portion, and in particular, the tip is less likely to be restricted by the frame body, so it is easy to suppress damage such as cracks associated with the temperature cycle.

[0014] 〔3〕In [1] or [2], when viewed in cross-section, the equivalent circle diameter of the filler contained in the raised portion may all be 10 μm or less. When forming an epoxy resin material using a liquid epoxy resin containing a filler, a raised portion is formed due to surface tension, but a filler with an equivalent circle diameter greater than 10 μm is unlikely to be contained in the raised portion.

[0015] 〔4〕In any one of [1] to [3], when viewed in cross-section, in the base portion, the number of fillers with an equivalent circle diameter of 5 μm or more may be 0.1 or more per mm 2 This case makes it easy to obtain high strength at the base.

[0016] 〔5〕In any one of [1] to [4], the depth of the gap may be equal to or less than the height of the raised portion. In this case, it is easy to suppress the expansion of cracks starting from the gap.

[0017] 〔6〕In any one of [1] to [5], the height of the raised portion may be 0.1 mm or more and 1.5 mm or less. If the height of the raised portion is less than 0.1 mm, there is a risk that thermal stress may easily act on the base. Also, if the height of the raised portion is greater than 1.5 mm, there is a risk that damage such as cracks may easily occur in the raised portion.

[0018] 〔7〕In any one of [1] to [6], the width of the raised portion may be 0.1 mm or more and 3 mm or less. If the width of the raised portion is less than 0.1 mm, there is a risk that thermal stress may easily act on the base. Also, if the width of the raised portion is greater than 3 mm, there is a risk that damage such as cracks may easily occur in the raised portion.

[0019] 〔8〕In any one of [1] to [7], the width of the gap may be 5 μm or more and 50 μm or less. If the width of the gap is less than 5 μm, depending on the magnitude of the thermal stress, the raised portion may be restricted by the frame. Also, it is difficult to form a gap with a width greater than 50 μm.

[0020] [9] In any of [1] to [8], the surface roughness Ra of the inner wall surface may be 0.01 μm or more and 1.0 μm or less. Having a surface roughness Ra of 0.01 μm or more and 1.0 μm or less makes it easier to form appropriately sized raised portions and gaps.

[0021] [Embodiments of this Disclosure] The embodiments relate to semiconductor devices. Figure 1 is a plan view showing a semiconductor device according to the embodiment. Figure 2 is a cross-sectional view showing a semiconductor device according to the embodiment. Figure 3 is a cross-sectional view showing an enlarged view of region R1 in Figure 2. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0022] As shown in Figure 1, the semiconductor device 1 according to this embodiment includes an insulating substrate 10, conductive layers 11 and 12, bonding materials 13 and 14, external terminals 15 and 16, a die 17, a semiconductor element 20, a frame 30, and an epoxy resin material 40.

[0023] The frame 30 has an inner wall surface 30A and an outer wall surface 30B opposite to the inner wall surface 30A. The planar shape of the inner wall surface 30A and the planar shape of the outer wall surface 30B are rectangular. The inner wall surface 30A and the outer wall surface 30B may have protrusions or recesses formed therein for contact with other members, etc. The material of the frame 30 is, for example, a thermoplastic resin. The material of the frame 30 may be a super engineering plastic or an engineering plastic. Examples of super engineering plastics are amorphous polyarylate, polysulfone, polyethersulfone, polyphenylene sulfide, polyetheretherketone, polyimide, polyetherimide, and liquid crystal polymer. Examples of engineering plastics are polyacetal, polyamide, polycarbonate, modified polyphenylene ether, polybutylene terephthalate, glass fiber reinforced polyethylene terephthalate, ultra-high molecular weight polyethylene, and syndiotactic polyethylene. The material of the frame 30 may be, for example, polyethylene, polypropylene, polyvinyl chloride, polystyrene, polyvinyl acetate, acrylonitrile butadiene styrene, or acrylic.

[0024] The insulating substrate 10 is housed in a frame 30. The insulating substrate 10 has a first main surface 10A and a second main surface 10B opposite to the first main surface 10A. The first main surface 10A is the top surface, and the second main surface 10B is the bottom surface. The material of the insulating substrate 10 is, for example, silicon nitride (SiN), aluminum oxide (Al2O3), or aluminum nitride (AlN). A conductive layer 11 is provided on the first main surface 10A, and a conductive layer 12 is provided on the second main surface 10B. The material of the conductive layers 11 and 12 is, for example, copper (Cu). The conductive layers 11 and 12 are, for example, copper plates or copper foils.

[0025] The die 17 is joined to the conductive layer 11 by a bonding material 13. The die 17 is located above the conductive layer 11. The material of the die 17 is, for example, copper. The die 17 is, for example, a copper plate. The bonding material 13 is, for example, solder or a metal sintered material.

[0026] The semiconductor element 20 is bonded to the die 17 by a bonding material 14. The semiconductor element 20 is located on the upper side of the die 17. The semiconductor element 20 is housed in a frame 30. The semiconductor element 20 is, for example, a field-effect transistor (FET) or an insulated-gate bipolar transistor (IGBT). The semiconductor element 20 may also be a Schottky barrier diode (SBD). The bonding material 14 is, for example, solder or a metal sintered material and is conductive. The semiconductor element 20 has a semiconductor substrate 21, an electrode 22 provided on the upper surface of the semiconductor substrate 21, and an electrode 23 provided on the lower surface of the semiconductor substrate 21. The semiconductor substrate 21 has, for example, a silicon carbide single crystal substrate and a silicon carbide epitaxial layer provided on the silicon carbide single crystal substrate.

[0027] External terminals 15 and 16 are fixed to the frame 30. External terminal 15 and electrode 22 are connected to each other by a wire (not shown). External terminal 16 and die 17 are connected to each other by a wire (not shown). Electrode 23 is electrically connected to die 17 via a bonding material 14.

[0028] The epoxy resin material 40 is provided within the frame 30 and encapsulates the semiconductor element 20. The epoxy resin material 40 contains a filler 43. The filler 43 is, for example, silicon oxide, aluminum oxide, boron nitride, aluminum nitride, graphite, carbon fiber, iron powder, calcium oxide, or magnesium oxide.

[0029] The epoxy resin material 40 has a base portion 41 and a raised portion 42. The base portion 41 has a flat surface 41A on its surface. The base portion 41 is in contact with the semiconductor element 20. The raised portion 42 rises from the base portion 41 in the +Z direction along the inner wall surface 30A and has a curved surface 42A on its surface. The curved surface 42A is curved so that it rises more as it approaches the inner wall surface 30A. A gap 45 exists between the raised portion 42 and the inner wall surface 30A. The gap 45 connects to the curved surface 42A. Therefore, the upper end of the gap 45 has an opening. The depth D of the gap 45 is not particularly limited, but for example it is less than or equal to the height H of the raised portion 42. The depth D of the gap 45 is the depth of the deepest part of the gap 45, and the height H of the raised portion 42 is the height of the highest part of the raised portion 42 relative to the flat surface 41A.

[0030] Next, the manufacturing method of the semiconductor device 1 will be described. When manufacturing the semiconductor device 1, first, a first structure is prepared in which an insulating substrate 10, conductive layers 11 and 12, bonding materials 13 and 14, a die 17, and a semiconductor element 20 are integrated. A second structure is also prepared in which external terminals 15 and 16 and a frame 30 are integrated. Next, the first structure is housed in the second structure, and wire bonding is performed to connect the external terminal 15 and the electrode 22, and wire bonding is performed to connect the external terminal 16 and the die 17. Next, a thermosetting epoxy resin containing filler and in an uncured liquid state is injected into the inside of the frame 30.

[0031] Next, the epoxy resin is cured by heat treatment to obtain an epoxy resin material 40. The heat treatment temperature at this time is, for example, 120°C to 250°C. By performing heat treatment under these conditions, surface tension acts on the liquid epoxy resin, and an epoxy resin material 40 having a base portion 41 and a raised portion 42 is obtained, and a gap 45 is formed between the raised portion 42 and the inner wall surface 30A.

[0032] In this way, semiconductor device 1 is manufactured.

[0033] In the semiconductor device 1, when the semiconductor element 20 is operating, the semiconductor element 20 generates heat, and the temperature of the epoxy resin material 40 rises to, for example, 150°C or higher. When the semiconductor element 20 is not operating, the temperature of the epoxy resin material 40 is about the same as the ambient temperature, for example, between 10°C and 30°C. Therefore, as the semiconductor element 20 repeatedly turns on and off, the epoxy resin material 40 repeatedly undergoes thermal expansion and contraction. This repeated thermal expansion and contraction, i.e., temperature cycle, acts on the epoxy resin material 40, but in this embodiment, the thermal stress is concentrated in the raised portion 42, and the base portion 41 in contact with the semiconductor element 20 is less susceptible to thermal stress. Furthermore, because a gap 45 exists between the raised portion 42 and the inner wall surface 30A, the raised portion 42 is less constrained by the frame 30 and can easily undergo thermal contraction. Therefore, according to this embodiment, damage such as cracks in the epoxy resin material 40 is less likely to occur, and deterioration of properties due to temperature cycles can be suppressed.

[0034] As the curved surface 42A curves upwards as it approaches the inner wall surface 30A, thermal stress tends to concentrate at the tip of the raised portion 42. In particular, the tip is less constrained by the frame, making it easier to suppress damage such as cracks caused by temperature cycling.

[0035] In a cross-sectional view, the equivalent circular diameter of the filler 43 contained in the raised portion 42 is, for example, 10 μm or less in all cases. When forming the epoxy resin material 40 using a liquid epoxy resin containing filler, the raised portion 42 is formed by surface tension as described above, but filler with an equivalent circular diameter larger than 10 μm remains in the base 41 and is less likely to be included in the raised portion 42. The equivalent circular diameter of the filler 43 contained in the raised portion 42 may be 5 μm or less, 4 μm or less, or 3 μm or less in all cases.

[0036] In cross-sectional view, the base 41 contains fillers with an equivalent circular diameter of 5 μm or more, for example, at a rate of 0.1 pieces / mm². 2 The above is included. In this case, high strength can be easily obtained in the base 41. The base 41 contains 0.1 fillers / mm with an equivalent circular diameter of 10 μm or more. 2 The above may also be included, with one filler with an equivalent circular diameter of 10 μm or more per mm in the base 41. 2 The above may be included.

[0037] Since the depth D of the gap 45 is less than or equal to the height H of the raised portion, it is easier to suppress the propagation of cracks originating from the gap 45.

[0038] The height H of the raised portion 42 is, for example, 0.1 mm or more and 1.5 mm or less. If the height H of the raised portion 42 is less than 0.1 mm, there is a risk that thermal stress will easily act on the base portion 41. Also, if the height H of the raised portion 42 is greater than 1.5 mm, there is a risk that damage such as cracks will easily occur in the raised portion 42. The height H of the raised portion 42 may be 0.3 mm or more and 1.3 mm or less, or 0.5 mm or more and 1.1 mm or less.

[0039] The width W1 of the raised portion 42 is, for example, 0.1 mm or more and 3 mm or less. If the width W1 of the raised portion 42 is less than 0.1 mm, there is a risk that thermal stress will easily act on the base portion 41. Also, if the width W1 of the raised portion 42 is greater than 3 mm, there is a risk that damage such as cracks will easily occur in the raised portion 42. The width W1 of the raised portion 42 may be 0.3 mm or more and 2.5 mm or less, or 0.5 mm or more and 1.5 mm or less.

[0040] The width W2 of the gap 45 is, for example, 5 μm or more and 50 μm or less. If the width W2 of the gap 45 is less than 5 μm, the raised portion 42 may be constrained by the frame 30 depending on the magnitude of the thermal stress. Also, it is difficult to form a gap 45 with a width W2 greater than 50 μm. The width W2 of the gap 45 may be 10 μm or more and 40 μm or less, or 15 μm or more and 30 μm or less.

[0041] The surface roughness (arithmetic mean roughness) Ra of the inner wall surface 30A is, for example, 0.01 μm or more and 1.0 μm or less. In particular, in the portion facing the raised portion 42, the surface roughness Ra of the inner wall surface 30A is, for example, 0.01 μm or more and 1.0 μm or less. Having a surface roughness Ra of 0.01 μm or more and 1.0 μm or less of the inner wall surface 30A makes it easy to form a raised portion 42 and gap 45 of an appropriate size. The surface roughness Ra of the inner wall surface 30A may also be 0.03 μm or more and 0.8 μm or less, or 0.05 μm or more and 0.5 μm or less. The surface roughness Ra of the inner wall surface 30A can be measured using a tactile surface roughness measuring instrument.

[0042] The number of fillers 43 in the epoxy resin material 40 with an equivalent circle diameter of X μm or more (where X is, for example, 5 or 10) can be counted as follows: First, the base 41 or raised portion 42 is observed using a scanning electron microscope (SEM), and the number of fillers 43 with an equivalent circle diameter of X μm or more within a square field of view with sides of 100 μm is counted. Then, the number obtained in this way is measured in 1 mm². 2Convert to the number per unit. At this time, with respect to the base 41, if there are fillers 43 with an equivalent circle diameter of 50 μm or more within a square field of view with a side length of 100 μm, count the number of fillers 43 using a square field of view with a side length greater than 100 μm, and count per 1 mm 2 It may also be converted to a number per unit. Furthermore, with respect to the raised portion 42, if the raised portion 42 is small and there is space in addition to the raised portion 42 within a square field of view with a side length of 100 μm, the area of ​​the raised portion 42 within the field of view is determined, and the number of fillers 43 in that area is counted, and 1 mm 2 You can also convert it to the number per unit.

[0043] Furthermore, for fillers 43 that straddle the boundary of the field of view, if a portion of the filler 43 with a diameter of X μm or more exists within the field of view, the equivalent circle diameter is considered to be X μm or more; if no portion with a diameter of X μm or more exists, the equivalent circle diameter is considered to be less than X μm.

[0044] Furthermore, if there is a large variation in the equivalent diameter of the filler 43 across multiple fields of view, the average value across multiple fields of view, for example, five or more fields of view, can be used to determine the 1mm value. 2 You may specify the number of hits.

[0045] Here, we will describe SEM images of a semiconductor device actually manufactured by the present inventor. Figure 4 is a diagram showing an SEM image including the base portion 41 and the raised portion 42. Figure 5 is a diagram showing an SEM image of region R2 in Figure 4. Figure 6 is a diagram showing an SEM image of region R3 in Figure 5. Figure 7 is a diagram showing an SEM image of region R4 in Figure 4. Figure 8 is a diagram showing an SEM image of region R5 in Figure 7.

[0046] Figures 5 and 6 show the frame 30, the raised portion 42, and the gap 45, while Figures 7 and 8 show the frame 30 and the base 41. As shown in Figures 4 to 8, there is a gap 45 between the raised portion 42 and the inner wall surface 30A, but the base 41 and the inner wall surface 30A are in direct contact with each other.

[0047] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of Symbols]

[0048] 1: Semiconductor equipment 10: Insulating substrate 10A: First main surface 10B: Second main surface 11, 12: Conductive layer 13, 14: Bonding material 15, 16: External terminals 17: Die 20: Semiconductor elements 21: Semiconductor substrates 22, 23: Electrode 30:Frame body 30A: Interior wall surface 30B: External wall surface 40: Epoxy resin material 41: Base 41A:Flat surface 42: Excitement Club 42A: Curved surface 43: Filler 45: Gap R1, R2, R3, R4, R5: area

Claims

1. A frame having an inner wall surface, A semiconductor element housed in the aforementioned frame, Provided within the frame, encapsulating the semiconductor element, and comprising an epoxy resin material containing filler, It has, The epoxy resin material is A base having a flat surface, A raised portion that extends from the base along the inner wall surface and has a curved surface, It has, The curved surface is located between the flat surface and the inner wall surface. A semiconductor device having a gap between the raised portion and the inner wall surface that leads to the curved surface.

2. The semiconductor device according to claim 1, wherein the curved surface is curved so as it approaches the inner wall surface, with the curved surface becoming more raised as it approaches the inner wall surface.

3. The semiconductor device according to claim 1 or claim 2, wherein, in a cross-sectional view, the equivalent circular diameter of the filler contained in the raised portion is 10 μm or less in all cases.

4. In cross-sectional view, the base contains 0.1 fillers per mm with an equivalent circular diameter of 5 μm or more. ２ The semiconductor device according to claim 1 or claim 2, comprising the above.

5. The semiconductor device according to claim 1 or claim 2, wherein the depth of the gap is less than or equal to the height of the raised portion.

6. The semiconductor device according to claim 1 or claim 2, wherein the height of the raised portion is 0.1 mm or more and 1.5 mm or less.

7. The semiconductor device according to claim 1 or claim 2, wherein the width of the raised portion is 0.1 mm or more and 3 mm or less.

8. The semiconductor device according to claim 1 or claim 2, wherein the width of the gap is 5 μm or more and 50 μm or less.

9. The semiconductor device according to claim 1 or claim 2, wherein the surface roughness Ra of the inner wall surface is 0.01 μm or more and 1.0 μm or less.

Images