Semiconductor equipment

Abstract

To provide a semiconductor device whose characteristics can be improved. [Solution] The semiconductor device comprises a substrate, a semiconductor layer provided on a first surface of the substrate, a plurality of field plate electrodes provided within the semiconductor layer, the plurality of field plate electrodes located at the vertices of a triangle in a plane parallel to the first surface, and a gate electrode located between the plurality of field plate electrodes in a plane parallel to the first surface, the pattern surrounding one field plate electrode being hexagonal, and having six sides around one field plate electrode. The semiconductor layer has a first side surface which is six equivalent crystal planes facing each of the six sides of the gate electrode.

Description

Technical Field

[0003]

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] [[ID=))12]]There has been proposed a power semiconductor device in which trench gates are formed in a honeycomb shape between a plurality of columnar field plate electrodes arranged in close packing. <)

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device capable of improving characteristics.

Means for Solving the Problems

[0005] According to an embodiment, a semiconductor device includes a substrate having a first surface, a semiconductor layer provided on the first surface of the substrate, and a plurality of field plate electrodes provided in the semiconductor layer. The plurality of field plate electrodes are located at the vertices of a triangle in a plane parallel to the first surface, and in a plane parallel to the first surface, there is a pattern located between the plurality of field plate electrodes and surrounding the periphery of one of the field plate electrodes, which is hexagonal, and a gate electrode having six side surfaces around the one field plate electrode. The semiconductor layer has a first side surface which is six equivalent crystal surfaces respectively facing the six side surfaces of the gate electrode.

Brief Description of the Drawings

[0006] [Figure 1] This is a schematic plan view of a semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view of AA in Figure 1. [Figure 3] This is a schematic plan view of a semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. Note that the same components are denoted by the same reference numerals in each drawing.

[0008] Figure 1 is a schematic plan view showing the arrangement of the main components in the semiconductor device 1 according to the embodiment. Figure 2 is a cross-sectional view of AA in Figure 1. In Figure 1, the second electrode 32 and the insulating layer 63 shown in Figure 2 are omitted from the illustration.

[0009] As shown in Figure 2, the semiconductor device 1 according to this embodiment comprises a first electrode 31, a second electrode 32, a substrate 10, and a semiconductor layer 20. The substrate 10 and the semiconductor layer 20 are provided between the first electrode 31 and the second electrode 32. In this specification, the direction from the first electrode 31 toward the second electrode 32 is defined as up or upward, and the direction from the second electrode 32 toward the first electrode 31 is defined as down or downward.

[0010] The substrate 10 has a first surface 11 and a second surface 12 located on the opposite side of the first surface 11. The second surface 12 is in contact with the first electrode 31 and is electrically connected to the first electrode 31.

[0011] The semiconductor layer 20 is provided on the first surface 11 of the substrate 10. In this embodiment, the semiconductor layer 20 is described as having an n-type first conductivity and a p-type second conductivity, but the first conductivity may be p-type and the second conductivity may be n-type.

[0012] The semiconductor layer 20 has an n-type first semiconductor portion 21, a p-type second semiconductor portion 22 provided on the first semiconductor portion 21, and an n-type third semiconductor portion 23 provided on the second semiconductor portion 22. The n-type impurity concentration in the third semiconductor portion 23 is higher than that in the first semiconductor portion 21.

[0013] The second electrode 32 is provided on the semiconductor layer 20. The third semiconductor portion 23 is in contact with the second electrode 32 and is electrically connected to it. In addition, a portion 22A of the second semiconductor portion 22 adjacent to the third semiconductor portion 23 is in contact with the second electrode 32.

[0014] The semiconductor device 1 according to this embodiment has, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. In the MOSFET, the first electrode 31 is the drain electrode, the second electrode 32 is the source electrode, the first semiconductor portion 21 is the drift layer, the second semiconductor portion 22 is the base layer, the third semiconductor portion 23 is the source layer, and the substrate 10 functions as an n-type drain layer with a higher n-type impurity concentration than the first semiconductor portion 21.

[0015] Alternatively, the semiconductor device according to the embodiment may have a vertical IGBT (Insulated Gate Bipolar Transistor) structure. In the IGBT, the first electrode 31 functions as a collector electrode, the second electrode 32 as an emitter electrode, the first semiconductor portion 21 as a drift layer, the second semiconductor portion 22 as a base layer, the third semiconductor portion 23 as an emitter layer, and the substrate 10 as a p-type collector layer. In the IGBT, an n-type buffer layer with a higher n-type impurity concentration than the first semiconductor portion 21 may be provided between the substrate 10 (collector layer) and the first semiconductor portion 21 (drift layer).

[0016] The semiconductor device 1 according to this embodiment further comprises a gate electrode 50 and a gate insulating film 61.

[0017] The gate electrode 50 extends downward from the upper surface located on the side of the second electrode 32 in the semiconductor layer 20 and is located within the semiconductor layer 20. The gate electrode 50 is provided in a trench t formed in the semiconductor layer 20 via a gate insulating film 61. The lower end of the gate electrode 50 is located within the first semiconductor portion 21 below the pn junction between the second semiconductor portion 22 and the first semiconductor portion 21. As the material of the gate electrode 50, for example, polycrystalline silicon having conductivity can be used.

[0018] The gate insulating film 61 is provided between the gate electrode 50 and the semiconductor layer 20. The side surface 50A of the gate electrode 50 faces the second semiconductor portion 22 via the gate insulating film 61.

[0019] The semiconductor device 1 according to the embodiment further includes a field plate electrode 40 and a field insulating film 62.

[0020] The field plate electrode 40 extends downward from the upper surface of the semiconductor layer 20 and is located within the semiconductor layer 20. A plurality of columnar field plate electrodes 40 are provided within the semiconductor layer 20 via a field insulating film 62. Each field plate electrode 40 is provided in a hole h formed in the semiconductor layer 20 via a field insulating film 62. The field insulating film 62 is provided between the field plate electrode 40 and the semiconductor layer 20.

[0021] The field plate electrode 40 does not reach the substrate 10. The lower end portion of the field plate electrode 40 is located within the first semiconductor portion 21. The depth from the upper surface of the semiconductor layer 20 of the hole h in which the field plate electrode 40 is provided is deeper than the depth from the upper surface of the semiconductor layer 20 of the trench t in which the gate electrode 50 is provided. The shortest distance between the lower end of the field plate electrode 40 and the first electrode 31 is shorter than the shortest distance between the lower end of the gate electrode 50 and the first electrode 31. As the material of the field plate electrode 40, for example, polycrystalline silicon having conductivity can be used.

[0022] The semiconductor device 1 according to the embodiment further includes an insulating layer 63. The insulating layer 63 is provided between the upper surface of the gate electrode 50 and the second electrode 32.

[0023] When a first potential (for example, a positive potential) is applied to the first electrode 31, a second potential (for example, a ground potential) lower than the first potential is applied to the second electrode 32, and a gate voltage equal to or higher than the threshold value is applied to the gate electrode 50, an n-type channel is formed in a region of the second semiconductor portion 22 facing the side surface 50A of the gate electrode 50. A current flows between the first electrode 31 and the second electrode 32 through the substrate 10, the first semiconductor portion 21, the channel, and the third semiconductor portion 23, and the semiconductor device 1 is in an on state.

[0024] In the off state of the semiconductor device 1 in which the application of a voltage equal to or higher than the threshold value to the gate electrode 50 is stopped, a depletion layer spreads from the pn junction between the second semiconductor portion 22 and the first semiconductor portion 21 and the boundary between the field insulating film 62 and the first semiconductor portion 21, and the breakdown voltage of the semiconductor device 1 is maintained.

[0025] For example, the upper part of the field plate electrode 40 is in contact with the second electrode 32, and the field plate electrode 40 is electrically connected to the second electrode 32. Alternatively, the field plate electrode 40 may be electrically connected to the gate electrode 50. Such a field plate electrode 40 relaxes the electric field distribution of the first semiconductor portion 21 (drift layer) in the off state and improves the breakdown voltage of the semiconductor device 1. [[ID=I4]]

[0026] As shown in FIG. 1, in a plane parallel to the first surface 11 of the substrate 10 (in plan view), a plurality of triangles (regular triangles in this example) arranged in contact with each other without gaps are virtually indicated by a two-dot chain line. Each of the plurality of field plate electrodes 40 is arranged at the vertex of a triangle. Thereby, the gate electrode 50 can be arranged in a honeycomb mesh pattern between the plurality of field plate electrodes 40 arranged in the closest packing. Such a configuration enables reduction of the on-resistance as compared with a configuration in which the gate electrode 50 is arranged in a lattice mesh pattern between the plurality of field plate electrodes 40 arranged in a square lattice.

[0027] The gate electrode 50 is located between a plurality of field plate electrodes 40 in a plane parallel to the first surface 11 of the substrate 10 (in a plan view), and surrounds one field plate electrode 40 with a hexagonal pattern (regular hexagons in this example). The planar pattern of the gate electrode 50 is a honeycomb mesh pattern in which the multiple hexagonal patterns are repeated. The gate electrode 50 has six sides 50A around one field plate electrode 40. In a plane parallel to the first surface 11 of the substrate 10, the gate electrode 50 has an intersection 51 and extensions 52 extending from the intersection 51 in three different directions. The three extensions 52 are arranged around the intersection 51 at intervals of approximately 120°.

[0028] In a plan view, the semiconductor layer 20 located inside the hexagonal gate electrode 50 has six equivalent crystal planes, which are first side surfaces 20A, each facing one of the six side surfaces 50A of the gate electrode 50. The first side surfaces 20A correspond to the side walls of the trench t in which the gate electrode 50 is placed. The first side surfaces 20A include a region in the second semiconductor portion 22 where a channel is formed, and a third semiconductor portion 23, which includes a region in which the main current path in the ON state is formed.

[0029] The substrate 10 has a cubic crystal structure and is, for example, a silicon substrate. The first surface 11 of the substrate 10 is the (111) plane. The semiconductor layer 20 is a silicon layer epitaxially grown on the (111) plane of the substrate 10. Therefore, in the semiconductor layer 20, the plane parallel to the first surface 11 of the substrate 10 is the (111) plane. Also, the six first side surfaces 20A of the semiconductor layer 20 located inside the hexagonal gate electrode 50 in a plan view are planes perpendicular to the (111) plane and, due to the symmetry of the crystal lattice, are crystallographically equivalent {110} planes. Crystallographically equivalent planes mean that the arrangement of atoms and the spacing between atoms on that plane are the same.

[0030] Generally, a silicon layer is formed on the (100) plane of a silicon substrate. In this case, of the six sides of the silicon layer facing the six sides of the gate electrode, which is formed in a honeycomb pattern of multiple regular hexagons in a plan view, two are {100} planes and four are {470} planes. In these six sides of a silicon layer with a mixture of high Miller index planes, variations in characteristics are likely to occur due to differences in channel mobility and threshold depending on the plane orientation.

[0031] According to this embodiment, in the semiconductor layer 20 located inside the hexagonal gate electrode 50 in a plan view, by making all six first side surfaces 20A facing each of the six side surfaces 50A of the gate electrode equivalent crystal planes, variations in channel mobility and threshold values ​​across the six first side surfaces 20A can be reduced.

[0032] The gate insulating film 61 is, for example, a silicon oxide film, and can be formed by thermal oxidation after trenches t are formed in the semiconductor layer 20. According to this embodiment, the first side surface 20A of the semiconductor layer 20, which is the side wall of the trench t, ​​is an equivalent crystal plane in all directions in which the trench t extends when viewed in plan. Therefore, variations in the growth rate of the silicon oxide film on the six first side surfaces 20A mentioned above can be reduced, and variations in the thickness of the gate insulating film 61 located between the first side surfaces 20A and the side surface 50A of the gate electrode 50 can be reduced. This reduces variations in thresholds and the like.

[0033] Furthermore, the third surface 20C of the semiconductor layer 20 that constitutes the bottom surface of the trench t is parallel to the first surface 11 of the substrate 10 and is the (111) surface. In silicon, the growth rate of the silicon oxide film on the (110) surface and the growth rate of the silicon oxide film on the (111) surface are approximately the same. Therefore, variations in the thickness of the gate insulating film 61 located between the first side surface 20A and the side surface 50A of the gate electrode 50, and the thickness of the gate insulating film 61 located between the third surface 20C and the lower end of the gate electrode 50 can be reduced. As a result, local dielectric breakdown in the gate insulating film 61 is less likely to occur, and the breakdown voltage can be improved.

[0034] In this embodiment, the field plate electrode 40 extends columnarly within the semiconductor layer 20 in a direction parallel to the

[0111] direction. In the example shown in Figure 1, one field plate electrode 40 is a hexagonal prism having six side surfaces 40A. In plan view, the semiconductor layer 20 surrounding one field plate electrode 40 has six equivalent crystal planes, which are second side surfaces 20B, opposite each of the six side surfaces 40A of the field plate electrode 40. These six second side surfaces 20B are planes perpendicular to the (111) plane (first plane 11) of the substrate 10 and are equivalent {110} planes.

[0035] The field insulating film 62 is, for example, a silicon oxide film, and can be formed by thermal oxidation after forming hexagonal holes h in the semiconductor layer 20. In this embodiment, the six second side surfaces 20B of the semiconductor layer 20, which are the side walls of the holes h, are equivalent crystal planes. Therefore, variations in the growth rate of the silicon oxide film on the six second side surfaces 20B can be reduced, and variations in the thickness of the field insulating film 62 located between the second side surfaces 20B and the side surface 40A of the field plate electrode 40 can be reduced. As a result, local dielectric breakdown in the field insulating film 62 is less likely to occur, and the breakdown voltage can be improved.

[0036] Furthermore, the fourth surface 20D of the semiconductor layer 20 that constitutes the bottom surface of hole h is parallel to the first surface 11 of the substrate 10 and is the (111) surface. As described above, in silicon, the growth rate of the silicon oxide film on the (110) surface and the growth rate of the silicon oxide film on the (111) surface are approximately the same. Therefore, variations in the thickness of the field insulating film 62 located between the second side surface 20B and the side surface 40A of the field plate electrode 40, and the thickness of the field insulating film 62 located between the fourth surface 20D and the lower end of the field plate electrode 40 can be reduced. This makes it less likely for local dielectric breakdown to occur in the field insulating film 62 and improves the breakdown voltage.

[0037] The trench t in which the gate electrode 50 is placed can be formed in the semiconductor layer 20, for example, by the RIE (Reactive Ion Etching) method. In this case, the depth of the intersection where the extended portions of the trenches, which extend in three different directions in a plan view, meet is greater than the depth of the extended portions of the trenches. Therefore, the lower end of the intersection portion 51 of the gate electrode 50 is located below the lower end of the extended portion 52.

[0038] Between a single field plate electrode 40 and a hexagonal gate electrode 50 surrounding the field plate electrode 40 in a plan view, the shortest distance between the center of the field plate electrode 40 in a plan view and the center of the intersection 51 of the gate electrode 50 in a plan view is longer than the shortest distance between the center of the field plate electrode 40 and the extension 52 of the gate electrode 50. Due to this difference in distance, the electric field from the field plate electrode 40 is less likely to affect the intersection 51 of the gate electrode 50 than the extension 52. By positioning the lower end of the intersection 51 of the gate electrode 50 lower than the lower end of the extension 52, the electric field from the field plate electrode 40 is more likely to act on the lower end of the intersection 51 of the gate electrode 50, thereby mitigating the concentration of the electric field at the lower end of the intersection 51 of the gate electrode 50.

[0039] The field plate electrode 40 may be cylindrical, as shown in Figure 3. The shape of the hole h in plan view where the field plate electrode 40 is placed is circular.

[0040] The substrate 10 is not limited to a silicon substrate; for example, a gallium nitride (GaN) substrate may be used. In this case, by forming a GaN layer as the semiconductor layer 20 on the c-plane of the GaN substrate as the first surface 11 of the substrate 10, the surface orientations of the first side surface 20A and the second side surface 20B of the semiconductor layer 20 can be aligned with the equivalent m-plane. Furthermore, the same effect as described above can be obtained by using a silicon carbide (SiC) substrate as the substrate 10 and forming a SiC layer as the semiconductor layer 20 on the c-plane of the SiC substrate.

[0041] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0042] 1...Semiconductor device, 10...Substrate, 11...First surface, 12...Second surface, 20...Semiconductor layer, 20A...First side surface, 20B...Second side surface, 20C...Third surface, 20D...Fourth surface, 21...First semiconductor section, 22...Second semiconductor section, 23...Third semiconductor section, 31...First electrode, 32...Second electrode, 40...Field plate electrode, 40A...Side surface of field plate electrode, 50...Gate electrode, 50A...Side surface of gate electrode, 51...Intersection, 52...Stretched section, 61...Gate insulating film, 62...Field insulating film, 63...Insulating layer, h...Hole, t...Trench

Claims

1. A substrate having a first surface, A semiconductor layer provided on the first surface of the substrate, A plurality of field plate electrodes provided within the semiconductor layer, wherein a plurality of field plate electrodes are located at the vertices of a triangle in a plane parallel to the first plane, In a plane parallel to the first plane, the gate electrode is located between the plurality of field plate electrodes, the pattern surrounding one of the field plate electrodes is hexagonal, and the gate electrode has six sides around one of the field plate electrodes, Equipped with, A semiconductor device wherein the semiconductor layer has a first side surface which is six equivalent crystal planes facing each of the six side surfaces of the gate electrode.

2. The aforementioned substrate is a silicon substrate, The semiconductor layer is a silicon layer, The first face is the (111) face, The semiconductor device according to claim 1, wherein the six first surfaces are {110} surfaces.

3. The semiconductor device according to claim 2, wherein the field plate electrode extends in a direction parallel to the [111] direction within the semiconductor layer.

4. The aforementioned field plate electrode is a hexagonal prism having six sides, The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer has second surfaces which are six equivalent crystal planes facing each of the six surfaces of the field plate electrode.

5. The gate electrode has an intersection portion and extension portions extending in three different directions from the intersection portion. The semiconductor device according to any one of claims 1 to 3, wherein the lower end of the intersection portion is located below the lower end of the extended portion.

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