Semiconductor equipment

Abstract

Miniaturize semiconductor devices. [Solution] The semiconductor device 10 includes a circuit section including a base pattern 110 having a first terminal 111, a second terminal 120, and a third terminal 130; an N-type semiconductor element 200 and a P-type semiconductor element 300 located on the base pattern 110 and electrically connected to the base pattern 110, through which current flows in the thickness direction; a first connecting member 410 connecting the N-type semiconductor element 200 to the second terminal 120; and a second connecting member 420 connecting the P-type semiconductor element 300 to the third terminal 130.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

[0002] In semiconductor devices, miniaturization of semiconductor devices is required.

[0003] Patent Document 1 describes a miniaturized semiconductor device in which a semiconductor element 106 with a second adhesive layer is laminated on a semiconductor element 16 with a first adhesive layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An example of the object in the present invention is to miniaturize a semiconductor device.

Means for Solving the Problems

[0006] According to the present invention, the following semiconductor device is provided. [1] A circuit layer including a base pattern having a first terminal, a second terminal, and a third terminal, An N-type semiconductor element and a P-type semiconductor element that are located on the base pattern, electrically connected to the base pattern, and through which current flows in the thickness direction, A first connection member that connects the N-type semiconductor element to the second terminal, A second connection member that connects the P-type semiconductor element to the third terminal, And a semiconductor device having the above. [2] The maximum value of the amount of current controlled by the N-type semiconductor element and the P-type semiconductor element is 1 A or more. [1] The semiconductor device described above. [3] The N-type semiconductor element is located on the first surface of the base pattern, and the P-type semiconductor element is located on the second surface of the base pattern, which is the surface opposite to the first surface. The semiconductor device described in [1] or [2]. [4] The second and third terminals are located on the opposite side of the base pattern from the first terminal. A semiconductor device as described in any of [1] to [3]. [Effects of the Invention]

[0007] According to the present invention, semiconductor devices can be miniaturized. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 4] This is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 5] This is a cross-sectional view of the first process showing the manufacturing method of a semiconductor device. [Figure 6] This is a cross-sectional view of the second process, showing the manufacturing method of a semiconductor device. [Figure 7] This is a cross-sectional view of the third process, showing the manufacturing method of a semiconductor device. [Figure 8] This is a cross-sectional view of the fourth process, showing the manufacturing method of a semiconductor device. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings, similar components are denoted by similar reference numerals, and descriptions thereof may be omitted as appropriate. Note that the drawings are for illustrative purposes only. The shapes, dimensional ratios, etc. of the respective members in the drawings do not necessarily correspond to those of actual articles.

[0010] In this specification, the notation "a~b" in the description of a numerical range represents "a or more and b or less" unless otherwise specified. For example, "1 mass%~5 mass%" means "1 mass% or more and 5 mass% or less".

[0011] FIG. 1 is a diagram showing an example of a top view of a semiconductor device 10 according to the present embodiment. The semiconductor device 10 includes a circuit layer 100 including a base pattern 110 having a first terminal 111, a second terminal 120, and a third terminal 130, an N-type semiconductor element 200 and a P-type semiconductor element 300 that are located on the base pattern 110 and electrically connected to the base pattern 110, and through which current flows in the thickness direction, a first connection member 410 that connects the N-type semiconductor element 200 to the second terminal 120, and a second connection member 420 that connects the P-type semiconductor element 300 to the third terminal 130. In FIG. 1, a sealing layer 600 described later is only represented by an outline with a broken line. Also, as shown in the drawing, the second terminal 120 and the third terminal 130 may be located on the opposite side of the first terminal with the base pattern 110 interposed therebetween.

[0012] As shown in FIG. 1, the base pattern 110 has a substantially rectangular portion and a convex portion in a plan view. Both the N-type semiconductor element 200 and the P-type semiconductor element 300 are mounted on the substantially rectangular portion of the base pattern 110. Also, as an example, the convex portion serves as the first terminal 111.

[0013] In FIG. 1, the x direction is the direction in which the N-type semiconductor element 200 and the P-type semiconductor element 300 are arranged, and the y direction is the direction orthogonal to the x direction.

[0014] The distance in the x-direction between the center of the base pattern 110 (refer to the straight line L0 in FIG. 1) and the center of the first terminal 111 in the x-direction (refer to the straight line L1 in FIG. 1) is preferably small (0 in FIG. 1). Specifically, the distance in the x-direction between the center of the base pattern 110 and the center of the first terminal 111 in the x-direction is preferably 10% or less of the width W of the base pattern 110 in the x-direction, more preferably 5% or less, and even more preferably 1% or less.

[0015] Also, the difference between the distance W2 between the center of the N-type semiconductor element 200 in the x-direction (refer to the straight line l2 in FIG. 1) and the center of the first terminal 111 in the x-direction, and the distance W3 between the center of the P-type semiconductor element 300 in the x-direction (refer to the straight line l3 in FIG. 1) and the center of the first terminal 111 in the x-direction is preferably small. Specifically, the difference distance between W2 and W3 is preferably 10% or less of the width W of the base pattern 110 in the x-direction, more preferably 5% or less, and even more preferably 1% or less.

[0016] With the above configuration, it is possible to reduce the difference in electrical resistance and the difference in response speed between the electrical circuit via the N-type semiconductor element 200 and the electrical circuit via the P-type semiconductor element 300.

[0017] FIG. 2 is a cross-sectional view showing an overview of the semiconductor device 10 according to the present embodiment. As shown in FIG. 2, the first connection member 410 electrically connects the second terminal 120 and the terminal on the opposite side of the base pattern 110 of the N-type semiconductor element 200. Also, the second connection member 420 electrically connects the third terminal 130 and the terminal on the opposite side of the base pattern 110 of the P-type semiconductor element 300.

[0018] The N-type semiconductor element 200 is, as an example, a power MOSFET in which an NPN junction is formed between the source and the drain, and electrons serve as carriers.

[0019] The source and drain of the N-type semiconductor device 200 are located on opposite sides in the thickness direction. When a voltage is applied to the gate formed on the source side in the thickness direction, a channel is formed in the P-type semiconductor portion of the NPN junction, and current flows between the source and drain. In the N-type semiconductor device 200, the carriers are electrons, and the current flows from the drain towards the source.

[0020] From the standpoint of simplifying wiring, the drain side of the N-type semiconductor element 200 faces the base pattern 110. That is, the drain of the N-type semiconductor element 200 is connected to the first terminal 111, and the source is connected to the second terminal 120.

[0021] The P-type semiconductor device 300 is, as an example, a power MOSFET in which a PNP junction is formed between the source and drain, and holes act as carriers.

[0022] The source and drain of the P-type semiconductor device 300P are located on opposite sides in the thickness direction. When a voltage is applied to the gate formed on the source side in the thickness direction, a channel is formed in the N-type semiconductor portion of the PNP junction, and current flows between the source and drain. In the P-type semiconductor device 300, the carriers are holes, and the current flows from the source to the drain.

[0023] From the standpoint of simplifying wiring, the drain side of the P-type semiconductor element 300 faces the base pattern 110. That is, the drain of the P-type semiconductor element 300 is connected to the first terminal 111, and the source is connected to the third terminal 130.

[0024] Furthermore, the N-type semiconductor element 200 and the P-type semiconductor element 300 are connected in parallel to the first terminal 111. With the above configuration, the semiconductor device 10 according to this embodiment can pass current from the first terminal 111 to the second terminal 120 by controlling the N-type semiconductor element 200, and can pass current from the third terminal 130 to the first terminal 111 by controlling the P-type semiconductor element 300.

[0025] The semiconductor device 10 according to this embodiment is used, for example, in an electric vehicle. The first terminal 111 is connected to, for example, a motor, and the second terminal 120 and the third terminal 130 are connected to a power source, for example, a secondary battery. The semiconductor device 10 controls the N-type semiconductor element 200 to supply current from the motor to the power source and the P-type semiconductor element 300 to supply current from the power source to the motor, for example, when driving the motor or when generating power from the motor through regenerative braking. The control of the current flow described above can be switched as appropriate according to the frequency of the current, etc.

[0026] Furthermore, if the motor is driven by three-phase AC power, the motor can be driven by, for example, three semiconductor devices 10. In this case, each of the first terminals 111 of each semiconductor device 10 is connected to one of the u, v, or w phase terminals of the motor. In addition, the second terminals 120 and third terminals 130 of each semiconductor device 10 are connected to a power supply.

[0027] In the semiconductor device 10 according to this embodiment, the N-type semiconductor element 200 and the P-type semiconductor element 300 are mounted on the same base pattern 110. Therefore, the semiconductor device 10 is smaller than conventional semiconductor devices.

[0028] The details of each configuration are described below.

[0029] [N-type semiconductor device 200 and P-type semiconductor device 300] The N-type semiconductor element 200 and the P-type semiconductor element 300 control the flow of current in the thickness direction in the semiconductor device 10. As described above, the N-type semiconductor element 200 and the P-type semiconductor element 300 control the current between the motor and the secondary battery, for example.

[0030] The N-type semiconductor element 200 and the P-type semiconductor element 300 are, for example, power semiconductors. The N-type semiconductor element 200 and the P-type semiconductor element 300 control a current of 1A or more. This current may be 10A or more, or even 100A or more.

[0031] Furthermore, the N-type semiconductor element 200 and the P-type semiconductor element 300 may have the same dimensions and current specifications, or they may have different dimensions and current specifications.

[0032] Furthermore, in the example shown in Figures 1 and 2, one N-type semiconductor element 200 and one P-type semiconductor element 300 are provided, but two or more of each may be provided. Alternatively, the number of N-type semiconductor elements 200 and P-type semiconductor elements 300 may be different. Also, the current controlled by the semiconductor device 10 increases in approximately proportion to the number of N-type semiconductor elements 200 and P-type semiconductor elements 300. When two or more N-type semiconductor elements 200 and P-type semiconductor elements 300 are provided, the semiconductor device 10 may control a current of 400A or more, or a current of 900A or more.

[0033] [Circuit layer 100] The circuit layer 100 includes a base pattern 110, a second terminal 120, and a third terminal 130. The base pattern 110 includes a first terminal 111. The circuit layer 100 is formed, for example, by press-forming a metal plate. Alternatively, the circuit layer 100 is a general lead frame. The material constituting the circuit layer 100 can be one or more combinations of metals selected from, for example, copper, copper alloys, aluminum, and aluminum alloys, from the viewpoint of conductivity and mechanical strength. Among these, the material constituting the circuit layer 100 preferably includes copper from the viewpoint of heat resistance and cost.

[0034] Furthermore, the thickness T1 of the circuit layer 100 is not particularly limited, but the upper limit of the thickness T1 is, for example, 3.0 mm or less, preferably 2.5 mm or less, and more preferably 2.0 mm or less. By making the thickness T1 less than or equal to this value, the entire semiconductor device 10 can be made thinner. Furthermore, the lower limit of the thickness T1 is, for example, 0.3 mm or more, preferably 0.4 mm or more, and more preferably 0.5 mm or more. By making the thickness T1 greater than or equal to this value, the conductivity of the circuit layer 100 can be improved.

[0035] [First connecting member 410 and second connecting member 420] The first connecting member 410 connects the N-type semiconductor element 200 to the second terminal 120. The second connecting member 420 connects the P-type semiconductor element 300 to the third terminal 130.

[0036] The first connecting member 410 and the second connecting member 420 are, for example, Ag wire, Ni wire, Cu wire, Au wire, and Al wire. Preferably, the first connecting member 410 and the second connecting member 420 are made of Ag, Ni, or Cu, or an alloy containing one or more of these.

[0037] [Base board 500] The semiconductor device 10 according to this embodiment may include a base substrate 500, as shown in Figure 1. The base substrate 500 supports each of the above configurations and dissipates the heat generated by the N-type semiconductor element 200 and the P-type semiconductor element 300.

[0038] From the viewpoint of more efficiently dissipating the heat generated by the N-type semiconductor element 200 and the P-type semiconductor element 300, it is preferable that the base substrate 500 be provided with a heat dissipation member on the side opposite to the N-type semiconductor element 200 and the P-type semiconductor element 300. Furthermore, heat dissipation fins or radiators can be used as the heat dissipation member. The heat dissipation member may be integrated with the base substrate 500 or attached to the base substrate 500.

[0039] The material constituting the base substrate 500 can be one or more combinations of metals selected from, for example, copper, copper alloys, aluminum, and aluminum alloys, from the viewpoint of thermal conductivity and mechanical strength. Among these, the material constituting the base substrate 500 preferably contains at least one of copper or aluminum from the viewpoint of strength.

[0040] The thickness T2 of the base substrate 500 is not particularly limited, but the upper limit of the thickness T2 is, for example, 6 mm or less, preferably 5 mm or less, and more preferably 4 mm or less. By making the thickness T2 less than or equal to this value, the entire semiconductor device 10 can be made thinner. Furthermore, the lower limit of the thickness T2 is, for example, 1 mm or more, preferably 1.5 mm or more, and more preferably 2 mm or more. By making the thickness T2 greater than or equal to this value, the heat dissipation of the base substrate 500 can be improved.

[0041] [Sealing layer 600] The sealing layer 600 seals at least the N-type semiconductor element 200 and the P-type semiconductor element 300, suppressing deterioration of the N-type semiconductor element 200 and the P-type semiconductor element 300, as well as the connection parts. However, from the viewpoint of facilitating connection to a power supply, etc., it is preferable that at least a portion of the first terminal 111, the second terminal 120, and the third terminal 130 are not covered by the sealing layer 600. The sealing layer 600 is formed, for example, by a cured thermosetting resin. The thermosetting resin may be one or more selected from, for example, epoxy resin, phenolic resin, polyimide resin, bismaleimide resin, urea resin, melamine resin, polyurethane resin, cyanate ester resin, silicone resin, oxetane resin (oxetane compound), (meth)acrylate resin, unsaturated polyester resin, diallyl phthalate resin, benzoxazine resin, etc. In particular, if the material constituting the insulating layer 700 includes epoxy resin, it is preferable that the thermosetting resin also includes epoxy resin.

[0042] Further examples of thermosetting resins include novolac-type phenolic resins such as phenol novolac resins, cresol novolac resins, bisphenol A type novolac resins, and triazine skeleton-containing phenol novolac resins; Phenolic resins such as unmodified resol phenolic resins, oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc., phenol aralkyl resins such as phenol aralkyl resins and biphenyl aralkyl phenolic resins, and triphenylmethane phenolic resins; Bisphenol-type epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, tetramethylbisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol E type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin, and bisphenol Z type epoxy resin; novolac-type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin; Epoxy resins such as biphenyl-type epoxy resins, biphenyl aralkyl-type epoxy resins, arylalkylene-type epoxy resins, naphthalene-type epoxy resins, anthracene-type epoxy resins, phenoxy-type epoxy resins, dicyclopentadiene-type epoxy resins, norbornene-type epoxy resins, adamantane-type epoxy resins, fluorene-type epoxy resins, and trisphenylmethane-type epoxy resins; One or more types of resins can be selected from the following: resins having a triazine ring such as urea resin and melamine resin; unsaturated polyester resins; maleimide resins such as bismaleimide compounds; polyurethane resins; diallyl phthalate resins; silicone resins; benzoxazine resins; polyimide resins; polyamideimide resins; cyanate ester resins such as benzocyclobutene resin, novolac-type cyanate resin, bisphenol A-type cyanate resin, bisphenol E-type cyanate resin, tetramethylbisphenol F-type cyanate resin, etc.

[0043] The sealing layer 600 may also contain a filler. The materials constituting the filler may be one or more selected from silica, alumina, kaolin, talc, clay, mica, rock wool, wollastonite, glass powder, glass flakes, glass beads, glass fiber, silicon carbide, silicon nitride, aluminum nitride, carbon black, graphite, titanium dioxide, calcium carbonate, calcium sulfate, barium carbonate, magnesium carbonate, magnesium sulfate, barium sulfate, cellulose, aramid, or wood, etc.

[0044] [Insulating layer 700] The insulating layer 700 maintains insulation between the base substrate 500 and the circuit layer 100, and also functions as an adhesive layer to bond the circuit layer 100. Furthermore, it is preferable that the insulating layer 700 has thermal conductivity.

[0045] The thickness of the insulating layer 700 is set appropriately according to the purpose, but from the viewpoint of improving mechanical strength and heat resistance while more effectively transferring heat from the N-type semiconductor element 200 and the P-type semiconductor element 300 to the base substrate 500, the thickness of the insulating layer 700 is preferably 30 μm to 300 μm, and from the viewpoint of further improving the balance between heat dissipation and insulation of the base substrate 500 as a whole, it is more preferable to set it to 50 μm to 200 μm. By setting the thickness of the insulating layer 700 to the upper limit above, it is possible to easily transfer heat from the N-type semiconductor element 200 and the P-type semiconductor element 300 to the base substrate 500. Furthermore, by setting the thickness of the insulating layer 700 to the lower limit above, it is possible to sufficiently mitigate the generation of thermal stress due to the difference in thermal expansion coefficients between the base substrate 500 and the insulating layer 700. In addition, the insulation properties of the base substrate 500 are improved.

[0046] Furthermore, the insulating layer 700 according to this embodiment preferably has a thermal conductivity of 3 W / (m·K) or more, more preferably 7 W / (m·K) or more, and even more preferably 12 W / (m·K) or more.

[0047] The insulating layer 700 is formed, for example, by attaching a resin sheet containing a thermosetting resin and a thermally conductive filler to the first substrate 110 and the second substrate 120 and then thermosetting it. Alternatively, it is formed by applying a resin paste containing the above materials and then thermosetting it.

[0048] <Thermosetting resin> As the thermosetting resin in the above-mentioned resin paste, one or more types selected from epoxy resin, phenolic resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, and polyurethane resin can be used.

[0049] The upper limit of the thermosetting resin content in 100 parts by mass of resin paste is preferably 80 parts by mass or less, more preferably 70 parts by mass or less, and even more preferably 60 parts by mass or less. The lower limit of the thermosetting resin content in 100 parts by mass of resin paste is preferably 10 parts by mass or more, more preferably 15 parts by mass or more, and even more preferably 20 parts by mass or more.

[0050] <Thermal conductive filler> Furthermore, as the constituent material of the thermally conductive filler in the resin paste, for example, at least one of a metal oxide such as alumina and a nitride such as boron nitride can be used.

[0051] The upper limit of the content of thermally conductive filler per 100 parts by mass of thermosetting resin is preferably 400 parts by mass or less, more preferably 350 parts by mass or less, and even more preferably 320 parts by mass or less. The lower limit of the content of thermally conductive filler per 100 parts by mass of thermosetting resin is preferably 150 parts by mass or more, more preferably 200 parts by mass or more, and even more preferably 250 parts by mass or more.

[0052] As described above, the semiconductor device 10 according to this embodiment can be miniaturized.

[0053] [First variation] Next, a semiconductor device 10 according to the first modified example will be described. Figure 3 shows a cross-sectional view of the semiconductor device 10 according to the first modified example. As shown in Figure 3, the first modified example does not include a base substrate 500. The base pattern 110 supports the N-type semiconductor element 200 and the P-type semiconductor element 300.

[0054] In the first modified example, the thickness T1 of the circuit portion 100 including the base pattern 110 is preferably greater than that of the base substrate 500, for example, preferably 1 mm or more, and more preferably 2 mm or more.

[0055] As described above, the semiconductor device 10 can be miniaturized even in the first modified example.

[0056] [Second variation] Next, a semiconductor device 10 according to a second modified example will be described. Figure 4 shows a cross-sectional view of the semiconductor device 10 according to the second modified example. As shown in Figure 4, the base substrate 500 is not included in the second modified example either. The base pattern 110 supports the N-type semiconductor element 200 and the P-type semiconductor element 300.

[0057] Furthermore, in the second modified example, the N-type semiconductor element 200 and the P-type semiconductor element 300 are mounted on opposite sides of the base pattern 110. That is, the N-type semiconductor element 200 is located on the first surface of the base pattern 110, and the P-type semiconductor element 300 is located on the second surface, which is the opposite surface to the first surface of the base pattern 110. As a result, the area of ​​the base pattern 110 can be further reduced.

[0058] As described above, the semiconductor device 10 can be miniaturized in the second modified example as well. Furthermore, in the second modified example, since both sides of the base pattern 110 are used for mounting the N-type semiconductor element 200 and the P-type semiconductor element 300, the area of ​​the base pattern 110 can be further reduced.

[0059] [Manufacturing method for semiconductor device 10] Next, a method for manufacturing the semiconductor device 10 according to this embodiment will be described. Figure 5 is a cross-sectional view showing the process for manufacturing the semiconductor device 10 according to this embodiment.

[0060] First, as shown in Figure 5, a circuit layer 100 is formed on the base substrate 500 (step S10). Specifically, for example, the circuit layer 100 is formed by pressing a copper plate. Then, the resin sheet described above is placed on the base substrate 500, the circuit layer 100 is placed on the placed resin sheet, and the resin sheet is hardened by heating. As a result, the circuit layer 100 is formed on the base substrate 500, and an insulating layer 700 is formed between the base substrate 500 and the circuit layer 100.

[0061] Next, as shown in Figure 6, the N-type semiconductor element 200 and the P-type semiconductor element 300 are mounted on the base pattern 110 (step S20). Specifically, the N-type semiconductor element 200 and the P-type semiconductor element 300 are fixed onto the base pattern 110 using a conductive adhesive material such as a silver-containing paste.

[0062] Next, as shown in Figure 7, the first connecting member 410 and the second connecting member 420 are formed to electrically connect the second terminal 120 and the N-type semiconductor element 200, and the third terminal 130 and the P-type semiconductor element 300 (step S30). Specifically, for example, the first connecting member 410 and the second connecting member 420 are formed by soldering wire members such as copper wire.

[0063] Finally, as shown in Figure 8, the region containing at least the N-type semiconductor element 200 and the P-type semiconductor element 300 is sealed with a sealing layer 600. Specifically, the semiconductor device 10 is placed in a mold, and a sealing material containing a thermosetting resin is poured in and cured. The N-type semiconductor element 200 and the P-type semiconductor element 300 may be sealed separately or together. Furthermore, if there are multiple N-type semiconductor elements 200 and P-type semiconductor elements 300, they may be sealed separately or together.

[0064] The embodiments of the present invention have been described above with reference to the drawings, but these are merely examples of the present invention, and various other configurations can also be adopted. [Explanation of Symbols]

[0065] 10 Semiconductor Devices 100 Circuit section 110 Base Pattern 111 First terminal 120 Second terminal 130 Third terminal 200 N-type semiconductor device 300 P-type semiconductor device 410 First connecting member 420 Second connecting member 500 base board 600 sealing layer

Claims

1. A circuit layer including a base pattern having a first terminal, a second terminal, and a third terminal, An N-type semiconductor element and a P-type semiconductor element are located on the base pattern and electrically connected to the base pattern, and through which current flows in the thickness direction. A first connecting member for connecting the N-type semiconductor element to the second terminal, A second connecting member connects the P-type semiconductor element to the third terminal, Semiconductor device.

2. The maximum current controlled by the N-type semiconductor element and the P-type semiconductor element is 1A or more. The semiconductor device according to claim 1.

3. The N-type semiconductor element is located on the first surface of the base pattern, and the P-type semiconductor element is located on the second surface of the base pattern, which is the surface opposite to the first surface. The semiconductor device according to claim 1 or 2.

4. The second and third terminals are located on the opposite side of the base pattern from the first terminal. The semiconductor device according to claim 1 or 2.

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