Molded power semiconductor packages for improved thermal operation

Abstract

This invention provides a molded power semiconductor package that improves the cooling of the source connection. [Solution] A semiconductor device 1 comprising a die carrier 7 and a first semiconductor die 9 having at least a first load electrode and a second load electrode, wherein the first semiconductor die 9 is mounted on the die carrier 7, the first load electrode is electrically connected to the die carrier 7, a first set 3 of external connectors is electrically and thermally connected to the die carrier 7, a second set 4 of external connectors is separated from the die carrier 7 and electrically connected to the second load electrode 10, and the overall wire size of the second set 4 of external connectors is larger than the overall wire size of the first set of external connectors.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a die carrier and a first semiconductor die having at least a first load electrode and a second load electrode, the first semiconductor die being mounted on the die carrier, the first load electrode being electrically connected to the die carrier, a first set of external connectors being electrically and thermally connected to the die carrier, and a second set of external connectors being spaced apart from the die carrier and electrically connected to the second load electrode.

Background Art

[0002] The rated current in a TO package is limited by chip technology or drain pad area. When expanding the rated current beyond a certain point (generally about 150 A in TO247), wider leads are required.

[0003] In photovoltaic applications, generally, long lead / pin lengths are required. In the following description, the terms "pin", "lead", and "connector" may be used as synonyms.

[0004] When the ampacity limit is exceeded, ohmic heating of the pins causes a new over-temperature condition, i.e., the temperature of the pins exceeds the allowable temperature. Moreover, the temperature of the pins may exceed the allowable temperature of the substrate material, e.g., FR4, at the substrate connection point. This effect is most pronounced in the source leads since there is no direct cooling connection to an existing heat sink. Typically, the source posts inside the package are cooled to the substrate via the leads, while the drain pins are cooled via the heat sink, i.e., through the drain pad connection.

[0005] Therefore, there is a general need to improve the cooling of the source connection.

Summary of the Invention

[0006] According to a first aspect of the present disclosure, a semiconductor device of the above-described type is provided, wherein the overall wire size of a second set of external connectors is larger than the overall wire size of a first set of external connectors.

[0007] To ensure a constant ampere capacitance for each conductive element in the load current path of a semiconductor device, a constant minimum wire size, i.e., minimum conductive cross-sectional area, is required throughout the entire load current path. However, when a semiconductor device is switched on, all elements in the load current path heat up due to their own ohmic resistance. Therefore, thermal energy that needs to be dissipated to the surrounding environment is generated throughout the entire load current path. However, there are significant differences in thermal conductivity along the load current path. Specifically, the thermal conductivity on the source side is usually lower than that on the drain side. This is because the insulating properties on the source side are different from those on the drain side. As a result, the effective temperature on the source side, i.e., at the external source lead, is higher than that on the drain side, i.e., at the external drain lead.

[0008] By designing an asymmetrical number of leads with equal lead sizes, an additional source lead can be introduced, which, since no electrical contact is required, can be connected to an insulated heatsink. As a result, the wire size in the source connector is larger than the wire size in the drain connector. More specifically, the wire size of each connector in the first set of external connectors is equal to the wire size of each connector in the second set of external connectors. However, the overall wire size of the second set of external connectors, i.e., the overall conductive cross-sectional area, is larger than the overall conductive cross-sectional area of ​​the first set of external connectors. This allows for better thermal management of the source post and potentially enables a higher overall amperage capacity in the individual package.

[0009] An asymmetric lead ratio, i.e., an unequal number of source leads to drain leads, allows for thermal division. For example, two pin inputs (drains) and three pin outputs (sources) can each contact one pin separately without reducing the ampere capacity of the load current path.

[0010] Additional pins may be used, for example, to contact an insulating heatsink on a printed circuit board (PCB). This divides the flux of thermal energy, i.e., distributes it among several source pins. For example, the thermal load is reduced by only 50% with 4 pins to 2 pins, and by 33% with 3 pins to 2 pins.

[0011] In one embodiment, the semiconductor device includes a encapsulant that seals at least a portion of the first semiconductor die and at least the proximal end of each of the external connectors such that the distal ends of both the external connectors of a first set of external connectors and the external connectors of a second set of external connectors protrude from the encapsulant.

[0012] Since the proximal ends of both the second set of external connectors and the first set of external connectors are embedded in the encapsulant, the heat generated by the internal ohmic resistance of each proximal portion of the set of external connectors cannot be effectively dissipated because the encapsulant acts as an insulator. Therefore, the heat generated in the proximal portions of the external connectors needs to be directed out of the encapsulant by the external connectors themselves toward the distal ends of the external connectors. In particular, direct connection to the die pads, which can act as heat dissipators, is not available for the second set of external connectors, which may be source connections. Furthermore, the external source connectors are heated by any internal connectors that transfer heat from the source electrodes to the source connectors. That is, with respect to the load current path from the source electrodes of the semiconductor die toward the distal ends of the external source connectors, there is no possibility of further cooling other than the external connectors themselves. By providing an asymmetrical wire size along the load current path, i.e., an increased wire size in the external source connectors, heat transfer from the inside to the outside of the encapsulant is improved.

[0013] As a result of the above, a molded power semiconductor package with an asymmetrical pin / lead layout for thermally improved operation is provided.

[0014] In one embodiment, the die carrier is a lead frame, the lead frame comprising a first portion that forms a die pad. The die carrier may be a lead frame consisting of a single sheet of ground metal. However, the die carrier may be ceramic or AMB or DCB or an insulating metal substrate (IMS) or any other interposer. In addition, any isolation technique, such as FullPak, Advanced Isolation or a thermal interface material (TIM) sheet, may be applied to the opposite side of the chip carrier. The die carrier may be in contact with or attached to the thermal interface material (TIM).

[0015] In one embodiment, the second set of external connectors comprises at least one additional connector to the first set of external connectors.

[0016] In particular, at least one additional connector is a thermal connector to facilitate heat transfer from the inside of the encapsulant to the ambient environment. The additional connector provides an asymmetrical number of pins. The pins are of equal size, and the additional pins have a larger wire size in the source connector compared to the wire size in the drain connector.

[0017] In one embodiment, the semiconductor device comprises a lead post attached to a second set of external connectors, the lead post forming an integral part with the second set of external connectors. The second set of external connectors can be attached to the lead post, and the lead post brings together all the connectors into a single integral part. Thereafter, the lead post can act as a thermal dispersant.

[0018] In one embodiment, a first set of external connectors is an integral part with a first portion of the lead frame. The drain lead may be formed by grounding together with the first portion of the lead frame and thus may be in an integral thermal and electrical connection with the die pad. As a result, the drain pin is cooled through the drain pad connection. In detail, the drain lead may be cooled via a heat sink which may be coupled to the lead frame. The first set of external connectors may have a downset toward the die carrier such that the drain lead is inline and at the same height as the source lead.

[0019] In one embodiment, the semiconductor device is a single in-line package (SIP), and a first set of external connectors is laterally separated from a second set of external connectors by a distance greater than both the distance between the external connectors of the first set of external connectors and the distance between the external connectors of the second set of external connectors.

[0020] In a single in-line package, all external connectors are arranged in a line on the common side, i.e., on the common portion of the periphery surface of the package. That is, all leads protrude from the mold body in substantially the same direction and are substantially parallel on the same surface of the mold body. In this embodiment, the source lead and drain lead need to be spaced apart from each other to maintain a clearance distance corresponding to the voltage difference. In detail, the drain lead may be located on a first side, and the source lead and any control lead may be located on a second opposite side of the common portion of the periphery surface. The drain lead and the group of source lead and any control lead are spaced apart from each other, forming an asymmetric in-line pin layout on the mold body.

[0021] To ensure the required creepage distance along the surface of the mold body between the drain connector and the source connector, pockets may be placed on the surrounding surface of the sealant between a first set of external connectors and a second set of external connectors.

[0022] In one embodiment, the outermost surface of the die carrier is exposed from the encapsulant. To facilitate thermal connection to further devices, an exposed portion of the die carrier may be formed. This exposed portion of the die carrier is sometimes called an exposed die pad.

[0023] In particular, the outermost surface of the die carrier may be configured to be attached to a heat sink. A thermal interface material may be placed on the exposed outermost surface of the die carrier to connect the semiconductor device to the heat sink.

[0024] In one embodiment, the lateral dimension of each connector of the first set of external connectors is equal to the lateral dimension of each connector of the second set of external connectors. That is, the connectors can be of equal size. The connectors can also have the same conductive cross-sectional area, i.e., wire size. If the connectors are of equal size, only one size of the second-level connectors, e.g., the through-hole size of the PCB, is required, which facilitates the attachment to the second-level devices, e.g., the printed circuit board. This reduces the manufacturing effort on the customer side.

[0025] In one embodiment, at least one additional connector is configured to be attached to a heat sink, e.g., to the copper-plated insulating area of a printed circuit board (PCB). Since the additional pins are not required for electrical purposes, i.e., not required to carry drain-source current, the additional pins can be used as thermal pins. This means that the additional pins are for only thermal purposes and can thus be used to connect to the heat sink to cool the source connection.

[0026] In one embodiment, the die carrier includes a second portion that forms a tie bar, and the second portion is disposed on the opposite side with respect to the external connector. The tie bar is disposed on the side of the lead frame opposite to the side where the pins are attached. The tie bar keeps the array of lead frames in a predetermined position during the manufacturing process. In particular, the tie bar serves as a connection between the lead frames during the manufacturing process to provide mechanical stability. Rotation of the lead frame during the manufacturing process, and thus misalignment between the lead frame and the semiconductor die, is prevented.

[0027] In one embodiment, the semiconductor device includes a second semiconductor die attached to the die carrier, the second semiconductor die being electrically and thermally connected to the lead post by an internal electrical connector, the internal electrical connector being formed by, for example, one of wire bonding, wedge bonding, nail head bonding, or a clip. In particular, materials such as Al, Cu, or Ag can be used for the internal electrical connector. The second semiconductor die can be a diode or a second transistor. A combination of a transistor die and a diode or several transistors is possible. For example, the first semiconductor die and the second semiconductor die may form a half - bridge configuration.

[0028] In one embodiment, the first semiconductor die is one of a MOSFET, an IGBT, a JFET, an SFET, a bipolar transistor, or a GaN HEMT, and the second semiconductor die is a diode.

[0029] In one embodiment, the lead post includes a first portion to which a second set of external connectors of the external connectors are attached, and a second portion extending between the second set of external connectors and the first set of external connectors to which an internal electrical connector from the second semiconductor die is attached. Thereby, the lead post is partitioned into two portions, each portion being for attaching an internal electrical connector from each semiconductor die.

[0030] In one embodiment, the external connectors of the second set of external connectors are attached to the lead post by a trapezoidal interconnect portion having a mold lock. Due to the trapezoidal shape of the interconnect portion and the reduction of the effective via size, the effective conductive cross - sectional area in the interconnect portion decreases. Thereby, a circular - shaped mold lock may be required to mitigate the delamination effect between the external connector and the mold compound on the surrounding surface of the mold compound.

[0031] In one embodiment, the second portion of the lead post is staggered to maintain the largest possible wire size toward the interconnect portion. By staggering the second portion of the lead post, the effective conductive cross-sectional area relative to the input current is increased. This can ensure a larger heat dissipation surface with a thermal dispersion effect.

[0032] Furthermore, the semiconductor device may include an overcurrent protection circuit (OCP-IC) and / or a gate driver circuit. Both the OCP-IC and the gate driver may be mounted on a lead frame together with the first and second semiconductor dies. Additional external electrical connectors for controlling each IC may be located in place.

[0033] In one embodiment, the first semiconductor die comprises a control electrode and a third set of external connectors, the third set of external connectors comprising at least one control connector connected to the control electrode of the first semiconductor die, and the third set of external connectors being laterally separated from the first set of external connectors by a second set of external connectors.

[0034] According to a second aspect of the present disclosure, a single in-line package (SIP) is provided, wherein a set of external drain connectors, a set of external source connectors, and a set of external control connectors are arranged along the respective periphery package surface such that the external connectors form an asymmetrical arrangement, and the overall wire size of the set of external source connectors is greater than the overall wire size of the set of external drain connectors. The external connectors may form an asymmetrical arrangement in the sense of an asymmetrical number of leads, an asymmetrical lead layout along one edge of the single in-line package, and / or more specifically, an asymmetrical wire size along the load current path with respect to the external source and drain connectors.

[0035] A third aspect of the present disclosure provides a system comprising a first semiconductor device and a second semiconductor device according to a first or second aspect of the present disclosure, wherein the first semiconductor device and the second semiconductor device are electrically connected and arranged in parallel such that the outermost exposed surfaces of the die carriers of the semiconductor devices are in the same plane.

[0036] In one embodiment of a third aspect of the present disclosure, the system further comprises a common heat sink to which the respective exposed outermost surfaces of the die carriers of the first semiconductor device and the second semiconductor device are thermally coupled.

[0037] Exemplary embodiments of this disclosure will be described with reference to the following figures. [Brief explanation of the drawing]

[0038] [Figure 1a] This figure shows a semiconductor device as disclosed herein. [Figure 1b] This figure shows a semiconductor device as disclosed herein. [Figure 2a] This figure shows an internal diagram of a semiconductor device as disclosed herein. [Figure 2b] This figure shows an internal diagram of a semiconductor device as disclosed herein. [Figure 3a] This figure shows a cross-sectional view of a semiconductor device according to this disclosure. [Figure 3b] This figure shows a cross-sectional view of a semiconductor device according to this disclosure. [Figure 4] This figure shows a schematic diagram of the connection method for the external connector of a semiconductor device according to this disclosure. [Modes for carrying out the invention]

[0039] In the embodiments for carrying out the invention described below, references are made to the accompanying drawings, which illustrate specific examples in which the invention may be put into practice. It should be understood that the features and principles described in relation to the various examples may be combined with each other unless otherwise stated. Similarly in the claims, the designations of specific elements such as “first element,” “second element,” and “third element” should not be understood as enumerative. Instead, such designations serve only to distinguish different “elements.” That is, for example, the presence of a “third element” does not require the presence of a “first element” and a “second element.” The electric wire described herein may be a single conductive element or may include at least two individual conductive elements connected in series and / or in parallel. The electric wire may include metallic and / or semiconductor materials and may be permanently conductive (in other words, non-switchable). The electric wire may have an electrical resistivity that is independent of the direction of the current flowing through it. The semiconductor bodies described herein may be made from (doped) semiconductor material and may be semiconductor chips or contained within semiconductor chips. The semiconductor body includes at least one semiconductor element having an electrode and having electrically connected pads. The pads may be electrically connected to the electrodes, and the pads may be electrodes and vice versa.

[0040] Referring to Figure 1a, a semiconductor device 1 is shown. The semiconductor device 1 comprises a mold body 2 formed of a encapsulating material. The semiconductor device 1 is a single in-line package, meaning that all external connectors protrude from the mold body on the common surface of the semiconductor device 1, which is the peripheral surface.

[0041] The semiconductor device 1 includes a first set 3 of external connectors. The first set 3 of external connectors is the drain connector of the semiconductor device 1. Furthermore, the semiconductor device 1 includes a second set 4 of external connectors. The second set 4 of external connectors is the source connector of the semiconductor device 1. Furthermore, the semiconductor device 1 includes a third set 5 of external connectors.

[0042] The external connector is embodied as a lead or pin, protruding from the mold body 2 and configured to connect a circuit from inside the mold body to a further external device (not shown).

[0043] The second set 4 of the external connector is laterally separated from the first set 3 of the external connector to maintain the required clearance distance between the different voltage regions of the external connector. Specifically, the clearance distance is greater than both the distance between the leads of the first set 3 of the external connector and the distance between the leads of the second set 4 of the external connector.

[0044] In order to increase the creepage distance along the surface of the mold body 2 between the first set 3 of external connectors and the second set 4 of external connectors, recesses / pockets 6 are positioned on the surrounding surface between the first set 3 of external connectors and the second set 4 of external connectors.

[0045] The second set 4 of the external connector has three leads, while the first set 3 of the external connector has only two leads. As a result, the drain and source connectors have an asymmetrical number of pins. Consequently, the ampere capacity of the second set 4 of the external connector is greater than that of the first set 3 of the external connector. Further as a consequence, the ampere capacity is not constant along the load current path.

[0046] Both the leads of the first set 3 of the external connector and the leads of the second set 4 of the external connector have the same pitch, i.e., the same spacing, between them.

[0047] The third set of external connectors 5 is positioned adjacent to the second set of external connectors 4. The third set of external connectors 5 is a control connector for connecting to control circuits inside the mold body 2. For example, the control connector 5 may connect to a gate driver circuit or to the gate electrode of a semiconductor die inside the mold body 2.

[0048] The cross-sectional area of ​​the leads of the first set 3 of the fixed external connector is equal to the cross-sectional area of ​​the leads of the second set 4 of the external connector.

[0049] Figure 1b shows the semiconductor device 1 of Figure 1a as viewed from the back. The pin layout is the same as that in Figure 1a. On the back, the exposed portion of the die carrier 7, i.e., the exposed die pad 7a, is visible. The exposed die pad 7a forms a flat surface with the outermost part of the mold body 2. Thus, the semiconductor device 1 is configured to be attached to a flat heat sink by aligning the exposed die pad 7a with the corresponding surface of the heat sink.

[0050] Figure 2a shows an internal view of semiconductor device 1 according to an embodiment of the present disclosure.

[0051] The semiconductor device 1 includes a encapsulant that forms a mold body 2. Inside the encapsulant, a lead frame 8 is provided, which includes a first portion that forms a die pad 7a. The first semiconductor die 9 is attached to the lead frame 8. The first semiconductor die 9 includes a first load electrode 9a (invisible) which is a drain electrode. The first semiconductor die 9 is attached to the die pad 7a by a die attach adhesive, for example, soft soldering. The first semiconductor die 9 further includes a second load electrode 10 which is a source electrode. Furthermore, the first semiconductor die 9 includes at least one control electrode 11 which may be a gate electrode or a temperature sensing electrode.

[0052] The semiconductor device 1 further comprises a second semiconductor die 12. The second semiconductor die 12 is a diode and also has first and second load electrodes 13, the first load electrode being coupled to the die pad 7a and the second load electrode 13 being located on the uppermost (invisible) surface of the second semiconductor die 12 opposite the first load electrode.

[0053] The first set 3 of external connectors, i.e., the external drain connector, forms an integrated portion with the die pad 7a. The first set 3 of external connectors is electrically connected to both the first load electrode 9a of the first semiconductor die 9 and the first load electrode of the second semiconductor die 12.

[0054] The first mold lock 14 is positioned on the connection portion of the first set 3 of the external connector. Furthermore, the semiconductor device 1 includes a lead post 15. The lead post 15 forms one integrated portion with the second set 4 of the external connector. The lead post 15 will be described in more detail below with reference to Figure 2b.

[0055] The second load electrode 10 of the first semiconductor die 9 is electrically connected to the first portion 16 of the lead post 15 by a first set 17 of internal electrical connectors, such as bonding wires.

[0056] The second load electrode 13 of the second semiconductor die 12 is electrically coupled to the second portion 18 of the lead post 15 by a second set 19 of internal electrical connectors, such as bonding wires.

[0057] At least one control electrode 11 is electrically connected to a third set 5 of external connectors by a third set 20 of internal electrical connectors.

[0058] The mold body 2 has a perimeter surface 21. All electrical connectors protrude from a first portion 22 of the perimeter first surface 21 that forms a single in-line package (SIP). A second portion 23 of the perimeter surface 21 is provided on the opposite side of the first portion 22 of the perimeter surface 21. The second portion 23 of the perimeter surface 21 has stepped recesses 24. The recesses 24 are provided at the outer corners of the mold body 2. The second portions of the lead frame that form the tie bars 25 protrude from the surface portions of each recess 24. The tie bars 25 are integral parts of the grounding metal of the lead frame 8.

[0059] A second mold lock 26 is provided on the outermost part of the second portion of the lead frame 8.

[0060] The first set 3 of the external connector has two leads. The leads of the first set of the external connector are spaced apart from each other by a first distance d. The first distance d is sometimes called the pitch of the leads.

[0061] The second set 4 of the external connector has three leads. Therefore, the second set 4 of the external connector has more leads than the first set 3 of the external connector. The leads of the second set 4 of the external connector are also spaced apart from each other by a first distance d. However, the first set 3 of the external connector is spaced apart from the second set 4 of the external connector by a larger distance D. The larger distance D is the clearance distance between the external source connection and the external drain connection of the semiconductor device 1. The clearance distance D is greater than the first distance d. To increase the creepage distance between the external source connector and the external drain connector, a pocket 6 is provided on the peripheral surface 21 of the mold body 2.

[0062] The leads of the first set 3 of the external connector and the leads of the second set 4 of the external connector have the same cross-sectional area, i.e., the same width and thickness, and are made of the same material. Therefore, each lead of the first set 3 of the external connector and the second set 4 of the external connector have the same wire size, i.e., the same conductive cross-sectional area.

[0063] Since the second set 4 of the external connectors has at least one more lead than the first set of external connectors, the overall effective wire size of the second set 4 of external connectors is greater than the overall effective wire size of the first set 3 of external connectors. The external source connector has a larger wire size than the external drain current connector.

[0064] Figure 2b shows a magnified view of the lead post 15 in Figure 2a.

[0065] The first portion 16 of the lead post 15 is a single integrated part with the second set 4 of the electrical connector. In the first portion 16 of the lead post 15, the first set 17 of the internal electrical connector, i.e., the first bonding wires, is electrically attached to the lead post 15. Each lead of the second set 4 of the external connector is integrally attached to the first portion 16 of the lead post by an interconnecting portion 27. The interconnecting portion 27 is trapezoidal in shape; that is, the cross-section of the lead extending from each lead widens toward the first portion 16 of the lead post 15. The interconnecting portion 27 includes a third mold lock 28. Due to the shape of the interconnecting portion 27, the electrically effective, i.e., conductive cross-section of the lead is kept constant throughout the interconnecting portion 27 despite the third mold lock 28.

[0066] The second portion 18 of the lead post 15 extends away from the second set 4 of the external connector. The second portion 18 of the lead post 15 includes a stepped portion that extends away from the second set 4 of the external connector. In the second portion 18 of the lead post 15, the second set 19 of the internal electrical connector is electrically coupled to the lead post 15.

[0067] Figures 3a and 3b show cross-sectional views of semiconductor device 1 according to this disclosure.

[0068] In Figure 3a, a first amount of thermal energy W1 is generated along the drain side of the load current path, i.e., along the current path between the external drain connector 3 and the first semiconductor die 9. The first semiconductor die 9 is coupled to the die carrier 7 at the first load electrode 9a of the first semiconductor die 9. As a result, the first semiconductor die 9, the die carrier 7, and the external drain connector 3 become hot. However, the thermal energy W1 is dissipated to the surrounding environment through the die pad 7a exposed on the back surface of the semiconductor device 1. That is, a first portion of the thermal energy W1 is dissipated. cool,dp However, it is ejected from the semiconductor device 1 by the die pad 7a, and the second portion W cool,DHowever, it is discharged from the semiconductor device 1 via the external drain connector 3. As a result, the first portion of the thermal energy W1 generated on the drain side of the load current path W cool,dp Since the heat is already dissipated by the exposed die pad 7a, the external drain connector 3 has a relatively low temperature. The external drain connector 3 forms an integral part of the lead frame 8 and therefore has a good thermal connection to the die pad 7a, so the external drain connector 3 is cooled via the die pad 7a.

[0069] In Figure 3b, a second amount of thermal energy W2 is generated along the source side of the load current path, i.e., along the current path between the external source connector 3 and the first semiconductor die 9. The load current is constant along the load current path, i.e., constant along the path from the external drain connector 3 through the semiconductor die 9 to the external source connector 4.

[0070] Since the semiconductor die and almost the entire source side of the load current path are sealed by the mold compound, thermal energy W2 cannot be effectively directed outside the semiconductor device 1. That is, although the amount of thermal energy generated is almost the same (W1=W2), less cooling occurs on the source side of the load current path than on the drain side of the load current path.

[0071] As a result, there is one portion of the source-side load current path from which thermal energy can be discharged from the semiconductor device 1, i.e., dissipated into the surrounding environment. That portion is the second set 4 of external connectors, i.e., the external source connector. Thermal energy W cool,SThe transfer is made possible by the source lead 3. The lead post 15 to which the leads of the second set 4 of the external connector are connected is electrically and thermally connected to the first set 17 of the internal electrical connector, so each part 16 of the lead post 15 receives even more thermal energy. First, each part 16 of the lead post 15 receives thermal energy generated by its own ohm resistance. Next, each part 16 of the lead post 15 receives an additional amount of thermal energy due to thermal convection from the first set 17 of the internal electrical connector. As a result, the second set 4 of the external connector heats up due to ohm resistance and convection, at least at the proximal end of the second set 4, which is embedded inside the molded compound and well isolated from the surrounding environment. This results in an increased temperature at the source connector compared to the drain connector.

[0072] Note that in Figure 3b, the first set 3 of external connectors and the second set 4 of external connectors are shown stacked vertically. However, this is only for better visibility. In a single in-line package (SIP), all connectors are arranged in a single row adjacent to each other.

[0073] Figure 4 shows a schematic diagram of the second level connection scheme for semiconductor device 1. Semiconductor device 1, which may be THD or SMD, is mounted on a printed circuit board (PCB) 29. A first set of external connectors 3 is connected to a first portion 30 of the PCB 29, which may be the drain portion. A second set of external connectors 4 has three leads, the first lead 31 is connected to a second portion 32 of the PCB, and the second lead 33 is connected to a third portion 34 of the PCB.

[0074] The second portion 32 of the PCB is an insulating portion that acts as a heat sink. The second portion 32 of the PCB may be an insulated copper-plated area on the PCB 29. To connect to the second portion 32 of the PCB, the first lead 31 may be shaped differently from the second lead 33. For example, the first lead 31 may have a stepped, downset, J-shape, gull-wing shape, or be bent into any preferred shape. [Explanation of symbols]

[0075] 1. Semiconductor devices 2. Mold body 3. First set of external connectors 4. Second set of external connectors 5. Third set of external connectors 6 pockets / recesses 7 Die Carrier 7a die pad 8 Lead Frame 9. First semiconductor die 9a First load electrode 10. Second load electrode / source electrode 11 Control electrodes 12. Second semiconductor die 13. Second load electrode of the second semiconductor die 14. First Moldlock 15 Leadpost 16. Part 1 of the lead post 17. First internal electrical connector 18. Part 2 of the lead post 19. Second internal electrical connector 20 Third internal electrical connector 21 Surrounding surface of the mold body 22 First portion of the surrounding surface 23 Second part of the surrounding surface 24-step recessed 25 Tie Bar 26. Second Moldlock 27 Interconnection section 28. The third moldlock 29 PCB Part 1 of 30 PCBs 31. First lead / thermal pin of the second set of external connectors Part 2 of 32 PCBs 33. Second lead of the second set of external connectors 34 Part 3 of the PCB

Claims

1. Diacarrier (7) and, A first semiconductor die (9) comprising at least a first load electrode (9a) and a second load electrode (10), wherein the first semiconductor die (9) is mounted on the die carrier (7), and the first load electrode (9a) is electrically connected to the die carrier (7), A first set (3) of external connectors electrically and thermally connected to the die carrier (7), A second set (4) of external connectors is separated from the die carrier (7) and electrically connected to the second load electrode (10). Equipped with, A semiconductor device (1) in which the overall wire size of the second set (4) of external connectors is larger than the overall wire size of the first set (3) of external connectors.

2. The semiconductor device (1) according to claim 1, comprising a sealing material that seals at least a portion of the first semiconductor die (9) and at least the proximal end of each of the external connectors such that the distal ends of both the external connectors of the first set (3) of external connectors and the external connectors of the second set (4) of external connectors protrude from the sealing material.

3. The semiconductor device (1) according to claim 1, wherein the die carrier (7) is a lead frame (8), and the lead frame (8) includes a first portion that forms a die pad (7a).

4. The semiconductor device (1) according to claim 1, wherein the second set (4) of external connectors comprises at least one additional connector relative to the first set (3) of external connectors.

5. The semiconductor device (1) according to claim 4, wherein the at least one additional connector is a thermal connector for facilitating heat transfer from the inside of the encapsulant to the surrounding environment.

6. The semiconductor device (1) according to claim 1, comprising a lead post (15) attached to the second set (4) of the external connector, wherein the lead post (15) forms an integral portion with the second set (4) of the external connector.

7. The semiconductor device (1) according to claim 3, wherein the first set (3) of external connectors is an integral part with the first portion of the lead frame (8).

8. The semiconductor device (1) according to claim 1, wherein the semiconductor device (1) is a single in-line package (SIP), and the first set of external connectors (3) is laterally separated from the second set of external connectors (4) by a distance greater than both the distance between the external connectors of the first set of external connectors (3) and the distance between the external connectors of the second set of external connectors (4).

9. The semiconductor device (1) according to claim 2, wherein the outermost surface of the die carrier (7) is exposed from the sealing material.

10. The semiconductor device (1) according to claim 9, wherein the outermost surface of the die carrier (7) is configured to be attached to a heat sink.

11. The semiconductor device (1) according to claim 1, wherein the first set (3) of the external connector has a downset toward the die carrier (7).

12. The semiconductor device (1) according to claim 1, wherein the cross-sectional area of ​​each connector in the first set (3) of external connectors is equal to the cross-sectional area of ​​each connector in the second set (4) of external connectors.

13. The semiconductor device (1) according to claim 4, wherein the at least one additional connector is configured to be attached to a heatsink, for example, to a copper-plated insulating area of ​​a printed circuit board (PCB) (29).

14. The semiconductor device (1) according to claim 2, wherein the second set (4) of external connectors is separated from the first set (3) of external connectors, and the pocket (6) is positioned on the peripheral surface (21) of the sealing material between the first set and the second set of external connectors.

15. The semiconductor device (1) according to claim 1, wherein the die carrier (7) comprises a second portion that forms a tie bar (25), and the second portion is located on the opposite side with respect to the external connector.

16. The semiconductor device (1) according to claim 6, comprising a second semiconductor die (12) attached to the die carrier (7), wherein the second semiconductor die (12) is electrically and thermally connected to the lead post (15) by an internal electrical connector (19), the internal electrical connector (19) being formed, for example, by wire bonding, wedge bonding, nail head bonding, or clipping.

17. The semiconductor device (1) according to claim 16, wherein the lead post (15) comprises a first portion (16) to which the external connector of the second set (4) of the external connector is attached, and a second portion (18) extending between the first set (3) of the external connector and the second set (4) of the external connector to which the internal electrical connector (19) from the second semiconductor die (12) is attached.

18. The semiconductor device (1) according to claim 6, wherein the external connector of the second set (4) of external connectors is attached to the lead post (15) by a trapezoidal interconnect portion (27) having a mold lock (28).

19. The semiconductor device (1) according to claim 17, wherein the second portion (18) of the lead post (15) is staggered to maintain the largest possible wire size toward the interconnect portion (27).

20. The semiconductor device (1) according to claim 1, wherein the first semiconductor die (9) is one of a MOSFET, IGBT, JFET, SFET, bipolar transistor, or GaN HEMT, and the second semiconductor die (12) is a diode.

21. The semiconductor device (1) according to claim 1, comprising an overcurrent protection circuit (OCP-IC) and / or a gate driver circuit.

22. The semiconductor device (1) according to claim 1, wherein the first semiconductor die (9) comprises a control electrode (11) and a third set (5) of external connectors, the third set (5) of external connectors comprising at least one control connector (20) connected to the control electrode (11) of the first semiconductor die (9), and the third set (5) of external connectors being laterally separated from the first set (3) of external connectors by the second set (4) of external connectors.

23. A single in-line package (SIP) comprising a set of external drain connectors (3), a set of external source connectors (4), and a set of external control connectors (5), arranged along the respective periphery package surface such that the external connectors form an asymmetrical arrangement, wherein the overall wire size of the set of external source connectors is greater than the overall wire size of the set of external drain connectors.

24. A system comprising a first semiconductor device (1) and a second semiconductor device (1) according to any one of claims 1 to 22, wherein the first semiconductor device (1) and the second semiconductor device (1) are electrically connected and arranged in parallel such that the outermost exposed surfaces of the die carriers of the semiconductor devices are arranged in the same plane.

25. The system according to claim 24, further comprising a common heat sink to which the exposed outermost surfaces of the die carriers of the first semiconductor device and the second semiconductor device are thermally bonded.

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