Semiconductor equipment

Abstract

To provide a semiconductor device that can improve reliability. [Solution] The semiconductor device comprises a wiring board, a control circuit board having an insulating layer, a semiconductor chip mounted on the wiring board and spaced apart from the control circuit board when viewed in the thickness direction of the wiring board, a main terminal spaced apart from the wiring board when viewed in the thickness direction of the wiring board, and a conductive member having conductivity and including a first end and a second end, the first end being joined to the main terminal and the second end being joined to the semiconductor chip. The semiconductor chip and the main terminal are arranged so as to sandwich the control circuit board. When viewed in the thickness direction of the wiring board, the control circuit board and the conductive member have overlapping regions. The conductive member is joined to the control circuit board.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Techniques related to semiconductor modules including semiconductor elements have been disclosed (see, for example, Patent Document 1). The semiconductor module disclosed in Patent Document 1 includes a conductive substrate, a semiconductor element, a conductive member including a first conductive member and a second conductive member, a first input terminal, a second input terminal, and a third input terminal, a control terminal, and a sealing resin.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the semiconductor module disclosed in Patent Document 1, the second conductive member is connected to the second input terminal and the semiconductor element. When stress is applied to the second input terminal in such a situation, since a cantilever structure is formed, stress is also applied to the connection region with the semiconductor chip. Then, due to the stress applied to the second input terminal, the semiconductor element joined to the second conductive member may be damaged or the joining state with the semiconductor element may become unstable. In particular, before sealing with the sealing resin, the stress applied to the second input terminal is directly applied to the joining region with the semiconductor element, and damage and poor joining of the semiconductor element are likely to occur. As a result, it becomes difficult to ensure stable operation, and the reliability of the semiconductor device may be impaired.

[0005] Therefore, one of the objectives is to provide a semiconductor device that can improve reliability.

Means for Solving the Problems

[0006] A semiconductor device according to this disclosure comprises a wiring board, a control circuit board having an insulating layer, a semiconductor chip mounted on the wiring board and spaced apart from the control circuit board when viewed in the thickness direction of the wiring board, a main terminal spaced apart from the wiring board when viewed in the thickness direction of the wiring board, and a conductive member having conductivity and including a first end and a second end, the first end being joined to the main terminal and the second end being joined to the semiconductor chip. The semiconductor chip and the main terminal are arranged so as to sandwich the control circuit board. When viewed in the thickness direction of the wiring board, the control circuit board and the conductive member have overlapping regions. The conductive member is joined to the control circuit board. [Effects of the Invention]

[0007] Such semiconductor devices can improve reliability. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic plan view of the semiconductor device in Embodiment 1. [Figure 2] Figure 2 is a schematic plan view of the semiconductor device in Embodiment 1. [Figure 3] Figure 3 is a schematic perspective view of the semiconductor device shown in Figure 2. [Figure 4] Figure 4 is a schematic side view of the semiconductor device shown in Figure 2. [Figure 5] Figure 5 is a schematic plan view of the semiconductor device shown in Figure 2, with the conductive members described later omitted from the illustration. [Figure 6] Figure 6 is a schematic plan view of the semiconductor device shown in Figure 5, with the connecting members described later omitted from the illustration. [Figure 7] Figure 7 is a schematic side view showing an enlarged view of the area where the joint is located. [Figure 8] Figure 8 is a simplified circuit diagram showing a current path that includes a configuration functioning as a capacitor in a semiconductor device. [Figure 9]Figure 9 is a schematic side view showing an enlarged portion of the semiconductor device in Embodiment 2. [Figure 10] Figure 10 is a schematic plan view of the semiconductor device in Embodiment 3. [Figure 11] Figure 11 is a schematic plan view of the semiconductor device in Embodiment 3. [Figure 12] Figure 12 is a schematic plan view of the semiconductor device shown in Figure 11, with the conductive members omitted from the illustration. [Figure 13] Figure 13 is a schematic plan view of the semiconductor device shown in Figure 12, with the connecting members omitted from the illustration. [Figure 14] Figure 14 is a schematic cross-sectional view showing a part of the semiconductor device shown in Figure 11. [Figure 15] Figure 15 is a schematic cross-sectional view showing a part of the semiconductor device shown in Figure 11. [Figure 16] Figure 16 is a schematic cross-sectional view showing a part of the semiconductor device shown in Figure 11. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] (1) The semiconductor device according to the present disclosure comprises a wiring board, a control circuit board having an insulating layer, a semiconductor chip mounted on the wiring board and spaced apart from the control circuit board when viewed in the thickness direction of the wiring board, a main terminal spaced apart from the wiring board when viewed in the thickness direction of the wiring board, and a conductive member having conductivity and including a first end and a second end, the first end being joined to the main terminal and the second end being joined to the semiconductor chip. The semiconductor chip and the main terminal are arranged so as to sandwich the control circuit board. When viewed in the thickness direction of the wiring board, the control circuit board and the conductive member have overlapping regions. The conductive member is joined to the control circuit board.

[0010] According to the above semiconductor device, the semiconductor chip and the main terminal are arranged so as to sandwich the control circuit board. And, the first end portion of the conductive member is joined to the main terminal, and the second end portion of the conductive member is joined to the semiconductor chip. Here, since the conductive member is joined to the control circuit board, the conductive member is supported by the control circuit board, and even when stress is applied to the main terminal, the stress is not directly applied to the semiconductor chip joined to the second end portion. Then, it is possible to reduce the risk that the semiconductor chip joined at the second end portion is damaged or the joining state between the semiconductor chip and the conductive member becomes unstable due to the stress applied to the main terminal. Also, by adopting a configuration in which the conductive member is joined to the control circuit board having an insulating layer, the joining region between the conductive member and the control circuit board can function as a capacitor. Then, since the current path can be substantially shortened, the parasitic inductance is reduced, and as a result, the surge voltage can be reduced. Therefore, according to the above semiconductor device, it becomes easier to ensure stable operation and reliability can be improved.

[0011] (2) In the above (1), the semiconductor device may further include a capacitor disposed between the conductive member and the control circuit board. A semiconductor device having such a configuration can further reduce the parasitic capacitance by the capacitor and reduce the surge voltage. Therefore, more stable operation can be ensured.

[0012] (3) In the above (1) or (2), the conductive member may be joined to the control circuit board by solder. By doing so, while ensuring conductivity, the conductive member can be more reliably joined to the control circuit board. Therefore, it is possible to realize a reliable joining between the conductive member and the control circuit board while surely ensuring the function as a capacitor in the joining region and reducing the surge voltage.

[0013] (4) In any of the above (1) to (3), the conductive member may be plate-shaped. Such a configuration is preferably used because a large current can flow through the conductive member.

[0014] (5) In any of (1) to (4) above, the semiconductor device may further include a control terminal that extends in the thickness direction of the wiring board and is electrically connected to the control circuit board. By doing so, the operation of the semiconductor chip can be controlled using the control terminal. In this case, since it is in a shape that extends in the thickness direction of the wiring board, the electrical connection between the control terminal and the outside can be made easier.

[0015] (6) In (5) above, the semiconductor chip may be a transistor chip. The control terminal may include a gate terminal that is electrically connected to the gate electrode of the semiconductor chip and an auxiliary source terminal that is electrically connected to the source electrode of the semiconductor chip. By doing so, when the semiconductor chip is applied as a transistor chip, the precise control of the operation of the semiconductor chip can be more reliably performed. Therefore, the reliability can be further improved.

[0016] (7) In any of (1) to (6) above, a plurality of main terminals may be provided. The conductive member may be joined to each main terminal respectively. By doing so, a large current can flow through the plurality of main terminals, so that the semiconductor device can be used more efficiently.

[0017] (8) In any of (1) to (7) above, a plurality of semiconductor chips may be provided. The plurality of semiconductor chips may be arranged at intervals. By doing so, the operation of the semiconductor device can be controlled more efficiently by the plurality of semiconductor chips. Therefore, the reliability can be further improved.

[0018] (9) In any of (1) to (8) above, the capacitor may include a ceramic capacitor. Such a capacitor is relatively inexpensive and can be preferably used because various types can be selected and applied according to the use and purpose.

[0019] (10) In any of (1) to (9) above, the semiconductor device may further include a sealing resin that covers the wiring board, control circuit board, semiconductor chip, and conductive member, and exposes a part of the main terminal. By doing so, the wiring board, control circuit board, semiconductor chip, conductive member, and a part of the main terminal can be reliably sealed.

[0020] [Details of the embodiments of this disclosure] Next, embodiments of the semiconductor device of this disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their descriptions will not be repeated.

[0021] (Embodiment 1) A semiconductor device in Embodiment 1 of this disclosure will now be described. Figures 1 and 2 are schematic plan views of the semiconductor device in Embodiment 1. In Figure 2, the sealing resin, which will be described later, is shown with a dashed line. Figure 3 is a schematic perspective view of the semiconductor device shown in Figure 2. Figure 4 is a schematic side view of the semiconductor device shown in Figure 2. Figure 4 is a view from the direction indicated by arrow IV in Figure 2. Figure 5 is a schematic plan view of the semiconductor device shown in Figure 2, with the conductive member, which will be described later, omitted from the illustration. Figure 6 is a schematic plan view of the semiconductor device shown in Figure 5, with the connecting member, which will be described later, omitted from the illustration. In the drawings shown in Figure 1 and subsequent figures, the direction indicated by arrow Z indicates the thickness direction of the semiconductor chip (height direction of the semiconductor device), the direction indicated by arrow X indicates the vertical direction of the semiconductor device, and the direction indicated by arrow Y indicates the horizontal direction of the semiconductor device. The directions indicated by arrow X, arrow Y, and arrow Z are perpendicular to each other.

[0022] Referring to Figures 1 to 6, the semiconductor device 10a in Embodiment 1 includes a wiring board 11a, a control circuit board 12a, a control circuit board 12b, semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f, main terminals 14a, 14b, 14c, 14d, and 14e, control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i, connecting members 16a, 16b, and 16c, a conductive member 17a, and a sealing resin 18a. In this embodiment, the semiconductor device 10a includes six semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f, five main terminals 14a, 14b, 14c, 14d, and 14e, and nine control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i. In this embodiment, when driving the semiconductor device 10a, for example, main terminals 14a and 14b can be set as N terminals, main terminals 14c and 14d as O terminals, and main terminal 14e as a P terminal.

[0023] The wiring board 11a includes an insulating substrate 21a and a pair of first metal plates 22a and second metal plates 22b arranged on both sides of the insulating substrate 21a in the thickness direction. That is, the wiring board 11a has a laminated structure in which the insulating substrate 21a is sandwiched between a pair of first metal plates 22a and second metal plates 22b. One of the first metal plates 22a includes a first divided portion 23a and a second divided portion 23b. The first divided portion 23a and the second divided portion 23b are arranged side by side with a gap between them in the Y direction. That is, the first metal plate 22a is divided into a first divided portion 23a and a second divided portion 23b. The second metal plate 22b is in the shape of a single plate.

[0024] The control circuit board 12a includes an insulating layer 25a and a pair of third metal plates 26a and fourth metal plates 27a arranged on both sides of the insulating layer 25a in the thickness direction. That is, the control circuit board 12a has a laminated structure in which the insulating layer 25a is sandwiched between a pair of third metal plates 26a and fourth metal plates 27a. The third metal plate 26a includes a first circuit board 31a, a second circuit board 32a, a third circuit board 33a, a fourth circuit board 34a, and a fifth circuit board 35a. The first circuit board 31a, the second circuit board 32a, the third circuit board 33a, the fourth circuit board 34a, and the fifth circuit board 35a are each provided spaced apart on the insulating layer 25a. The first circuit board 31a, the second circuit board 32a, the third circuit board 33a, the fourth circuit board 34a, and the fifth circuit board 35a are used as components that constitute the control circuit when controlling semiconductor chips 13a, 13b, and 13c, respectively. The fourth metal plate 27a is in the form of a single plate.

[0025] The third metal plate 26a included in the control circuit board 12a further includes a first support plate 36a and a second support plate 36b. The first support plate 36a and the second support plate 36b are also made of metal, similar to the first circuit board 31a. That is, both the first support plate 36a and the second support plate 36b are conductive. The first support plate 36a is positioned adjacent to the first circuit board 31a with a gap between them in the X direction. The second support plate 36b is positioned adjacent to the fifth circuit board 35a with a gap between them in the X direction. That is, the first support plate 36a and the second support plate 36b are provided on both ends of the control circuit board 12a in the X direction.

[0026] The control circuit board 12b includes an insulating layer 25b and a pair of third metal plates 26b and fourth metal plates 27b arranged on both sides of the insulating layer 25b in the thickness direction. That is, the control circuit board 12b has a laminated structure in which the insulating layer 25b is sandwiched between a pair of third metal plates 26b and fourth metal plates 27b. The third metal plate 26b includes a first circuit board 31b, a second circuit board 32b, a third circuit board 33b, a fourth circuit board 34b, and a fifth circuit board 35b. The first circuit board 31b, the second circuit board 32b, the third circuit board 33b, the fourth circuit board 34b, and the fifth circuit board 35b are each provided spaced apart on the insulating layer 25b. The first circuit board 31b, the second circuit board 32b, the third circuit board 33b, the fourth circuit board 34b, and the fifth circuit board 35b are used as components that constitute the control circuit when controlling semiconductor chips 13d, 13e, and 13f, respectively. The fourth metal plate 27b is a single plate. Note that the control circuit board 12b does not have the first support plate 36a and the second support plate 36b as the control circuit board 12a.

[0027] As the semiconductor chip 13a, for example, a transistor is used, specifically a vertical transistor such as a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or an insulated gate bipolar transistor (IGBT (Insulated Gate Bipolar Transistor)). In this embodiment, the semiconductor chip 13a is a MOSFET. Alternatively, a diode, specifically an SBD (Schottky Barrier Diode), may be used as the semiconductor chip 13a. In this embodiment, the semiconductor chip 13a is rectangular in shape when viewed in the thickness direction (Z direction). The configurations of the other semiconductor chips 13b, 13c, 13d, 13e, and 13f are the same as the configuration of semiconductor chip 13a, so their descriptions are omitted.

[0028] The semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f are each positioned at a distance from the control circuit boards 12a and 12b when viewed in the Z direction. The semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f are each mounted on the wiring board 11a.

[0029] Specifically, semiconductor chips 13a, 13b, and 13c are each mounted on the first divided section 23a with spacing in the X direction. Each of the semiconductor chips 13a, 13b, and 13c is bonded to the first divided section 23a by a bonding material. This electrically connects the drain electrodes of each semiconductor chip 13a, 13b, and 13c to the first divided section 23a of the first metal plate 22a. A conductive bonding material such as solder is used as the bonding material. The same applies to the bonding materials described below. The source electrodes of each semiconductor chip 13a, 13b, and 13c are each bonded to the second circuit board 32a by conductive wires 37a, 37b, and 37c. This electrically connects the source electrodes of each semiconductor chip 13a, 13b, and 13c to the second circuit board 32a. The gate electrodes of each semiconductor chip 13a, 13b, and 13c are connected to the third circuit board 33a by wires 38a, 38b, and 38c, respectively. This electrically connects the gate electrodes of each semiconductor chip 13a, 13b, and 13c to the third circuit board 33a.

[0030] Furthermore, semiconductor chips 13d, 13e, and 13f are each mounted on the second divided section 23b with spacing in the X direction. Each semiconductor chip 13d, 13e, and 13f is bonded to the second divided section 23b by a bonding material. This electrically connects the drain electrodes of each semiconductor chip 13d, 13e, and 13f to the second divided section 23b of the first metal plate 22a. The source electrodes of each semiconductor chip 13d, 13e, and 13f are each bonded to the second circuit board 32b by conductive wires 37d, 37e, and 37f. This electrically connects the source electrodes of each semiconductor chip 13d, 13e, and 13f to the second circuit board 32b. The gate electrodes of each semiconductor chip 13d, 13e, and 13f are connected to the third circuit board 33b by wires 38d, 38e, and 38f, respectively. This electrically connects the gate electrodes of each semiconductor chip 13d, 13e, and 13f to the third circuit board 33b.

[0031] Control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i are each metal rod-shaped members. Each of the control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i has a shape that extends in the Z direction, which is the thickness direction of the wiring board 11a. Each of the control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i is used for inputting input signals when controlling the operation of semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f, respectively. Control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i are each provided to protrude from the sealing resin 18a in the Z direction. Control terminal 15a is connected to the first circuit board 31a. Control terminal 15b is connected to the second circuit board 32a. Control terminal 15c is connected to the third circuit board 33a. Control terminal 15d is connected to the fourth circuit board 34a. Control terminal 15e is connected to the fifth circuit board 35a. Control terminal 15f is connected to the second circuit board 32b. Control terminal 15g is connected to the third circuit board 33b. Control terminal 15h is connected to the fourth circuit board 34b. Control terminal 15i is connected to the fifth circuit board 35b. Control terminals 15c and 15g each function as gate terminals. Control terminals 15b and 15f function as auxiliary source terminals, respectively.

[0032] Main terminals 14a, 14b, 14c, 14d, and 14e are each strip-shaped metal plates. Main terminals 14c and 14d are electrically connected to the second metal plate 22b included in the wiring board 11a. In this embodiment, main terminals 14c and 14d are formed to be integrated with the second metal plate 22b. Main terminal 14e is electrically connected to the first metal plate 22a included in the wiring board 11a. In this embodiment, main terminal 14e is formed to be integrated with the first metal plate 22a. Both main terminals 14a and 14b are not directly joined to the first metal plate 22a and the second metal plate 22b.

[0033] Main terminals 14a and 14b are each positioned at a distance from the wiring board 11a when viewed in the Z direction, which is the thickness direction of the wiring board 11a. Furthermore, semiconductor chips 13a, 13b, and 13c and main terminal 14a are positioned so as to sandwich the control circuit board 12a in the Y direction. Similarly, semiconductor chips 13a, 13b, and 13c and main terminal 14b are positioned so as to sandwich the control circuit board 12a in the Y direction.

[0034] The connecting members 16a, 16b, and 16c are each strip-shaped metal plates. Each of the connecting members 16a, 16b, and 16c is formed by bending a strip-shaped metal plate. The connecting member 16a is joined to the source pad and the second metal plate 22b of the semiconductor chip 13a. The connecting member 16a electrically connects the source pad and the second metal plate 22b of the semiconductor chip 13a. The connecting member 16b is joined to the source pad and the second metal plate 22b of the semiconductor chip 13b. The connecting member 16b electrically connects the source pad and the second metal plate 22b of the semiconductor chip 13b. The connecting member 16c is joined to the source pad and the second metal plate 22b of the semiconductor chip 13c. The connecting member 16c electrically connects the source pad and the second metal plate 22b of the semiconductor chip 13c.

[0035] The encapsulating resin 18a is arranged to cover the electronic components constituting the semiconductor device 10a. Specifically, the encapsulating resin 18a covers the wiring board 11a, control circuit board 12a, control circuit board 12b, semiconductor chips 13a, 13b, 13c, 13d, 13e, 13f, connecting members 16a, 16b, 16c, and conductive member 17a, while exposing a portion of each of the main terminals 14a, 14b, 14c, 14d, 14e, control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i. As the encapsulating resin 18a, for example, a thermosetting resin, specifically an epoxy resin, is used. In this embodiment, the sealing resin 18a is formed by transfer molding so as to cover the wiring board 11a, the control circuit board, semiconductor chips, control circuit boards 12a and 12b, semiconductor chips 13a, 13b, 13c, 13d, 13e, 13f, connecting members 16a, 16b, 16c and conductive member 17a, while exposing a portion of each of the main terminals 14a, 14b, 14c, 14d, 14e, control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h and 15i.

[0036] The conductive member 17a is plate-shaped. Specifically, the conductive member 17a is a metal plate-shaped member that has conductivity. The conductive member 17a is formed by partially bending a metal plate-shaped member that has been cut into a predetermined shape. The conductive member 17a includes a first region 41a, a second region 42a, a third region 43a, a fourth region 44a, a fifth region 45a, and a sixth region 46a. The first region 41a, the second region 42a, the third region 43a, and the fourth region 44a are each provided to extend in the Y direction with a gap in the X direction. The first region 41a and the second region 42a are each positioned at both ends in the X direction. The third region 43a and the fourth region 44a are positioned between the first region 41a and the second region 42a in the X direction. The fifth region 45a and the sixth region 46a are each provided to extend in the X direction. The fifth region 45a is connected to the first region 41a, the second region 42a, the third region 43a, and the fourth region 44a at their ends in the Y direction. The sixth region 46a is connected to the ends in the Y direction of the third region 43a and the fourth region 44a, and to the intermediate parts in the Y direction of the first region 41a and the second region 42a. In the Z direction, the control circuit board 12a and the conductive member 17a have overlapping regions. Specifically, the region of the control circuit board 12a including its end in the X direction overlaps with the first region 41a and the second region 42a of the conductive member 17a.

[0037] The conductive member 17a includes a first end 51a, a first end 51b, and a second end 52a. The first end 51a is the end in the direction indicated by arrow Y in the first region 41a. The first end 51b is the end in the direction indicated by arrow Y in the second region 42a. The second end 52a is the end in the opposite direction to that indicated by arrow Y. The second end 52a corresponds to the fifth region 45a of the conductive member 17a.

[0038] The first end 51a is joined to the main terminal 14a. The conductive member 17a, including the first end 51a, and the main terminal 14a are electrically connected. The first end 51b is joined to the main terminal 14b. The conductive member 17a, including the first end 51b, and the main terminal 14b are electrically connected. The second end 52a is joined to each of the semiconductor chips 13d, 13e, and 13f. Specifically, the second end 52a is joined to the source pads of each of the semiconductor chips 13d, 13e, and 13f. The conductive member 17a, including the second end 52a, and the source pads of each of the semiconductor chips 13d, 13e, and 13f are electrically connected.

[0039] Here, the conductive member 17a is joined to the control circuit board 12a. The conductive member 17a is joined to the control circuit board 12a by solder. Specifically, at the joint 53a located midway in the Y direction in the first region 41a of the conductive member 17a, it is joined to the first support plate 36a of the control circuit board 12a. Furthermore, at the joint 53b located midway in the Y direction in the second region 42a of the conductive member 17a, it is joined to the second support plate 36b of the control circuit board 12a.

[0040] Figure 7 is a schematic side view showing an enlarged view of the region where the joint 53a is located. Figure 7 is an enlarged view of the region indicated as VII in Figure 4. Referring to Figure 7 as well, at the joint 53a, the conductive member 17a and the control circuit board 12a are joined by solder, which is the joining material 28a. The joining material 28a is shown with a thicker thickness. An insulating layer 25a is placed between the conductive joining material 28a in the Z direction and the fourth metal plate 27a included in the first support plate 36a and the control circuit board 12a. The configuration in which the insulating layer 25a is sandwiched between conductive members in the Z direction (thickness direction), that is, the configuration in which the insulating layer 25a is sandwiched between the conductive third metal plate 26a and the conductive fourth metal plate 27a, functions as a capacitor.

[0041] In the semiconductor device 10a described above, semiconductor chips 13a, 13b, and 13c and main terminals 14a and 14b are arranged so as to sandwich the control circuit board 12a. The first ends 51a and 51b of the conductive member 17a are joined to the main terminals 14a and 14b, and the second end 52a of the conductive member 17a is joined to the semiconductor chips 13a, 13b, and 13c. Here, since the conductive member 17a is joined to the control circuit board 12a, the conductive member 17a is supported by the control circuit board 12a, and even if stress is applied to the main terminals 14a and 14b in the direction indicated by arrow P in Figure 4, for example, stress will not be directly applied to the semiconductor chips 13a, 13b, and 13c which are joined to the second end 52a. This reduces the risk of damage to the semiconductor chips 13a, 13b, and 13c joined at the second end 52a due to stress applied to the main terminals 14a and 14b, or of instability in the bonding state between the semiconductor chips 13a, 13b, and 13c and the conductive member 17a. Furthermore, by adopting a configuration in which the conductive member 17a is bonded to a control circuit board 12a having an insulating layer 25a, the bonding region between the conductive member 17a and the control circuit board 12a can function as a capacitor. This substantially shortens the current path, reducing parasitic inductance and consequently lowering surge voltage. Therefore, the semiconductor device 10a makes it easier to ensure stable operation and improves reliability.

[0042] Here, we will explain how to reduce surge voltage. Figure 8 is a simplified circuit diagram showing a current path in the semiconductor device 10a that includes a configuration functioning as a capacitor. Referring to Figure 8, the circuit 55a includes power supplies 56a and 56b, body diodes 58a and 58b of the semiconductor chip 13a, and capacitors 59a and 59b. For ease of understanding, the inductive load 57c and the parasitic inductances 57a and 57b caused by the long wiring length are schematically illustrated in Figure 8. Capacitors 59a and 59b both correspond to the components that function as capacitors as described above. In a configuration that does not include the above-mentioned capacitor configuration, the current path loop becomes long, as shown by arrow V1 in Figure 8. With such a long current path loop, the parasitic inductance increases. This leads to a larger surge voltage and makes ringing more likely to occur. In contrast, the semiconductor device 10a in Embodiment 1 includes a configuration that functions as a capacitor, so the current path loop is shortened as shown by arrow V2 in Figure 8. This shortens the current path loop and reduces parasitic inductance. As a result, surge voltage is reduced, making ringing less likely to occur.

[0043] In this embodiment, the conductive member 17a is joined to the control circuit board 12a by solder. Therefore, the conductive member 17a can be more reliably joined to the control circuit board 12a while ensuring conductivity. Thus, a reliable connection between the conductive member 17a and the control circuit board 12a can be achieved while reliably ensuring the function of the capacitor in the joining region and reducing surge voltage.

[0044] In this embodiment, the conductive member 17a is plate-shaped. This configuration is preferable because it allows a large current to flow through the conductive member 17a.

[0045] In this embodiment, the semiconductor device 10a extends in the thickness direction of the wiring board 11a and includes control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i that are electrically connected to the control circuit board 12a and the control circuit board 12b. Therefore, the operation of the semiconductor chip can be controlled using the control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i. In this case, because the shape extends in the thickness direction of the wiring board 11a, electrical connections between the control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i and the outside can be made easier.

[0046] In this embodiment, semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f are each transistor chips. Control terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i include gate terminals electrically connected to the respective gate electrodes of semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f, and auxiliary source terminals electrically connected to the respective source electrodes of semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f. Therefore, when semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f are applied as transistor chips, the operation of semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f can be controlled more precisely and reliably. Consequently, reliability can be improved.

[0047] In this embodiment, multiple main terminals 14a and 14b are provided. Conductive member 17a is joined to the main terminals 14a and 14b, respectively. Therefore, a large current can be carried by the multiple main terminals 14a and 14b, allowing the semiconductor device 10a to be utilized more efficiently.

[0048] In this embodiment, multiple semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f are provided. The multiple semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f are arranged at intervals from each other. Therefore, the operation of the semiconductor device 10a can be controlled more efficiently by the multiple semiconductor chips 13a, 13b, 13c, 13d, 13e, and 13f. Consequently, reliability can be improved.

[0049] In this embodiment, the semiconductor device 10a includes a sealing resin 18a formed by transfer molding, which covers the wiring board 11a, control circuit board 12a, control circuit board 12b, semiconductor chips 13a, 13b, 13c, 13d, 13e, 13f, and conductive member 17a, while exposing a portion of the main terminals 14a, 14b, 14c, 14d, and 14e. Thus, the wiring board 11a, control circuit board 12a, control circuit board 12b, semiconductor chips 13a, 13b, 13c, 13d, 13e, 13f, conductive member 17a, and a portion of the main terminals 14a, 14b, 14c, 14d, and 14e can be reliably sealed.

[0050] (Embodiment 2) Another embodiment, Embodiment 2, will now be described. Figure 9 is a schematic side view showing an enlarged portion of the semiconductor device in Embodiment 2. The semiconductor device in Embodiment 2 has basically the same configuration as in Embodiment 1 and produces the same effects. However, the semiconductor device in Embodiment 2 differs from that in Embodiment 1 in its configuration, including the capacitor.

[0051] The semiconductor device 10b includes a capacitor 29a disposed between the conductive member 17a and the control circuit board 12a. For example, a ceramic capacitor is used as the capacitor 29a. That is, in this embodiment, the conductive member 17a and the control circuit board 12a are joined via the capacitor 29a. Solder is used for joining the capacitor 29a to the conductive member 17a and for joining the capacitor 29a to the control circuit board 12a. Specifically, solder as a bonding material 28a is placed between the capacitor 29a and the conductive member 17a, and solder as a bonding material 28b is placed between the capacitor 29a and the control circuit board 12a.

[0052] In this configuration, the semiconductor device 10b can further reduce parasitic inductance by using the capacitor 29a, thereby reducing surge voltage. Therefore, more stable operation can be ensured.

[0053] In this embodiment, capacitor 29a includes a ceramic capacitor. Such capacitors are relatively inexpensive and various types can be selected and applied depending on the application and purpose, making them suitable for use.

[0054] (Embodiment 3) Embodiment 3, another embodiment, will now be described. Figures 10 and 11 are schematic plan views of the semiconductor device in Embodiment 3. In Figure 11, the sealing resin is shown with a dashed line. Figure 12 is a schematic plan view of the semiconductor device shown in Figure 11, with the conductive members omitted. Figure 13 is a schematic plan view of the semiconductor device shown in Figure 12, with the connecting members omitted. Figures 14, 15, and 16 are schematic cross-sectional views showing a part of the semiconductor device shown in Figure 11. Figure 14 is a cross-sectional view taken along the arrows XIV-XIV in Figure 11. Figure 15 is a cross-sectional view taken along the arrows XV-XV in Figure 11. Figure 16 is a cross-sectional view taken along the arrows XVI-XVI in Figure 11. The semiconductor device in Embodiment 3 has basically the same configuration as in Embodiment 1 and produces the same effects. However, the semiconductor device in Embodiment 3 differs from that of Embodiment 1 in configuration such as the number of main terminals.

[0055] Referring to Figures 10 to 16, the semiconductor device 10c in Embodiment 3 includes a wiring board 11c, a control circuit board 12c, a control circuit board 12d, a semiconductor chip 13g, a semiconductor chip 13h, main terminals 14f, 14g, and 14h, control terminals 15j, 15k, 15m, and 15n, a connecting member 16d, a conductive member 17b, and a sealing resin 18b. In this embodiment, the semiconductor device 10c includes two semiconductor chips 13g and 13h, three main terminals 14f, 14g, and 14h, and four control terminals 15j, 15k, 15m, and 15n. In this respect, it differs from the semiconductor device 10a in Embodiment 1. In this embodiment, when driving the semiconductor device 10c, for example, the main terminal 14f can be set as the N terminal, the main terminal 14g as the O terminal, and the main terminal 14h as the P terminal.

[0056] The conductive member 17b is conductive and includes a first end 51c and a second end 52c. The first end 51c is joined to the main terminal 14f, and the second end 52c is joined to the semiconductor chip 13h. The semiconductor chip 13g and the main terminal 14f are arranged so as to sandwich the control circuit board 12c. Viewed in the thickness direction of the wiring board 11c, the control circuit board 12c and the conductive member 17b have overlapping regions. The conductive member 17b is joined to the control circuit board 12c.

[0057] The semiconductor device 10c with the above configuration makes it easier to ensure stable operation and improves reliability.

[0058] (Other embodiments) In the above embodiment, solder was used as the bonding material, but the invention is not limited to solder, and other bonding materials, such as conductive adhesives, may also be used.

[0059] Furthermore, in the above embodiment, the sealing resin is formed by transfer molding, but the semiconductor device is not limited to this, and may also be configured to include a case on which a wiring board is mounted as a semiconductor device, and a sealing resin enclosed within the case.

[0060] The embodiments disclosed herein should be understood to be illustrative in all respects and not restrictive in any way. The scope of the present invention is defined not by the foregoing description but by the claims, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0061] 10a, 10b, 10c Semiconductor equipment 11a, 11c Wiring board 12a, 12b, 12c, 12d Control circuit board 13a, 13b, 13c, 13d, 13e, 13f, 13g, 13h Semiconductor chips 14a, 14b, 14c, 14d, 14e, 14f, 14g, 14h Main terminals 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, 15i, 15j, 15k, 15m, 15n Control terminals 16a, 16b, 16c, 16d Connecting members 17a, 17b Conductive material 18a,18b Sealing resin 21a Insulating substrate 22a 1st metal plate 22b 2nd metal plate 23a 1st division 23b 2nd division 25a, 25b insulating layer 26a,26b 3rd metal plate 27a,27b 4th metal plate 28a,28b Bonding material 29A Capacitor 31a,31b 1st circuit board 32a,32b 2nd circuit board 33a,33b 3rd circuit board 34a,34b 4th circuit board 35a,35b 5th circuit board 36a 1st support plate 36b 2nd support plate 37a, 37b, 37c, 37d, 37e, 37f, 38a, 38b, 38c, 38d, 38e, 38f wire 41a 1st area 42a 2nd area 43a Third area 44a 4th area 45a 5th area 46a 6th area 51a, 51b, 51c 1st end 52a 2nd end 53a,53b joint 55a circuit 56a,56b Power supply 57a, 57b Parasitic inductance 57c inductive load 58a, 58b Body Diodes 59a, 59b Capacitors.

Claims

1. Wiring board and A control circuit board having an insulating layer, A semiconductor chip mounted on the wiring board is positioned at a distance from the control circuit board when viewed in the thickness direction of the wiring board, Viewed in the thickness direction of the aforementioned wiring board, the main terminals are arranged at a distance from the wiring board, A conductive member having conductivity and including a first end and a second end, wherein the first end is joined to the main terminal and the second end is joined to the semiconductor chip, The semiconductor chip and the main terminal are arranged so as to sandwich the control circuit board. Viewed in the thickness direction of the wiring board, the control circuit board and the conductive member have overlapping regions. The conductive member is a semiconductor device bonded to the control circuit board.

2. The semiconductor device according to claim 1, further comprising a capacitor disposed between the conductive member and the control circuit board.

3. The semiconductor device according to claim 1 or claim 2, wherein the conductive member is joined to the control circuit board by solder.

4. The semiconductor device according to claim 1 or claim 2, wherein the conductive member is in the shape of a plate.

5. The semiconductor device according to claim 1 or claim 2, further comprising control terminals extending in the thickness direction of the wiring board and electrically connected to the control circuit board.

6. The aforementioned semiconductor chip is a transistor chip, The aforementioned control terminal is The gate terminal electrically connected to the gate electrode of the semiconductor chip, The semiconductor device according to claim 5, further comprising an auxiliary source terminal electrically connected to the source electrode of the semiconductor chip.

7. The aforementioned main terminals are provided in multiple locations. The semiconductor device according to claim 1 or claim 2, wherein the conductive member is joined to each of the main terminals.

8. The aforementioned semiconductor chip is provided in multiple quantities. The semiconductor device according to claim 1 or claim 2, wherein the plurality of semiconductor chips are arranged at intervals from each other.

9. The semiconductor device according to claim 2, wherein the capacitor includes a ceramic capacitor.

10. The semiconductor device according to claim 1 or claim 2, further comprising a sealing resin that covers the wiring board, the control circuit board, the semiconductor chip, and the conductive member, and exposes a portion of the main terminal.

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