Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device with reduced on-resistance and a method for manufacturing the same. [Solution] The semiconductor device 1 comprises a first electrode 6, a second electrode 7 spaced apart from the first electrode in the Z-axis direction, a plurality of control electrodes 3 provided between the first electrode and the second electrode and extending in the Y-axis direction, a semiconductor layer 5 provided between the first electrode and the second electrode and having a first semiconductor region 13 that is in ohmic contact with the first electrode, a plurality of insulating portions 4 provided within the semiconductor layer, a plurality of third electrodes provided so as to face the control electrodes in the X-axis direction intersecting the Z-axis direction and the Y-axis direction, sandwiched between adjacent insulating portions 4 in the X-axis direction, electrically connected to the second electrode, and spaced apart from each other along the Y-axis direction, and a second semiconductor region 12 provided on the first semiconductor region within the semiconductor layer, having a higher impurity concentration than the first semiconductor region, sandwiched between the third electrodes along the Y-axis direction, in Schottky contact with the third electrode, and having a width along the X-axis direction that is wider than the width along the Y-axis direction.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] A semiconductor device is known that switches between an on state and an off state by controlling the height of the Schottky barrier by the voltage applied to the gate electrode. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 02-238671 [Patent Document 2] Japanese Patent Application Publication No. 03-289176 [Patent Document 3] Japanese Patent Publication No. 2015-056492 [Overview of the project] [Problems that the invention aims to solve]

[0004] This embodiment provides a semiconductor device capable of reducing on-resistance and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes: a first electrode; a second electrode provided spaced apart from the first electrode in a first direction; a plurality of control electrodes provided between the first electrode and the second electrode and extending in a second direction intersecting the first direction; a semiconductor layer provided between the first electrode and the second electrode and having a first semiconductor region that makes ohmic contact with the first electrode; a plurality of insulating portions provided within the semiconductor layer and between the semiconductor layer and the control electrodes, respectively; a plurality of third electrodes provided so as to face the control electrodes in a third direction intersecting the first and second directions, sandwiched between adjacent insulating portions in the third direction, electrically connected to the second electrode, and spaced apart from each other along the second direction; and a second semiconductor region provided on the first semiconductor region within the semiconductor layer, having a higher impurity concentration than the first semiconductor region, sandwiched between the third electrodes along the second direction, making Schottky contact with the third electrode, and having a width along the third direction that is wider than the width along the second direction.

[0006] A method for manufacturing a semiconductor device according to this embodiment is a method for manufacturing a semiconductor device having a first electrode, a second electrode provided spaced apart from the first electrode in a first direction, and a control electrode provided facing the second electrode in the first direction and extending in a second direction intersecting the first direction, wherein control electrodes are formed in a plurality of insulating portions provided in a semiconductor layer, each arranged in a first direction and a third direction intersecting the second direction, a plurality of trenches are formed on one main surface of the semiconductor layer between the plurality of control electrodes so as to be arranged in the second direction, the semiconductor layer is removed until the side walls of the plurality of trenches reach the insulating portions, and a plurality of third electrodes that make Schottky contact with the semiconductor layer and the second electrode that connects to the plurality of third electrodes are formed in the plurality of trenches. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure. [Figure 2A] A first schematic cross-sectional view along line AA in Figure 1. [Figure 2B] Second schematic cross-sectional view taken along line B-B of FIG. 1. [Figure 3] Schematic perspective view illustrating a semiconductor device centered on range D of FIG. 1. [Figure 4A] Enlarged view of range D of FIG. 1 in the off state. [Figure 4B] Enlarged view of range D of FIG. 1 in the on state. [Figure 5] Diagram for explaining parasitic capacitance in a semiconductor element according to an embodiment of the present disclosure. [Figure 6] Diagram for explaining parasitic capacitance of a semiconductor element according to a modified example. [Figure 7] Schematic plan view showing the configuration of a semiconductor device according to a comparative example. [Figure 8] Schematic cross-sectional view showing the configuration of a semiconductor device taken along line D-D of FIG. 7. [Figure 9A] Diagram showing the formation process of an insulating portion of a semiconductor device according to an embodiment of the present disclosure. [Figure 9B] Diagram showing the trench formation process of a semiconductor device according to an embodiment of the present disclosure, following FIG. 9A. [Figure 9C] [[ID=3‚2]]Diagram showing the etching process of a trench of a semiconductor device according to an embodiment of the present disclosure, following FIG. 9B. [Figure 9D] Diagram showing the film formation process of a Schottky metal of a semiconductor device according to an embodiment of the present disclosure, following FIG. 9C.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the previous drawings, and detailed descriptions are omitted as appropriate.

[0009] For convenience of explanation, as shown in FIG. 1 and the like, an XYZ orthogonal coordinate system is adopted. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. The Y-axis direction is one direction in the plane direction of the semiconductor device, and more specifically, it is the direction in which a plurality of semiconductor elements are arranged. Also, in the Z-axis direction, the source electrode side is also referred to as "up", and the drain electrode side is also referred to as "down". However, this expression is for convenience and has nothing to do with the direction of gravity.

[0010] Also, in the following description, in order to represent the relative high and low impurity concentrations in each conductivity type, n + , n, n - , and p + , p, p - notations may be used. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. These notations represent the relative high and low net impurity concentrations after the p-type and n-type impurities compensate for each other when both p-type and n-type impurities are included in each region. In this specification, n-type, n + type and n - type are also referred to as the first conductivity type. Also, in this specification, p-type, p + type and p - type are also referred to as the second conductivity type. Note that in the following description, n-type and p-type may be reversed.

[0011] Also, the impurity concentration of the semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS). Also, the relative high and low of the impurity concentration can be determined, for example, from the high and low of the carrier concentration obtained by scanning capacitance microscopy (SCM).

[0012] Furthermore, dimensions such as the width of the diffusion region can be measured, for example, by surface and / or cross-sectional analysis using a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or scanning electron microscope (SEM).

[0013] Furthermore, the composition of conductive parts and other components can be analyzed using methods such as energy-dispersive X-ray spectroscopy. <Embodiments of this Disclosure>

[0014] A semiconductor device 1 according to an embodiment of the present disclosure will be described with reference to Figures 1, 2A, and 2B. Figure 1 is a schematic plan view illustrating a semiconductor device 1 according to an embodiment of the present disclosure. The horizontal and vertical directions in Figure 1 correspond to the X-axis direction (third direction) and Y-axis direction (second direction) described above, respectively. The depth direction in Figure 1 corresponds to the Z-axis direction (first direction) described above. Note that the plan view in Figure 1 corresponds to the plane of the CC line in Figures 2A and 2B.

[0015] Figure 2A is a first schematic cross-sectional view along line AA in Figure 1, and Figure 2B is a second schematic cross-sectional view along line B-B in Figure 1. Figure 2A shows a cross-section of the Schottky electrode 11, and Figure 2B shows a cross-section of the diffusion region 12. The horizontal and vertical directions in Figures 2A and 2B correspond to the X-axis and Z-axis directions, respectively. As shown in Figures 2A and 2B, the semiconductor element 2 of this embodiment is a MOSFET having a field plate (FP) electrode, i.e., an FPMOS.

[0016] The semiconductor device 1 shown in Figures 1, 2A, and 2B includes a control electrode 3, an insulating portion 4, a semiconductor layer 5, an electrode (first electrode) 6, an electrode (second electrode) 7, a Schottky electrode (third electrode) 11, a diffusion region (second semiconductor region) 12, a semiconductor region (first semiconductor region) 13, and a conductive portion 14. The semiconductor device 1 has a plurality of semiconductor elements 2.

[0017] Semiconductor element 2 is a vertical transistor through which current flows in the Z-axis direction. More specifically, semiconductor element 2 is a vertical MOSFET (Metal Oxide Silicon Field Effect Transistor) that switches between on and off states by controlling the thickness of the Schottky barrier through controlling the potential of the control electrode 3. In the example in Figure 1, multiple semiconductor elements 2 are arranged in the X-axis and Y-axis directions.

[0018] The control electrode 3 extends in the Y-axis direction. In the example shown in Figure 1, multiple control electrodes 3 are arranged in the X-axis direction. As shown in Figure 2A, etc., the control electrode 3 is positioned opposite electrode 7 in the Z-axis direction. The control electrode 3 contains polysilicon containing, for example, p-type or n-type impurities. The control electrode 3 functions as the gate electrode of the MOSFET and controls the current flowing between electrode 6 and electrode 7.

[0019] The insulating portion 4 is arranged to surround the control electrode 3. As shown in Figure 1, the insulating portion 4 insulates the control electrode 3 from the Schottky electrode 11. Furthermore, the insulating portion 4 insulates the control electrode 3 from the diffusion region 12. The insulating portion 4 is, for example, a silicon oxide film (SiO2).

[0020] As shown in Figure 1, the Schottky electrodes 11 are positioned so as to be sandwiched between adjacent insulating portions 4 in the X-axis direction. In addition, multiple Schottky electrodes 11 are arranged along the Y-axis direction. More specifically, in the example in Figure 1, multiple Schottky electrodes 11 are arranged along the Y-axis direction between the two control electrodes 3.

[0021] The diffusion region 12 is positioned between the two Schottky electrodes 11 (the first Schottky electrode and the second Schottky electrode). As shown in Figure 1, the Schottky electrodes 11 and the diffusion region 12 are alternately arranged between the two control electrodes 3 along the Y-axis. In addition to the two Schottky electrodes 11, the diffusion region 12 is also in contact with the electrode 7 in the Z-axis direction, as shown in Figure 2B.

[0022] Furthermore, the Schottky electrode 11 and the diffusion region 12 are not limited to being placed between the insulating portions 4, but may also be placed between the control electrode 3 and an element isolation film or protective film (not shown) that separates the semiconductor element 2 from other components (for example, other transistors, diodes, or wiring layers controlled independently of the semiconductor device 1).

[0023] The semiconductor layer 5 is an n-type (first conductivity type) semiconductor region. The semiconductor layer 5 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate. In this specification, an example in which the semiconductor layer 5 is made of silicon (Si) is described.

[0024] As shown in Figure 2B, the semiconductor layer 5 includes a diffusion region 12 and a semiconductor region 13 that are electrically connected to each other. A semiconductor region (not shown) with a higher n-type impurity concentration than the semiconductor region 13 may be provided between the semiconductor region 13 and the electrode 6.

[0025] The diffusion region 12 is located on top of the semiconductor region 13. The diffusion region 12 is an n-type semiconductor region with a higher impurity concentration than the semiconductor region 13. The n-type impurity concentration of the semiconductor region 13 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 2 x 10 18 cm -3 The following applies. In contrast, the concentration of n-type impurities in the diffusion region 12 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 2 x 10 22 cm -3 The following applies: In the diffusion region 12, for example, arsenic (As), phosphorus (P), or antimony (Sb) is implanted as an n-type (first conductivity type) impurity.

[0026] Electrode 6 is positioned on the first surface A1 side of the semiconductor layer 5. Electrode 6 is a flat electrode extending in the X-axis and Y-axis directions. Electrode 6 is electrically connected to the semiconductor layer 5. Electrode 6 makes ohmic contact with the semiconductor layer 5. Electrode 6 is made of, for example, Cu, Ti, W, or Al. Electrode 6 functions as the drain electrode of the MOSFET.

[0027] Electrode 7 is positioned isolated from electrode 6 in the Z-axis direction. Electrode 7 is a flat electrode extending in the X-axis and Y-axis directions. Electrode 7 is positioned on the second surface side A2 of semiconductor layer 5 and is electrically connected to semiconductor layer 5. Electrode 7 is electrically connected to Schottky electrode 11, as shown in Figure 2A.

[0028] The Schottky electrode 11 extends from the electrode 7 toward the first surface A1 between adjacent insulating portions 4. The Schottky electrode 11 is positioned opposite the control electrode 3 in the X-axis direction. The Schottky electrode 11 makes Schottky contact with the diffusion region 12, forming a Schottky barrier at the interface with the diffusion region 12. For example, a metal with a higher work function than electrode 7 is used for the Schottky electrode 11.

[0029] The Schottky electrode 11 includes at least one of the following materials (e.g., Pt): Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, Co, or Hf. The electrode 7 includes at least one of the following materials (e.g., W): Al, Cu, Mo, W, Ta, Co, Ru, Ti, or Pt.

[0030] The Schottky electrode 11 and electrode 7 may be made of the same metal. If they are made of the same metal, the Schottky electrode 11 and electrode 7 may be formed as a single unit.

[0031] It is desirable that the Schottky electrode 11 be embedded at a shallower position in the depth direction (Z-axis direction) of the semiconductor layer 5 than the control electrode 3, or at approximately the same position. Specifically, it is desirable that the lower end surface A3 of the Schottky electrode 11 be positioned above or at approximately the same position in the depth direction of the semiconductor layer 5 as the lower end surface A4 of the control electrode 3. As a result, the lower end surface of the depletion layer (depletion layer 31 described later) formed in the diffusion region 12 is formed above, and more preferably at approximately the same position as, the lower end surface A3 of the Schottky electrode 11. Consequently, the gate-drain parasitic capacitance (parasitic capacitor 41 described later) can be further reduced.

[0032] In this specification, the state in which a predetermined voltage is applied to the control electrode 3 and current flows between electrodes 6 and 7 is referred to as the ON state of the semiconductor element 2. The state in which a current smaller than that of the ON state flows between electrodes 6 and 7, or in which no current flows, is referred to as the OFF state of the semiconductor element 2. When the semiconductor element 2 is in the ON state, a channel (channel 32, described later) through which current flows between electrodes 6 and 7 is formed in the diffusion region 12.

[0033] Furthermore, by increasing the Schottky barrier at the interface between the Schottky electrode 11 and the diffusion region 12, the threshold voltage of the semiconductor device 2 can be increased. This allows the semiconductor device 2 to be configured as a normally-off MOSFET.

[0034] On the other hand, a low source contact resistance is desirable between the electrode 7 and the diffusion region 12. Reducing the source contact resistance reduces the on-resistance of the semiconductor element 2, enabling faster switching of the semiconductor element 2 and suppression of turn-on and turn-off losses.

[0035] As shown in Figure 2A, etc., the conductive portion 14 is located inside the insulating portion 4, below the control electrode 3, and functions as a field plate electrode. The conductive portion 14 is electrically connected to the electrode 7. The conductive portion 14 contains, for example, polysilicon containing p-type or n-type impurities. By providing the conductive portion 14, when the semiconductor device 1 is in the off state, a depletion layer extends from the conductive portion 14 to the surrounding drift region due to the reverse voltage applied between the drain electrode and the source electrode. This depletion layer connects with the depletion layer of the adjacent conductive portion 14, thereby improving the breakdown voltage of the semiconductor device 1.

[0036] Furthermore, the semiconductor element 2 may have a configuration in which the conductive portion 14 is omitted. That is, the semiconductor element 2 may be a trench MOS structure according to the modified example described later.

[0037] Figure 3 is a schematic perspective view illustrating a semiconductor device 1 centered on area D in Figure 1. Figure 3 shows two control electrodes 3, two insulating parts 4, two Schottky electrodes 11, a diffusion region 12, a semiconductor region 13, and a conductive part 14.

[0038] Next, the semiconductor element 2 will be described in detail with reference to Figures 4A and 4B. Figures 4A and 4B are enlarged views of area D in Figure 1. Figure 4A illustrates the off state of the semiconductor element 2. Figure 4B illustrates the on state of the semiconductor element 2.

[0039] Figures 4A and 4B illustrate two control electrodes 3, two insulating sections 4, two Schottky electrodes 11, and a diffusion region 12. The two control electrodes 3 are positioned opposite each other along the X-axis. The two Schottky electrodes 11 are positioned opposite each other along the Y-axis. The two insulating sections 4 insulate the control electrodes 3 from the Schottky electrodes 11 and the diffusion region 12, respectively. The diffusion region 12 is positioned between adjacent control electrodes 3 and between adjacent Schottky electrodes 11.

[0040] A depletion layer 31 is formed at the interface between the diffusion region 12 and the Schottky electrode 11. The depletion layer 31 is a region of the diffusion region 12 that has less charge or no charge at all compared to other regions of the diffusion region 12.

[0041] As shown in Figure 4A, when the semiconductor element 2 is in the off state, the depletion layer 31 is formed over substantially the entire surface of the diffusion region 12 along the X-axis and Y-axis directions.

[0042] The depletion layer 31 is formed, for example, by the bonding of two depletion layers formed at the two interfaces of the diffusion region 12. Specifically, a first depletion layer is formed at the interface between the diffusion region 12 and one of the two Schottky electrodes 11 (hereinafter also referred to as the first Schottky electrode 11). A second depletion layer is formed at the interface between the diffusion region 12 and the other of the two Schottky electrodes 11 (hereinafter also referred to as the second Schottky electrode 11). The depletion layer 31 is formed by the bonding of the first and second depletion layers.

[0043] In Figure 4B, a voltage is applied to the control electrode 3, and the semiconductor element 2 turns on. When the semiconductor element 2 turns on, the depletion layer 31 shrinks (recedes) in the X-axis direction from the interface between the insulating portion 4 and the diffusion region 12. As a result, as shown in Figure 4B, channels (conductive regions) 32 are formed in the diffusion region 12. The channels 32 do not extend across the entire surface of the diffusion region 12 in the X-axis direction. That is, channels 32 are formed at the interface between one insulating portion 4 and the diffusion region 12, and at the interface between the other insulating portion 4 and the diffusion region 12, respectively.

[0044] In this specification, the length from the interface between the diffusion region 12 and the first Schottky electrode 11 to the interface between the diffusion region 12 and the second Schottky electrode 11 (i.e., the width of the diffusion region 12 along the Y-axis) is referred to as the thickness T of the diffusion region 12. The length from the interface between the diffusion region 12 and the first insulating portion 4 to the interface between the diffusion region 12 and the second insulating portion 4 (i.e., the width of the diffusion region 12 along the X-axis) is referred to as the width W of the diffusion region. The width W is sometimes referred to as the mesa width or pitch of the semiconductor element 2.

[0045] In the examples of Figures 4A and 4B, the thickness T is smaller than the width W. More specifically, the thickness T may be less than or equal to half the width W. For example, the thickness T is 50 nm to 100 nm. For example, the width W is 100 nm to 200 nm. This numerical range of thickness T and width W is one guideline for individually forming channels 32 at the interface between the insulating portion 4 and the diffusion region 12.

[0046] As shown in Figure 4B, in the ON state of the diffusion region 12, the first interface where the Schottky barrier is formed (i.e., the interface between the diffusion region 12 and the Schottky electrode 11) and the second interface where the channel 32 is formed (i.e., the interface between the diffusion region 12 and the insulating portion 4) do not face each other. Compared to a structure in which the first and second interfaces face each other, the semiconductor element 2 forms a wide channel at the second interface when a voltage is applied to the control electrode 3. This reduces the ON resistance of the semiconductor element 2.

[0047] Furthermore, in the ON state, channels 32 are locally formed at the interface between the insulating portion 4 and the diffusion region 12, and do not extend across the entire surface of the diffusion region 12 in the X-axis direction. As a result, the semiconductor element 2 can be turned OFF at high speed.

[0048] However, the thickness T of the diffusion region 12 should be sufficiently thin so that the first depletion layer formed at the interface between the diffusion region 12 and the first Schottky electrode 11 bonds with the second depletion layer formed at the interface between the diffusion region 12 and the second Schottky electrode 11. Also, the width W should be sufficiently large so that the channel 32 does not extend across the entire surface of the diffusion region 12 in the X-axis direction when the semiconductor device 2 is in the ON state.

[0049] The thickness T and width W can be arbitrarily adjusted, for example, depending on the material of the Schottky electrode 11 and the diffusion region 12, the type or concentration of impurities injected into the diffusion region 12, the voltage applied to the control electrode 3 to turn it on, or the temperature design of the semiconductor element 2.

[0050] The thickness T and width W of the semiconductor element 2 can be arbitrarily adjusted within the range in which the channel 32 is locally formed at the interface between the diffusion region 12 and the insulating portion 4. For example, by reducing the width W of the semiconductor element 2, the pitch can be reduced (pitch shrink), and the semiconductor device 1 can be miniaturized. Furthermore, by increasing the density of the drift current, the on-resistance can be reduced.

[0051] In this embodiment, the diffusion region 12 is in contact with both the first Schottky electrode 11 and the second Schottky electrode 11. This increases the contact area between the Schottky electrode 11 and the diffusion region 12 compared to a configuration where the diffusion region 12 is in contact with only one Schottky electrode, thereby reducing the source contact resistance. Furthermore, the increased contact area improves the degree of freedom in determining the thickness T, allowing for a larger thickness T.

[0052] Figure 5 illustrates the parasitic capacitance reduction effect of the semiconductor element 2 according to the embodiment of this disclosure. Figure 5 shows a parasitic capacitor 41 formed between the control electrode 3 and the electrode 6. The parasitic capacitor 41 is formed between the control electrode 3 and the electrode 6 via a semiconductor layer 5 that faces the control electrode 3 in the X-axis direction.

[0053] The parasitic capacitor 41 is the gate-drain capacitance (Cgd). Furthermore, the parasitic capacitor 41 constitutes the feedback capacitance (Crss). If the parasitic capacitor 41 is large, the rise and fall times of the drain-source voltage of the semiconductor element 2 become slow, resulting in a problem where the switching speed of the semiconductor element 2 slows down.

[0054] The semiconductor element 2 has a depletion layer 31 extending in the X-axis direction formed by the Schottky electrode 11. This reduces the capacitance of the parasitic capacitor 41.

[0055] Furthermore, in the off state, the semiconductor element 2 has a depletion layer 31 formed over almost the entire area of ​​the diffusion region 12 along the X-axis (i.e., from one insulating portion 4 to the other insulating portion 4). Therefore, the capacitance reduction effect of the parasitic capacitor 41 is greater than that of a structure in which the depletion layer is formed only in a part of the diffusion region 12.

[0056] Of the depletion layer 31, the portion positioned at the same height as the control electrode 3 contributes to a greater reduction in parasitic capacitance. Therefore, it is desirable that the depletion layer 31 be formed at approximately the same height as the lower end of the control electrode 3. Alternatively, the lower end of the depletion layer 31 may be formed at a higher position than the lower end of the control electrode 3. In order to form such a depletion layer 31, it is desirable that the Schottky electrode 11 be embedded at a shallower position in the depth direction (Z-axis direction) of the semiconductor layer 5 than the control electrode 3, or at approximately the same position, as shown in Figure 2B. <Variation>

[0057] Figure 6 illustrates the parasitic capacitance of a modified semiconductor element 200. As shown in Figure 6, the semiconductor element 200 differs from the semiconductor element 2 in that it does not have a conductive portion 14. The semiconductor element 200 has a trench MOS structure in which a control electrode 201 is embedded in a trench of the semiconductor layer. In addition, a depletion layer 202 is formed in the semiconductor element 200 by a Schottky electrode (not shown).

[0058] In the semiconductor device 200, a parasitic capacitor 203 is formed between the control electrode 201 and electrode 6 via a semiconductor layer 5 facing the control electrode 201 in the X-axis direction. Furthermore, in the semiconductor device 200, a parasitic capacitor 204 is formed between the control electrode 201 and electrode 6 via a semiconductor layer 5 facing the control electrode 201 in the Z-axis direction. Parasitic capacitors 203 and 204 constitute the gate-drain capacitance Cgd, which forms the feedback capacitance Crss.

[0059] The parasitic capacitor 204 does not have a depletion layer 202 formed nearby, and therefore the parasitic capacitance reduction effect of the depletion layer 202 cannot be obtained.

[0060] In comparison with the semiconductor element 200 in Figure 6, the semiconductor element 2 in Figure 5 has a conductive portion 14 positioned between the control electrode 3 and the semiconductor layer 5 facing it in the Z-axis direction. Therefore, in the semiconductor element 2 of Figure 5, no parasitic capacitor corresponding to the parasitic capacitor 204 is formed. Thus, the semiconductor element 2 achieves a greater reduction in parasitic capacitance than the semiconductor element 200 according to the modified example.

[0061] Next, we will describe comparative examples for comparison with the embodiments described above. <Comparative Example>

[0062] Figure 7 is a schematic plan view showing the configuration of a semiconductor device 100 according to one comparative example. As shown in Figure 7, the semiconductor device 100 differs from the semiconductor device 1 of the embodiment in that only one Schottky electrode 101 extending in the Y-axis direction is arranged between adjacent control electrodes 3. In addition, in Figure 7, a diffusion region 102 is arranged between the Schottky electrode 101 and the insulating portion 4, in which a channel (channel 104 described later) is formed when the device is ON.

[0063] Figure 8 is a schematic cross-sectional view showing the configuration of a semiconductor device 100 according to one comparative example. Figure 8 shows a cross-section of the DD line in Figure 7. Figure 8 also illustrates the depletion layer 103 formed in the diffusion region 102 and the channel 104 formed when a predetermined voltage is applied to the control electrode 3 and it becomes ON.

[0064] As shown in Figure 8, the depletion layer 103 and channel 104 in one comparative example are formed on the interface surfaces facing each other. In particular, in the semiconductor device 100, if the Schottky barrier is increased to reduce leakage current, it becomes difficult to form the channel 104, affecting the resistance of the channel 104. For this reason, it is difficult to achieve both an improvement in the Schottky barrier and a reduction in on-resistance. Also, if the width (length in the X-axis direction) of the diffusion region 102 is narrowed, the source contact resistance increases, making it difficult to reduce the pitch.

[0065] Compared to a comparative example semiconductor device 100, in the semiconductor device 1 according to the embodiment of this disclosure, the channel 32 is formed at an interface different from the interface between the diffusion region 12 and the Schottky electrode 11 (i.e., the interface between the diffusion region 12 and the insulating portion 4). This makes it possible to achieve both an improvement in the Schottky barrier and a reduction in source contact resistance.

[0066] Furthermore, in semiconductor device 1, the diffusion region 12 is in contact with the two Schottky electrodes 11, resulting in a large contact area with the Schottky electrodes 11. This reduces source contact resistance. In addition, pitch shrinking is easier than in semiconductor device 100 while maintaining low source contact resistance. For example, in the semiconductor device 1 according to the embodiment of this disclosure, the pitch of the semiconductor element 2 can be narrowed by about 10 times compared to semiconductor device 100 according to one comparative example. <Manufacturing method for semiconductor device 1>

[0067] Next, an example of a manufacturing method for the semiconductor device 1 of the embodiment will be described. Figures 9A to 9D are diagrams illustrating the manufacturing process of the semiconductor device 1 according to the embodiment of this disclosure.

[0068] Figure 9A shows the process of forming the interlayer film (insulating portion 4). In this process, the control electrode 3 and the insulating portion 4, which is the interlayer film of the semiconductor element 2, are formed. For example, a trench (not shown) is formed from one main surface of the semiconductor layer 5 by etching or the like, and the insulating portion is formed to cover the side walls of the trench. Then, the control electrode 3 is formed within this insulating portion. Subsequently, the insulating portion is formed to embed the control electrode 3, thereby forming the insulating portion 4. Multiple control electrodes 3 are formed so as to be arranged in the X-axis direction.

[0069] Figure 9B shows the trench contact formation process. In this process, multiple trenches 51a for embedding the Schottky electrode 11 are formed in the semiconductor layer 5. The multiple trenches 51a are formed in a dot-like pattern between adjacent control electrodes 3, arranged in the Y-axis direction, which is the direction in which the control electrodes 3 extend. The multiple trenches 51a are formed by methods such as PEP (Photo Engraving Process) or Reactive Ion Etching (RIE).

[0070] Figure 9C shows the etching process of the trench contact. In this process, the sidewall of the trench 51a is etched using a highly selective (SiO2 / Si) CDE (Chemical Dry Etching) or the like to form a trench 51b with a wider contact width. The trench 51b is formed so as to extend from one end of the insulating portion 4 to one end of the adjacent insulating portion 4.

[0071] Figure 9D shows the Schottky metal film deposition process. In this process, a Schottky electrode 11 is formed by depositing a metallic material in a trench 51b. In this process, an electrode 7 may be formed continuously as an integral part of the Schottky electrode 11. Alternatively, the electrode 7 may be formed after this process.

[0072] In the post-processing step shown in Figure 9D, or in any of the pre-processing steps shown in Figures 9A to 9D, impurities are injected from one main surface of the semiconductor layer 5, and a diffusion region 12 is formed by a thermal diffusion process or the like. The thermal diffusion process may be performed as a separate process.

[0073] The Schottky electrode 11 and diffusion region 12 shown in Figure 1 can be formed by the steps shown in Figures 9A to 9D above. According to this embodiment, compared to the comparative example described above, even if the formation position of the Schottky electrode is slightly shifted, it does not significantly affect the characteristics of the semiconductor device.

[0074] In the manufacturing process according to the embodiment of this disclosure, even if there is variation in the width of the trench 51a in the process shown in Figure 9B, the width W of the Schottky electrode 11 can be made uniform by the etching process shown in Figure 9C. Specifically, in the CDE process shown in Figure 9C, the etching rate ratio of silicon (Si) in the semiconductor layer 5 is higher than that of the oxide film (SiO2) in the insulating part 4, and the insulating part 4 functions as an etching stopper. Therefore, even if there is variation in the width of the trench 51a, the width of the trench 51b can be made uniform. Consequently, the width W of the Schottky electrode 11 can be made uniform. Therefore, a fitting margin can be secured in the etching process shown in Figure 9C.

[0075] Furthermore, as described above, the semiconductor device 1 according to this disclosure allows for improved design flexibility in the thickness T of the diffusion region 12 shown in Figure 4A, etc. That is, it allows for improved flexibility in the spacing between adjacent Schottky electrodes 11 in the Y-axis direction. As a result, it is also possible to simplify the manufacturing process of the semiconductor device 2.

[0076] As described above, the semiconductor device 1 according to the embodiment of this disclosure has a diffusion region 12 sandwiched between adjacent Schottky electrodes 11. In the diffusion region 12 according to the embodiment of this disclosure, when the semiconductor element 2 is in the ON state, a channel 32 is formed on an interface that does not face the interface that contacts the Schottky electrode 11. Furthermore, the channel 32 is not formed over the entire surface of the diffusion region 12 in the X-axis direction. This makes it possible to reduce the ON resistance of the semiconductor device 1. It also makes it possible to speed up the OFF operation of the semiconductor device 1.

[0077] Furthermore, the diffusion region 12 has the characteristic of having a large contact area with the Schottky electrodes 11 because it is in contact with the two Schottky electrodes 11. This reduces the source contact resistance. In addition, the semiconductor device 1 can achieve low source contact resistance even when the pitch is narrowed. In other words, the semiconductor device 1 can be miniaturized and source contact resistance reduced.

[0078] Furthermore, in the manufacturing process of the semiconductor device 1, after forming the trench contacts into which the Schottky electrodes 11 are embedded, the side walls are etched. The etching process of the side walls ensures a width adjustment margin for the trench contacts. This simplifies the manufacturing process.

[0079] It should be noted that the present invention is not limited to the embodiments described above, and the components can be modified and implemented in practice without departing from the spirit of the invention. Furthermore, various inventions can be formed by appropriately combining the multiple components disclosed in the embodiments described above. For example, a configuration in which some components are removed from all the components shown in each embodiment is also conceivable. Moreover, components described in different embodiments may be appropriately combined. [Explanation of Symbols]

[0080] 1,100 Semiconductor Machine 2,200 semiconductor devices 3. 201 Control electrode (gate electrode) 4. Insulation part 5 Semiconductor layer 6. Electrodes (drain electrodes) 7. Electrodes (Source Electrodes) 11, 101 Schottky electrodes 12, 102 Diffusion region 13 Semiconductor Field 14 Conductive part (FP electrode) 31, 103, 202 Depletion layers 32, 104 channels 41, 203, 204 Parasitic Capacitors 51a, 51b Trench

Claims

1. First electrode and A second electrode is provided spaced apart from the first electrode in a first direction, A plurality of control electrodes are provided between the first electrode and the second electrode, extending in a second direction intersecting the first direction, A semiconductor layer provided between the first electrode and the second electrode, having a first semiconductor region that makes ohmic contact with the first electrode, A plurality of insulating portions are provided within the semiconductor layer and between the semiconductor layer and the control electrode, A plurality of third electrodes are provided so as to face the control electrode in a third direction intersecting the first and second directions, sandwiched between adjacent insulating portions in the third direction, electrically connected to the second electrode, and spaced apart from each other along the second direction, The semiconductor layer comprises a second semiconductor region provided on the first semiconductor region, having a higher impurity concentration than the first semiconductor region, sandwiched between the third electrodes along the second direction, in Schottky contact with the third electrode, and having a width along the third direction that is wider than the width along the second direction. Semiconductor equipment.

2. When the semiconductor device is in the ON state, the control electrode forms a conductive region at the interface between the second semiconductor region and the insulating portion sandwiching the third electrode, and does not form the conductive region in other regions of the second semiconductor region. The semiconductor device according to claim 1.

3. When the semiconductor device is in the off state, a depletion layer is formed in the second semiconductor region, extending from one insulating portion to the other insulating portion of the insulating portion sandwiching the third electrode. The semiconductor device according to claim 1.

4. When the semiconductor device changes from an off state to an on state, the depletion layer shrinks along the third direction from the insulating portion. The semiconductor device according to claim 3.

5. The second semiconductor region has a width along the second direction that is less than or equal to half the width along the third direction. The semiconductor device according to claim 1.

6. The width of the second semiconductor region along the second direction is 50 nm or more and 100 nm or less. The width of the second semiconductor region along the third direction is 100 nm or more and 200 nm or less. The semiconductor device according to claim 1.

7. The control electrode and the first electrode are further provided with a conductive portion that is electrically connected to the second electrode. The semiconductor device according to any one of claims 1 to 6.

8. First electrode and A second electrode is provided spaced apart from the first electrode in a first direction, A plurality of control electrodes are provided between the first electrode and the second electrode, extending in a second direction intersecting the first direction, A semiconductor layer provided between the first electrode and the second electrode, having a first semiconductor region that makes ohmic contact with the first electrode, A plurality of insulating portions are provided within the semiconductor layer and between the semiconductor layer and the control electrode, A plurality of third electrodes are provided so as to face the control electrode in a third direction intersecting the first and second directions, sandwiched between adjacent insulating portions in the third direction, electrically connected to the second electrode, and spaced apart from each other along the second direction, Within the semiconductor layer, a second semiconductor region is provided on the first semiconductor region, has a higher impurity concentration than the first semiconductor region, is sandwiched between the third electrodes along the second direction, and is in Schottky contact with the third electrode, The control electrode and the first electrode are further provided with a conductive portion that is electrically connected to the second electrode. Semiconductor equipment.

9. First electrode and A second electrode is provided spaced apart from the first electrode in a first direction, A method for manufacturing a semiconductor device, comprising: a control electrode provided opposite to the second electrode in the first direction and extending in a second direction intersecting the first direction, Control electrodes are formed within a plurality of insulating portions provided in the semiconductor layer, each arranged in a third direction intersecting the first and second directions. A plurality of trenches are formed on one main surface of the semiconductor layer, between a plurality of control electrodes, so as to be arranged in the second direction. The semiconductor layer is removed until the side walls of the plurality of trenches reach the insulating portion. A plurality of third electrodes that make Schottky contact with the semiconductor layer and a plurality of second electrodes that connect to the plurality of third electrodes are formed in the plurality of trenches. A method for manufacturing a semiconductor device.

10. The spacing between the plurality of third electrodes is narrower than the spacing between the plurality of insulating portions that insulate each of the plurality of control electrodes from the semiconductor layer, and the third electrodes are formed accordingly. The method for manufacturing a semiconductor device according to claim 9.

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