Semiconductor equipment

Abstract

To provide a semiconductor device with a novel configuration. [Solution] A semiconductor device comprising a plurality of memory cells, each containing a transistor and a capacitive element, wherein the capacitive elements contained in adjacent memory cells are stacked on top of each other. The first capacitive element contained in the first memory cell is arranged such that a portion of the first capacitive element overlaps with the second memory cell adjacent to the first memory cell. The second capacitive element contained in the second memory cell is provided on a different layer from the first capacitive element. The second capacitive element is arranged such that a portion of the second capacitive element overlaps with the first memory cell. The first and second capacitive elements have overlapping regions. The first and second capacitive elements have a ferroelectric material. The ferroelectric material preferably contains hafnium, zirconium, or at least one element selected from the III-V group elements. The transistor preferably contains an oxide semiconductor in the semiconductor layer in which the channel is formed.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, as a more specific technical field of one aspect of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof can be cited as an example.

Background Art

[0003] In recent years, the development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has been proceeding. These semiconductor devices are used in various electronic devices such as computers and portable information terminals. In addition, memories of various storage methods have been developed according to applications such as temporary storage during arithmetic processing execution and long-term data storage. Representative storage method memories include DRAM, SRAM, and flash memory.

[0004] Also, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics have been actively conducted. Further, for next-generation ferroelectric memories, research on ferroelectric HfO2-based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4), and demonstration of integration of FeRAM using ferroelectric Hf 0.5 Zr 0.5 O2 and CMOS (Non-Patent Document 5), etc., research related to hafnium oxide has also been actively conducted.

Prior Art Documents

Non-Patent Documents

[0005] [Non-Patent Document 1] TSBoescke,et al,“Ferroelectricity in hafnium oxide thin films”,APL99,2011 [Non-Patent Document 2] Zhen Fan,et al,“Ferroelectric HfO2-based materials for next-generation ferroelectric memories”,JOURNAL OF ADVANCED DIELECTRICS,Vol.6,No.2,2016 [Non-Patent Document 3] Jun Okuno,et al,“SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2”,VLSI 2020 [Non-Patent Document 4] Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," Journal of the Japan Society of Applied Physics, Vol. 88, No. 9, 2019. [Non-Patent Document 5] T.Francois,et al,“Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”,IEDM 2019 [Overview of the project] [Problems that the invention aims to solve]

[0006] In ferroelectric memory, data writing and reading operations are performed by utilizing the reversal of polarization of the ferroelectric material (a material capable of possessing ferroelectric properties). Furthermore, increasing the residual polarization of the ferroelectric material is required to accurately retain the written data.

[0007] Furthermore, in ferroelectric memory equipped with capacitive elements using ferroelectric materials (also called "ferroelectric capacitance"), the reliability of data retention can be improved by increasing the capacitance value of the capacitance element. Increasing the capacitance value can be achieved by thinning the dielectric and / or increasing the area of ​​the capacitance element. However, the former method is difficult to achieve because it reduces residual polarization. The latter method is in a trade-off relationship with the reduction of occupied area due to the high density of memory elements ("memory cells").

[0008] One aspect of the present invention aims to provide a novel memory device. Alternatively, one aspect of the present invention aims to provide a memory device with a small footprint. Alternatively, one aspect of the present invention aims to provide a highly reliable memory device. Alternatively, one aspect of the present invention aims to provide a memory device with low power consumption. Alternatively, one aspect of the present invention aims to provide a memory device with a large storage capacity. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a small footprint. Alternatively, one aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large storage capacity.

[0009] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be deduced by those skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device comprising first and second transistors and first and second capacitance elements, wherein the first transistor is electrically connected to the first capacitance element, the second transistor is electrically connected to the second capacitance element, the first and second capacitance elements are provided above the first and second transistors, the first and second capacitance elements each have a ferroelectric material, and the first and second capacitance elements have overlapping regions.

[0011] (2) Another aspect of the present invention is a semiconductor device comprising first and second transistors, first and second capacitance elements, and first to third wirings, wherein the gate of the first transistor is electrically connected to the first wiring, the gate of the second transistor is electrically connected to the second wiring, one of the source or drain of the first transistor is electrically connected to the first capacitance element, one of the source or drain of the second transistor is electrically connected to the second capacitance element, and the other of the source or drain of each of the first and second transistors is electrically connected to the third wiring, and the first and second capacitance elements each have a ferroelectric material and the first and second capacitance elements have overlapping regions.

[0012] In (1) or (2) above, the first and second transistors may be provided on the same layer.

[0013] (3) Another aspect of the present invention is a semiconductor device comprising first to fourth transistors and first to fourth capacitance elements, wherein the first transistor is electrically connected to the first capacitance element, the second transistor is electrically connected to the second capacitance element, the third transistor is electrically connected to the third capacitance element, and the fourth transistor is electrically connected to the fourth capacitance element, the first to fourth capacitance elements are provided above the first to fourth transistors, each of the first to fourth capacitance elements has a ferroelectric material, the third capacitance element and the fourth capacitance element are provided on the same layer, and the first to third capacitance elements have overlapping regions.

[0014] (4) Another aspect of the present invention is a semiconductor device comprising first to fourth transistors, first to fourth capacitance elements, and first to fourth wiring, wherein the gates of the first and third transistors are electrically connected to the first wiring, the gates of the second and fourth transistors are electrically connected to the second wiring, one of the source or drain of the first transistor is electrically connected to the first capacitance element, one of the source or drain of the second transistor is electrically connected to the second capacitance element, one of the source or drain of the third transistor is electrically connected to the third capacitance element, one of the source or drain of the fourth transistor is electrically connected to the fourth capacitance element, the other of the source or drain of the first and second transistors is electrically connected to the third wiring, the other of the source or drain of the third and fourth transistors is electrically connected to the second wiring, the third capacitance element and the fourth capacitance element are provided on the same layer, and the first to third capacitance elements have overlapping regions.

[0015] (5) Another aspect of the present invention is a semiconductor device comprising first to fourth transistors and first to fourth capacitance elements, wherein the first transistor is electrically connected to the first capacitance element, the second transistor is electrically connected to the second capacitance element, the third transistor is electrically connected to the third capacitance element, and the fourth transistor is electrically connected to the fourth capacitance element, the first to fourth capacitance elements are provided above the first to fourth transistors, each of the first to fourth capacitance elements has a ferroelectric material, and the first to fourth capacitance elements have overlapping regions.

[0016] (6) Another aspect of the present invention is a semiconductor device comprising first to fourth transistors, first to fourth capacitance elements, and first to fourth wiring, wherein the gates of the first and third transistors are electrically connected to the first wiring, the gates of the second and fourth transistors are electrically connected to the second wiring, one of the source or drain of the first transistor is electrically connected to the first capacitance element, one of the source or drain of the second transistor is electrically connected to the second capacitance element, one of the source or drain of the third transistor is electrically connected to the third capacitance element, one of the source or drain of the fourth transistor is electrically connected to the fourth capacitance element, the other of the source or drain of the first and second transistors is electrically connected to the third wiring, the other of the source or drain of the third and fourth transistors is electrically connected to the second wiring, and the first to fourth capacitance elements each have a ferroelectric material and the first to fourth capacitance elements have overlapping regions.

[0017] In any one of the above (3) to (6), the first to fourth transistors may be provided on the same layer.

[0018] Furthermore, in any one of (3) to (6) above, the first to fourth transistors preferably include an oxide semiconductor in the semiconductor layer where the channel is formed. The oxide semiconductor preferably includes at least one of indium or zinc. The ferroelectric material may be a material containing at least one of hafnium or zirconium, or a material containing at least one element selected from the elements of Group III-V. [Effects of the Invention]

[0019] According to one aspect of the present invention, a novel storage device can be provided. Alternatively, according to one aspect of the present invention, a storage device with a small footprint can be provided. Alternatively, according to one aspect of the present invention, a highly reliable storage device can be provided. Alternatively, according to one aspect of the present invention, a storage device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a storage device with a large storage capacity can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a small footprint can be provided. Alternatively, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large storage capacity can be provided.

[0020] The effects of one aspect of the present invention are not limited to those listed above. The listed effects do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0021] [Figure 1] Figures 1A and 1B show examples of semiconductor device configurations. [Figure 2] Figure 2A shows an example of the circuit configuration of two adjacent memory cells. Figure 2B is a perspective view showing an example of the configuration of two adjacent memory cells. Figure 2C is a top view of two adjacent memory cells. Figure 2D is a front view of two adjacent memory cells. [Figure 3] Figures 3A to 3C are top views illustrating one aspect of the present invention. [Figure 4] Figure 4A is a perspective view showing an example configuration of two adjacent memory cells. Figure 4B is a front view of two adjacent memory cells. Figure 4C is a diagram showing an example circuit configuration of two adjacent memory cells. [Figure 5] Figures 5A to 5E are top views illustrating one aspect of the present invention. [Figure 6] Figure 6A is a perspective view showing an example configuration of two adjacent memory cells. Figure 6B is a front view of two adjacent memory cells. Figure 6C is a diagram showing an example circuit configuration of two adjacent memory cells. [Figure 7] Figures 7A to 7F are top views illustrating one aspect of the present invention. [Figure 8] Figure 8 shows an example of hysteresis characteristics. [Figure 9] Figure 9A is a top view showing an example of a transistor configuration. Figures 9B to 9D are cross-sectional views showing an example of a transistor configuration. [Figure 10] Figures 10A and 10B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 11] Figure 11A is a diagram illustrating the classification of crystal structures. Figure 11B is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 11C is a diagram illustrating the micro-electron diffraction pattern of the CAAC-IGZO film. [Figure 12] Figure 12 is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 13] Figure 13 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 14] Figure 14 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 15] Figure 15A is a perspective view showing an example of a semiconductor wafer, Figure 15B is a perspective view showing an example of a chip, and Figures 15C and 15D are perspective views showing examples of electronic components. [Figure 16] Figures 16A to 16J are perspective views or schematic diagrams illustrating an example of electronic equipment. [Figure 17]Figures 17A to 17E are perspective views or schematic diagrams illustrating an example of electronic equipment. [Figure 18] Figures 18A to 18C illustrate an example of an electronic device. [Modes for carrying out the invention]

[0022] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices and may contain semiconductor devices.

[0023] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0024] One example of a case where X and Y are electrically connected is that one or more elements that enable the electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y.

[0025] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, such as operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y.

[0026] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0027] Furthermore, for example, it can be expressed as, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both the wire and the electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0029] Furthermore, in this specification, the term "resistive element" can refer to, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistive element" includes wiring having a resistance value, transistors, diodes, coils, etc., through which current flows between the source and drain. Therefore, the term "resistive element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0030] Furthermore, when using wiring as a resistive element, the resistance value may be determined by the length of the wiring. Alternatively, a conductor with a different resistivity than the conductor used for the wiring may be used as the resistive element. Or, the resistance value may be determined by doping the semiconductor with impurities.

[0031] Furthermore, in this specification, "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification, "capacitive element" includes not only a circuit element comprising a pair of electrodes and a dielectric material contained between the electrodes, but also parasitic capacitance occurring between wirings, the gate capacitance occurring between one of the sources or drains of a transistor and the gate, etc. Also, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." In addition, the term "a pair of electrodes" in "capacitance" can be replaced with terms such as "a pair of conductors," "a pair of conductive regions," and "a pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0032] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain can be used interchangeably. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode, or first terminal) and "the other of the source or drain" (or second electrode, or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0033] Furthermore, in this specification, the term "node" can be replaced with terminals, wiring, electrodes, conductive layers, conductors, impurity regions, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node".

[0034] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0035] Furthermore, in this specification, the terms "high-level potential" (also referred to as "high-level potential," "H potential," or "H") and "low-level potential" (also referred to as "low-level potential," "L potential," or "L") do not mean specific potentials. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0036] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction is occurring in a positively charged body" can be rephrased as "electrical conduction is occurring in the opposite direction in a negatively charged body." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement (electrical conduction) associated with the movement of carriers. Carriers here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., is the direction in which positive carriers move and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, if there is no specification regarding the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, descriptions such as "current is input to element A" can be rephrased as "current is output from element A."

[0037] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0038] Furthermore, in this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0039] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require electrode B to be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0040] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator."

[0041] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0042] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Also, for example, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances or situation. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0043] In this specification, semiconductor impurities refer to elements other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements (excluding oxygen and hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements.

[0044] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically short-circuited. Conversely, the "non-conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically disconnected. When a transistor is simply operated as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] One example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0047] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. "Approximately parallel" or "roughly parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. "Perpendicular" means that two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° or more and 120° or less.

[0048] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute a channel-forming region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when "OS transistor" is mentioned, it can be replaced with a transistor having a metal oxide or oxide semiconductor.

[0049] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0050] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0051] The embodiments described herein will be explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be interpreted as being limited to the contents of the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in order to make the drawings easier to understand, some components may be omitted in perspective views or top views, etc.

[0052] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the size or aspect ratio. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0053] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying character such as "A", "a", "_1", "[i]", or "[m,n]" may be appended to the end of the symbol. For example, if there are two wirings A, one may be written as wiring A[1] and the other as wiring A[2].

[0054] (Embodiment 1) First, we will describe an example configuration of a semiconductor device 100 that includes a memory cell 10 (also called a "memory element").

[0055] Figure 1A shows a block diagram illustrating an example configuration of a semiconductor device 100 according to one aspect of the present invention. The semiconductor device 100 shown in Figure 1A includes a drive circuit 21 and a memory array 20. The memory array 20 has a plurality of memory cells 10. Figure 1A shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in an m x n matrix (where m and n are integers of 2 or more).

[0056] Note that rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction (direction along the X-axis) is defined as a "row" and the Y direction (direction along the Y-axis) is defined as a "column," but the X direction may be defined as a "column" and the Y direction as a "row."

[0057] In Figure 1A, the memory cell 10 in the 1st row and 1st column is shown as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is shown as memory cell 10[m,n]. In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the memory cell 10 in the ith row and jth column is shown as memory cell 10[i,j]. In this embodiment, when "i+α" (where α is a positive or negative integer) is used, "i+α" is not less than 1 and not greater than m. Similarly, when "j+α" is used, "j+α" is not less than 1 and not greater than n.

[0058] Furthermore, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first wiring WL (first row) is denoted as wiring WL[1], and the mth wiring WL (mth row) is denoted as wiring WL[m]. Similarly, the first wiring PL (first row) is denoted as wiring PL[1], and the mth wiring PL (mth row) is denoted as wiring PL[m]. Similarly, the first wiring BL (first column) is denoted as wiring BL[1], and the nth wiring BL (nth column) is denoted as wiring BL[n].

[0059] Multiple memory cells 10 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple memory cells 10 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0060] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0061] In semiconductor device 100, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0062] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated by the control circuit 32.

[0063] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 100. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 100 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 so that this operating mode is executed.

[0064] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0065] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0066] The row decoder 42 and column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to access, and the column decoder 44 is a circuit for specifying the column to access. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data.

[0067] The input circuit 47 has the function of holding the signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory cell 10. The data (Dout) read by the column driver 45 from the memory cell 10 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. The output circuit 48 also has the function of outputting Dout to the outside of the semiconductor device 100. The data output from the output circuit 48 is the signal RDA.

[0068] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the semiconductor device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW22 is controlled by signal PON1, and the on / off state of PSW23 is controlled by signal PON2. In Figure 1A, the number of power supply domains to which VDD is supplied in the peripheral circuit 31 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0069] The drive circuit 21 and the memory array 20 may be provided on the same plane. Alternatively, as shown in Figure 1B, the drive circuit 21 and the memory array 20 may be stacked on top of each other. By stacking the drive circuit 21 and the memory array 20, the signal propagation distance can be shortened. Furthermore, the semiconductor device 100 can be miniaturized.

[0070] <Example of memory cell configuration 1> Next, we will describe an example configuration of the memory cell 10. Figure 2 shows an example configuration of two adjacent memory cells 10 (memory cell 10a and memory cell 10b). Figure 2A is a diagram showing an example circuit configuration of two adjacent memory cells 10.

[0071] Memory cell 10a includes a transistor 120a and a capacitive element 130a. Memory cell 10b includes a transistor 120b and a capacitive element 130b. One source or drain of transistor 120a is electrically connected to wiring BL1, and the other is electrically connected to one electrode of capacitive element 130a. The gate of transistor 120a is electrically connected to wiring WL1, and the other electrode of capacitive element 130a is electrically connected to wiring PL1. One source or drain of transistor 120b is electrically connected to wiring BL1, and the other is electrically connected to one electrode of capacitive element 130b. The gate of transistor 120b is electrically connected to wiring WL2, and the other electrode of capacitive element 130b is electrically connected to wiring PL2.

[0072] For example, when memory cell 10a is memory cell 10[i,j], memory cell 10b can be represented as memory cell 10[i+1,j]. Also, when wiring WL1 is wiring WL[i], wiring WL2 can be represented as wiring WL[i+1]. Furthermore, wiring BL1 can be represented as wiring BL[j].

[0073] Furthermore, when wiring PL1 is wiring PL[i], wiring PL2 can be represented as wiring PL[i+1]. It is preferable that a fixed potential is supplied to wiring PL. Also, in this embodiment, wiring PL is assumed to extend along the X-axis, but this is not limited to this. For example, wiring PL may extend along the Y-axis. Wiring PL1 and wiring PL2 may be electrically connected.

[0074] A ferroelectric material is used as the dielectric material constituting the capacitive element 130 (such as capacitive element 130a and capacitive element 130b). The capacitive element 130 functions as a ferroelectric capacitor.

[0075] As a material that can possess ferroelectric properties, for example, hafnium oxide is preferred. Alternatively, zirconium oxide, HfZrO are also suitable as materials that can possess ferroelectric properties. XMetal oxides such as (X is a real number greater than 0. Hereinafter simply referred to as HfZrOx) can be used. Alternatively, as a material that may possess ferroelectric properties, a material obtained by adding element J1 (where element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide can be used. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate; for example, the number of hafnium atoms to element J1 atoms can be set to 1:1 or close to it. Alternatively, as a material that may possess ferroelectric properties, a material obtained by adding element J2 (where element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide can be used. Furthermore, the ratio of zirconium atoms to element J2 atoms can be set as appropriate; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to it. Also, as a material that can possess ferroelectric properties, lead titanate (PbTiO) X ), piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate may also be used.

[0076] Furthermore, aluminum scandium nitride (Al) is an example of a material that may possess ferroelectric properties. 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value in its vicinity. Hereinafter simply referred to as AlScN.)) Al-Ga-Sc nitride, Ga-Sc nitride, etc., can be used. In addition, as a material that may possess ferroelectricity, a metal nitride having element M1, element M2, and nitrogen can be used. Here, element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanides (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), actinides (15 elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectric properties even without containing element M2. Additionally, as a material that can exhibit ferroelectric properties, a material to which element M3 is added to the above metal nitride can be used. Element M3 is one or more elements selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate. Since the above metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element, such metal nitrides are sometimes called group III-V ferroelectrics, group III nitride ferroelectrics, etc.

[0077] Furthermore, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure can be used as materials that may possess ferroelectric properties.

[0078] Furthermore, a material that may possess ferroelectricity can be, for example, a mixture or compound consisting of multiple materials selected from the materials listed above. Alternatively, a material that may possess ferroelectricity can be a laminated structure consisting of multiple materials selected from the materials listed above. Incidentally, since the crystal structure or properties of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but are also called materials that may possess ferroelectricity or materials that are made to possess ferroelectricity.

[0079] As a material that can possess ferroelectric properties, hafnium oxide, or a material containing both hafnium oxide and zirconium oxide (typically HfZrOx), is suitable because it can exhibit ferroelectric properties even when processed into thin films of a few nanometers.

[0080] Alternatively, as a material that can possess ferroelectric properties, scandium aluminum nitride (AlScN) is suitable because it can be formed by sputtering, which can reduce the concentration of impurities in the film or form a dense film. When scandium aluminum nitride (AlScN) is used as a material that can possess ferroelectric properties, a highly reliable film can be expected.

[0081] Also, the film thickness of the material that can have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). For example, it is preferable that the film thickness be 8 nm or more and 12 nm or less. By setting the film thickness of the material that can have ferroelectricity as described above, it is possible to make the film thinner and achieve the expression of ferroelectricity. By forming a ferroelectric layer that can be made thinner, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitor element, and a semiconductor device can be formed by combining the capacitor element with a semiconductor element such as a miniaturized transistor. That is, it becomes easy to realize a semiconductor device with a reduced occupied area. In this specification and the like, in some cases, a material having ferroelectricity formed in layers is referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification and the like, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.

[0082] Also, when using HfZrO as the material that can have ferroelectricity X it is preferable to form a film using the atomic layer deposition (ALD: Atomic Layer Deposition) method, particularly the thermal ALD method. Also, when forming a film of a material that can have ferroelectricity using the thermal ALD method, it is suitable to use a material that does not contain a hydrocarbon (also referred to as HC). When either one or both of hydrogen and carbon are contained in the material that can have ferroelectricity, it may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, by using a precursor that does not contain a hydrocarbon, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be cited as a precursor that does not contain a hydrocarbon. In addition, as a material that can have ferroelectricity, a material having hafnium oxide and zirconium oxide (HfZrO xWhen using ), HfCl4 and / or ZrCl4 may be used as precursors. Alternatively, a dopant (typically silicon, carbon, etc.) may be added to a material that can have ferroelectric properties to control the polarization state. In this case, one method of adding carbon as a dopant may be to use a formation method in which a material containing hydrocarbons as a precursor is used.

[0083] Furthermore, when forming a film using a material capable of ferroelectricity, a film with high purity and intrinsic ferroelectricity can be formed by thoroughly eliminating impurities in the film, specifically hydrogen, hydrocarbons, and carbon. Moreover, the manufacturing process compatibility between a film with high purity and intrinsic ferroelectricity and the high purity and intrinsic oxide semiconductor shown in the embodiments described later is extremely high. Therefore, a highly productive method for manufacturing semiconductor devices can be provided.

[0084] Furthermore, it is preferable that the impurity concentration of the material capable of ferroelectricity be low. In particular, lower concentrations of hydrogen (H) and carbon (C) are preferable. Specifically, the hydrogen concentration of the material capable of ferroelectricity is 5 × 10⁻¹⁰. 20 atoms / cm 3 The following is preferable: 1 × 10 20 atoms / cm 3 The following is more preferable. Also, the carbon concentration of the material that may have ferroelectric properties is 5 × 10 19 atoms / cm 3 The following is preferable: 1 × 10 19 atoms / cm 3 The following are preferable.

[0085] Furthermore, HfZrO is a material that can possess ferroelectric properties. X When using this method, it is preferable to alternately deposit hafnium oxide and zirconium oxide in a 1:1 composition using the thermal ALD method.

[0086] Furthermore, when depositing a ferroelectric material using the thermal ALD method, H2O or O3 can be used as the oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0087] Furthermore, the crystal structure of a material that may possess ferroelectric properties is not particularly limited. For example, the crystal structure of a material that may possess ferroelectric properties may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic systems. In particular, a material that may possess ferroelectric properties is preferred if it has an orthorhombic crystal structure, as this is because ferroelectricity is exhibited in such materials. Note that a layer to enhance crystallinity may be formed before forming the material that may possess ferroelectric properties. For example, when using HfZrOx as the material that may possess ferroelectric properties, the layer to enhance crystallinity can be a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium. Also, when using AlScN as the material that may possess ferroelectric properties, it is preferable to use a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium, as the layer to enhance crystallinity. Note that the layer to enhance crystallinity may be formed after forming the material that may possess ferroelectric properties. Alternatively, the material may have ferroelectric properties and may be a composite structure having both an amorphous structure and a crystalline structure.

[0088] Ferroelectric materials can exhibit hysteresis characteristics. Figure 8 shows an example of hysteresis characteristics. Hysteresis characteristics can be measured in a capacitive device (ferroelectric capacitor) that uses a ferroelectric layer as the dielectric layer. In Figure 8, the horizontal axis shows the voltage (electric field) applied to the ferroelectric layer. This voltage is the potential difference between one electrode and the other electrode of a capacitive device that uses a ferroelectric layer as the dielectric layer. The electric field strength can be obtained by dividing this potential difference by the thickness of the ferroelectric layer.

[0089] In Figure 8, the vertical axis represents the polarization of the ferroelectric layer. A positive polarization indicates that the positive charges in the ferroelectric layer are concentrated on one electrode side of the capacitive element, and the negative charges are concentrated on the other electrode side of the capacitive element. Conversely, a negative polarization indicates that the negative charges in the ferroelectric layer are concentrated on one electrode side of the capacitive element, and the positive charges are concentrated on the other electrode side of the capacitive element.

[0090] Furthermore, the polarization shown on the vertical axis of the graph in Figure 8 may be defined as positive when the negative charge is biased towards one electrode side of the capacitive element and the positive charge is biased towards the other electrode side, and negative when the positive charge is biased towards one electrode side of the capacitive element and the negative charge is biased towards the other electrode side.

[0091] As shown in Figure 8, the hysteresis characteristics of the ferroelectric layer can be represented by curves 51 and 52. The voltages at the intersection of curves 51 and 52 are called the saturation polarization voltage VSP and the saturation polarization voltage -VSP. VSP and -VSP can be said to have different polarities.

[0092] When a voltage of -VSP or less is applied to the ferroelectric layer, and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 51. On the other hand, when a voltage of VSP or more is applied to the ferroelectric layer, and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 52. VSP is sometimes called the "positive saturation polarization voltage" or "first saturation polarization voltage," and -VSP is sometimes called the "negative saturation polarization voltage" or "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0093] Here, the voltage at which the polarization of the ferroelectric layer becomes zero as the polarization changes according to curve 51 is called the deterrent voltage Vc. Also, the voltage at which the polarization of the ferroelectric layer becomes zero as the polarization changes according to curve 52 is called the deterrent voltage -Vc. The values ​​of Vc and -Vc are between -VSP and VSP. Note that Vc is sometimes called the "positive deterrent voltage" or "first deterrent voltage," and -Vc is sometimes called the "negative deterrent voltage" or "second deterrent voltage." The absolute values ​​of the first deterrent voltage and the absolute values ​​of the second deterrent voltage may be the same or different.

[0094] Furthermore, when no voltage is applied to the ferroelectric layer (when the voltage is 0V), the maximum value of the polarization is called "residual polarization Pr," and the minimum value is called "residual polarization -Pr." The absolute value of the difference between residual polarization Pr and residual polarization -Pr is called "residual polarization 2Pr." The larger the residual polarization 2Pr, the greater the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. A larger residual polarization 2Pr is preferable.

[0095] The memory cell 10 includes a capacitive element 130, which is a ferroelectric capacitor, and a transistor 120, and has the function of storing information using the change in capacitance value due to the reversal of the polarization of the capacitive element 130. The memory cell 10 functions as a ferroelectric memory. A memory cell composed of one transistor and one ferroelectric capacitor is also called a 1T1F type memory cell.

[0096] The semiconductor layer on which the channels of transistor 120 (such as transistor 120a and transistor 120b) are formed can be a single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor, either individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0097] Furthermore, it is preferable that the transistor 120 is an oxide semiconductor (also called an "OS transistor") in which the semiconductor layer on which the channel of the transistor 120 is formed uses an oxide semiconductor, which is a type of metal oxide. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the semiconductor device 100 including the memory cell 10 can be reduced.

[0098] Furthermore, a memory cell containing an OS transistor can be called an "OS memory." Similarly, a semiconductor device 100 containing such a memory cell can also be called an "OS memory."

[0099] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, the on-current does not decrease significantly even in high-temperature environments. Therefore, OS memory operates stably even in high-temperature environments, resulting in high reliability.

[0100] Furthermore, OS transistors have high dielectric strength between the source and drain. By using an OS transistor in transistor 120, the voltage required for polarization reversal can be supplied to the capacitive element 130 even if the channel length of transistor 120 is reduced. Therefore, the occupied area of ​​the memory cell 10 can be reduced. Thus, the memory capacity and / or memory density of the semiconductor device can be increased.

[0101] Figure 2B is a perspective view showing an example configuration of two adjacent memory cells 10. In drawings and other materials, arrows indicating the X direction (direction along the X-axis), Y direction (direction along the Y-axis), and Z direction (direction along the Z-axis) may be included. In this specification, "X direction" refers to the direction along the X-axis, and the forward and reverse directions may not be distinguished. The same applies to "Y direction" and "Z direction". Furthermore, the X direction, Y direction, and Z direction are directions that intersect each other. More specifically, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, one of the X direction, Y direction, or Z direction may be called the "first direction" or "first direction". Another may be called the "second direction" or "second direction". The remaining one may be called the "third direction" or "third direction". In Figure 2 and other diagrams, the direction in which wiring WL extends is defined as the X direction, and the direction in which wiring BL extends is defined as the Y direction.

[0102] Figure 2C is a top view of the configuration example shown in Figure 2B. Figure 2D is a front view of the configuration example shown in Figure 2B, viewed in the X direction. In the configuration example shown in Figure 2, the two memory cells 10 are provided on the transistor layer 151, the first capacitance layer 152, and the second capacitance layer 153. The first capacitance layer 152 is provided on the transistor layer 151, and the second capacitance layer 153 is provided on the first capacitance layer 152.

[0103] Furthermore, transistors 120a and 120b are provided in the transistor layer 151. Capacitive element 130b is provided in the first capacitance layer 152. Capacitive element 130a is provided in the second capacitance layer 153.

[0104] Figure 3A is a top view of the transistor layer 151 as seen in the Z direction. Figure 3B is a top view of the first capacitance layer 152 as seen in the Z direction. Figure 3C is a top view of the second capacitance layer 153 as seen in the Z direction.

[0105] The region where semiconductor Sem1 and wiring WL1 overlap functions as the channel formation region of transistor 120a. Similarly, the region where semiconductor Sem1 and wiring WL2 overlap functions as the channel formation region of transistor 120b. The region of semiconductor Sem1 that does not overlap with either wiring WL1 or wiring WL2 functions as either the source or the drain. Therefore, wiring WL1 functions as the gate of transistor 120a, and wiring WL2 functions as the gate of transistor 120b.

[0106] One of the sources or drains of transistors 120a and 120b is electrically connected to wiring BL1 via conductor 141. The other source or drain of transistor 120a is electrically connected to capacitive element 130a via conductor 142a. The other source or drain of transistor 120b is electrically connected to capacitive element 130b via conductor 142b.

[0107] Furthermore, the capacitive element 130a is electrically connected to the wiring PL1 via the conductor 143a. The capacitive element 130b is electrically connected to the wiring PL2 via the conductor 143b.

[0108] As shown in Figures 2B to 2D, the capacitive elements 130a and 130b are arranged on different layers. That is, when viewed from the Z direction, the capacitive elements 130a and 130b have overlapping regions. By arranging the capacitive elements 130a and 130b on top of the transistors 120a and 120b, the area of ​​the capacitive elements 130 can be increased without increasing the area occupied by the memory cell 10.

[0109] For example, in the configuration shown in Figure 2, since memory cells 10a and 10b are adjacent in the Y direction, capacitive elements 130a and 130b can be extended in the Y direction. Therefore, the reliability of memory cell 10 can be increased without reducing the integration density of memory cell 10. Thus, the reliability of the storage device including memory cell 10 can be increased.

[0110] Furthermore, it is preferable that the residual polarization of capacitive element 130a and the residual polarization of capacitive element 130b are equal. By aligning the residual polarizations, variations in write and read characteristics between memory cells are reduced, resulting in reduced power consumption and improved reliability.

[0111] Furthermore, it is preferable that the capacitance value of capacitive element 130a and the capacitance value of capacitive element 130b are equal. By matching the capacitance values, variations in characteristics between memory cells are reduced, which can lead to reduced power consumption and improved reliability.

[0112] <Example of memory cell configuration 2> In Memory Cell Configuration Example 1, a configuration in which two layers of capacitive elements 130 are stacked is shown, but the present invention is not limited to this. Figures 4 and 5 show a configuration example in which three layers of capacitive elements 130 of four adjacent memory cells 10 are stacked.

[0113] Figure 4 shows an example configuration of four adjacent memory cells 10 (memory cell 10a, memory cell 10b, memory cell 10c, and memory cell 10d). Figure 4A is a perspective view showing an example configuration of four adjacent memory cells 10. Figure 4B is a view (front view) of the configuration example shown in Figure 4A, viewed in the X direction. Figure 4C shows an example circuit configuration of four adjacent memory cells 10.

[0114] In Figure 4C, the circuit configurations of memory cells 10a and 10b are the same as those described in Figure 2A. Memory cell 10c includes a transistor 120c and a capacitive element 130c. Memory cell 10d includes a transistor 120d and a capacitive element 130d. One source or drain of transistor 120c is electrically connected to wiring BL2, and the other is electrically connected to one electrode of capacitive element 130c. The gate of transistor 120c is electrically connected to wiring WL1, and the other electrode of capacitive element 130c is electrically connected to wiring PL3. One source or drain of transistor 120d is electrically connected to wiring BL2, and the other is electrically connected to one electrode of capacitive element 130d. The gate of transistor 120d is electrically connected to wiring WL2, and the other electrode of capacitive element 130d is electrically connected to wiring PL4.

[0115] For example, when memory cell 10a is memory cell 10[i,j], memory cell 10b can be represented as memory cell 10[i+1,j]. Also, memory cell 10c can be represented as memory cell 10[i,j+1]. Also, memory cell 10d can be represented as memory cell 10[i+1,j+1]. Also, when wiring WL1 is wiring WL[i], wiring WL2 can be represented as wiring WL[i+1]. Also, when wiring BL1 is wiring BL[j], wiring BL2 can be represented as wiring BL[j+1]. Furthermore, wirings PL1, PL2, PL3, and PL4 may be electrically connected.

[0116] In the configuration examples shown in Figures 4A and 4B, the transistors 120 included in the four memory cells 10 are provided on the transistor layer 151, and the capacitive elements 130 are provided on either the first capacitive layer 152, the second capacitive layer 153, or the third capacitive layer 154. The first capacitive layer 152 is provided on the transistor layer 151, the second capacitive layer 153 is provided on the first capacitive layer 152, and the third capacitive layer 154 is provided on the second capacitive layer 153.

[0117] More specifically, transistors 120a, 120b, 120c, and 120d are provided in the transistor layer 151. Capacitor element 130b is provided in the first capacitance layer 152. Capacitor element 130a is provided in the second capacitance layer 153. Capacitor elements 130c and 130d are provided in the third capacitance layer 154.

[0118] Although not shown in Figure 4, the capacitive elements 130a to 130d are provided on an insulator (insulating layer). Furthermore, capacitive elements 130c and 130d are provided on the same insulating layer, while capacitive elements 130a and 130b are provided on different insulating layers.

[0119] Figure 5A is a top view of the transistor layer 151 as seen in the Z direction. Figure 5B is a top view of the first capacitance layer 152 as seen in the Z direction. Figure 5C is a top view of the second capacitance layer 153 as seen in the Z direction. Figure 5D is a top view of the third capacitance layer 154 as seen in the Z direction.

[0120] The region where semiconductor Sem1 and wiring WL1 overlap functions as the channel formation region of transistor 120a. Similarly, the region where semiconductor Sem1 and wiring WL2 overlap functions as the channel formation region of transistor 120b. The region of semiconductor Sem1 that does not overlap with either wiring WL1 or wiring WL2 functions as either the source or the drain. Therefore, wiring WL1 functions as the gate of transistor 120a, and wiring WL2 functions as the gate of transistor 120b.

[0121] The region where semiconductor Sem2 and wiring WL1 overlap functions as the channel formation region of transistor 120c. Similarly, the region where semiconductor Sem2 and wiring WL2 overlap functions as the channel formation region of transistor 120d. The region of semiconductor Sem2 that does not overlap with either wiring WL1 or wiring WL2 functions as either the source or the drain. Therefore, wiring WL1 functions as the gate of transistor 120c, and wiring WL2 functions as the gate of transistor 120d.

[0122] One source or drain of transistors 120a and 120b is electrically connected to wiring BL1 via conductor 141a. The other source or drain of transistor 120a is electrically connected to capacitive element 130a via conductor 142a. The other source or drain of transistor 120b is electrically connected to capacitive element 130b via conductor 142b.

[0123] Furthermore, the capacitive element 130a is electrically connected to the wiring PL1 via the conductor 143a. The capacitive element 130b is electrically connected to the wiring PL2 via the conductor 143b.

[0124] One of the sources or drains of transistors 120c and 120d is electrically connected to wiring BL2 via conductor 141b. The other source or drain of transistor 120a is electrically connected to capacitive element 130c via conductor 142c. The other source or drain of transistor 120d is electrically connected to capacitive element 130d via conductor 142d.

[0125] Furthermore, the capacitive element 130c is electrically connected to the wiring PL3 via the conductor 143c. The capacitive element 130d is electrically connected to the wiring PL4 via the conductor 143d.

[0126] As shown in Figures 4 and 5, the area of ​​the capacitive elements can be increased by stacking the capacitive elements of memory cells 10a, 10b, 10c, and 10d. In memory cell configuration example 1, the capacitive elements 130 can be expanded in the Y direction, but in the configuration disclosed in memory cell configuration example 2, they can be expanded not only in the Y direction but also in the X direction. Therefore, in the configuration disclosed in memory cell configuration example 2, the area of ​​the capacitive elements 130 can be increased even further than in the configuration disclosed in memory cell configuration example 1.

[0127] In addition, in memory cell configuration example 2, four capacitive elements 130 are provided in the first to third capacitive layers. Therefore, two of the four capacitive elements 130 (capacitive element 130c and capacitive element 130d) are provided in the same capacitive layer.

[0128] Therefore, in memory cell configuration example 2, when viewed from the Z direction, three of the four capacitance elements 130 have overlapping regions. Figure 5E shows the four capacitance elements 130 as viewed from the third capacitance layer 154 side in the Z direction. In region 901, parts of capacitance elements 130a, 130b, and 130c overlap. In region 902, parts of capacitance elements 130a, 130b, and 130d overlap.

[0129] The configuration disclosed in Memory Cell Configuration Example 2 allows for an increase in the area of ​​the capacitive element 130 compared to the configuration disclosed in Memory Cell Configuration Example 1. Therefore, the reliability of the memory device can be further improved.

[0130] <Example of memory cell configuration 3> Figures 6 and 7 show an example configuration in which four layers of capacitive elements 130 of four adjacent memory cells 10 are stacked. To avoid repetition, we will mainly explain the differences from the previously mentioned configuration example.

[0131] Figure 6 shows an example configuration of four adjacent memory cells 10 (memory cell 10a, memory cell 10b, memory cell 10c, and memory cell 10d). Figure 6A is a perspective view showing an example configuration of four adjacent memory cells 10. Figure 6B is a front view of the configuration example shown in Figure 6A, viewed in the X direction. Figure 6C shows an example circuit configuration of four adjacent memory cells 10.

[0132] The circuit configuration example shown in Figure 6C is substantially the same as the circuit configuration example shown in Figure 4C, except that the other electrode of the capacitive element 130c is electrically connected to the wiring PL1, and the other electrode of the capacitive element 130d is electrically connected to the wiring PL2.

[0133] In the configuration example shown in Figures 6A and 6B, the transistors 120 included in the four memory cells 10 are provided on the transistor layer 151, and the capacitive elements 130 are provided on either the first capacitive layer 152, the second capacitive layer 153, the third capacitive layer 154, or the fourth capacitive layer 155. The first capacitive layer 152 is provided on the transistor layer 151, the second capacitive layer 153 is provided on the first capacitive layer 152, the third capacitive layer 154 is provided on the second capacitive layer 153, and the fourth capacitive layer 155 is provided on the third capacitive layer 154.

[0134] More specifically, transistors 120a, 120b, 120c, and 120d are provided in the transistor layer 151. Capacitor element 130b is provided in the first capacitance layer 152. Capacitor element 130a is provided in the second capacitance layer 153. Capacitor element 130d is provided in the third capacitance layer 154. Capacitor element 130c is provided in the fourth capacitance layer 155.

[0135] Although not shown in Figure 6, each of the capacitive elements 130a to 130d is provided on a different insulator (insulating layer).

[0136] Figure 7A is a top view of the transistor layer 151 as seen in the Z direction. Figure 7B is a top view of the first capacitance layer 152 as seen in the Z direction. Figure 7C is a top view of the second capacitance layer 153 as seen in the Z direction. Figure 7D is a top view of the third capacitance layer 154 as seen in the Z direction. Figure 7E is a top view of the fourth capacitance layer 155 as seen in the Z direction.

[0137] The connection configuration of transistor 120, capacitive element 130, conductor 142, and conductor 143 is generally the same as that shown in Configuration Example 2, but differs in that wiring PL3 and PL4 are absent, and the arrangement of conductors 143a and conductor 143b when viewed from the Z direction is different. Also, because wiring PL3 and PL4 are absent, capacitive element 130c is electrically connected to wiring PL1 via conductor 143c. Capacitive element 130d is electrically connected to wiring PL2 via conductor 143d. Wiring PL1 and PL2 are provided above capacitive element 130c.

[0138] As shown in Figures 6 and 7, the area of ​​the capacitive elements can be increased by stacking the capacitive elements of memory cells 10a, 10b, 10c, and 10d. In memory cell configuration example 3, the number of wirings can be reduced compared to the configuration disclosed in memory cell configuration example 2. Furthermore, in memory cell configuration example 3, the capacitive elements 130 can be extended further in the Y direction than in the configuration disclosed in memory cell configuration example 2. Therefore, in the configuration disclosed in memory cell configuration example 3, the area of ​​the capacitive elements 130 can be increased compared to the configuration disclosed in memory cell configuration example 2.

[0139] Furthermore, in memory cell configuration example 3, when viewed from the Z direction, each of the four capacitive elements 130 has a region that overlaps with the others. Figure 7F shows the four capacitive elements 130 as viewed from the fourth capacitive layer 155 side in the Z direction. In region 911, parts of capacitive elements 130a, 130b, 130c, and 130d overlap.

[0140] By increasing the number of adjacent memory cells 10 and stacking the respective capacitive elements 130, the area of ​​the capacitive elements 130 can be increased. Therefore, the reliability of the memory device can be further improved.

[0141] This embodiment can be appropriately combined with other embodiments shown herein.

[0142] (Embodiment 2) In this embodiment, an example of a transistor configuration will be described as an example of a semiconductor device.

[0143] <Example of semiconductor device configuration> Figure 9A is a top view of transistor 200, which can be used in transistors 120a and 120b, etc. Figures 9B to 9D are cross-sectional views of the same transistor. Here, Figure 9B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 9A, and is also a cross-sectional view of transistor 200 in the channel length direction. Figure 9C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 9A, and is also a cross-sectional view of transistor 200 in the channel width direction. Figure 9D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 9A. Note that some elements have been omitted from the top view of Figure 9A for clarity.

[0144] The transistor 200 includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on an insulator 275 provided on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulator 283 and the insulator 274. The insulators 212, 214, 216, 275, 280, 282, 283, 285, and 274 function as interlayer films. Furthermore, the insulator 283 is in contact with the sides of insulator 214, the sides of insulator 216, the sides of insulator 222, the sides of insulator 275, the sides of insulator 280, and the sides and top surface of insulator 282.

[0145] The transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 214 and / or insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and a conductor on the oxide 230b. The device comprises a conductive body 242b, an insulator 271b on the conductive body 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductive body 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with a portion of the oxide 230b, and an insulator 275 arranged on the insulators 222, 224, oxide 230a, oxide 230b, conductive body 242a, conductive body 242b, insulator 271a, and insulator 275. Here, as shown in Figures 9B and 9C, insulator 252 is in contact with the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and top surface of oxide 230b, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. The top surface of conductor 260 is positioned so as to be roughly the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Insulator 282 is in contact with at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0146] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242. Furthermore, insulators 271a and 271b may be collectively referred to as insulator 271.

[0147] Insulators 280 and 275 are provided with openings that reach oxide 230b. Insulators 252, 250, 254, and 260 are arranged within these openings. In addition, in the channel length direction of transistor 200, conductors 260, 252, 250, and 254 are provided between insulators 271a and conductor 242a, and between insulators 271b and conductor 242b. Insulator 254 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0148] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0149] In the transistor 200, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0150] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulators 252, 250, and 254 function as the first gate insulators, and insulators 222 and 224 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0151] Here, an enlarged view of the vicinity of the channel formation region in Figure 9B is shown in Figure 10A. When oxygen is supplied to the oxide 230b, a channel formation region is formed in the region between the conductors 242a and 242b. Therefore, as shown in Figure 10A, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich region 230bc and function as the source region or drain region. At least a portion of region 230bc is superimposed on the conductor 260. In other words, region 230bc is provided in the region between the conductors 242a and 242b. Region 230ba is provided superimposed on the conductor 242a, and region 230bb is provided superimposed on the conductor 242b.

[0152] Region 230bc, which functions as a channel-forming region, is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations than regions 230ba and 230bb. Therefore, region 230bc can be said to be type i (intrinsic) or substantially type i. Region 230bc is easily formed, for example, by microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using a device that has a power supply that generates a high-density plasma using microwaves. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0153] Furthermore, regions 230ba and 230bb, which function as source or drain regions, are regions with high oxygen deficiencies or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, resulting in increased carrier concentration and low resistance. In other words, regions 230ba and 230bb are n-type regions with higher carrier concentration and lower resistance compared to region 230bc.

[0154] Here, the carrier concentration in region 230bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 1017 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 230bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0155] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 230ba and 230bb, and equal to or greater than that of region 230bc.

[0156] Although Figure 10A shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0157] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0158] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0159] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0160] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0161] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0162] In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed.

[0163] Furthermore, because oxides 230a and 230b share a common element other than oxygen (as a main component), the defect level density at the interface between oxide 230a and oxide 230b can be reduced. Because the defect level density at the interface between oxide 230a and oxide 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0164] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0165] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen deficiencies (V)). O It is a metal oxide with few impurities (e.g., 400°C to 600°C). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0166] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0167] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). OSometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0168] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0169] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0170] Therefore, with the conductors 242a and 242b placed on the oxide 230b, microwave treatment was performed in an oxygen-containing atmosphere to remove oxygen vacancies in region 230bc, and V OIt is preferable to reduce H.

[0171] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen H is removed from region 230bc, and oxygen is lost V. O It can be supplemented with oxygen. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V O This can reduce H and lower the carrier concentration.

[0172] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effects of oxygen plasma can be reduced by insulators 271 and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0173] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 252, or after the deposition of the insulating film that will become the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 252 or insulator 250 in this way, oxygen can be efficiently injected into region 230bc. In addition, by arranging the insulator 252 in contact with the side surface of the conductor 242 and the surface of region 230bc, the injection of more oxygen than necessary into region 230bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 242. Furthermore, oxidation of the side surface of the conductor 242 can be suppressed when the insulating film that will become the insulator 250 is deposited.

[0174] Furthermore, the oxygen injected into region 230bc can take various forms, including oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferred. Additionally, the film quality of insulators 252 and 250 can be improved, thereby enhancing the reliability of transistor 200.

[0175] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0176] Furthermore, as shown in Figure 9C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0177] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0178] It is preferable that oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used in oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used in oxide 230a.

[0179] Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0180] Here, at the junction of oxide 230a and oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b.

[0181] Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0182] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, In:M:Zn = 1:1:2 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0183] Here, oxides 230a and 230b are preferably formed using a sputtering method. Oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the amount of oxygen in the deposited film can be increased. Note that the method for depositing oxides 230a and 230b is not limited to sputtering; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0184] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0185] Furthermore, as shown in Figure 9C and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 230, particularly oxide 230b, the field-effect mobility of the transistor 200 can be improved.

[0186] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0187] It is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0188] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0189] For insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, and 283, it is preferable to use silicon nitride, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 282, and 285, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 285 towards the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., towards the substrate side via the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0190] In this specification, "oxide nitride" refers to a material in which the oxygen content is higher than the nitrogen content as the main component. For example, "silicon oxide nitride" refers to a material containing silicon, nitrogen, and oxygen in which the oxygen content is higher than the nitrogen content. Also, in this specification, "nitride oxide" refers to a material in which the nitrogen content is higher than the oxygen content as the main component. For example, "aluminum oxide nitride" refers to a material containing aluminum, nitrogen, and oxygen in which the nitrogen content is higher than the oxygen content.

[0191] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0192] Furthermore, while insulators 212, 214, 271, 275, 282, 283, and 285 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0193] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. Note that the deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0194] Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, and 283. For example, the resistivity of insulators 212, 275, and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, and 283 may be able to mitigate charge-up of conductors 205, 242, or 260 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0195] Furthermore, it is preferable that insulators 216, 274, 280, and 285 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216, 274, 280, and 285 as appropriate.

[0196] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205 may be embedded in the insulator 214.

[0197] The conductor 205 comprises a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately equal to the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0198] Here, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0199] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 205a. For example, titanium nitride can be used for the conductor 205a.

[0200] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0201] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0202] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0203] Furthermore, as shown in Figure 9A, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 9C, it is preferable that the conductor 205 extends to the region outside the edges of the oxide 230a and oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface of the oxide 230 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0204] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0205] Furthermore, as shown in Figure 9C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0206] In the transistor 200, the conductor 205 is shown as a stacked structure of conductor 205a and conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or as a stacked structure of three or more layers.

[0207] Insulators 222 and 224 function as gate insulators.

[0208] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0209] The insulator 222 may be an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, an oxide containing hafnium and zirconium, such as hafnium-zirconium oxide, is preferred. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0210] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0211] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 222.

[0212] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0213] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment while the surface of the oxide 230 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0214] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0215] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island shape by being superimposed with the oxide 230a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0216] Conductors 242a and 242b are provided in contact with the upper surface of oxide 230b. Conductors 242a and 242b function as the source electrode or drain electrode of transistor 200, respectively.

[0217] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0218] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0219] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 9D. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0220] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. It is preferable that the insulator 271 functions as at least a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, an insulator such as aluminum oxide or magnesium oxide may be used.

[0221] The insulator 275 is provided so as to cover the insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271. Preferably, the insulator 275 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 275 includes silicon nitride or an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 275.

[0222] By providing the insulators 271 and 275 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase its resistivity and reduce the on-current.

[0223] The insulator 252 functions as part of the gate insulator. Preferably, the insulator 252 is a barrier insulating film against oxygen. The insulator 252 can be any insulator that can be used for the insulator 282 described above. The insulator 252 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0224] As shown in Figure 9C, the insulator 252 is provided in contact with the top and side surfaces of oxide 230b, the side surface of oxide 230a, the side surface of insulator 224, and the top surface of insulator 222. In other words, the regions of oxide 230a, oxide 230b, and insulator 224 that overlap with the conductor 260 are covered by the insulator 252 in the cross-section in the channel width direction. This allows the insulator 252, which has an oxygen barrier property, to block the desorption of oxygen from oxide 230a and oxide 230b during heat treatment, etc. Thus, the formation of oxygen vacancies (Vo) in oxide 230a and oxide 230b can be reduced. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0225] Conversely, even if an excess amount of oxygen is present in the insulator 280 and insulator 250, it is possible to suppress the excessive supply of such oxygen to oxides 230a and 230b. Therefore, it is possible to suppress the excessive oxidation of regions 230ba and 230bb via region 230bc, which would otherwise cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility.

[0226] Furthermore, as shown in Figure 9B, the insulator 252 is provided in contact with the sides of the conductor 242, insulator 271, insulator 275, and insulator 280. Therefore, oxidation of the side surface of the conductor 242 and the formation of an oxide film on that side surface can be reduced. This makes it possible to suppress a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0227] Furthermore, the insulator 252, along with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 252 be thin. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 252 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 252 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0228] To deposit the insulator 252 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0229] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 252 can be deposited with good coverage on the sides of openings formed in the insulator 280, etc., with the thin film thickness described above.

[0230] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0231] The insulator 250 functions as part of the gate insulator. It is preferable that the insulator 250 is placed in contact with the upper surface of the insulator 252. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are stable with respect to heat. In this case, the insulator 250 will be an insulator having at least oxygen and silicon.

[0232] Similar to the insulator 224, it is preferable that the insulator 250 has a reduced concentration of impurities such as water and hydrogen. The film thickness of the insulator 250 is preferably 1 nm to 20 nm, and more preferably 0.5 nm to 15.0 nm. In this case, it is sufficient that the insulator 250 has a region with the above-mentioned film thickness in at least a portion of it.

[0233] Figures 9A to 9D show a configuration in which the insulator 250 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 10B, the insulator 250 may be a laminated structure of two layers: an insulator 250a and an insulator 250b on top of the insulator 250a.

[0234] As shown in Figure 10B, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulator 250a may be made using a material that can be used for the insulator 250 as described above, and the insulator 250b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b is an insulator having at least oxygen and hafnium. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 250b has at least a portion of the above-mentioned film thickness region.

[0235] Furthermore, when silicon oxide or silicon oxynitride is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to make the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator thinner. Thus, the dielectric breakdown voltage of insulator 250 can be increased.

[0236] The insulator 254 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and oxide 230b. The insulator 254 can be any insulator that can be used for the insulator 283 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0237] Furthermore, the insulator 254 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250 into the conductor 260.

[0238] Furthermore, the insulator 254, along with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 254 be thin. The film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 254 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0239] The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 9B and 9C, the top surface of the conductor 260 is roughly coincided with the top surface of the insulator 250. In Figures 9B and 9C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0240] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0241] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0242] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0243] In the transistor 200, the conductor 260 is self-alignedly formed so as to fill an opening formed in an insulator 280 or the like. By forming the conductor 260 in this manner, it is possible to surely arrange the conductor 260 in the region between the conductors 242a and 242b without alignment.

[0244] Also, as shown in FIG. 9C, in the channel width direction of the transistor 200, when the bottom surface of the insulator 222 is used as a reference, the height of the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 230b via an insulator 250 or the like, it becomes easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b, when the bottom surface of the insulator 222 is used as a reference, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0245] The insulator 280 is provided on the insulator 275, and an opening is formed in the region where the insulator 250 and the conductor 260 are provided. Also, the upper surface of the insulator 280 may be planarized.

[0246] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably provided using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen that desorbs by heating.

[0247] The insulator 280 preferably has an excess oxygen region or contains excess oxygen. Also, it is preferable that the impurity concentrations such as water and hydrogen in the insulator 280 are reduced. For example, the insulator 280 may be appropriately formed of silicon oxide, silicon oxynitride, etc. By providing an insulator having excess oxygen in contact with the oxide 230, the oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved. The insulator 280 containing excess oxygen can be formed by forming a film of the insulator 280 by a sputtering method in an oxygen-containing atmosphere. Also, by using a sputtering method in which hydrogen need not be used as the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. Further, an insulator 282 in contact with the upper surface of the insulator 280 may be formed by a sputtering method in an oxygen-containing atmosphere to add oxygen to the insulator 280. When oxygen is added to the insulator 280 by forming the film of the insulator 282, the film-forming method of the insulator 280 is not limited to the sputtering method, and CVD method, MBE method, PLD method, ALD method, etc. may be appropriately used. Also, for example, the insulator 280 may have a laminated structure of silicon oxide formed by a sputtering method and silicon oxynitride formed by a CVD method laminated thereon. Further, silicon nitride may be laminated thereon.

[0248] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 282 will be an insulator having at least oxygen and aluminum. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 282 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0249] The insulator 282 is preferably formed using a sputtering method. By depositing the insulator 282 using a sputtering method, oxygen can be added to the insulator 280. However, the method for depositing the insulator 282 is not limited to sputtering, and CVD, MBE, PLD, ALD, etc. may be used as appropriate.

[0250] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 283, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0251] Figure 9 also shows a conductor 240 (conductor 240a and conductor 240b) connected to the transistor 200. The conductor 240 is provided to fill the openings formed in the insulators 271, 275, 280, 282, 283, and 285. The lower surface of conductor 240a is in contact with the upper surface of conductor 242a. The lower surface of conductor 240b is in contact with the upper surface of conductor 242b. It is preferable that the conductor 240 is made of a conductive material mainly composed of tungsten, copper, or aluminum. Alternatively, the conductor 240 may have a laminated structure consisting of a thin first conductor provided along the side and bottom surfaces of the opening, and a second conductor on the first conductor.

[0252] When the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor placed near the insulators 285 and 280. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above the insulator 283 into the oxide 230 through the conductor 240. As for the second conductor, conductive materials mainly composed of tungsten, copper, or aluminum as described above may be used.

[0253] Although Figure 9B shows a configuration in which the conductor 240 consists of a first conductor and a second conductor stacked together, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a stacked structure of three or more layers.

[0254] Furthermore, it is preferable that an insulator 241a, which functions as a barrier insulating film, is provided between the conductor 240a and the insulator 280. It is also preferable that an insulator 241b, which functions as a barrier insulating film, is provided between the conductor 240b and the insulator 280. It is preferable that the insulator 241 (insulators 241a and 241b) is arranged in contact with the side surfaces of the openings formed in insulators 271, 275, 280, 282, 283, and 285.

[0255] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0256] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0257] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0258] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0259] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0260] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0261] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0262] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0263] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0264] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0265] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0266] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may also be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may also be used. Further, indium gallium zinc oxide containing nitrogen may also be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0267] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.

[0268] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Further, in addition to them, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0269] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is sometimes permissible to use a combination of multiple of the aforementioned elements as element M.

[0270] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0271] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 11A. Figure 11A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0272] As shown in Figure 11A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0273] The structure within the thick frame shown in Figure 11A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0274] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 11B may simply be referred to as the XRD spectrum in this specification. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0275] In Figure 11B, the horizontal axis represents 2θ [deg.] and the vertical axis represents intensity [au]. As shown in Figure 11B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ = 31°. As shown in Figure 11B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0276] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 11C. Figure 11C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0277] As shown in Figure 11C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0278] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 11A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0279] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0280] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0281] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0282] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0283] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0284] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0285] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0286] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0287] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0288] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0289] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0290] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0291] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0292] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0293] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0294] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0295] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0296] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0297] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0298] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0299] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0300] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0301] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0302] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0303] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0304] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0305] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0306] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the concentrations of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are measured in 2 × 10⁻¹⁰ units. 18atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0307] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0308] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0309] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , still more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0310] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0311] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the above-described metal oxides. As the oxide 230, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0312] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0313] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0314] As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0315] This embodiment can be appropriately combined with other embodiments shown herein.

[0316] (Embodiment 3) In this embodiment, an example of a semiconductor device according to one aspect of the present invention will be described with reference to Figure 12.

[0317] [Example of semiconductor device configuration] Figure 12 shows an example of a cross-sectional configuration of a semiconductor device (memory device) according to one aspect of the present invention. Figure 12 is a cross-sectional view showing a part of a semiconductor device 100 using memory cell configuration example 1 in a memory array 20.

[0318] The semiconductor device shown in Figure 12 has transistors 120a and 120b provided above transistor 300, which is located in the drive circuit 21. Capacitive elements 130a and 130b are also provided above transistors 120a and 120b. Transistor 120a can be the same as transistor 200 described in the previous embodiment. For example, transistor 120a shown in Figure 12 has a configuration in which insulators 241b and 241b are removed from transistor 200 shown in Figure 9. Transistor 120b can be the same as transistor 200 described in the previous embodiment. For example, transistor 120b shown in Figure 12 has a configuration in which insulators 241a and 241a are removed from transistor 200 shown in Figure 9.

[0319] Furthermore, in Figure 12, transistors 120a and 120b are provided on a single oxide 230. In Figure 12, the conductor 240b that is electrically connected to transistor 120a is omitted. Also, in Figure 12, the conductor 240a that is electrically connected to transistor 120b is omitted.

[0320] The insulator 228, which functions as the dielectric of the capacitive element 130a, and the insulator 234, which functions as the dielectric of the capacitive element 130b, are made of ferroelectric materials that exhibit polarization when an external electric field is applied, and the polarization remains even when the electric field is removed. This makes it possible to form a non-volatile memory element using these capacitive elements. In other words, a 1-transistor, 1-capacitor type ferroelectric memory can be formed using a capacitive element that functions as a ferroelectric capacitor and a transistor.

[0321] Transistors 120a and 120b are OS transistors. OS transistors have the characteristic of high voltage resistance. Therefore, even if transistors 120a and 120b are miniaturized, high voltage can be applied to them. By miniaturizing transistors 120a and 120b, the occupied area of ​​the semiconductor device can be reduced.

[0322] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0323] In Figure 12, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0324] Note that the transistor 300 shown in Figure 12 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0325] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0326] For example, on transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have conductors 328 and 330 embedded in them, which are electrically connected to transistors 120a and 120b. Conductors 328 and 330 function as contact plugs or wiring.

[0327] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0328] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 12, insulators 350, 352, and 354 are sequentially stacked on the insulator 326 and the conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a contact plug or wiring.

[0329] An insulator 357 is provided on the insulator 354 and the conductor 356, and a conductor 359 is provided on the insulator 357. The conductor 359 corresponds to the wiring BL shown in the above embodiment. A conductor 358 is embedded in the insulator 357. The conductor 358 functions as a contact plug or wiring. The conductor 359 and the conductor 356 are electrically connected via the conductor 358.

[0330] An insulator 361 is provided on the conductor 359, and transistors 120a and 120b are provided above the insulator 361. The conductor 260 corresponds to the wiring WL shown in the above embodiment. The conductor 359 is electrically connected to the oxide 230 via the conductor 141. The conductor 141 functions as a contact plug or wiring. In contact with the side surface of the conductor 141, which functions as a contact plug, an insulator 241 is provided, similar to the conductor 240 shown in the above embodiment.

[0331] Furthermore, a conductor 233 is provided on the insulator 285 and the conductor 240b. The conductor 233 is electrically connected to the transistor 120b via the conductor 240b. An insulator 234 is provided on the conductor 233, and a conductor 235 is provided on the insulator 234. The region where the conductor 233 and the conductor 235 overlap via the insulator 234 functions as a capacitive element 130b.

[0332] It is preferable to use a ferroelectric material for the insulator 234. By using a ferroelectric material for the insulator 234, the capacitive element 130b can function as a ferroelectric capacitor. In addition, insulators 236, 237, 238, and 239 are provided covering the conductor 235.

[0333] Conductors 225 are provided embedded in insulators 234, 236, 237, 238, and 239. Conductors 225 function as contact plugs or wiring. Conductors 225 are electrically connected to conductor 240a. Conductors 226 are also provided embedded in insulators 236, 237, 238, and 239. Conductors 226 function as contact plugs or wiring. Conductors 226 are electrically connected to conductor 235.

[0334] Furthermore, a conductor 227 is provided on the insulator 239 and the conductor 225. The conductor 227 is electrically connected to the transistor 120a via the conductors 225 and 240a. An insulator 228 is provided on the conductor 227, and a conductor 229 is provided on the insulator 228. The region where the conductors 229 and 227 overlap via the insulator 228 functions as a capacitive element 130a.

[0335] It is preferable to use a ferroelectric material for the insulator 228. By using a ferroelectric material for the insulator 228, the capacitive element 130b can function as a ferroelectric capacitor. In addition, insulators 243, 244, and 247 are provided covering the conductor 229.

[0336] Conductors 249 are provided embedded in insulators 247, 244, 243, and 228. Conductors 249 function as contact plugs or wiring. Conductors 249 are electrically connected to conductor 235 via conductor 226. Conductors 248 are also provided embedded in insulators 247, 244, and 243. Conductors 248 function as contact plugs or wiring. Conductors 248 are electrically connected to conductor 229.

[0337] Furthermore, a conductor 256 is provided on top of the conductor 248 and the insulator 247. Conductor 256 is electrically connected to conductor 229 via conductor 248. Also, a conductor 257 is provided on top of the conductor 249 and the insulator 247. Conductor 257 is electrically connected to conductor 235 via conductor 249 and conductor 226. Conductors 256 and 257 function as wiring PLs.

[0338] Furthermore, insulators 258a, 258b, and 261 may be provided to cover the conductors 256 and 257. Preferably, at least one of insulators 258a or 258b is an insulating film that has barrier properties against hydrogen. As the insulating film that has barrier properties against hydrogen, a barrier insulating film that can be used for the above-mentioned insulator 283, etc., may be used. By providing such a barrier insulating film, the diffusion of impurities such as hydrogen contained in the insulator 261, etc., into the transistor 200 via the conductors 256 and 257, etc. can be reduced.

[0339] The insulator 258a can be deposited using the sputtering method. For example, silicon nitride deposited by the sputtering method can be used as the insulator 258a. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of the insulator 258a can be reduced.

[0340] The insulator 258b is preferably deposited using the ALD method, particularly the PEALD method. For example, silicon nitride deposited by the PEALD method can be used as the insulator 258b. This allows for good coverage of the insulator 258b, so even if pinholes or gaps are formed in the insulator 258a due to unevenness in the substrate, covering them with the insulator 258b reduces the diffusion of hydrogen into the transistor 200.

[0341] However, the film deposition method for insulators 258a and 258b is not limited to sputtering and ALD; CVD, MBE, PLD, etc., can also be used as appropriate. Furthermore, although a two-layer structure of insulators 258a and 258b is shown above, the present invention is not limited to this, and a single-layer structure or a laminated structure of three or more layers may also be used.

[0342] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0343] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0344] For example, it is preferable that insulators 361, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0345] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0346] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0347] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0348] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 141, 256, and 257, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance. Furthermore, the capacitive element 130, which functions as a ferroelectric capacitor, can have its residual polarization increased without performing high-temperature baking after formation by depositing conductors 229 and 235 using a method involving substrate heating, such as thermal ALD. Therefore, semiconductor devices can be manufactured without high-temperature baking, allowing the use of low-resistance conductive materials such as copper with a low melting point.

[0349] <Capacitive element> Conductor 229 functions as the upper electrode of capacitive element 130a, conductor 227 functions as the lower electrode of capacitive element 130a, and insulator 228 functions as the dielectric of capacitive element 130a. Conductor 235 functions as the upper electrode of capacitive element 130b, conductor 233 functions as the lower electrode of capacitive element 130b, and insulator 234 functions as the dielectric of capacitive element 130b.

[0350] As insulators 228 and 234, materials capable of ferroelectricity as described in the above embodiment are used. Insulators 228 and 234 may be laminates of multiple materials capable of ferroelectricity.

[0351] As a material capable of ferroelectricity, hafnium oxide, or a material containing both hafnium oxide and zirconium oxide, is preferred because it can exhibit ferroelectricity even when processed into a thin film of a few nanometers. Here, the film thickness of insulators 228 and 234 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By creating a ferroelectric layer that can be made into a thin film, a semiconductor device can be formed by combining a capacitive element 130 with a miniaturized transistor 120.

[0352] Furthermore, insulators 228 and 234 may be constructed as a laminated structure of a material that may possess the ferroelectric properties described above and a material with high dielectric strength. Materials with high dielectric strength include silicon oxide, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide or resin. By using laminated insulators with high dielectric strength, the dielectric strength can be improved, and the leakage current of the capacitive element 130 can be suppressed.

[0353] Conductors 227 and 233, which function as lower electrodes, and conductors 229 and 235, which function as upper electrodes, can be deposited using methods such as ALD, CVD, or sputtering. For example, titanium nitride may be deposited as the lower electrode using thermal ALD.

[0354] Furthermore, the conductor functioning as the upper electrode and the conductor functioning as the lower electrode may be a stack of multiple conductors. For example, as the upper electrode, titanium nitride may be deposited using the ALD method, and then tungsten may be deposited using the sputtering method.

[0355] After the formation of the upper electrode, a heat treatment of approximately 400°C to 500°C may be performed. For example, after the formation of the upper electrode, a heat treatment of 500°C for 60 seconds may be performed using the RTA method.

[0356] <Wiring or plugs in layers containing oxide semiconductors> When an oxide semiconductor is used in the transistor 120, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0357] For example, an insulator 241 may be provided between the insulator 280 having excess oxygen and the conductor 240 (see Embodiment 2). By providing the insulator 241, insulator 282, and insulator 283 in contact with each other, the transistor 120 can be sealed with an insulator having barrier properties.

[0358] In other words, by providing the insulator 241, excess oxygen in the insulator 280 is less likely to be absorbed by the conductor 240. Furthermore, the presence of the insulator 241 suppresses the diffusion of hydrogen, an impurity, to the transistor 200 via the conductor 240.

[0359] As the insulator 241, an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferably used. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide is preferred. Silicon nitride is particularly preferred because of its high blocking properties for hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0360] As shown in the above embodiment, the transistor 120 is preferably sealed with insulators 212, 214, 282, and 283. This configuration reduces the contamination of insulators 280 with hydrogen contained in insulators 274, 285, etc. In this case, insulators 212, 214, 282, and 283 function as sealing films.

[0361] Here, the conductor 240 penetrates insulators 283 and 282, and the conductor 141 penetrates insulators 214 and 212. However, as described above, the insulator 241 is in contact with the conductors 240 and 141, respectively. This reduces the amount of hydrogen that enters the inside of insulators 212, 214, 282, and 283 via the conductors 240 and 141. In this way, the transistor 120 is sealed, and the ingress of impurities such as hydrogen contained in the insulator 274 into the transistor 120 is reduced. Note that in Figure 12, two transistors 120 are shown within the region sealed by insulators 212 and 283, but the arrangement is not limited to this, and one or more transistors 120 can be provided within the sealed region.

[0362] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0363] Here, for example, it is preferable to design the region where insulator 283 and insulator 212 are in contact to overlap with the dicing line. That is, in the vicinity of the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200, openings are provided in insulators 282, 280, 275, 224, 222, 216, and 214.

[0364] In other words, insulator 283 and insulator 212 are in contact at the openings provided in insulators 282, 280, 275, 224, 222, 216, and 214. Note that insulators 212 and 283 may be formed using the same material and method. By providing insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride may be used.

[0365] Furthermore, for example, openings may be provided in insulators 282, 280, 275, 224, 222, and 216. With this configuration, insulator 283 and insulator 214 will be in contact at the openings provided in insulators 282, 280, 275, 224, 222, and 216.

[0366] This structure allows the transistor 120 to be enclosed by insulators 212, 214, 282, and 283. At least one of insulators 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water. By dividing the substrate for each circuit region on which the semiconductor element according to this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from diffusing from the divided portion to the transistor 120.

[0367] Furthermore, this structure prevents excess oxygen from insulators 280 and 224 from diffusing to the outside. Therefore, excess oxygen from insulators 280 and 224 is efficiently supplied to the oxide in which the channels of transistor 120 are formed. This oxygen reduces oxygen deficiencies in the oxide in which the channels of transistor 120 are formed. As a result, the oxide in which the channels of transistor 120 are formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 120 can be suppressed and reliability can be improved.

[0368] <Example 1 of a memory device> A modified version of the memory device shown in Figure 12 is shown in Figure 13. In Figure 12, the conductor 141 was provided embedded in the insulators 224, 222, 216, 214, 212, and 361, but it may also be provided embedded in the insulators 285, 283, 282, 280, 271, and 275.

[0369] In Figure 13, a conductor 292 is provided on top of the conductor 141 and the insulator 285, and insulators 293 and 294 are provided on top of the conductor 292 and the insulator 285. Furthermore, conductors 295 and 296 are provided so as to be embedded in insulators 293 and 294.

[0370] Conductors 233 and 234 are provided above the insulator 294. Conductors 225 and 240a are electrically connected via conductor 295. Conductor 233 is electrically connected to conductor 240b via conductor 296. Conductor 292 is electrically connected to conductor 359. In Figure 13, conductor 359 is provided below transistor 120, but it may also be provided above transistor 120.

[0371] <Modified Memory Device 2> As shown in the above embodiment, the superposition of capacitive elements 130 is not limited to two. Three or more capacitive elements 130 may be superimposed. Figure 14 shows an example configuration in which not only capacitive elements 130a and 130b, but also capacitive elements 130m and 130n are superimposed.

[0372] This embodiment can be appropriately combined with other embodiments shown herein.

[0373] (Embodiment 4) This embodiment shows an example of a semiconductor wafer on which a semiconductor device according to one aspect of the present invention is formed, and an example of an electronic component into which the semiconductor device is incorporated.

[0374] <Semiconductor wafers> First, an example of a semiconductor wafer on which semiconductor devices and other components are formed will be explained using Figure 15A.

[0375] The semiconductor wafer 4800 shown in Figure 15A comprises a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801. The portion of the upper surface of the wafer 4801 without circuit sections 4802 is the spacing 4803, which is the region for dicing.

[0376] The semiconductor wafer 4800 can be manufactured by forming multiple circuit sections 4802 on the surface of wafer 4801 in a previous process. Alternatively, the wafer 4801 may be thinned by grinding the opposite side of the wafer 4801 from where the circuit sections 4802 are formed. This process reduces warping of the wafer 4801, enabling miniaturization of the component.

[0377] The next step is the dicing process. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by the dashed lines. In order to facilitate the dicing process, it is preferable to arrange the spacing 4803 so that multiple scribe lines SCL1 are parallel, multiple scribe lines SCL2 are parallel, and scribe lines SCL1 and SCL2 are perpendicular.

[0378] By performing the dicing process, a chip 4800a, as shown in Figure 15B, can be cut from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit section 4802, and spacing 4803a. It is preferable to make the spacing 4803a as small as possible. In this case, the width of the spacing 4803 between adjacent circuit sections 4802 should be approximately the same length as the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0379] The shape of the element substrate in one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Figure 15A. For example, it may be a rectangular semiconductor wafer. The shape of the element substrate can be appropriately changed depending on the manufacturing process of the element and the apparatus for manufacturing the element.

[0380] <Electronic Components> Figure 15C shows a perspective view of the electronic component 4700 and the substrate (mounted substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Figure 15C has a chip 4800a within the mold 4711. A semiconductor device according to one embodiment of the present invention can be used as the chip 4800a.

[0381] Figure 15C omits some details to show the interior of the electronic component 4700. The electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, which in turn is electrically connected to a chip 4800a by a wire 4714. The electronic component 4700 is mounted, for example, on a printed circuit board 4702. Multiple such electronic components are combined and electrically connected on the printed circuit board 4702 to complete the mounted circuit board 4704.

[0382] Figure 15D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi-Chip Module). Electronic component 4730 has an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 are provided on the interposer 4731.

[0383] The semiconductor device 4710 can be, for example, a chip 4800a, the semiconductor device described in the above embodiment, or a high-bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or memory device.

[0384] The package substrate 4732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 4731 can be a silicon interposer, a resin interposer, etc.

[0385] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 4731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 4732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0386] It is preferable to use a silicon interposer as the interposer 4731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0387] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0388] Furthermore, in SiP or MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0389] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 4730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0390] To mount the electronic component 4730 onto another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. Figure 15D shows an example where electrodes 4733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 4733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0391] The electronic component 4730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0392] This embodiment can be appropriately combined with other embodiments shown herein.

[0393] (Embodiment 5) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention.

[0394] A semiconductor device according to one aspect of the present invention can be applied to various electronic devices (for example, information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related equipment, etc. Here, "computer" includes tablet computers, notebook computers, desktop computers, as well as large computers such as server systems.

[0395] By using a semiconductor device according to one aspect of the present invention, electronic devices with a large storage capacity per unit area can be realized. By using a semiconductor device according to one aspect of the present invention, miniaturization of electronic devices can be achieved.

[0396] An example of an electronic device having a semiconductor device according to one aspect of the present invention will be described. Figures 16A to 16J and 17A to 17E illustrate how the electronic component 4700 having the semiconductor device is included in each electronic device.

[0397] [mobile phone] The information terminal 5500 shown in Figure 16A is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0398] The information terminal 5500 can store temporary files generated during application execution (for example, cache when using a web browser) by applying a semiconductor device according to one aspect of the present invention.

[0399] [Wearable devices] Figure 16B also shows an information terminal 5900, which is an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0400] Similar to the information terminal 5500 described above, a wearable device can store temporary files generated during application execution by applying a semiconductor device according to one aspect of the present invention.

[0401] [Information terminal] Figure 16C also shows a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display unit 5302, and a keyboard 5303.

[0402] The desktop information terminal 5300, like the information terminal 5500 described above, can store temporary files generated during application execution by applying a semiconductor device according to one aspect of the present invention.

[0403] In the above, smartphones, wearable devices, and desktop information terminals were used as examples of electronic devices and illustrated in Figures 16A to 16C, respectively. However, information terminals other than smartphones, wearable devices, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable devices, and desktop information terminals include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0404] [electric appliances] Figure 16D also shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that is compatible with IoT (Internet of Things).

[0405] A semiconductor device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to an information terminal or the like via the internet. The electric refrigerator 5800 can store temporary files generated when transmitting such information in the semiconductor device.

[0406] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0407] [Game console] Figure 16E also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a casing 5201, a display unit 5202, buttons 5203, etc.

[0408] Furthermore, Figure 16F illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 16F, the controller 7522 may also be equipped with a display unit for displaying game images, and input interfaces other than buttons, such as a touch panel, a joystick, a rotary knob, or a sliding knob. Moreover, the shape of the controller 7522 is not limited to the shape shown in Figure 16F, and its shape may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and shaped like a gun can be used. Also, for example, in music games, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be equipped with cameras, depth sensors, microphones, etc., and operated by the game player's gestures and / or voice.

[0409] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, and head-mounted displays.

[0410] By applying the semiconductor device described in the above embodiment to a portable game console 5200 or a home game console 7500, a portable game console 5200 or a home game console 7500 with a large memory capacity can be realized without increasing the occupied area. Furthermore, a portable game console 5200 or a home game console 7500 with low power consumption can be realized. In addition, because the heat generated from the circuit can be reduced, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0411] Furthermore, by applying the semiconductor device described in the above embodiment to a portable game console 5200 or a home game console 7500, it becomes possible to retain temporary files and other data necessary for calculations that occur during game execution.

[0412] Figure 16E shows a portable game console as an example of a game console. Figure 16F shows a home console for game use. However, the electronic devices of one aspect of the present invention are not limited to these. Examples of electronic devices of one aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0413] [Mobile] The semiconductor device described in the above embodiment can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0414] Figure 16G shows an example of a mobile vehicle, the automobile 5700.

[0415] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that provides various information by displaying the speedometer, tachometer, odometer, fuel gauge, gear status, and air conditioning settings. Additionally, a display device for showing this information may be provided around the driver's seat.

[0416] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0417] The semiconductor device described in the above embodiment can temporarily hold information, and therefore can be used, for example, to hold necessary temporary information in systems that perform autonomous driving, road guidance, and hazard prediction for the automobile 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Alternatively, it may be configured to hold video footage from a driving recorder installed in the automobile 5700.

[0418] While the above uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0419] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0420] Figure 16H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. Furthermore, the digital camera 6240 may be configured to allow for the attachment of a strobe device, viewfinder, etc. separately.

[0421] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a low-power digital camera 6240 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0422] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0423] Figure 16I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, etc. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0424] When recording video captured by the video camera 6300, encoding is required according to the data recording format. By using the semiconductor device described above, the video camera 6300 can retain temporary files generated during encoding.

[0425] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter-defibrillator (ICD).

[0426] Figure 16J is a schematic cross-sectional view showing an example of an ICD. The ICD unit 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0427] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0428] The ICD unit 5400 functions as a pacemaker, pacing the heart if the heart rate falls outside the specified range. If pacing does not improve the heart rate (e.g., in cases of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0429] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment was performed, the duration, etc., in the electronic component 4700.

[0430] Furthermore, the antenna 5404 can receive power, which is then used to charge the battery 5401. The ICD unit 5400 also benefits from having multiple batteries, thus enhancing safety. Specifically, even if some of the batteries in the ICD unit 5400 fail, the remaining batteries can still function, thus acting as an auxiliary power source.

[0431] In addition, the system may have an antenna capable of transmitting physiological signals, separate from the power receiving antenna 5404. For example, a system may be configured to monitor cardiac activity so that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0432] [Extension devices for PCs] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0433] Figure 17A shows an example of such an expansion device, an external expansion device 6100 for a PC, equipped with a portable chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 17A illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with, for example, a cooling fan.

[0434] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with circuits for driving semiconductor devices and the like as described in the above embodiment. For example, the circuit board 6104 is fitted with electronic components 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to external devices.

[0435] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0436] Figure 17B is a schematic diagram of the external appearance of an SD card, and Figure 17C is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 4700 and a controller chip 5115 are mounted on the circuit board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the writing circuit, load driver, and read circuit provided in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 4700.

[0437] By providing electronic components 4700 on the back side of the circuit board 5113, the capacity of the SD card 5110 can be increased. Alternatively, a wireless chip with wireless communication capabilities may be provided on the circuit board 5113. This allows for wireless communication between an external device and the SD card 5110, enabling reading and writing of data to and from the electronic components 4700.

[0438] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0439] Figure 17D is a schematic diagram of the external appearance of the SSD, and Figure 17E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to external devices. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is equipped with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 has an electronic component 4700, a memory chip 5155, and a controller chip 5156 mounted on it. The capacity of the SSD 5150 can be increased by also providing an electronic component 4700 on the back side of the circuit board 5153. The memory chip 5155 incorporates work memory. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be modified as appropriate depending on the circumstances. For example, the controller chip 5156 may also be provided with memory that functions as work memory.

[0440] [Calculator] The computer 5600 shown in Figure 18A is an example of a large-scale computer. The computer 5600 houses multiple rack-mount type computers 5620 in rack 5610.

[0441] Computer 5620 can have a configuration similar to the perspective view shown in Figure 18B. In Figure 18B, computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0442] The PC card 5621 shown in Figure 18C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 18C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, for information on these semiconductor devices, please refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below.

[0443] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and the connector 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0444] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0445] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0446] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the wiring provided on the board 5622 using these terminals. Examples of semiconductor devices 5627 include FPGAs (Field Programmable Gate Arrays), GPUs, and CPUs. For example, electronic component 4730 can be used as the semiconductor device 5627.

[0447] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 4700 can be used as the semiconductor device 5628.

[0448] Computer 5600 can also function as a parallel computer. By using Computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0449] By using a semiconductor device according to one aspect of the present invention in the various electronic devices described above, it is possible to miniaturize and / or reduce the power consumption of the electronic devices. Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, it is possible to reduce heat generation from the circuit. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using a semiconductor device according to one aspect of the present invention, it is possible to realize electronic devices that operate stably even in high-temperature environments. Therefore, the reliability of electronic devices can be improved.

[0450] This embodiment can be appropriately combined with other embodiments shown herein. [Explanation of Symbols]

[0451] 100: Semiconductor device, 120: Transistor, 130: Capacitive element, 141: Conductor, 142: Conductor, 143: Conductor, 151: Transistor layer, 152: Capacitive layer, 153: Capacitive layer, 154: Capacitive layer, 155: Capacitive layer

Claims

[Claim 1] First and second transistors, It has first and second capacitance elements, The first transistor is electrically connected to the first capacitive element, The second transistor is electrically connected to the second capacitive element, The first and second capacitance elements are provided above the first and second transistors, The first and second capacitance elements each have a ferroelectric material, The first and second capacitance elements are semiconductor devices having overlapping regions.

Images