A main control unit that can improve the amount of encoded setting signal received.
The main control device enhances lighting system coordination by doubling encoded signal reception using a processing module, DIP switches, and inversion, addressing signal pin limitations and cost issues, thus improving performance and flexibility.
Patent Information
- Application Number
- JP2025139365
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-09-10
- Filing Date
- 2025-08-25
- Publication Date
- 2026-03-23
AI Technical Summary
Conventional lighting systems face challenges in simultaneously activating lighting devices across adjacent groups due to insufficient signal pins in Bluetooth modules or microcontrollers, leading to gaps in lighting activation when objects move between groups.
A main control device incorporating a processing module, DIP switches, an inverting module, and switches, which uses control signals and inversion to effectively utilize existing signal pins, doubling the reception of encoded setting signals without requiring multitasking chips, and integrating a delay mechanism for accurate signal reading.
The solution allows for doubling the amount of encoded setting signals received, reducing costs, improving performance, and enhancing flexibility and applicability to various smart applications while meeting future development needs.
Smart Images
Figure 2026052019000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a main control device, and particularly to a main control device capable of improving the reception amount of an encoded setting signal.
Background Art
[0002] With the progress of technology, smart lighting systems have been continuously improved for the purpose of optimizing people's usage experiences. Among them, lighting systems with a group control function are widely applied to garages, parking lots, and other buildings. When a lighting device within a certain group detects a moving object (such as a person or a vehicle) and issues a sensing signal, the lighting device simultaneously activates and actuates other lighting devices within the same group. However, the lighting devices of this group cannot simultaneously activate and actuate the lighting devices of another adjacent group. Therefore, when a moving object moves to the boundary between this group and another adjacent group, there is a problem that the lighting devices of the other group cannot be immediately lit.
[0003] To solve this problem, it is necessary to make the lighting device at the end of this group also belong to another adjacent group simultaneously. Therefore, the lighting device needs to obtain the identifiers of the two groups simultaneously, and accordingly, the number of required signal pins (I / O pins) doubles compared to the original. However, the signal pins of conventional Bluetooth modules or microcontrollers do not have sufficient signal pins. Although this problem can be solved by using a multi-task capable chip, the cost increases significantly.
Summary of the Invention
Problems to be Solved by the Invention
[0004] An object of the present invention is to provide a main control device capable of improving the reception amount of an encoded setting signal.
Means for Solving the Problems
[0005] A main control device capable of improving the amount of encoded setting signal received is provided, based on one embodiment of the present invention, and including a processing module, a first DIP switch, a second DIP switch, an inverting module, a first switch, and a second switch. The processing module has switching pins and a plurality of signal pins. The first DIP switch has a plurality of first signal switches connected to a plurality of signal pins. The second DIP switch has a plurality of second signal switches connected to a plurality of signal pins. One end of the inverting module is connected to the processing module. The first end of the first switch is connected to the plurality of first signal switches, the second end of the first switch is connected to one end of the inverting module and to the switching pins, and the third end of the first switch is connected to an operating voltage source. The first end of the second switch is connected to a plurality of second signal switches, the second end of the second switch is connected to the other end of the inverting module, and the third end of the second switch is connected to an operating voltage source.
[0006] In one embodiment, the switching pins of the processing module transmit a first control signal having a first level to the first switch and the inverting module, turning on the first switch and activating the first DIP switch. The first control signal is inverted by the inverting module to generate a second control signal having a second level opposite to the first level. The second control signal is transmitted to the second switch, turning off the second switch. The processing module reads the encoded setting signal of the first DIP switch.
[0007] In one embodiment, the processing module generates a first control signal and, after a preset delay time has elapsed, reads the encoded setting signal of the first DIP switch.
[0008] In one embodiment, the switching pins of the processing module transmit a second control signal having a second level to the first switch and the inverting module, turning off the first switch. The second control signal is inverted by the inverting module to generate a first control signal having a first level opposite to the second level. The first control signal is transmitted to the second switch, turning on the second switch and activating the second DIP switch. The processing module reads the encoded setting signal of the second DIP switch.
[0009] The processing module generates a second control signal and, after the preset delay time has elapsed, reads the encoded setting signal of the second DIP switch.
[0010] In one embodiment, each signal pin is connected to ground via a resistor.
[0011] In one embodiment, the first switch and the second switch are metal oxide semiconductor field-effect transistors (MOSFETs) or bipolar junction transistors (BJTs).
[0012] In one embodiment, the inversion module is an inverter.
[0013] In one embodiment, the processing module is a microcontroller (MCU), a central processing unit (CPU), an application-specific integrated circuit chip (ASIC), or a field-programmable gate array (FPGA).
[0014] In one embodiment, the processing module is a Bluetooth module. [Effects of the Invention]
[0015] As described above, the main control device of the embodiment of the present invention, which can improve the amount of encoded setting signal received, may have one or more of the following advantages. (1) In one embodiment of the present invention, the main control device includes a processing module, a first DIP switch, a second DIP switch, an inverting module, a first switch, and a second switch. The processing module has switching pins and a plurality of signal pins. The first DIP switch has a plurality of first signal switches connected to the plurality of signal pins. The second DIP switch has a plurality of second signal switches connected to the plurality of signal pins. One end of the inverting module is connected to the processing module. The first end of the first switch is connected to the plurality of first signal switches, the second end of the first switch is connected to one end of the inverting module and the switching pins, and the third end of the first switch is connected to an operating voltage source. The first end of the second switch is connected to a plurality of second signal switches, the second end of the second switch is connected to the other end of the inverting module, and the third end of the second switch is connected to an operating voltage source. The switching pins of the processing module transmit a first control signal having a first level to the first switch and the inverting module, turning on the first switch and activating the first DIP switch. The first control signal is inverted by the inverting module to generate a second control signal having a second level opposite to the first level. The second control signal is transmitted to the second switch, turning it off. The processing module reads the encode setting signal of the first DIP switch. The switching pins of the processing module transmit a second control signal with a second level to the first switch and the inverting module, turning the first switch off. The second control signal is inverted by the inverting module, generating a first control signal with a first level opposite to the second level. The first control signal is transmitted to the second switch, turning it on and activating the second DIP switch. The processing module reads the encode setting signal of the second DIP switch. Through the above circuit structure and control mechanism, the main control unit can double the amount of encode setting signal received by the signal pins without requiring a multitasking chip, achieving the effect of improving the amount of encode setting signal received. Therefore, the cost of the main control unit can be reduced, meeting the requirements of actual applications. (2) In one embodiment of the present invention, the processing module of the main control unit generates a first control signal and, after a preset delay time has elapsed, reads the encoded setting signal of the first DIP switch. Similarly, the processing module of the main control unit generates a second control signal and, after a preset delay time has elapsed, reads the encoded setting signal of the second DIP switch. Since the first and second switches enter a stable state after a certain period of time following the receipt of the control signals, the processing module reads the encoded setting signal after the preset delay time has elapsed. The above-described delay time mechanism ensures that the processing module reads the encoded setting signal accurately. Therefore, the performance of the main control unit can be greatly improved. (3) In one embodiment of the present invention, the user can further improve the amount of encoded setting signal received by increasing the number of switching pins and / or the plurality of signal pins of the processing module of the main control unit. In this way, the main control unit can be applied to different smart applications and can satisfy the requirements of these smart applications. Therefore, the main control unit has greater flexibility in use and a wider range of applications. (4) In one embodiment of the present invention, the main control unit has a circuit design that can improve the amount of encoded setting signal received and integrates a delay time mechanism, thereby significantly improving the overall performance of the main control unit. Thus, the main control unit can meet the requirements of various future applications and is compatible with future development trends. (5) In one embodiment of the present invention, the circuit design of the main control unit is simple and integrates an effective control mechanism. Thus, the main control unit can achieve the desired effects without increasing or reducing costs. Therefore, the practicality of the main control unit can be greatly improved and it can meet the requirements of different smart applications. [Brief explanation of the drawing]
[0016] [Figure 1]This is a circuit diagram of a main control device that can improve the amount of encoded setting signal received in one embodiment of the present invention. [Figure 2] This is a first explanatory diagram of the operating state of a main control device that can improve the amount of encoded setting signal received in one embodiment of the present invention. [Figure 3] This is a second explanatory diagram of the operating state of a main control device that can improve the amount of encoded setting signal received in one embodiment of the present invention. [Figure 4] This is a flowchart of a control method for a main control unit that can improve the amount of encoded setting signal received in one embodiment of the present invention. [Modes for carrying out the invention]
[0017] The following embodiments describe the detailed features and advantages of the present invention, which are sufficient to enable those skilled in the art to understand and implement the technical aspects of the invention, and which, through the disclosures, claims, and drawings herein, will be readily understood by those skilled in the art.
[0018] The following describes embodiments of the main control device capable of improving the amount of encoded setting signal received according to the present invention, with reference to the relevant drawings. For clarity and ease of illustration, the dimensions and proportions of the components in the drawings may be exaggerated or reduced. In the following description and / or claims, when a component is described as “connected” or “joined” to another component, it may be a direct connection or coupling to that other component, or there may be an intermediary component. When a component is described as “directly connected” or “directly coupled” to another component, there is no intermediary component, and other terms used to describe relationships between components or layers should be interpreted similarly. For ease of understanding, the same components in the following embodiments are denoted by the same reference numerals.
[0019] Refer to FIG. 1. FIG. 1 is a circuit diagram of a main control device capable of improving the reception amount of an encoding setting signal according to an embodiment of the present invention. As shown in the figure, the main control device 1 includes a processing module 11, a first DIP switch 12, a second DIP switch 13, an inversion module 14, a first switch 15, and a second switch 16. The main control device 1 may be a main control board of a smart device (smart lighting device, etc.) or various electronic devices, or a part of the main control board of a smart device.
[0020] The processing module 11 has a switching pin P1 and a plurality of signal pins P2. Each signal pin P2 is connected to the ground GND through a resistor R1. In one embodiment, the processing module 11 is a microcontroller (MCU). In another embodiment, the processing module 11 may be a Bluetooth module or other similar components. In yet another embodiment, the processing module 11 may be a central processing unit (CPU), an application-specific integrated circuit chip (ASIC), a field programmable gate array (FPGA), or other similar components. [[ID=[]6]]
[0021] The first DIP switch 12 has a plurality of first signal switches S_1, and the plurality of first signal switches S_1 are respectively connected to the plurality of signal pins P2.
[0022] The second DIP switch 13 has a plurality of second signal switches S_2, and the plurality of second signal switches S_2 are respectively connected to the plurality of signal pins P2.
[0023] [[ID=[]16]]One end of the inversion module 14 is connected to the processing module 11. In one embodiment, the inversion module 14 is an inverter. In another embodiment, the inversion module 14 may be another inversion circuit having a similar function.
[0024] The first terminal of the first switch 15 is connected to the plurality of first signal switches S1 described above. The second terminal of the first switch 15 is connected to one terminal of the inverting module 14 and the switching pin P1. The third terminal of the first switch 15 is connected to the operating voltage source Vdd. In one embodiment, the first switch 15 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first terminal of the first switch 15 is the drain. The second terminal of the first switch 15 is the gate. The third terminal of the first switch 15 is the source. In one embodiment, the first switch 15 may be a bipolar junction transistor (BJT) or other similar component.
[0025] The first end of the second switch 16 is connected to the plurality of second signal switches S2 described above. The second end of the second switch 16 is connected to the other end of the inverting module 14. The third end of the second switch 16 is connected to the operating voltage source Vdd. In one embodiment, the second switch 16 is a metal oxide semiconductor field-effect transistor. The first end of the second switch 16 is the drain. The second end of the second switch 16 is the gate. The third end of the second switch 16 is the source. In one embodiment, the second switch 16 may be a bipolar junction transistor (BJT) or other similar component.
[0026] Naturally, this embodiment is for illustrative purposes only and does not limit the scope of the present invention, and equivalent modifications or changes made based on the main control unit that can improve the amount of encoded setting signal received in this embodiment should still be within the scope of protection of the present invention.
[0027] Figure 2 is a first explanatory diagram of the operating state of a main control unit that can improve the amount of encoded setting signal received in one embodiment of the present invention. As shown in the figure, the switching pin P1 of the processing module 11 transmits a first control signal Cs1 having a first level (high level) to the first switch 15 and the inverting module 14 to turn on the first switch 15 and activate the first DIP switch 12.
[0028] Next, the first control signal Cs1 is inverted by the inverting module 14 to generate a second control signal Cs2 having a second level (low level) that is the opposite of the first level. The second control signal Cs2 is sent to the second switch 16 to turn off the second switch 16. Therefore, the second DIP switch 13 is in the closed state.
[0029] Finally, the processing module 11 reads the encoded setting signal Fs1 of the first DIP switch 12. The processing module 11 generates a first control signal Cs1 and can read the encoded setting signal Fs1 of the first DIP switch 12 after a set delay time has elapsed. Since the first switch 15 and the second switch 16 require a certain amount of time to enter a stable state after receiving the control signal, the processing module 11 reads the encoded setting signal Fs1 of the first DIP switch 12 after a set delay time has elapsed to ensure accurate signal reading. For example, the encoded setting signal Fs1 may be a group identifier, light sensitivity, or the intensity of various sensitive signals.
[0030] Naturally, this embodiment is for illustrative purposes only and does not limit the scope of the present invention, and equivalent modifications or changes made based on the main control unit that can improve the amount of encoded setting signal received in this embodiment should still be within the scope of protection of the present invention.
[0031] Figure 3 is a second explanatory diagram of the operating state of a main control unit that can improve the amount of encoded setting signal received in one embodiment of the present invention. As shown in the figure, the switching pin P1 of the processing module 11 sends a second control signal Cs2 having a second level to the first switch 15 and the inverting module 14 to turn off the first switch 15. Therefore, the first DIP switch 12 is in the closed state.
[0032] Next, the second control signal Cs2 is inverted by the inverting module 14 to generate a first control signal Cs1 having a first level that is the opposite of the second level. The first control signal Cs1 is sent to the second switch 16 to turn on the second switch 16 and activate the second DIP switch 13.
[0033] Finally, the processing module 11 reads the encoding setting signal Fs2 from the second DIP switch 13. Similarly, since the first switch 15 and the second switch 16 enter a stable state after a certain period of time following the receipt of the control signal, the processing module 11 reads the encoding setting signal Fs2 from the second DIP switch 13 after a set delay period, ensuring that an accurate signal is read. For example, the encoding setting signal Fs2 may be a group identifier, light sensitivity, or the intensity of various sensitive signals.
[0034] The user can further improve the amount of encoded setting signal received by increasing the number of switching pins P1 and / or the above-mentioned signal pins P2 of the processing module 11 of the main control unit 1 according to actual requirements. For example, the processing module 11 of this embodiment has one switching pin P1 and four signal pins P2 and can receive an 8-bit encoded setting signal (Fs1 + Fs2). If the user increases the number of signal pins P2 by one, the processing module 11 can receive a 10-bit encoded setting signal (Fs1 + Fs2). For example, the processing module 11 of this embodiment has one switching pin P1 and four signal pins P2 and can receive an 8-bit encoded setting signal (Fs1 + Fs2). If the user increases the number of switching pins P1 and four signal pins P2, the processing module 11 can receive a 16-bit encoded setting signal (Fs1 + Fs2).
[0035] Through the circuit structure and control mechanism described above, the main control unit 1 can double the amount of encoded setting signal received by signal pin P2 without requiring a multitasking chip, thereby achieving the effect of improving the amount of encoded setting signal received. Therefore, the cost of the main control unit 1 can be reduced, and the requirements of actual applications can be met.
[0036] Furthermore, in this embodiment, the processing module 11 of the main control unit 1 generates a first control signal Cs1 and reads the encoded setting signal Fs1 of the first DIP switch 12 after a set delay time. Similarly, the processing module 11 of the main control unit 1 generates a second control signal Cs2 and reads the encoded setting signal Fs2 of the second DIP switch 13 after a set delay time. Since the first switch 15 and the second switch 16 enter a stable state after a certain period of time following the receipt of the control signals, the processing module 11 reads the encoded setting signals after a set delay time. The above-described delay time mechanism ensures that the processing module 11 reads the encoded setting signals accurately. Therefore, the performance of the main control unit 1 can be significantly improved.
[0037] Furthermore, in this embodiment, the user can further improve the amount of encoded setting signal received by increasing the number of switching pins P1 and / or the aforementioned signal pins P2 of the processing module 11 of the main control unit 1. In this way, the main control unit 1 can be applied to different smart applications and can meet the requirements of these smart applications. Therefore, the main control unit 1 has greater flexibility in use and a wider range of applications.
[0038] Furthermore, the main control unit 1 has a circuit design that improves the amount of encoded setting signal received and integrates a delay time mechanism, significantly improving the overall performance of the main control unit 1. Therefore, the main control unit 1 can meet the requirements of various future applications and is in line with future development trends. At the same time, the circuit design of the main control unit 1 is simple and integrates an effective control mechanism. In this way, the main control unit 1 can achieve the desired effect without increasing or reducing costs. Therefore, the practicality of the main control unit 1 can be greatly improved and it can meet the requirements of different smart applications.
[0039] Naturally, this embodiment is for illustrative purposes only and does not limit the scope of the present invention, and equivalent modifications or changes made based on the main control unit that can improve the amount of encoded setting signal received in this embodiment should still be within the scope of protection of the present invention.
[0040] Conventional Bluetooth modules or microcontrollers do not have sufficient signal pins P2, and therefore cannot improve the amount of encoded setting signal received. In contrast, according to an embodiment of the present invention, the main control device 1 includes a processing module 11, a first DIP switch 12, a second DIP switch 13, an inverting module 14, a first switch 15, and a second switch 16. The processing module 11 has a switching pin P1 and a plurality of signal pins P2. The first DIP switch 12 has a plurality of first signal switches S1, each connected to the plurality of signal pins P2. The second DIP switch 13 has a plurality of second signal switches S2, each connected to the plurality of signal pins P2. One end of the inverting module 14 is connected to the processing module 11. The first end of the first switch 15 is connected to the plurality of first signal switches S1, the second end of the first switch 15 is connected to one end of the inverting module 14 and the switching pin P1, and the third end of the first switch 15 is connected to an operating voltage source Vdd. The first end of the second switch 16 is connected to the plurality of second signal switches S2, the second end of the second switch 16 is connected to the other end of the inverting module 14, and the third end of the second switch 16 is connected to the operating voltage source Vdd. The switching pin P1 of the processing module 11 sends a first control signal Cs1 having a first level to the first switch 15 and the inverting module 14 to turn on the first switch 15 and activate the first DIP switch 12. The first control signal Cs1 is inverted by the inverting module 14 to generate a second control signal Cs2 having a second level that is the opposite of the first level. The second control signal Cs2 is sent to the second switch 16 to turn off the second switch 16. The processing module 11 reads the encoded setting signal Fs1 of the first DIP switch 12. The switching pin P1 of the processing module 11 sends a second control signal Cs2 having a second level to the first switch 15 and the inverting module 14 to turn off the first switch 15. The second control signal Cs2 is inverted by the inverting module 14 to generate a first control signal Cs1 having a first level that is the opposite of the second level.The first control signal Cs1 is transmitted to the second switch 16, which turns on the second switch 16 and activates the second DIP switch 13. The processing module 11 reads the encode setting signal Fs2 of the second DIP switch 13. Through the above circuit structure and control mechanism, the main control unit 1 can increase the amount of encode setting signal received on signal pin P2 to twice the original amount without requiring a multitasking chip, thereby achieving the effect of improving the amount of encode setting signal received. Therefore, the cost of the main control unit 1 can be reduced and the requirements of actual applications can be met.
[0041] Furthermore, according to an embodiment of the present invention, the processing module 11 of the main control device 1 generates a first control signal Cs1 and reads the encoded setting signal Fs1 of the first DIP switch 12 after a set delay time. Similarly, the processing module 11 of the main control device 1 generates a second control signal Cs2 and reads the encoded setting signal Fs2 of the second DIP switch 13 after a set delay time. Since the first switch 15 and the second switch 16 enter a stable state after a certain period of time following the receipt of the control signals, the processing module 11 reads the encoded setting signals after a set delay time. The above-described delay time mechanism ensures that the processing module 11 reads the encoded setting signals accurately. Therefore, the performance of the main control device 1 can be significantly improved.
[0042] Furthermore, according to embodiments of the present invention, the user can further improve the amount of encoded setting signal received by increasing the number of switching pins P1 and / or the plurality of signal pins P2 of the processing module 11 of the main control unit 1. In this way, the main control unit 1 can be applied to different smart applications and can satisfy the requirements of these smart applications. Therefore, the main control unit 1 has greater flexibility in use and a wider range of applications.
[0043] Furthermore, according to embodiments of the present invention, the main control unit 1 has a circuit design that improves the amount of encoded setting signal received and integrates a delay time mechanism, thereby significantly improving the overall performance of the main control unit 1. Therefore, the main control unit 1 can meet the requirements of various future applications and is compatible with future development trends.
[0044] Furthermore, according to embodiments of the present invention, the circuit design of the main control unit 1 is simple and integrates an effective control mechanism. Thus, the main control unit 1 can achieve the desired effect without increasing or even reducing costs. Therefore, the practicality of the main control unit 1 can be greatly improved and can meet the requirements of different smart applications. As can be seen from the above, the main control unit 1 that improves the amount of encoded setting signals received according to embodiments of the present invention can reliably achieve extremely excellent technical effects.
[0045] Figure 4 is a flowchart of a control method for a main control unit that can improve the amount of encoded setting signal received in one embodiment of the present invention. The control method of this embodiment may include the following steps. Step S41: A first control signal Cs1 having a first level is sent from the switching pin P1 of the processing module 11 to the first switch 15 and the inverting module 14 to turn on the first switch 15 and activate the first DIP switch 12. Step S42: The first control signal Cs1 is inverted through the inversion module 14 to generate a second control signal Cs2 having a second level that is the opposite of the first level. Step S43: The second control signal Cs2 is sent to the second switch 16 to turn off the second switch 16. Step S44: The processing module 11 reads the encoding setting signal Fs1 of the first DIP switch 12. Step S45: A second control signal Cs2 having a second level is sent to the first switch 15 and the inverting module 14 via the switching pin P1 of the processing module 11 to turn off the first switch 15. Step S46: The second control signal Cs2 is inverted through the inversion module 14 to generate a first control signal Cs1 having a first level that is the opposite of the second level. Step S47: The first control signal Cs1 is sent to the second switch 16 to turn on the second switch 16 and activate the second DIP switch 13. Step S48: The processing module 11 reads the encoding setting signal Fs2 of the second DIP switch 13.
[0046] Naturally, this embodiment is for illustrative purposes only and does not limit the scope of the present invention, and equivalent modifications or changes made based on the control method of the main control unit that can improve the amount of encoded setting signal received in this embodiment should still be included within the scope of protection of the present invention.
[0047] Although the steps of the method described in this invention are shown and explained in a specific order, the order of operations of each method may be changed, some steps may be performed in reverse order, or simultaneously with other steps. In another embodiment, different steps may be performed intermittently and / or alternately.
[0048] As described above, according to the embodiment of the present invention, the main control device 1 includes a processing module 11, a first DIP switch 12, a second DIP switch 13, an inverting module 14, a first switch 15, and a second switch 16. The processing module 11 has a switching pin P1 and a plurality of signal pins P2. The first DIP switch 12 has a plurality of first signal switches S1, each connected to the plurality of signal pins P2. The second DIP switch 13 has a plurality of second signal switches S2, each connected to the plurality of signal pins P2. One end of the inverting module 14 is connected to the processing module 11. The first end of the first switch 15 is connected to the plurality of first signal switches S1, the second end of the first switch 15 is connected to one end of the inverting module 14 and the switching pin P1, and the third end of the first switch 15 is connected to an operating voltage source Vdd. The first end of the second switch 16 is connected to the plurality of second signal switches S2, the second end of the second switch 16 is connected to the other end of the inverting module 14, and the third end of the second switch 16 is connected to the operating voltage source Vdd. The switching pin P1 of the processing module 11 sends a first control signal Cs1 having a first level to the first switch 15 and the inverting module 14 to turn on the first switch 15 and activate the first DIP switch 12. The first control signal Cs1 is inverted by the inverting module 14 to generate a second control signal Cs2 having a second level that is the opposite of the first level. The second control signal Cs2 is sent to the second switch 16 to turn off the second switch 16. The processing module 11 reads the encoded setting signal Fs1 of the first DIP switch 12. The switching pin P1 of the processing module 11 sends a second control signal Cs2 having a second level to the first switch 15 and the inverting module 14 to turn off the first switch 15. The second control signal Cs2 is inverted by the inversion module 14 to generate a first control signal Cs1 having a first level that is the opposite of the second level. The first control signal Cs1 is sent to the second switch 16 to turn on the second switch 16 and activate the second DIP switch 13. The processing module 11 reads the encoded setting signal Fs2 of the second DIP switch 13.Through the above circuit structure and control mechanism, the main control unit 1 can increase the amount of encoded setting signal received by signal pin P2 to twice the original amount without requiring a multitasking chip, thereby achieving the effect of improving the amount of encoded setting signal received. Therefore, the cost of the main control unit 1 can be reduced, and the requirements of actual applications can be met.
[0049] Furthermore, according to an embodiment of the present invention, the processing module 11 of the main control device 1 generates a first control signal Cs1 and reads the encoded setting signal Fs1 of the first DIP switch 12 after a set delay time. Similarly, the processing module 11 of the main control device 1 generates a second control signal Cs2 and reads the encoded setting signal Fs2 of the second DIP switch 13 after a set delay time. Since the first switch 15 and the second switch 16 enter a stable state after a certain period of time following the receipt of the control signals, the processing module 11 reads the encoded setting signals after a set delay time. The above-described delay time mechanism ensures that the processing module 11 reads the encoded setting signals accurately. Therefore, the performance of the main control device 1 can be significantly improved.
[0050] Furthermore, according to embodiments of the present invention, the user can further improve the amount of encoded setting signal received by increasing the number of switching pins P1 and / or the plurality of signal pins P2 of the processing module 11 of the main control unit 1. In this way, the main control unit 1 can be applied to different smart applications and can satisfy the requirements of these smart applications. Therefore, the main control unit 1 has greater flexibility in use and a wider range of applications.
[0051] Furthermore, according to embodiments of the present invention, the main control unit 1 has a circuit design that improves the amount of encoded setting signal received and integrates a delay time mechanism, thereby significantly improving the overall performance of the main control unit 1. Therefore, the main control unit 1 can meet the requirements of various future applications and is compatible with future development trends.
[0052] Furthermore, according to embodiments of the present invention, the circuit design of the main control unit 1 is simple and integrates an effective control mechanism. Thus, the main control unit 1 can achieve the desired effect without increasing or even reducing costs. Therefore, the practicality of the main control unit 1 can be greatly improved and it can meet the requirements of various smart applications.
[0053] While the embodiments described herein are explained, it should be noted that this does not limit the scope of the claims of the present invention. Therefore, any changes and modifications to the embodiments described herein, or substitution of equivalent structures or processes using the contents of the specification and drawings of the present invention, or direct or indirect application of the above-described technology to other related technical fields, based on the innovative concept of the present invention, are all included within the scope of the claims of the present invention. [Explanation of symbols]
[0054] 1. Main control unit 11 Processing Modules 12. First DIP switch 13. Second DIP switch 14 Inverting Module 15. First switch 16. Second switch P1 Switching Pin P2 signal pin S1 First signal switch S2 Second signal switch Vdd operating voltage source GND (Ground) R1 Resistor Cs1 First Control Signal Cs2 Second Control Signal Fs1 First DIP switch encoding setting signal Fs2 Second DIP Switch Encoding Setting Signal S41 Step S42 Step S43 Step S44 Step S45 Step S46 Step S47 Step S48 Step
Claims
1. A processing module having switching pins and multiple signal pins, A first DIP switch having a plurality of first signal switches connected to the plurality of signal pins, A second DIP switch having a plurality of second signal switches connected to the plurality of signal pins, An inversion module, one end of which is connected to the processing module, A first switch, the first end of which is connected to the plurality of first signal switches, the second end of which is connected to one end of the inverting module and the switching pin, and the third end of which is connected to the operating voltage source, A second switch, the first end of which is connected to the plurality of second signal switches, the second end of which is connected to the other end of the inverting module, and the third end of which is connected to the operating voltage source, A main control device that can improve the amount of encoding setting signal received, characterized by having the following features.
2. The main control device according to claim 1, characterized in that the switching pin of the processing module transmits a first control signal having a first level to the first switch and the inverting module, turning on the first switch and activating the first DIP switch; the first control signal is inverted by the inverting module to generate a second control signal having a second level opposite to the first level; the second control signal is transmitted to the second switch, turning off the second switch; and the processing module reads the encode setting signal of the first DIP switch.
3. The processing module is a main control device that can improve the amount of encoding setting signal received according to claim 2, characterized in that it generates the first control signal and reads the encoding setting signal of the first DIP switch after a preset delay time has elapsed.
4. A main control device that can improve the amount of encoded setting signal received according to claim 1, characterized in that the switching pin of the processing module transmits a second control signal having a second level to the first switch and the inverting module, turning off the first switch; the second control signal is inverted by the inverting module to generate a first control signal having a first level opposite to the second level; the first control signal is transmitted to the second switch, turning on the second switch and activating the second DIP switch; and the processing module reads the encoded setting signal of the second DIP switch.
5. The processing module is a main control device that can improve the amount of encoding setting signal received according to claim 4, characterized in that it generates the second control signal and reads the encoding setting signal of the second DIP switch after a preset delay time has elapsed.
6. The main control device according to claim 1, characterized in that each of the signal pins is connected to ground via a resistor, thereby improving the amount of encoded setting signal received.
7. The main control device according to claim 1, characterized in that the first switch and the second switch are metal oxide semiconductor field-effect transistors or bipolar junction transistors, which can improve the amount of encoded setting signal received.
8. The main control device according to claim 1, characterized in that the inversion module is an inverter, which can improve the amount of encoding setting signal received.
9. The main control device according to claim 1, characterized in that the processing module is a microcontroller, a central processing unit, an application-specific integrated circuit chip, or a field-programmable gate array, which can improve the amount of encoded setting signal received.
10. The main control device according to claim 1, characterized in that the processing module is a Bluetooth module, which can improve the amount of encoding setting signal received.