Electronic components

Abstract

This suppresses the deterioration of performance that occurs with miniaturization. [Solution] The electronic component 100 comprises a first body 1 and a second body 2 mounted on the first body 1. The first body 1 includes a first circuit portion 10, a second circuit portion 20, and a first structure 8 and a second structure 9, respectively, connected to ground. The second body 2 includes a first sub-circuit portion 41 and a second sub-circuit portion 42, which are electrically isolated from each other. The first structure 8 includes a first conductor layer 61 located between the first circuit portion 10 and the second circuit portion 20. The second structure 9 includes a second conductor layer 62 that overlaps with a region R20 located between the first sub-circuit portion 41 and the second sub-circuit portion 42. The first conductor layer 61 is not directly connected to the second conductor layer 62.

Description

Technical Field

[0001] The present invention relates to an electronic component including a main body and components mounted on the main body.

Background Art

[0002] In small mobile communication devices, a configuration is widely used in which an antenna commonly used in a plurality of applications having different systems and operating frequency bands is provided, and a plurality of signals transmitted and received by this antenna are separated using a diplexer.

[0003] Generally, a diplexer that separates a first signal having a frequency within a first frequency band and a second signal having a frequency within a second frequency band higher than the first frequency band includes a common port, a first signal port, a second signal port, a first filter provided in a first signal path extending from the common port to the first signal port, and a second filter provided in a second signal path extending from the common port to the second signal port.

[0004] As resonators used in the first and second filters, for example, an LC resonator configured using an inductor and a capacitor, and an elastic wave resonator configured using an elastic wave element are known. An elastic wave element is an element that utilizes an elastic wave. Elastic wave elements include surface acoustic wave elements that utilize surface acoustic waves and bulk acoustic wave elements that utilize bulk acoustic waves. For example, Patent Documents 1 and 2 disclose a diplexer configured using a laminate including an LC resonator and two elastic wave resonators mounted on the upper surface of the laminate.

Prior Art Documents

Patent Documents

[0006] In recent years, there has been a market demand for miniaturization and space saving in small mobile communication devices, and there is also a demand for miniaturization of the demultiplexers used in these communication devices. Here, in a demultiplexer constructed using a laminate, we consider providing a partition connected to ground between the first element included in the first filter and the second element included in the second filter in order to suppress coupling between the first element and the second element. This partition may be a structure composed of multiple conductor layers and multiple through holes. When the demultiplexer is miniaturized, the distance between each of the first and second elements and the partition decreases. As a result, unintended current flow may occur between the first or second element and other elements through the partition, making it impossible to achieve the desired characteristics.

[0007] The above problem applies not only to demultiplexers but to all electronic components containing multiple elements separated from each other by partitions. In particular, in electronic components where a second body is mounted on a first body, such as the demultiplexers described in Patent Documents 1 and 2, if an unintended current flow occurs between the elements of the first body and the elements of the second body, it becomes more difficult to achieve the desired characteristics.

[0008] The present invention has been made in view of the above problems, and its object is to provide an electronic component in which a second body is mounted on a first body, and which can suppress the deterioration of characteristics that occurs with miniaturization. [Means for solving the problem]

[0009] The electronic component of the present invention comprises a first body including a plurality of stacked dielectric layers, and a second body mounted on the first body. The first body further includes a first circuit portion, a second circuit portion, and a first structure and a second structure connected to ground, respectively. The second body includes a first sub-circuit portion and a second sub-circuit portion that are electrically isolated from each other. The first structure includes a first conductor layer located between the first circuit portion and the second circuit portion when viewed from the stacking direction of the plurality of dielectric layers. The second structure includes a second conductor layer that overlaps with the region located between the first sub-circuit portion and the second sub-circuit portion when viewed from the stacking direction. The first conductor layer is not directly connected to the second conductor layer. [Effects of the Invention]

[0010] In the electronic component of the present invention, the first conductor layer of the first structure is not directly connected to the second conductor layer of the second structure. As a result, according to the present invention, it is possible to suppress the deterioration of characteristics that occurs with miniaturization. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram showing the configuration of an electronic component according to one embodiment of the present invention. [Figure 2] This is a perspective view showing an electronic component according to one embodiment of the present invention. [Figure 3] This is a perspective view showing the first body in one embodiment of the present invention. [Figure 4] This is a plan view showing the first body in one embodiment of the present invention. [Figure 5] This is a plan view showing a part of the interior of the first body in one embodiment of the present invention. [Figure 6] This is a perspective view showing a part of the interior of the first body in one embodiment of the present invention. [Figure 7] This is a plan view showing a portion of the interior of the first body of the comparative electronic component. [Figure 8]This is a circuit diagram showing the circuit configuration in the model of the embodiment used in the simulation. [Figure 9] This characteristic diagram shows the frequency characteristics of the isolation of the model in the example and the model in the comparative example, as determined by simulation. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, with reference to Figure 1, the general configuration of an electronic component 100 according to one embodiment of the present invention will be described. Figure 1 is a block diagram showing the configuration of the electronic component 100.

[0013] The electronic component 100 according to this embodiment is a triplexer comprising a first filter 4, a second filter 5, and a third filter 6. The first filter 4 is configured to selectively pass a first signal with a frequency within a first passband. The second filter 5 is configured to selectively pass a second signal with a frequency within a second passband that is different from the first passband. The third filter 6 is configured to selectively pass a third signal with a frequency within a third passband that is different from both the first and second passbands. In this embodiment in particular, the second passband has a higher frequency band than the first passband, and the third passband has a lower frequency band than the first passband.

[0014] The first filter 4 includes the first circuit section 10. The second filter 5 includes the second circuit section 20. The third filter 6 includes the third circuit section 30. The first circuit section 10, the second circuit section 20, and the third circuit section 30 are each LC circuits including at least one inductor and at least one capacitor.

[0015] The first filter 4 further includes a first sub-circuit portion 41. The second filter 5 further includes a second sub-circuit portion 42. The first circuit portion 10 is connected to the first sub-circuit portion 41. The second circuit portion 20 is connected to the second sub-circuit portion 42. The first and second sub-circuit portions 41, 42 are electrically separated from each other. Also, the first and second sub-circuit portions 41, 42 are each constituted by using at least one elastic wave element. The elastic wave element may be, for example, a bulk elastic wave element or a surface acoustic wave element. The first and second sub-circuit portions 41, 42 may each be an elastic wave resonator.

[0016] The first circuit portion 10 and the first sub-circuit portion 41 constitute one filter circuit (the first filter 4). The second circuit portion 20 and the second sub-circuit portion 42 constitute another filter circuit (the second filter 5).

[0017] The electronic component 100 further includes a common terminal 1a, a first signal terminal 1b, a second signal terminal 1c, and a third signal terminal 1d. The first filter 4 is provided between the common terminal 1a and the first signal terminal 1b in terms of circuit configuration. The second filter 5 is provided between the common terminal 1a and the second signal terminal 1c in terms of circuit configuration. The third filter 6 is provided between the common terminal 1a and the third signal terminal 1d in terms of circuit configuration. In the present application, the expression "in terms of circuit configuration" is used to refer to the arrangement on the circuit diagram rather than the arrangement in the physical configuration.

[0018] Next, referring to FIGS. 1 to 3, the configuration of the electronic component 100 will be specifically described. FIG. 2 is a perspective view showing the electronic component 100. FIG. 3 is a perspective view showing the first main body in the present embodiment. As shown in FIG. 2, the electronic component 100 includes a first main body 1, a second main body 2 mounted on the first main body 1, and a sealing portion 3 that seals the first and second main bodies 1, 2. The sealing portion 3 is constituted by, for example, resin.

[0019] The first body 1 includes the first circuit section 10, the second circuit section 20, and the third circuit section 30 shown in Figure 1. The first body 1 also includes a laminate 50. The laminate 50 includes a plurality of stacked dielectric layers, a plurality of conductor layers formed on these dielectric layers, and a plurality of through-holes. Each LC circuit of the first circuit section 10, the second circuit section 20, and the third circuit section 30 is constructed using a plurality of dielectric layers, a plurality of conductor layers, and a plurality of through-holes.

[0020] Each of the through-holes is formed by filling the through-hole with conductive paste. Each of the through-holes is connected to an electrode, a conductive layer, or another through-hole.

[0021] The laminate 50 has a first surface 50A and a second surface 50B located at both ends in the stacking direction of the multiple dielectric layers, and four side surfaces 50C to 50F connecting the first surface 50A and the second surface 50B. Side surfaces 50C and 50D face opposite each other, and side surfaces 50E and 50F also face opposite each other. Side surfaces 50C to 50F are perpendicular to the first surface 50A and the second surface 50B.

[0022] Here, as shown in Figures 2 and 3, we define the X, Y, and Z directions. The X, Y, and Z directions are orthogonal to each other. In this embodiment, the Z direction is defined as one direction parallel to the stacking direction. The Z direction is also one direction parallel to the direction in which the first body 1 and the second body 2 are aligned. Furthermore, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction. In addition, the expression "when viewed from a predetermined direction (for example, the stacking direction)" means viewing the object from a position at a distance in the predetermined direction or one direction parallel to the predetermined direction.

[0023] As shown in Figure 3, the first surface 50A is located at the Z-direction end of the laminate 50. The first surface 50A is also part of the outer surface of the first body 1 on which the second body 2 is mounted, and is the top surface of the laminate 50. The second surface 50B is located at the -Z-direction end of the laminate 50. The second surface 50B is also the surface opposite to the first surface 50A, and is the bottom surface of the laminate 50. The side surface 50C is located at the -X-direction end of the laminate 50. The side surface 50D is located at the X-direction end of the laminate 50. The side surface 50E is located at the -Y-direction end of the laminate 50. The side surface 50F is located at the Y-direction end of the laminate 50.

[0024] The first body 1 further includes a plurality of electrodes 111, 112, 113, 114, 115, 116, 117, 118, and 119 provided on the second surface 50B of the laminate 50. Electrode 111 is positioned near a corner where the second surface 50B intersects with side surfaces 50C and 50E. Electrode 113 is positioned near a corner where the second surface 50B intersects with side surfaces 50D and 50E. Electrode 115 is positioned near a corner where the second surface 50B intersects with side surfaces 50D and 50F. Electrode 117 is positioned near a corner where the second surface 50B intersects with side surfaces 50C and 50F.

[0025] Electrode 112 is positioned between electrode 111 and electrode 113. Electrode 114 is positioned between electrode 113 and electrode 115. Electrode 116 is positioned between electrode 115 and electrode 117. Electrode 118 is positioned between electrode 111 and electrode 117. Electrode 119 is positioned in the center or near the center of the second surface 50B.

[0026] The first main body 1 further includes the common terminal 1a, the first signal terminal 1b, the second signal terminal 1c, and the third signal terminal 1d shown in Figure 1. Electrode 111 corresponds to the third signal terminal 1d, electrode 113 corresponds to the common terminal 1a, electrode 115 corresponds to the second signal terminal 1c, and electrode 117 corresponds to the first signal terminal 1b. Therefore, the common terminal 1a and the first to third signal terminals 1b to 1d are provided on the second surface 50B of the laminate 50. Electrodes 112, 114, 116, 118, and 119 are each connected to ground.

[0027] The first body 1 further includes four electrode pads 121, 122, 123, and 124 provided on the first surface 50A of the laminate 50. The electrode pads 121 to 124 may be located near the center of the first surface 50A. Electrode pads 121 and 122 are arranged in this order in the -Y direction. Electrode pads 123 and 124 are located closer to the X direction than electrode pads 121 and 122, and are arranged in this order in the Y direction.

[0028] The second body 2 includes the first and second sub-circuit sections 41 and 42. The second body 2 also has a third surface 2A and a fourth surface 2B located at both ends in a direction parallel to the Z direction, and four side surfaces 2C to 2F connecting the third surface 2A and the fourth surface 2B. Side surfaces 2C and 2D face opposite each other, and side surfaces 2E and 2F also face opposite each other. Side surfaces 2C to 2F are perpendicular to the third surface 2A and the fourth surface 2B.

[0029] As shown in Figure 2, the third face 2A is located at the Z-direction end of the second body 2. The third face 2A is also the top surface of the second body 2. The fourth face 2B is located at the -Z-direction end of the second body 2. The fourth face 2B is also the face facing the first body 1 and is also the bottom surface of the second body 2. The side surface 2C is located at the -X-direction end of the second body 2. The side surface 2D is located at the X-direction end of the second body 2. The side surface 2E is located at the -Y-direction end of the second body 2. The side surface 2F is located at the Y-direction end of the second body 2.

[0030] The second body 2 further includes a first terminal 2a, a second terminal 2b, a third terminal 2c, and a fourth terminal 2d, which are located on the fourth face 2B of the second body 2. The first terminal 2a is located near the corner where the fourth face 2B intersects with the side 2C and side 2F. The second terminal 2b is located near the corner where the fourth face 2B intersects with the side 2C and side 2E. The third terminal 2c is located near the corner where the fourth face 2B intersects with the side 2D and side 2E. The fourth terminal 2d is located near the corner where the fourth face 2B intersects with the side 2D and side 2F.

[0031] The first sub-circuit section 41 is located between the first terminal 2a and the second terminal 2b in the circuit configuration. The second sub-circuit section 42 is located between the third terminal 2c and the fourth terminal 2d in the circuit configuration.

[0032] When the second body 2 is mounted on the first body 1, the first to fourth terminals 2a, 2b, 2c, and 2d of the second body 2 face the electrode pads 121, 122, 123, and 124 of the first body 1, respectively. The first to fourth terminals 2a, 2b, 2c, and 2d are connected to the electrode pads 121, 122, 123, and 124, respectively, via a conductive bonding material. In this embodiment in particular, the first to fourth terminals 2a, 2b, 2c, and 2d are electrically and physically connected to the electrode pads 121, 122, 123, and 124, respectively, by, for example, solder bumps 7.

[0033] Next, the first body 1 will be described in more detail with reference to Figures 4 to 6. Figure 4 is a plan view showing the first body 1. Figure 5 is a plan view showing a part of the interior of the first body 1. Figure 6 is a perspective view showing a part of the interior of the first body 1.

[0034] The first main body 1 further includes a first structure 8 and a second structure 9, each connected to ground. The second structure 9 is positioned between electrode pads 121 and 124, and between electrode pads 122 and 123, when viewed from the Z direction. Electrode pads 121 and 122 are positioned ahead of the second structure 9 in the -X direction when viewed from the Z direction. Electrode pads 123 and 124 are positioned ahead of the second structure 9 in the X direction when viewed from the Z direction. The first structure 8 is positioned between the second structure 9 and the side surface 50F.

[0035] Here, with reference to Figure 4, the three-dimensional region within the laminate 50 defined by the first and second structures 8, 9 and the interface P is described. The interface P is a virtual plane parallel to the XZ plane and is located between the first and second structures 8, 9 and the side surface 50E. The interface P may be located closer to the second structure 9 than to the side surface 50E.

[0036] The laminate 50 includes a first region R1, a second region R2, and a third region R3. The first region R1 is the region enclosed by the first and second structures 8,9, the sides 50C, 50F, and the boundary surface P. The second region R2 is the region enclosed by the first and second structures 8,9, the sides 50D, 50F, and the boundary surface P. The third region R3 is the region enclosed by the sides 50C, 50D, 50E, and the boundary surface P. In Figure 4, the region enclosed by the dashed line labeled R1 represents the first region R1, the region enclosed by the dashed line labeled R2 represents the second region R2, and the region enclosed by the dashed line labeled R3 represents the third region R3. The first and second structures 8 and 9 are used as partitions to separate the first region R1 and the second region R2.

[0037] The first region R1 is a region that includes at least a portion of the first circuit portion 10 but does not include the second circuit portion 20. The second region R2 is a region that includes at least a portion of the second circuit portion 20 but does not include the first circuit portion 10. The third region R3 is a region that includes the third circuit portion 30. The third region R3 may or may not include the other portion of the first circuit portion 10 and the other portion of the second circuit portion 20.

[0038] Next, the structures of the first and second structures 8 and 9 will be described with reference to Figures 5 and 6. The first structure 8 includes a plurality of first through-holes 71 and a plurality of first conductor layers 61 electrically connected to the plurality of first through-holes 71. Each of the plurality of first conductor layers 61 is positioned at a different location from each other in a direction parallel to the stacking direction, i.e., the Z direction. The second structure 9 includes a plurality of second through-holes 72 and a plurality of second conductor layers 62 electrically connected to the plurality of second through-holes 72. Each of the plurality of second conductor layers 62 is positioned at a different location from each other in a direction parallel to the stacking direction, i.e., the Z direction.

[0039] Each of the plurality of first conductor layers 61 and the plurality of second conductor layers 62 includes a portion that extends along the same direction, which is perpendicular to the lamination direction. In particular in this embodiment, each of the plurality of first conductor layers 61 and the plurality of second conductor layers 62 extends as a whole along a direction parallel to the Y direction.

[0040] Furthermore, the shapes of the multiple first conductor layers 61 are the same. The arrangement of the multiple first conductor layers 61 is the same, except for their position in the stacking direction. Two adjacent first conductor layers 61 spaced apart in the stacking direction are connected to each other by at least one first through-hole 71. In the example shown in Figures 5 and 6, the two first conductor layers 61 are connected to each other by three first through-holes 71.

[0041] Furthermore, the shapes of the multiple second conductor layers 62 are the same. The arrangement of the multiple second conductor layers 62 is the same, except for their position in the stacking direction. Two adjacent second conductor layers 62 spaced apart in the stacking direction are connected to each other by at least one second through-hole 72. In the example shown in Figures 5 and 6, the two second conductor layers 62 are connected to each other by three second through-holes 72.

[0042] The plurality of first conductor layers 61 include a specific first conductor layer 61. The specific first conductor layer 61 may be, for example, the conductor layer closest to the first surface 50A among the plurality of first conductor layers 61. Since the plurality of first conductor layers 61 are components of the first structure 8, it can also be said that the first structure 8 includes a specific first conductor layer 61. In Figure 5, reference numeral 61 indicates a specific first conductor layer 61.

[0043] The multiple second conductor layers 62 include a specific second conductor layer 62. The specific second conductor layer 62 may be, for example, the conductor layer closest to the first surface 50A among the multiple second conductor layers 62. Since the multiple second conductor layers 62 are components of the second structure 9, it can also be said that the second structure 9 includes a specific second conductor layer 62. In Figure 5, reference numeral 62 indicates a specific second conductor layer 62.

[0044] A specific first conductor layer 61 and a specific second conductor layer 62 are located between the first region R1 and the second region R2, and between the first circuit portion 10 and the second circuit portion 20, when viewed from the stacking direction (parallel to the Z direction). As shown in Figure 5, the specific first conductor layer 61 is not directly connected to the specific second conductor layer 62.

[0045] In this embodiment, the above description of a specific first conductor layer 61 also applies to first conductor layers 61 other than the specific first conductor layer 61. Similarly, the above description of a specific second conductor layer 62 also applies to second conductor layers 62 other than the specific second conductor layer 62. The first conductor layer 61 is not directly connected to a second conductor layer 62 located at the same position in the stacking direction.

[0046] Next, with reference to Figures 4 to 6, the features of the first and second structures 8, 9 and the first and second circuit portions 10, 20 will be described. Each of the first and second circuit portions 10, 20 includes at least one inductor and at least one capacitor. In this embodiment, the first circuit portion 10 includes inductors L1, L2 and a capacitor C1. The second circuit portion 20 includes inductors L3, L4 and a capacitor C2.

[0047] Inductors L1 and L2 are located in the first region R1. Inductor L2 is located between the second structure 9 and the side surface 50C. Inductor L1 is located between inductor L2 and the side surface 50F, as well as between the first structure 8 and the side surface 50C.

[0048] Inductors L3 and L4 are located in the second region R2. Inductor L3 is located between the second structure 9 and side surface 50D. Inductor L4 is located between inductor L3 and side surface 50F, as well as between the first structure 8 and side surface 50D.

[0049] The first structure 8 is positioned between inductors L1 and L4 when viewed from the Z direction. The second structure 9 is positioned between inductors L2 and L3 when viewed from the Z direction.

[0050] Capacitor C1 is located between inductor L1 and the second surface 50B. Capacitor C2 is located between inductor L4 and the second surface 50B.

[0051] The first body 1 further includes a ground conductor layer 91 connected to ground. The ground conductor layer 91 is electrically connected to at least one of the electrodes 112, 114, 116, 118, and 119 connected to ground.

[0052] The first and second structures 8 and 9 are connected to the ground conductor layer 91. In this embodiment in particular, at least one of the plurality of first through-holes 71 and at least one of the plurality of second through-holes 72 are connected to the ground conductor layer 91.

[0053] When viewed from the Z direction, the ground conductor layer 91 overlaps with at least a portion of at least one of the first circuit portion 10 and the second circuit portion 20. In particular, in this embodiment, when viewed from the Z direction, the ground conductor layer 91 overlaps with the entirety of each of the inductors L1 to L4.

[0054] The first body 1 further includes capacitor conductor layers 92 and 93 disposed within the laminate 50. Each of the capacitor conductor layers 92 and 93 faces the ground conductor layer 91 via at least one dielectric layer. Capacitor C1 is composed of the ground conductor layer 91 and the capacitor conductor layer 92, and at least one dielectric layer interposed between the ground conductor layer 91 and the capacitor conductor layer 92. Capacitor C2 is composed of the ground conductor layer 91 and the capacitor conductor layer 93, and at least one dielectric layer interposed between the ground conductor layer 91 and the capacitor conductor layer 93. The capacitor conductor layer 92 is disposed between the inductor L1 and the ground conductor layer 91. The capacitor conductor layer 93 is disposed between the inductor L4 and the ground conductor layer 91.

[0055] The first main body 1 may further include a third structure (not shown) that separates a part of the first circuit portion 10 from a part of the third circuit portion 30, and a fourth structure (not shown) that separates a part of the second circuit portion 20 from the other part of the third circuit portion 30. The third and fourth structures may be directly or indirectly connected to the ground conductor layer 91. The third and fourth structures may or may not be directly connected to each other.

[0056] Next, with reference to Figures 2 to 5, the features of the first and second structures 8 and 9 and the second body 2 will be described. As mentioned above, the first to fourth terminals 2a, 2b, 2c, and 2d of the second body 2 are connected to the electrode pads 121, 122, 123, and 124 of the first body 1 via a conductive bonding material, respectively. The second structure 9 is positioned between electrode pads 121 and 124, and between electrode pads 122 and 123, when viewed from the Z direction. Therefore, the second structure 9 is positioned between the first terminal 2a and the fourth terminal 2d, and between the second terminal 2b and the third terminal 2c, when viewed from the Z direction.

[0057] Furthermore, when viewed from the Z direction, the electrode pads 121 and 122 are positioned ahead of the second structure 9 in the -X direction. Therefore, when viewed from the Z direction, the first and second terminals 2a and 2b are positioned ahead of the second structure 9 in the -X direction.

[0058] Furthermore, the electrode pads 123 and 124 are positioned ahead of the second structure 9 in the X direction. Therefore, the third and fourth terminals 2c and 2d are positioned ahead of the second structure 9 in the X direction when viewed from the Z direction.

[0059] As mentioned above, the first sub-circuit portion 41 is located between the first terminal 2a and the second terminal 2b in terms of the circuit configuration. Although not shown in the diagram, at least a portion of the first sub-circuit portion 41 is positioned ahead of the second structure 9 in the -X direction when viewed from the Z direction.

[0060] Furthermore, as mentioned above, the second sub-circuit portion 42 is located between the third terminal 2c and the fourth terminal 2d in terms of the circuit configuration. Although not shown in the diagram, at least a portion of the second sub-circuit portion 42 is positioned ahead of the second structure 9 in the X direction when viewed from the Z direction.

[0061] In Figure 4, the rectangular region denoted by R20 indicates the region located between the first sub-circuit portion 41 and the second sub-circuit portion 42 in the second main body 2. Region R20 may be a three-dimensional region or a two-dimensional region. Region R20 may also be located between a part of the first sub-circuit portion 41 and a part of the second sub-circuit portion 42. A specific second conductor layer 62 of the second structure 9 overlaps with region R20 when viewed from the Z direction.

[0062] As shown in Figure 4, the second structure 9 may protrude outside the second body 2 when viewed from the Z direction, that is, on the Y direction side and the -Y direction side of the second body 2.

[0063] A specific first conductor layer 61 of the first structure 8 does not overlap with region R20 when viewed from the Z direction. As long as the requirement that the specific first conductor layer 61 does not overlap with region R20 is met, the first structure 8 may or may not overlap with the second body 2 when viewed from the Z direction. As shown in Figure 4, in this embodiment, a specific first conductor layer 61 of the first structure 8 does not overlap with the second body 2 when viewed from the Z direction.

[0064] Next, the characteristics of inductors L1 to L4 will be described with reference to Figures 5 and 6. Inductor L1 includes at least one inductor conductor layer wound around an axis extending in a direction parallel to the lamination direction, such that an opening surrounded by inductor L1 is formed. Hereinafter, the opening surrounded by inductor L1 or at least one inductor conductor layer of inductor L1 will be referred to as the opening of inductor L1. The opening of inductor L1 faces the first surface 50A of the laminate 50. Furthermore, the entire opening of inductor L1 is located in the first region R1. Hereinafter, for inductors other than inductor L1, the opening surrounded by that inductor or at least one inductor conductor layer of that inductor will be referred to as the opening of that inductor.

[0065] Similarly, each of the inductors L2, L3, and L4 includes at least one inductor conductor layer wound around an axis extending in a direction parallel to the lamination direction, such that an opening is formed surrounded by each of the inductors L2, L3, and L4. Each opening of the inductors L2, L3, and L4 faces the first surface 50A of the laminate 50. The entire opening of inductor L2 lies within the first region R1. The entire openings of inductors L3 and L4 lies within the second region R2.

[0066] The inductor L1 includes a plurality of inductor conductor layers 81, which are arranged at predetermined intervals in the stacking direction, as at least one inductor conductor layer. Each of the plurality of inductor conductor layers 81 is wound around an axis extending in a direction parallel to the stacking direction so as to surround the opening of the inductor L1. The first body 1 further includes a conductor layer 85 connected to the first specific inductor conductor layer 81 that is closest to the first surface 50A, and a through-hole T1 connecting the conductor layer 85 to the electrode pad 121. In Figure 5, the boundary between the first specific inductor conductor layer 81 and the conductor layer 85 is shown by a dotted line.

[0067] The inductor L1 may or may not be connected to the capacitor C1. If the inductor L1 is connected to the capacitor C1, the first body 1 may further include through-holes (not shown) connecting a second specific inductor conductor layer 81, which is closest to the second surface 50B of the plurality of inductor conductor layers 81, to a capacitor conductor layer 92.

[0068] The inductor L2 includes a plurality of inductor conductor layers 82, each arranged at a predetermined interval in the stacking direction, as at least one inductor conductor layer. Each of the plurality of inductor conductor layers 82 is wound around an axis extending in a direction parallel to the stacking direction so as to surround the opening of the inductor L2. The first body 1 further includes a conductor layer 86 connected to the first specific inductor conductor layer 82 closest to the first surface 50A among the plurality of inductor conductor layers 82, and a through-hole T2 connecting the conductor layer 86 to the electrode pad 122. In Figure 5, the boundary between the inductor conductor layer 82 and the conductor layer 86 is shown by a dotted line.

[0069] The inductor L2 may or may not be connected to ground. If the inductor L2 is connected to ground, the first body 1 may further include a number of through-holes (not shown) that connect a second specific inductor conductor layer 82, which is closest to the second surface 50B of the plurality of inductor conductor layers 82, to the ground conductor layer 91.

[0070] The inductor L3 includes a plurality of inductor conductor layers 83, which are arranged at predetermined intervals in the stacking direction, as at least one inductor conductor layer. Each of the plurality of inductor conductor layers 83 is wound around an axis extending in a direction parallel to the stacking direction so as to surround the opening of the inductor L3. The first body 1 further includes a conductor layer 87 connected to the first specific inductor conductor layer 83 that is closest to the first surface 50A among the plurality of inductor conductor layers 83, and a through-hole T3 connecting the conductor layer 87 to the electrode pad 123. In Figure 5, the boundary between the inductor conductor layer 83 and the conductor layer 87 is shown by a dotted line.

[0071] The inductor L3 may or may not be connected to ground. If the inductor L3 is connected to ground, the first body 1 may further include a number of through-holes (not shown) connecting a second specific inductor conductor layer 83, which is closest to the second surface 50B of the plurality of inductor conductor layers 83, to the ground conductor layer 91.

[0072] The inductor L4 includes a plurality of inductor conductor layers 84, each arranged at predetermined intervals in the stacking direction, as at least one inductor conductor layer. Each of the plurality of inductor conductor layers 84 is wound around an axis extending in a direction parallel to the stacking direction so as to surround the opening of the inductor L4. The first body 1 further includes a conductor layer 88 connected to a first specific inductor conductor layer 84 that is closest to the first surface 50A, and a through-hole T4 connecting the conductor layer 88 to the electrode pad 124. In Figure 5, the boundary between the inductor conductor layer 84 and the conductor layer 88 is shown by a dotted line.

[0073] The inductor L4 may or may not be connected to the capacitor C2. If the inductor L4 is connected to the capacitor C2, the first body 1 may further include through holes (not shown) connecting a second specific inductor conductor layer 84, which is closest to the second surface 50B of the plurality of inductor conductor layers 84, to a capacitor conductor layer 93.

[0074] Inductor L1 is connected to the first sub-circuit section 41 of the second body 2 via a conductor layer 85, a through-hole T1, an electrode pad 121, and a first terminal 2a. Inductor L2 is connected to the first sub-circuit section 41 of the second body 2 via a conductor layer 86, a through-hole T2, an electrode pad 122, and a second terminal 2b. Inductor L3 is connected to the second sub-circuit section 42 of the second body 2 via a conductor layer 87, a through-hole T3, an electrode pad 123, and a third terminal 2c. Inductor L4 is connected to the second sub-circuit section 42 of the second body 2 via a conductor layer 88, a through-hole T4, an electrode pad 124, and a fourth terminal 2d.

[0075] The multiple inductor conductor layers 81 of inductor L1, a specific first conductor layer 61, and the multiple inductor conductor layers 84 of inductor L4 are arranged in this order along a first direction perpendicular to the stacking direction. In this embodiment in particular, the multiple inductor conductor layers 81, the specific first conductor layer 61, and the multiple inductor conductor layers 84 are arranged in this order along the X direction. The dimensions of the specific first conductor layer 61 in a second direction (Y direction) perpendicular to each of the stacking direction and the first direction (X direction) may be larger than the dimensions in the second direction (Y direction) of the opening surrounded by each of the multiple inductor conductor layers 81 and the dimensions in the second direction (Y direction) of the opening surrounded by each of the multiple inductor conductor layers 84.

[0076] Furthermore, the multiple inductor conductor layers 82 of inductor L2, a specific second conductor layer 62, and the multiple inductor conductor layers 83 of inductor L3 may be arranged in this order along a first direction perpendicular to the stacking direction. In this embodiment in particular, the multiple inductor conductor layers 82, the specific second conductor layer 62, and the multiple inductor conductor layers 83 are arranged in this order along the X direction. The dimensions of the specific second conductor layer 62 in a second direction (Y direction) perpendicular to each of the stacking direction and the first direction (X direction) may be larger than the dimensions in the second direction (Y direction) of the opening surrounded by each of the multiple inductor conductor layers 82 and the dimensions in the second direction (Y direction) of the opening surrounded by each of the multiple inductor conductor layers 83.

[0077] Next, the operation and effects of the electronic component 100 according to this embodiment will be described. The first body 1 includes first and second circuit portions 10, 20 and first and second structures 8, 9. The second body 2 includes first and second sub-circuit portions 41, 42. The first sub-circuit portion 41 and the second sub-circuit portion 42 are electrically isolated from each other. The first structure 8 includes a specific first conductor layer 61 located between the first circuit portion 10 and the second circuit portion 20 when viewed from the Z direction. The second structure 9 includes a specific second conductor layer 62 that overlaps with a region R20 located between the first sub-circuit portion 41 and the second sub-circuit portion 42 when viewed from the Z direction. The specific first conductor layer 61 is not directly connected to the specific second conductor layer 62. In this embodiment, in particular, the multiple first conductor layers 61 other than the specific first conductor layer 61 are not directly connected to the multiple second conductor layers 62, including the specific second conductor layer 62. As a result, according to this embodiment, deterioration of characteristics associated with miniaturization can be suppressed.

[0078] The effects of the electronic component 100 according to this embodiment will be explained below in comparison with the electronic component of the comparative example. First, the electronic component of the comparative example will be described. Figure 7 is a plan view showing a part of the first body of the electronic component of the comparative example.

[0079] The configuration of the comparative electronic component differs from that of the electronic component 100 according to this embodiment in the following respects: The comparative electronic component includes a first body 101 instead of the first body 1 in this embodiment. The first body 101 includes a structure 18 connected to ground instead of the first and second structures 8 and 9 in this embodiment. The structure 18 includes a plurality of through-holes 171 and a plurality of conductor layers 161 electrically connected to the plurality of through-holes 171. The other configurations of the comparative electronic component are the same as those of the electronic component 100 according to this embodiment.

[0080] Each of the multiple conductor layers 161 includes a first portion, a second portion, and a third portion connecting the first and second portions. The multiple conductor layers 161 also include a specific conductor layer 161 closest to the first surface 50A of the laminate 50. The shape and arrangement of the first portion of the specific conductor layer 161 is substantially the same as the shape and arrangement of the specific first conductor layer 61 of the first structure 8 in this embodiment. The shape and arrangement of the second portion of the specific conductor layer 161 is substantially the same as the shape and arrangement of the specific second conductor layer 62 of the second structure 9 in this embodiment.

[0081] The shapes of the first to third portions of each of the multiple conductor layers 161 other than the specific conductor layer 161 are the same as the shapes of the first to third portions of the specific conductor layer 161. The arrangement of the first to third portions of each of the multiple conductor layers 161 other than the specific conductor layer 161 is the same as the arrangement of the first to third portions of the specific conductor layer 161, except for their position in the stacking direction (direction parallel to the Z direction).

[0082] In the comparative example, each first portion of the multiple conductor layers 161 is positioned between the inductor L1 of the first circuit portion 10 of the first body 101 and the inductor L4 of the second circuit portion 20. Each second portion of the multiple conductor layers 161 is positioned between the inductor L2 of the first circuit portion 10 of the first body 1 and the inductor L3 of the second circuit portion 20. Furthermore, each second portion of the multiple conductor layers 161 overlaps with the region R20 (see Figure 4) located between the first sub-circuit portion 41 and the second sub-circuit portion 42 in the second body 2 when viewed from the Z direction. Each second portion of the multiple conductor layers 161 is positioned between at least a part of the first sub-circuit portion 41 and at least a part of the second sub-circuit portion 42 when viewed from the Z direction.

[0083] The first sub-circuit section 41 and the second sub-circuit section 42 are electrically isolated from each other. Furthermore, the second portion of each of the multiple conductor layers 161 suppresses coupling between the inductor L2 connected to the first sub-circuit section 41 and the inductor L3 connected to the second sub-circuit section 42. This achieves the desired characteristics.

[0084] Incidentally, when the laminate 50 is miniaturized, depending on the shape and arrangement of the inductor L1, the inductor L1 may couple with the first portion of each of the multiple conductor layers 161. In the comparative example, since the first portion and the second portion of each of the multiple conductor layers 161 are connected by the third portion, unintended current flows may occur between inductor L1 and inductor L2, and between inductor L1 and inductor L3. Furthermore, unintended current flows may also occur between inductor L1 and the second sub-circuit portion 42. As a result, the isolation characteristics between the first filter 4 and the second filter 5 may deteriorate.

[0085] Similarly, as the laminate 50 is miniaturized, depending on the shape and arrangement of the inductor L4, the inductor L4 may couple with the first portion of each of the multiple conductor layers 161. In the comparative example, since the first and second portions of each of the multiple conductor layers 161 are connected by the third portion, unintended current flows may occur between inductor L2 and inductor L4, and between inductor L3 and inductor L4. Furthermore, unintended current flows may also occur between inductor L4 and the first sub-circuit portion 41. As a result, the isolation characteristics between the first filter 4 and the second filter 5 may deteriorate.

[0086] In contrast, in this embodiment, as described above, a specific first conductor layer 61 of the first structure 8 is not directly connected to a specific second conductor layer 62 of the second structure 9. In particular, in this embodiment, multiple first conductor layers 61 other than the specific first conductor layer 61 are not directly connected to multiple second conductor layers 62, including the specific second conductor layer 62. As a result, according to this embodiment, the occurrence of unintended current flow associated with the miniaturization of the laminate 50 can be suppressed. Consequently, according to this embodiment, the deterioration of isolation characteristics associated with miniaturization can be suppressed.

[0087] Next, we will describe the results of a simulation that investigated the isolation characteristics of the electronic component 100 according to this embodiment. First, we will describe the model of the embodiment used in the simulation. The model of the embodiment is a model of the electronic component 100 according to this embodiment. In the simulation, the first circuit portion 10 and the first sub-circuit portion 41 of the first filter 4, the second circuit portion 20 and the second sub-circuit portion 42 of the second filter 5, and the third circuit portion 30 of the third filter 6 were designed so that the model of the embodiment would operate as a demultiplexer.

[0088] Figure 8 is a circuit diagram showing the circuit configuration of the embodiment model. The embodiment model includes an inductor L41 and a capacitor C41 in addition to the first to third filters 4 to 6. One end of the inductor L41 is connected to the common terminal 1a. One end of the third filter 6 and one end of the capacitor C41 are connected to the other end of the inductor L41. The other end of the third filter is connected to the third signal terminal 1d.

[0089] One end of the first filter 4 and the second filter 5 are connected to the other end of capacitor C41. The other end of the first filter 4 is connected to the first signal terminal 1b. The other end of the second filter 5 is connected to the second signal terminal 1c.

[0090] The third circuit section 30 of the third filter 6 includes inductors L31 and L32, and capacitors C31, C32, and C33. One end of inductor L31 is connected to the other end of inductor L41. One end of inductor L32 is connected to the other end of inductor L31. The other end of inductor L32 is connected to the third signal terminal 1d.

[0091] Capacitor C31 is connected in parallel with inductor L32. One end of capacitor C32 is connected to the connection point between inductor L31 and inductor L32. One end of capacitor C33 is connected to the other end of inductor L32. The other ends of capacitors C32 and C33 are connected to ground.

[0092] The first circuit portion 10 of the first filter 4 includes inductors L11, L12, L13, L14, L15, L16 and capacitors C11, C12, C13, C14. The first sub-circuit portion 41 of the first filter 4 includes four elastic wave elements 411, 412, 413, 414.

[0093] One end of inductor L11 is connected to the other end of capacitor C41. One end of inductor L12 is connected to the other end of inductor L11. One end of capacitor C11 is connected to the other end of inductor L12. The other end of capacitor C11 is connected to the first terminal 2a of the second body 2.

[0094] One end of inductor L13 is connected to the junction point of inductors L11 and L12. One end of capacitor C12 is connected to the other end of inductor L13. The other end of capacitor C12 is connected to ground.

[0095] One end of inductor L14 is connected to the other end of capacitor C11 and to the first terminal 2a of the second body 2. One end of capacitor C13 is connected to the other end of inductor L14. The other end of capacitor C13 is connected to ground.

[0096] One end of each elastic wave element 411 and 413 is connected to the first terminal 2a. One end of elastic wave element 412 is connected to the other end of elastic wave element 411. One end of elastic wave element 414 is connected to the other end of elastic wave element 413. The other ends of each elastic wave element 412 and 414 are connected to the second terminal 2b of the second body 2.

[0097] One end of inductors L15 and L16 is connected to the second terminal 2b. The other end of inductor L15 is connected to the first signal terminal 1b. The other end of inductor L16 is connected to ground.

[0098] One end of capacitor C14 is connected to one end of inductor L15. The other end of capacitor C14 is connected to ground.

[0099] The second circuit section 20 of the second filter 5 includes inductors L21, L22, L23 and capacitors C21, C22, C23, C24, C25, C26. The second sub-circuit section 42 of the second filter 5 includes four elastic wave elements 421, 422, 423, 424.

[0100] One end of capacitor C21 is connected to the other end of capacitor C41. The other end of capacitor C21 and one end of inductor L21 are connected to the third terminal 2c of the second body 2. One end of capacitor C22 is connected to the other end of inductor L21. The other end of capacitor C22 is connected to ground.

[0101] One end of each elastic wave element 421 and 423 is connected to the third terminal 2c. One end of elastic wave element 422 is connected to the other end of elastic wave element 421. One end of elastic wave element 424 is connected to the other end of elastic wave element 423. The other ends of each elastic wave element 422 and 424 are connected to the fourth terminal 2d of the second body 2.

[0102] One end each of capacitor C23 and inductor L23 is connected to the fourth terminal 2d. One end of inductor L22 is connected to the other end of capacitor C23. The other end of inductor L22 is connected to the second signal terminal 1c. Capacitor C24 is connected in parallel with inductor L22.

[0103] One end of capacitor C25 is connected to the other end of inductor L23. The other end of capacitor C25 is connected to ground.

[0104] One end of capacitor C26 is connected to the other end of inductor L22. The other end of capacitor C26 is connected to ground.

[0105] The multiple inductors and multiple capacitors shown in Figure 8 are constructed using multiple dielectric layers, multiple conductor layers, and multiple through-holes in the laminate 50.

[0106] Note that inductors L14 and L16 may correspond to "Inductor L1" and "Inductor L2" shown in Figures 5 and 6, respectively. In this case, capacitor C13 may correspond to "Capacitor C1" shown in Figures 5 and 6.

[0107] Furthermore, inductors L21 and L23 may correspond to "inductor L3" and "inductor L4" shown in Figures 5 and 6, respectively. In this case, capacitor C25 may correspond to "capacitor C2" shown in Figures 5 and 6.

[0108] Next, we will describe the comparative example model used in the simulation. The comparative example model is a model of the comparative electronic components. In particular, the comparative example model has a structure 18 connected to ground instead of the first and second structures 8 and 9. The circuit configuration of the comparative example model is the same as the circuit configuration of the embodiment model shown in Figure 8.

[0109] Next, the simulation results will be explained. In the simulation, the frequency characteristics of the isolation between the first filter 4 and the second filter 5 were determined for both the example model and the comparative example model. The definition of isolation in the simulation is as follows: When a high-frequency signal with power P1 is input to the first signal terminal 1b, P2 is the power of the signal output from the second signal terminal 1c. Isolation I is defined by the following equation (1).

[0110] I = 10log(P2 / P1) …(1)

[0111] Figure 9 is a characteristic diagram showing the frequency characteristics of isolation. In Figure 9, the horizontal axis represents frequency, and the vertical axis represents isolation. In Figure 9, the curve labeled 301 shows the frequency characteristics of isolation in the model of the embodiment. The curve labeled 302 shows the frequency characteristics of isolation in the model of the comparative example. As shown in Figure 9, the absolute value of isolation is larger in the model of the embodiment (301) compared to the model of the comparative example (302). As can be understood from the simulation results, according to this embodiment, the isolation can be sufficiently large by the first and second structures 8 and 9.

[0112] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are possible. For example, the electronic component of the present invention may be a diplexer equipped with two filters, or a bandpass filter equipped with multiple filters.

[0113] As described above, the electronic component of the present invention comprises a first body including a plurality of stacked dielectric layers, and a second body mounted on the first body. The first body further includes a first circuit portion, a second circuit portion, and a first structure and a second structure connected to ground, respectively. The second body includes a first sub-circuit portion and a second sub-circuit portion that are electrically isolated from each other. The first structure includes a first conductor layer located between the first circuit portion and the second circuit portion when viewed from the stacking direction of the plurality of dielectric layers. The second structure includes a second conductor layer that overlaps with the region located between the first sub-circuit portion and the second sub-circuit portion when viewed from the stacking direction. The first conductor layer is not directly connected to the second conductor layer.

[0114] In the electronic component of the present invention, the first conductive layer does not need to overlap with the second body when viewed from the stacking direction.

[0115] Furthermore, in the electronic component of the present invention, each of the first structure and the second structure may further include a plurality of through-holes and a plurality of conductive layers electrically connected to the plurality of through-holes. The plurality of conductive layers of the first structure may include a first conductive layer. The plurality of conductive layers of the second structure may include a second conductive layer.

[0116] Furthermore, in the electronic component of the present invention, the first body may further include a ground conductor layer connected to ground. The first structure and the second structure may be arranged between the second body and the ground conductor layer in the stacking direction and connected to the ground conductor layer. The ground conductor layer may overlap with at least a portion of at least one of the first circuit portion and the second circuit portion when viewed from the stacking direction. The first circuit portion may include a first inductor including a first inductor conductor layer wound around a first axis parallel to the stacking direction. The second circuit portion may include a second inductor including a second inductor conductor layer wound around a second axis parallel to the stacking direction. The first inductor conductor layer, the first conductor layer, and the second inductor conductor layer may be arranged in this order along a first direction perpendicular to the stacking direction. The dimensions of the first conductor layer in a second direction perpendicular to the lamination direction and the first direction may be greater than the dimensions of the opening surrounded by the first inductor conductor layer in the second direction and the dimensions of the opening surrounded by the second inductor conductor layer in the second direction.

[0117] Furthermore, in the electronic component of the present invention, the first circuit portion may be connected to the first sub-circuit portion. The second circuit portion may be connected to the second sub-circuit portion.

[0118] Furthermore, the electronic component of the present invention may further include a first filter that selectively passes signals with frequencies within a first passband, and a second filter that selectively passes signals with frequencies within a second passband different from the first passband. The first filter may include a first circuit portion and a first sub-circuit portion. The second filter may include a second circuit portion and a second sub-circuit portion.

[0119] Furthermore, the electronic component of the present invention may further include a third filter that selectively passes signals with frequencies within a third passband that is different from each of the first and second passbands.

[0120] Furthermore, in the electronic component of the present invention, the first conductive layer and the second conductive layer may each include portions that extend in the same direction, perpendicular to the lamination direction. [Explanation of symbols]

[0121] 1...First main body, 1a...Common terminal, 1b...First signal terminal, 1c...Second signal terminal, 1d...Third signal terminal, 2...Second main body, 2a...First terminal, 2b...Second terminal, 2c...Third terminal, 2d...Fourth terminal, 3...Sealing part, 4...First filter, 5...Second filter, 6...Third filter, 7...Solder bump, 8...First structure, 9...Second structure, 10...First circuit section, 20...Second circuit section, 30...Third circuit section, 41...First sub-circuit section, 42...Second Subcircuit section 2: 50...Laminate, 50A...First surface, 50B...Second surface, 50C~50F...Side, 61...First conductor layer, 62...Second conductor layer, 71...First through-hole, 72...Second through-hole, 81~84...Conductor layer for inductor, 91...Conductor layer for ground, 92,93...Conductor layer for capacitor, 100...Electronic component, 111~119...Electrodes, 121~124...Electrode pads, C1,C2...Capacitors, L1~L4...Inductors, T1~T4...Through-holes.

Claims

1. A first body comprising multiple stacked dielectric layers, The system comprises a second body mounted on the first body, The first main body further includes a first circuit portion, a second circuit portion, and a first structure and a second structure, respectively, connected to ground. The second body includes a first subcircuit section and a second subcircuit section that are electrically isolated from each other. The first structure includes a first conductor layer located between the first circuit portion and the second circuit portion when viewed from the stacking direction of the plurality of dielectric layers, The second structure includes a second conductive layer that, when viewed from the stacking direction, overlaps with the region located between the first sub-circuit portion and the second sub-circuit portion. An electronic component characterized in that the first conductor layer is not directly connected to the second conductor layer.

2. The electronic component according to claim 1, characterized in that the first conductive layer does not overlap with the second body when viewed from the stacking direction.

3. Each of the first and second structures further includes a plurality of through-holes and a plurality of conductive layers electrically connected to the plurality of through-holes. The plurality of conductor layers of the first structure include the first conductor layer, The electronic component according to claim 1, characterized in that the plurality of conductive layers of the second structure include the second conductive layer.

4. The first body further includes a ground conductor layer connected to ground, The electronic component according to claim 1, characterized in that the first structure and the second structure are arranged between the second body and the ground conductor layer in the stacking direction and connected to the ground conductor layer.

5. The electronic component according to claim 4, characterized in that the ground conductor layer overlaps with at least a portion of at least one of the first circuit portion and the second circuit portion when viewed from the stacking direction.

6. The first circuit portion includes a first inductor, which includes a first inductor conductor layer wound around a first axis parallel to the stacking direction. The second circuit portion includes a second inductor, which includes a second inductor conductor layer wound around a second axis parallel to the stacking direction. The first inductor conductor layer, the first conductor layer, and the second inductor conductor layer are arranged in this order along a first direction perpendicular to the lamination direction. The electronic component according to claim 5, characterized in that the dimensions of the first conductor layer in a second direction perpendicular to each of the stacking direction and the first direction are greater than the dimensions of the opening surrounded by the first inductor conductor layer in the second direction and the dimensions of the opening surrounded by the second inductor conductor layer in the second direction.

7. The first circuit section is connected to the first sub-circuit section, The electronic component according to claim 1, characterized in that the second circuit portion is connected to the second sub-circuit portion.

8. Furthermore, a first filter that selectively passes signals within the first passband, The system includes a second filter that selectively passes signals with frequencies within a second passband different from the first passband, The first filter includes the first circuit portion and the first sub-circuit portion, The electronic component according to claim 7, characterized in that the second filter includes the second circuit portion and the second sub-circuit portion.

9. Furthermore, the electronic component according to claim 8 is characterized by comprising a third filter that selectively passes signals with frequencies within a third passband that is different from each of the first and second passbands.

10. The electronic component according to claim 1, characterized in that the first conductive layer and the second conductive layer each include portions extending in the same direction perpendicular to the stacking direction.

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