Calibration of electrical parameters in deep learning artificial neural networks

Abstract

This system provides a mechanism for calibrating electrical parameters in deep learning artificial neural networks. [Solution] The system comprises a digital-to-analog converter for receiving k bits of input and generating a first analog output, a mapping scalar for converting the first analog output to a second analog output, and an analog-to-digital converter for generating an n-bit output from the second analog output, where n is a different value from k.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Provisional Application No. 63 / 307,983, filed on 8 February 2022, entitled "Calibration of Electrical Parameters Using Heuristics and Machine Learning in a Deep Learning Artificial Neural Network," and U.S. Patent Application No. 17 / 727,650, filed on 22 April 2022, entitled "Calibration of Electrical Parameters In A Deep Learning Artificial Neural Network," which are incorporated herein by reference.

[0002] (Field of Invention) Numerous examples have been disclosed for performing various electrical parameter calibrations in deep learning artificial neural networks. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain) and are used to estimate or approximate functions that may depend on numerous inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with one another.

[0004] Figure 1 shows an artificial neural network, in which the circles illustrate the input or layers of neurons. The connections (referred to as synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This enables the neural network to adapt to the input and become learnable. Typically, a neural network includes multiple input layers. Typically, there is one or more intermediate layers of neurons and an output layer of neurons that provides the output of the neural network. Neurons at each level make decisions individually or collectively based on the data received from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of appropriate hardware technologies. In fact, practical neural networks rely on a very large number of synapses, which enables a high connectivity between neurons, that is, a very high degree of parallelization of computational processing. In principle, such complexity can be realized by a digital supercomputer or a dedicated graphics processing unit cluster. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog calculations and consume much less energy. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses have been too bulky assuming a large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application Publication No. 2017 / 0337466(A1), incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses comprises a plurality of memory cells, each of which comprises spaced source and drain regions formed in a semiconductor substrate, with a channel region extending between them, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells stores weight values ​​corresponding to many electrons in the floating gate. The plurality of memory cells generate a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values. <Non-volatile skin cell>

[0007] Non-volatile memories are well known. For example, U.S. Patent No. 5,029,130 (the “’130 patent”), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, and there is a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18), and is formed spanning a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) is disposed insulated above a second portion of the channel region 18, having a first portion (which controls the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0008] By applying a high positive voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), whereby the electrons in the floating gate 20 pass from the floating gate 20 to the word line terminal 22 through the insulator therebetween via Fowler-Nordheim (FN) tunneling.

[0009] The memory cell 210 is programmed (electrons are added to the floating gate) by source side injection (SSI) by hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. The electron flow is from the drain region 16 towards the source region 14. The electrons are accelerated and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. A portion of the heated electrons is injected into the floating gate 20 through the gate oxide due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain area 16 and the word line terminal 22 (turning on the portion of the channel area 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel area 18 below the floating gate 20 is also turned on, and current flows through the channel area 18, which is detected as the erased state, or the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel area below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel area 18, which is detected as the programmed state, or the "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 in Figure 2 [Table 1]

[0012] Other types of flash memory cells, other split-gate memory cell configurations, are also known. For example, Figure 3 shows a four-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 in Figure 3 [Table 2]

[0014] Figure 4 shows a different type of flash memory cell, a 3-gate memory cell 410. Memory cell 410 is identical to memory cell 310 in Figure 3, except that memory cell 410 does not have a separate control gate. The erase operation (erasure occurs through the use of an erase gate) and read operation are the same as those in Figure 3, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; as a result, a higher voltage is applied to the source line during the programming operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0016] Figure 5 shows a different type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that a floating gate 20 extends above the entire channel region 18, and a control gate 22 (where coupled to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, and programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 to the drain region 16, and by a read operation similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5 [Table 4]

[0018] The methods and means described herein, without limitation, may be applied to other non-volatile memory technologies such as FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase change memory), MRAM (magnetoresistive memory), FeRAM (ferroelectric memory), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one-time programmable, bi-level or multi-level), and CeRAM (correlated electron memory).

[0019] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously with minimal disturbance to other memory cells, from a completely erased state to a fully programmed state, and vice versa. This means that the cell memory is essentially analog, or can store at least one of a number of discontinuous values ​​(such as 16 or 64 different values), making every memory cell in the memory array highly precise and individually tunable, and making the memory array ideal for fine-tuning memory and the weights of neural network synapses. <Neural network using non-volatile memory cell arrays>

[0021] Figure 6 conceptually illustrates an unrestricted example of a neural network utilizing a non-volatile memory array in this example. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different weight sets to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different weight sets to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0023] In this example, layer C1 contains 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filter scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first weight set shared across all scans used to generate this first map) can identify circular edges, and a second map (generated using a second weight set different from the first) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0024] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or use the max function), reduce dependence on edge positions, and reduce data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0025] Each layer of a synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for that purpose. The vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Input to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the weights stored in it by the inputs, adds them up for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing operational amplifier or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential summer 38 is configured to perform the summing of positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then fed to an activation function block 39, which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summing operational amplifier 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert the output analog level to digital bits).

[0031] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0032] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is then provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as the synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e), i.e., one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example, and that the system could instead include more than two hidden layers and more than two fully connected layers. <Vector Matrix Multiplication (VMM) Array>

[0033] Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0034] In the VMM array 900, control gate lines such as control gate line 903 extend vertically (thus, the reference array 902 in the row direction is orthogonal to the control gate line 903), and erase gate lines such as erase gate line 904 extend horizontally. Here, the input to the VMM array 900 is provided to the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 900 appears on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current of each source line (SL0 and SL1 respectively) performs a sum function of all currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, are configured to operate optionally in the subthreshold region.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids = Io 2 , * e (Vg-Vth) / nVt = w * Io * e (Vg) / nVt , where w = e (-Vth) / nVt and <​​​​​​​​​​​​It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV logarithmic converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector matrix multiplier (VMM) array with current input, the output current is as follows: Iout=wa * Io * e (Vg) / nVt That is to say Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Here, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows:

number

[0039] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0040] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region. Ids=beta * (Vgs-Vth) * Vds; beta = u * Cox * Wt / L W=α(Vgs-Vth) In other words, the weight W in the linear region is proportional to (Vgs - Vth).

[0041] Word lines, control gates, bit lines, or source lines can be used as inputs to memory cells operating within the linear region. Bit lines or source lines can be used as outputs to memory cells.

[0042] For IV linear converters, a memory cell (such as a reference memory cell or peripheral memory cell) or transistor operating in the linear domain can be used to linearly convert input / output currents into input / output voltages.

[0043] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 * beta * (Vgs-Vth) 2 , beta=u * Cox * Wt / L W∝(Vgs-Vth) 2 That is, the weight W is (Vgs - Vth) 2 proportional to

[0044] Word lines, control gates, or erase gates can be used as inputs to memory cells operating within a saturation region. Bit lines or source lines can be used as outputs to output neurons.

[0045] Alternatively, the memory cells of the VMM array described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturated) for each layer or multilayer of a neural network.

[0046] Another example for the VMM array 32 in Figure 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in the above application, source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2 and used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to the word lines WL0, WL1, WL2, and WL3), and then adds all the results (memory cell currents) to generate the output of each bit line (BL0~BLN), which becomes the input to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. The current in each bit line BL0 to BLN is a function of the sum of the currents from all non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of a first non-volatile reference memory cell, and a reference array 1102 of a second non-volatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1100 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current on each source line performs a function of the sum of all currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexer 1212 includes a corresponding multiplexer 1205 and a cascoding transistor 1204 to ensure a constant voltage across the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells during read operations. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line is a function of the sum of all currents from the memory cells connected to that particular bit line.

[0054] The VMM array 1200 implements one-way tuning of non-volatile memory cells within the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (e.g., an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (e.g., EG0 or EG1) are erased together (known as page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, a reference array 1301 or a first non-volatile reference memory cell, and a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using individual EG lines. As shown, reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), and these voltages are applied to memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0~BLN, and each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2200, inputs INPUT0, ..., INPUT N These are bit lines BL0, ...BL, respectively. N The signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0060] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received at, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0061] Figure 25 shows a neuron VMM array 2500 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received at, output OUTPUT0, ...OUTPUTN These are bit lines BL0, ..., BL N It is generated by [this method].

[0062] Figure 26 shows a neuron VMM array 2600 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapse and neuron between the input layer and the next layer. In this example, the input 0、 ..., INPUT n However, each of them is a vertical control gate line CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] Figure 27 shows a neuron VMM array 2700 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs are INPUT0, ..., INPUT N These are bit lines BL0, ..., BL, respectively. N The data is received by the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N, which are coupled to the source line. The example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] Figure 28 shows a neuron VMM array 2800, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received to, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0065] Figure 29 shows a neuron VMM array 2900 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received by OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL, respectively. N It is generated in each source line SL i It is coupled to the source lines of all memory cells in column i.

[0066] Figure 30 shows a neuron VMM array 3000, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received by OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL, respectively. N Generated in each bit line BL i It is coupled to the bit lines of all memory cells in column i. <Long-term and short-term memory>

[0067] Prior art includes the concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an example LSTM1400. In this example, the LSTM1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1402 receives the input vector x1, the output vector (hidden state) h0 from cell 1401, and the cell state c0 from cell 1401, and generates the output vector h1 and the cell state vector c1. Cell 1403 receives the input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402, and generates the output vector h2 and the cell state vector c2. Cell 1404 receives the input vector x3, the output vector (hidden state) h2 from cell 1403, and the cell state c2 from cell 1403, and generates the output vector h3. Additional cells can also be used, and an LSTM with four cells is just one example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. The LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from the preceding cell, and an output vector h(t-1) from the preceding cell, and generates a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the extent to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0071] Figure 16 shows an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the reader's convenience, the same numbering method used in LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each contain multiple VMM arrays 1601 and activation function blocks 1602. Thus, VMM arrays are found to be particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, and adder device 1509 are implemented in a digital or analog manner. Activation function block 1602 can be implemented in a digital or analog manner.

[0072] Figure 17 shows an alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500). In Figure 17, sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (including the activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, and a value f(t) * Register 1704 for storing c(t-1) when its value is output from multiplier device 1703 via multiplexer 1710, and value i(t) * Register 1705 for storing u(t) when its value is output from multiplier device 1703 via multiplexer 1710, and value o(t) * The set includes register 1706 and multiplexer 1709 for storing c~(t) when its value is output from multiplier device 1703 via multiplexer 1710.

[0073] While an LSTM cell 1600 contains multiple sets of VMM arrays 1601 and their respective activation function blocks 1602, an LSTM cell 1700 contains only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of an LSTM cell 1700. Compared to an LSTM cell 1600, an LSTM cell 1700 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than an LSTM cell 1600.

[0074] It can be further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself. <Gated recurrent unit>

[0075] Analog VMM implementations can be used in GRU (gated recurrent unit) systems. A GRU is a gate mechanism within an iterative neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] Figure 18 shows an illustrative GRU1800. In this example, GRU1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and produces output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and produces output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and produces output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0077] Figure 19 shows an illustrative implementation of a GRU cell 1900 that can be used in cells 1801, 1802, 1803, and 1804 of Figure 18. The GRU cell 1900 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding two vectors, and a complementary device 1908 for subtracting the input from 1 to produce an output.

[0078] Figure 20 shows GRU cell 2000, an example of an implementation of GRU cell 1900. For the reader's convenience, the same numbering method used in GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, the sigmoid function devices 1901 and 1902, and the tanh device 1903, each contain multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are used in particular in GRU cells used in specific neural network systems. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0079] Figure 21 shows an alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900). In Figure 21, GRU cell 2100 utilizes VMM array 2101 and activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902, and tanh device 1903, share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding two vectors, a complementary device 2109 for subtracting the input from 1 to generate an output, a multiplexer 2104, and a value h(t-1) * Register 2106 for holding r(t) when its value is output from multiplier device 2103 via multiplexer 2104, and value h(t-1) * A register 2107 holds the value of z(t) when its value is output from the multiplier device 2103 via the multiplexer 2104, and the value h^(t) *The register 2108 holds (1-z((t)) when its value is output from the multiplier device 2103 via the multiplexer 2104.

[0080] While GRU cell 2000 contains multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 contains only one set of VMM array 2101 and activation function block 2102, which is used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires 1 / 3 the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further understood that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is required to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] Generally, for each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells.

[0084] Figure 31 shows the VMM system 3100. In some examples, the weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In the VMM system 3100, half of a plurality of bit lines are designated as W+ lines, i.e., bit lines that will connect to memory cells that will store the positive weight W+, and the other half of the plurality of bit lines are designated as W- lines, i.e., bit lines that will connect to memory cells that will implement the negative weight W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3101 and 3102, which receive current from the W+ and W- lines. The outputs of the W+ lines and the W- lines are combined to effectively give W = W+ - W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. Up to this point, we have described W- lines that are alternately scattered between W+ lines, but in other examples, W+ and W- lines can be arbitrarily placed anywhere within the array.

[0085] Figure 32 shows another example. In the VMM system 3210, positive weights W+ are implemented in the first array 3211, and negative weights W- are implemented in the second array 3212, which is separate from the first array, and the resulting weights are appropriately combined by the adder circuit 3213.

[0086] Figure 33 shows the VMM system 3300. The weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). The VMM system 3300 comprises arrays 3301 and 3302. Half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that store the positive weights W+, and the other half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that implement the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3303, 3304, 3305 and 3306, which receive current from the W+ and W- lines. The outputs of the W+ line and the W- line from each array 3301 and 3302 are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. In addition, the W values ​​from each array 3301 and 3302 can be further combined via adders 3307 and 3308, such that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, meaning that the final result from adders 3307 and 3308 is the difference of one of the two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system holds a charge, i.e., the number of electrons, in a very specific and precise quantity within a floating gate, corresponding to the erase / program. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] Similarly, the read operation must be able to accurately distinguish between N different levels.

[0089] It can be understood that accuracy is extremely important in the programming and reading operations of VMM systems. However, inherent variations between memory cells can impair the accuracy of the system. For example, characteristics such as the maximum cell current a cell can conduct (Icell max), the number of bits stored in a cell, the cell's IV gradient (analog continuous input) (indicating the current drawn by the cell for each specific voltage at the cell's terminals), temperature behavior, and whether the cell is located in an odd or even row can affect neural network performance. Extrinsic variations in how cells are utilized can also impair accuracy. For example, circuit mismatches and variations between external components and cells, as well as characteristics such as current drop based on the cell's location within the array, affect accuracy.

[0090] What is needed is a calibration technique that can be performed in real time within the VMM system to compensate for intrinsic and extrinsic variations between cells during operation. [Overview of the project]

[0091] Numerous examples of performing various electrical parameter calibrations in deep learning artificial neural networks have been disclosed. Such electrical parameter calibrations can compensate for variations between transistors, memory cells, or other devices, or for changes in operating temperature. Electrical parameters can be calibrated for the entire deep learning artificial neural network, for each layer within the deep learning artificial neural network, or for a portion of the layers within the deep learning artificial neural network.

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[0171] [Brief explanation of the drawing]

[0172] [Figure 1] This is a diagram illustrating an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This diagram illustrates various levels of an example artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] This is a block diagram illustrating a vector matrix multiplication system. [Figure 8] This is a block diagram illustrating an example artificial neural network that utilizes one or more vector matrix multiplication systems. [Figure 9] Here is another example of a vector-matrix multiplication system. [Figure 10] Here is another example of a vector-matrix multiplication system. [Figure 11] Here is another example of a vector-matrix multiplication system. [Figure 12] Here is another example of a vector-matrix multiplication system. [Figure 13] Here is another example of a vector-matrix multiplication system. [Figure 14] This demonstrates prior art long- and short-term memory systems. [Figure 15] This shows an example cell used in a long- and short-term memory system. [Figure 16] Figure 15 shows an example implementation of a cell. [Figure 17] Figure 15 shows another example implementation of the cell. [Figure 18] This shows a prior art gated regression unit system. [Figure 19] An example cell is shown for use in a gated regression-type unit system. [Figure 20] Figure 19 shows an example implementation of a cell. [Figure 21] Figure 19 shows another example implementation of the cell. [Figure 22] Here is another example of a vector-matrix multiplication system. [Figure 23] Here is another example of a vector-matrix multiplication system. [Figure 24] Here is another example of a vector-matrix multiplication system. [Figure 25] Here is another example of a vector-matrix multiplication system. [Figure 26] Here is another example of a vector-matrix multiplication system. [Figure 27] Here is another example of a vector-matrix multiplication system. [Figure 28] Here is another example of a vector-matrix multiplication system. [Figure 29] Here is another example of a vector-matrix multiplication system. [Figure 30] Here is another example of a vector-matrix multiplication system. [Figure 31] Here is another example of a vector-matrix multiplication system. [Figure 32] Here is another example of a vector-matrix multiplication system. [Figure 33] Here is another example of a vector-matrix multiplication system. [Figure 34] Here is another example of a vector-matrix multiplication system. [Figure 35] An example of a calibration method is shown. [Figure 36] Another example of a calibration method is shown. [Figure 37] Another example of a calibration method is shown. [Figure 38] This graph shows a typical change in the operating temperature of a vector matrix multiplication system over time. [Figure 39] This shows the current-voltage characteristics of various non-volatile memory cells that store various values ​​at various operating temperatures. [Figure 40]This shows a differential current-to-voltage converter. [Figure 41] This shows a differential continuous address register analog-to-digital converter. [Figure 42] An example readout circuit is shown. [Figure 43] An example input block is shown. [Figure 44] An example input block is shown. [Figure 45] An example input block is shown. [Figure 46] An example input block is shown. [Figure 47] An example input block is shown. [Figure 48] An example of a dual register block is shown. [Figure 49] An example of an input block's input-output is shown. [Figure 50] An example output block is shown. [Figure 51] An example input block is shown. [Figure 52] An example of a global digital-to-analog converter and row decoder is shown. [Figure 53] An example of a global digital-to-analog converter and row decoder is shown. [Figure 54] An example of a global digital-to-analog converter and row decoder is shown. [Figure 55] An example waveform of a digital-to-analog converter is shown. [Figure 56] An example waveform of a digital-to-analog converter is shown. [Figure 57] The output of an example digital-to-analog converter is shown. [Figure 58] The output of an example digital-to-analog converter is shown. [Figure 59] An example calibration circuit is shown. [Figure 60] An example of a calibration circuit is shown. [Figure 61] An example of a calibration circuit is shown. [Figure 62] An example of a calibration circuit is shown. [Figure 63] An example of a calibration circuit is shown. [Figure 64] An example of a calibration circuit is shown. [Figure 65] An example of an exemplary input block is shown. [Figure 66] An example of an exemplary row input circuit is shown. [Figure 67] An example of an exemplary global input generator is shown. [Figure 68] An example of an exemplary array and sampling neuron circuit is shown. [Figure 69] An example of an exemplary array, reference array, and sampling neuron circuit is shown. [Figure 70] An example of an exemplary reference array and sampling neuron circuit is shown. [Figure 71] An example of an exemplary array calibrator is shown. ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ Figure 34 shows a block diagram of an exemplary VMM system 3400. The VMM system 3400 comprises a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit line driver 3405, an input circuit 3406, an output circuit 3407, a control logic 3408, and a bias generator 3409. The VMM system 3400 further comprises a high-voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage analog precision level generator 3413. The VMM system 3400 further comprises an algorithm controller 3414 (for program / erase or weight tuning), an analog circuit 3415, a control engine 3416 (which may include, but is not limited to, arithmetic functions, startup functions, embedded microcontroller logic, etc.), and a test control logic 3417. The systems and methods described below may be implemented in the VMM system 3400.

[0175] The input circuit 3406 may include circuits such as a DAC (digital-to-analog converter), DPC (digital-to-pulses converter, digital-to-time-modulated pulse converter), AAC (analog-to-analog converter, such as a current-to-voltage converter or logarithmic converter), PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The output circuit 3407 may include circuits such as an ADC (analog to digital converter, an analog-to-digital converter for converting the neuron's analog output to digital bits), an AAC (analog to analog converter, such as a current-to-voltage converter or logarithmic converter), an APC (analog to pulse converter, analog to time-modulated pulse converter), or any other type of converter. The output circuit 3407 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) of the neuron output. The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) in order to improve the accuracy of the array (neuron) output by keeping the power consumption of the array nearly constant or by keeping the slope of IV nearly the same.

[0176] Two approaches for performing real-time calibration are described herein. First, an approach using approximation is disclosed (shown in Figures 35 and 36), where the mean IV dataset is assumed to be based on data accumulated from an actual array, a sampled array, or a reference array. Second, an approach using learning behavior (shown in Figure 37) is disclosed, where the parameters are adapted to network performance.

[0177] Figure 35 shows an example calibration method 3500 for calibrating the VMM system 3400.

[0178] Firstly, one or more electrical parameters are adjusted and applied to the memory cell, memory array, or peripheral circuit (operation 3501). If this is the first instance of operation 3501 being performed, initial values ​​are used for the electrical parameters. If this is a second or subsequent instance of operation 3501 being performed, any adjusted electrical parameters determined in operation 3503 (described later) are applied.

[0179] Examples of electrical parameters that can be modified at the memory cell level include, but are not limited to, the resolution of the weights stored in the cell (changing n, where n is the bit resolution of the cell) (e.g., using a smaller n leads to better precision control), the maximum cell current (Icell max) and / or minimum cell current (Icell min) that can be drawn by the cell (e.g., a lower Icell max results in lower power, and a higher Icell min results in improved baseline noise immunity), the cell IV gradient (e.g., a gradient to achieve a specific performance metric), and the cell temperature behavior and associated compensation scheme (e.g., adjusting the bias voltage when the temperature changes).

[0180] Examples of electrical parameters that can be modified at the memory array level include, but are not limited to, the number of acceptable defects (stacked "1" or "0", bad rows or bad columns), the acceptable noise floor (e.g., from thermal noise or popcorn or flicker noise before replacing with redundant cell / array portions or rendering specific cell / array portions unusable), the number of banks (M rows and N columns), the write I / O width (number of cells written in parallel, which is, for example, a trade-off with IRdrop from operating current, i.e., voltage drop), the number of rows sharing source lines, the sector size (number of rows and columns, which is, for example, a trade-off of area with respect to interference due to sharing the same high-voltage lines), and array bias conditions (bias on bit lines, word lines, control gates, erase gates, etc.).

[0181] Examples of electrical parameters that can be varied at the peripheral circuit level include, but are not limited to, the resistance, capacitance, or other variable characteristics in the output neuron circuit, the degree of scaling performed on the output, the bit resolution of the digital output generated from the neuron output, offset calibration, the trade-off between power and speed, and the multiplexing for digital-to-analog converters, analog-to-digital converters, or activation circuits (how many are required per VMM array, the trade-off between latency and throughput versus area). Circuits such as normalization circuits or shaping circuits are further examples of peripheral circuits.

[0182] Secondly, a performance target check is performed (operation 3502). This may include, for example, checking whether the neuron current (bit line current from the array) or the average neuron current (where neuron current and average neuron current are examples of determined values) meets a target current (a predetermined threshold) at a certain temperature, or checking whether the neuron current or average neuron current meets a predetermined threshold after activation. The performance target may relate to a target neuron value, circuit accuracy, power, or latency. If the performance target (a predetermined threshold) is achieved, the calibration method 3500 proceeds to operation 3506 and completes. Otherwise, the method proceeds to the next operation 3503.

[0183] In operation 3503, the applied electrical parameters are adjusted (operation 3503).

[0184] In operation 3504, the system determines whether the applied electrical parameters are within a predetermined range, such as within the tolerances of the components or the system. If so, operations 3501, 3502, 3503, and 3504 are repeated. Otherwise, the network circuit is considered faulty (this means that the electrical parameters have now been adjusted beyond the acceptable limits) and is not used (operation 3505). For example, this could be the result of a faulty die.

[0185] Optionally, method 3500 can be performed in real time while the VMM system 3400 is operating, which is useful, for example, for calibrating parameters when the operating temperature of the VMM system 3400 changes.

[0186] Figure 36 shows an exemplary calibration method 3600 for calibrating the VMM system 3400. Calibration method 3600 utilizes neural network inference. The neural network for generating such inference can be any known type of neural network, such as a multilayer perceptron (MLP), a convolutional neural network (CNN) (e.g., residual network, ResNet-x), or a recurrent neural network (RNN) (e.g., long short-term memory, LSTM).

[0187] First, electrical parameters are applied (operation 3601). If this is the first instance of operation 3601 being performed, initial values ​​are used for the electrical parameters. If this is a second or subsequent instance of operation 3601 being performed, any adjusted electrical parameters determined in operation 3603 (described later) are applied. These parameters may be the same as those described above for operation 3501 of calibration method 3500.

[0188] Secondly, a performance neural network inference goal check is performed (operation 3602). This may include, for example, recognizing digits from the Modified National Institute of Standards and Technology (MNIST) or classifying images from ImageNet. If the goal is achieved, calibration method 3600 proceeds to operation 3606 and completes. Otherwise, the method proceeds to the next operation.

[0189] In operation 3603, the applied electrical parameters are adjusted.

[0190] Next, the system determines whether the applied electrical parameter is within a predetermined range, such as within the tolerance of the component or system (operation 3604). If so, operations 3601, 3602, 3604, and 3604 are repeated. If not, the network circuit is considered defective (which means that the electrical parameter has now been adjusted beyond the tolerance) and is not used (operation 3605). For example, this can be the result of a defective die.

[0191] Optionally, method 3600 can be executed in real time during the operation of VMM system 3400, which is useful, for example, for calibrating parameters when the operating temperature of VMM system 3400 changes.

[0192] FIG. 37 shows an exemplary calibration method 3700 for calibrating VMM system 3400. Calibration method 3700 utilizes machine learning.

[0193] First, a machine learning model set is generated by applying a range of electrical parameters, such as a bias voltage, to a first non-volatile memory system (e.g., VMM system 3400), measuring the resulting characteristics, such as neuron current or average neuron current, and comparing the measured resulting characteristics to a predetermined target range. (operation 3701). The parameters can be the same as the parameters described above with respect to operation 3501 of calibration method 3500.

[0194] Second, during the operation of the first non-volatile memory system or a second non-volatile memory system (e.g., another instance of VMM system 3400), the machine learning model is used to determine the electrical parameters to be applied to the memory cells, memory arrays, and peripheral circuits. (operation 3702).

[0195] FIG. 38 provides an example showing how quickly electrical parameters can change during operation as a function of temperature. FIG. 38 shows the silicon thermal conduction rate of a uniform silicon wafer, which is the amount of time it takes to change the temperature of the uniform wafer to a specific temperature. This rate can be affected by various factors including local power consumption within the silicon. Based on this graph, the rate is approximately 100 ms for each 1-degree change. This means that electrical parameters affected by temperature may require adjustment every 100 ms during operation.

[0196] FIG. 39 provides a variation example between different memory cells within the VMM system 3400. FIG. 39 shows the current-voltage data (showing the I-V gradient) of a plurality of memory cells when each cell is operating in the subthreshold region. The current is the current Icell drawn by the cell when the voltage VCG is applied to the control gate of the cell. As can be seen, the I-V gradient can vary for each value of VCG. The specific I-V gradient of each cell is affected by the cell's inherent characteristics, can vary based on the value W stored in the cell, and also based on the operating temperature of the cell. It also varies based on the physical dimensions or electrical parameters of the cell due to such variations (such as etching variations, etc.) in mask alignment or process steps or such variations in process implantation.

[0197] Figure 40 shows a differential current-to-voltage converter 4001. The differential current-to-voltage converter 4001 comprises an operational amplifier 4003 configured as shown, variable integrating resistors 4004 and 4005, and a common-mode circuit 4006 (used for differential amplifier implementation of operational amplifier 4003). The differential current-to-voltage converter 4001 converts two current inputs IBL+ and IBL- into differential output voltages VO+ and VO-, where the output voltages are proportional to the resistances of the variable resistors 4004 and 4005. The input currents IBL+ and IBL- are, optionally, currents representing positive and negative weights. For example, IBL+ can be a current Iw+ from a single cell, or a bit line current which is the sum of currents from multiple w+ cells coupled to a bit line, and IBL- can be a current Iw- from a single cell, or a bit line current which is the sum of currents from multiple w- cells coupled to a bit line. Such positive and negative weights can be used in a neural network to represent the weights (W = W+-W-). In another example, the two input currents IBL+ and IBL- could represent the cell current or bit line current from the array and the reference current.

[0198] Figure 41 shows a differential continuous address register (SAR) analog-to-digital converter (ADC) 4102.

[0199] The differential continuous address register analog-to-digital converter 4102 converts an analog input or differential analog input to a digital output using binary search through all possible quantization levels to identify the appropriate digital output.

[0200] The differential continuous address register analog-to-digital converter 4102 comprises a binary capacitive digital-to-analog converter (CDAC) 4107, a binary CDAC 4108 (complementary to CDAC 4107), a comparator 4109, and SAR logic and register 4110.

[0201] The differential continuous address register analog-to-digital converter 4102 receives differential current inputs Vinp and Vinn. The SAR logic and register 4110 cycles through all possible digital bit combinations and then controls switches in the CDAC 4107 and 4108 to couple the voltage source to the capacitor. When the output of comparator 4109 is inverted, the digital bit combination in the SAR logic and register 4110 is output as a digital output. Optionally, the SAR logic and register 4110 generates an additional 1-bit digital output DMAJ within the digital output, which is "1" if the majority of bits in the digital value are "1" and "0" if the majority of bits in the corresponding digital value are not "1".

[0202] Figure 42 shows an exemplary readout circuit 4200 that implements offset calibration for performing readout operations on one or more bit lines in a VMM array, such as the VMM array 3401 in Figure 34. The readout circuit 4200 comprises a comparator 4201, an offset calibration capacitor digital-to-analog converter 4202, an offset calibration capacitor digital-to-analog converter 4203, and a calibration controller 4204. The calibration controller 4204 enables various capacitors in the offset calibration capacitor digital-to-analog converters 4202 and 4203 by closing or opening various switches labeled en and enb to compensate for offsets generated due to temperature fluctuations, as illustrated in Figure 39.

[0203] The electrical parameters for learning during the calibration or training process shown in Figures 35 and 36 for the circuits in Figures 40 and 41 include the degree of bit resolution (e.g., 4-bit, 5-bit, or 8-bit resolution), the degree of neuron scaling (e.g., the magnitude of the scaling factor, such as 4X to 256X), the degree of power consumption due to bias current (e.g., higher bias current means more power and faster speed), and the amount of offset added for temperature compensation (higher added offset values ​​mean higher precision at the expense of more circuit complexity).

[0204] Figure 43 shows an exemplary input block 4300 used to provide input to a VMM array, such as the VMM array 3401 in Figure 34. The input block 4300 includes a global digital-to-analog converter (DAC) 4301, address row decoders 4302-0 to 4302-n, each corresponding to one of the numbered rows 0 to n in the VMM array, row registers 4303-0 to 4303-n, each corresponding to one of the numbered rows 0 to n in the VMM array, digital comparator blocks 4304-0 to 4304-n, each corresponding to one of the numbered rows 0 to n in the VMM array, row sample-and-hold (S / H) buffers 4305-0 to 4305-n, each corresponding to one of the numbered rows 0 to n in the VMM array, output signals 4306-0 to 4306-n, each corresponding to one of the numbered rows 0 to n in the VMM array, and a counter 4307.

[0205] The address row decoders 4302-0 to 4302-n receive the row address ADD[n:0] and the enable signal EN. The output of each address row decoder, indicated by ENROW, is high when EN is asserted, with ADD[n:0] being the address of that particular row. Row registers 4303-0 to 4303-n are loaded with the respective digital input bits DINx (x being the number of bits, such as 8 or 16 bits) of that particular row, where the load operation is triggered by the clock signal CLK and DINx is the activation input for that particular row. A vector matrix multiplication operation is performed. When the output of a particular address row decoder 4302 is high, the associated row register 4303 is enabled and outputs its digital bit DINx. The counter 4307, when enabled by the signal EN, counts pulses in another clock signal CLKB. The output of the counter 4307 is the count value. The digital comparator blocks 4304-0 to 4304-n compare the activation value DINx stored in each of the row registers 4303 with the count value. If the count value matches the value stored in a particular row register 4302, the corresponding row S / H buffer 4305 is enabled to sample and hold the analog output value from the global DAC 4301. The global DAC 4301 performs digital-to-analog conversion on the count value (which also matches the DINx in the row register 4303 of that row). Each row S / H buffer 4305 outputs the held analog value as the output signal 4306. For example, if x=8 and DINx is an 8-bit input (meaning there are 256 different values ​​for DINx), the counter 4307 counts up to 256 and then resets. In doing so, it covers all possible values ​​of DINx, and each row S / H buffer 4305 is loaded with its associated DINx value.

[0206] The output signal 4306 can be applied to control gate lines or word lines, for example, during programming or read operations on a specific row, or during neural read operations where all rows are read. During neural read operations, all S / H buffers 4305 are enabled to drive array input terminals via their respective output signals 4306, causing bit line currents to be output by the VMM array, which are then processed by output circuits such as ITV (current-voltage converter) and ADC (analog-to-digital converter) circuits.

[0207] The output signal 4306 may, for example, be applied to each control gate line or word line during programming operations in that particular row.

[0208] In another example, the row sample-hold buffer 4304 may be shared by multiple rows in a time-division multiplexing scheme.

[0209] Figure 44 shows an exemplary row input block 4400 used to provide input to a VMM array, such as the VMM array 3401 in Figure 34. The input block 4400 comprises a global digital-to-analog converter (DAC) 4401, address row decoders 4402-0 to 4402-n, each corresponding to one of the numbered rows 0 to n in the VMM array, row registers 4403-0 to 4403-n, each corresponding to one of the numbered rows 0 to n in the VMM array, digital multiplexer (mux) blocks 4404-0 to 4404-n, each corresponding to one of the numbered rows 0 to n in the VMM array, row sample-and-hold buffers 4405-0 to 4005-n, each corresponding to one of the numbered rows 0 to n in the VMM array, and output signals 4406-0 to 4406-n, each corresponding to one of the numbered rows 0 to n.

[0210] The address row decoders 4402-0 to 4402-n receive the row address ADD[n:0] and the enable signal EN. The output of each address row decoder, indicated by ENROW, is high when ADD[n:0] is the address of that particular row. Row registers 4403-0 to 4303-n are loaded with the respective digital input bits DINx (x is the number of bits, such as 8 or 16) of that particular row, where the loading operation is triggered by the clock signal CLK and DINx is the activation input for that particular row. When the output of a particular address row decoder 4402 is high and EN is asserted, the associated row register 4403 is enabled and outputs its respective digital bit DINx. CLKCOUNTx is a count value provided by a counter, which can range between 1 and the total number of rows. The digital multiplexer 4404, in response to CLKCOUNTx, multiplexes the data of each row register 4403 onto the bus DIN_GDACx. CLKCOUNTx enables each row in a sequential order (row 0, row 1, ...) so that the DINx of each row is applied sequentially to the global DAC 4401. Each row S / H buffer 4405 receives the output of its associated address row decoder 4402 and is enabled by the respective signal ENROW when the row address matches the row address for that particular row, in which case the row S / H buffer 4405 samples a value from the global DAC 4401 and provides it as its respective analog output 4406. The output signal 4406 may be applied, for example, to a control gate line or word line during programming operation in that particular row.

[0211] In another example, row sample-and-hold buffer 4405 may be shared across multiple rows to time-division multiplex the row sample-and-hold buffer.

[0212] Figure 45 shows an exemplary input block 4500 used to provide input to a VMM array, such as the VMM array 3401 in Figure 34. The input block 4500 is similar to the input block 4400 in Figure 44, but provides multiple outputs from a global digital-to-analog converter for neural readout operations. The input block 4500 comprises a global digital-to-analog converter and row decoder 4501, address row decoders 4502-0 to 4502-n, each corresponding to one of the rows numbered from 0 to n, row registers 4503-0 to 4503-n, each corresponding to one of the rows numbered from 0 to n, digital comparators 4504 to 4504-n, each corresponding to one of the rows numbered from 0 to n, row sample-and-hold buffers 4505-0 to 4505-n, each corresponding to one of the rows numbered from 0 to n, and output signals 4506-0 to 4506-n, each corresponding to one of the rows numbered from 0 to n.

[0213] The address row decoders 4502-0 to 4502-n receive the row address ADD[n:0] and the enable signal EN. The output of each address row decoder 4502, indicated by ENROW, is high when EN is asserted, with ADD[n:0] being the address of that particular row. Row registers 4503-0 to 4503-n are loaded with their respective digital input bits DINx (where x is the number of bits, such as 8 or 16 bits), where the load is triggered by the clock signal CLK for that particular row, and DINx is the activation input for that particular row. When the output ENROW of a particular address row decoder 4502 is high, the associated row register 4503 is enabled and outputs its digital bit DINx. The counter 4507, when enabled by the signal EN, counts pulses in another clock signal CLKB. The output of the counter 4507 is the count value. The digital comparator blocks 4504-0 to 4504-n compare the activation value DINx stored in each of the row registers 4503 with a count value. If the count value matches the value stored in a particular row register 4502, the corresponding row S / H buffer 4505 is enabled to sample and hold the analog output value from the GDAC 4501. As shown, there are two vertical analog output lines from the GDAC 4501. For example, in the case of an 8-bit GDAC 4501, one line can carry the output of analog levels from 0 to 127 (corresponding to 00000000 to 01111111), and the other line can carry the output of analog levels from 128 to 255 (corresponding to 10000000 to 11111111). Both lines can operate simultaneously to reduce the row DAC sampling time from 256 (DAC) clocks to 128 (DAC) clocks. The output signal 4506 may, for example, be applied to a control gate line or a word line during programming operations in that particular row.

[0214] Optionally, the global digital-to-analog converter 4501 may comprise a first global DAC for odd-numbered rows and a second global DAC for even-numbered rows.

[0215] Figure 46 shows an exemplary input block 4600 used to provide input to a VMM array, such as the VMM array 3401 in Figure 34. The input block 4600 comprises an analog voltage source 4601, address row decoders 4602-0 to 4602-n, each corresponding to one of the numbered rows 0 to n in the VMM array, row registers 4603-0 to 4603-n, each corresponding to one of the numbered rows 0 to n in the VMM array, local digital-to-analog converters 4604-0 to 4604-n (each row having its own DAC), each corresponding to one of the numbered rows 0 to n, row buffers 4605-0 to 4605-n, each corresponding to one of the numbered rows 0 to n, and output signals 4606-0 to 4606-n, each corresponding to one of the numbered rows 0 to n.

[0216] The address row decoder 4602 receives the row address ADD[n:0] and the enable signal ENx. The output ENROW of each address row decoder is high when ADD[n:0] is the address of that particular row and ENx is asserted. Row registers 4603-0 to 4303-n are loaded with the respective digital input bits DINx (x is the number of bits, such as 8 or 16 bits) of that particular row, where the load is triggered by the clock signal CLK and DINx is the activation input for that particular row. When the output ENROW of a particular address row decoder 4602 is high, the associated row register 4603 is enabled and outputs its digital bit DINx.

[0217] The local digital - analog converters 4604 - 0 to 4604 - n perform digital - analog conversion on the digital bits DINx stored in the associated row register 4603. The corresponding row sample - hold buffer 4605 of that row samples the analog output from the digital - analog converter 4604, holds the value, and that value is applied as the output signal 4606 for that particular row. The output signal 4606 can be applied to the control gate line or word line during the programming operation in that particular row (or rows), for example, in the manner described above with respect to other figures.

[0218] FIG. 47 shows an exemplary input block 4700 similar to the input block 4600 of FIG. 46 with a global DAC block 4707 added. The global DAC block 4707 operates in cooperation with the local DAC 4704. For example, in the case of a CDAC DAC (capacitive charge - redistribution DAC), the global DAC 4707 can provide an additional reference voltage to the local CDAC DAC to extend the DAC resolution.

[0219] The electrical parameters for calibration related to the input blocks 4300, 4400, 4500, 4600, and 4700 can include, but are not limited to, the degree of bit resolution (by changing the number of bits of DINx), the degree of bias (meaning adjusting the value of the reference voltage or adjusting variable elements such as variable resistors by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707), the degree of power consumption (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707), the speed (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707), the degree of offset (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707), and the degree of temperature compensation (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707).

[0220] Figure 48 shows an exemplary dual-register block 4800 that can be used in place of any individual register in Figures 43, 43, 44, 46, and 47, such as any of the row registers 4303, 4403, 4503, 4603, and 4703. The dual-register block 4800 comprises a multiplexer 4803 controlled by selection signal 1, a multiplexer 4804 controlled by selection signal 2, and row registers 4801 and 4802. Row register 4801 can be loaded with data via multiplexer 4803, while row register 4802 outputs data via multiplexer 4804, and vice versa. This reduces the amount of operating time required for loading and reading row registers because these operations can be performed simultaneously or partially simultaneously. In contrast, in a single-register configuration, the registers require time to be loaded before data can be read.

[0221] Figure 49 shows an example input-output value 4900 of an input block that may include a digital-to-analog converter. Here, the input block receives eight digital bits corresponding to 256 different values ​​L0 to L255. The input block generates an analog voltage Vin in response to the eight digital bits according to a logarithmic function, as shown in the graph.

[0222] Figure 50 shows an exemplary output block 5000. The output block comprises a current-to-voltage converter 5001 (scalable neuron circuit) and an analog-to-digital converter 5002. The current-to-voltage converter 5001 receives an output current Ineu as an output from a column in the VMM array and converts that current to a voltage. The analog-to-digital converter 5002 converts the voltage to a set of n+1 digital bits D[n:0]. As shown, the current-to-voltage converter 5001 and the analog-to-digital converter 5002 are configurable (e.g., n-bit resolution, power, latency, scaling).

[0223] Figure 51 shows the input block (row input bias generator) 5100. The input block 5100 comprises a k-bit digital-to-analog converter 5101, a mapping scalar 5102, and an n-bit analog-to-digital converter 5103. The k-bit digital-to-analog converter 5101 receives a k-bit input and generates an analog signal using a linear or logarithmic function. Graphs 5105 and 5107 show examples of analog signals generated according to a logarithmic function, and graphs 5104 and 5106 show examples of analog signals generated according to a linear function. The mapping scalar 5102 performs a scaling function on the analog signal, while the n-bit analog-to-digital converter 5103 converts the output of the mapping scalar 5102 to an n-bit digital output. Thus, the output block 5100 converts a k-bit value to an n-bit value via the mapping scalar 5102. For example, k is 10 to 14 bits, while n is 5 to 8 bits. The conversion (mapping) is supported, for example, by the calibration circuits shown in Figures 59 to 64.

[0224] Figure 52 shows an adjustable GDAC 5220 that can be used in the GDACs 4301, 4401, 4501, 4601, and 4707 in Figures 43 to 47, respectively, to generate analog signals for application to a non-volatile memory array in response to a digital input and one or more bias voltages. The adjustable GDAC 5220 includes a global DAC x 5221 and a bias generator 5227. The bias generator 5227 includes a reference array 5223 and a bias generation circuit 5222 that generates a bias 5224. The bias generation circuit 5222 uses the reference array 5223 to generate a bias 5224 that is automatically compensated for temperature based on the temperature changes experienced by the reference array 5223. For example, the bias 5224 can be based on the current drawn by the reference array 5223, which is affected by the temperature of the reference array 5223. This bias 5224 is supplied to the global DAC 5221 so that the output voltage 5226 resulting from being supplied to the array is compensated over temperature.

[0225] Figure 53 shows an example of a global digital-to-analog converter and row decoder 5350 that can be used in the global digital-to-analog converter and row decoders 4301, 4401, 4501, 4601, and 4707 in Figures 43 to 47. The global digital-to-analog converter and row decoder 5350 includes a DAC 5351, a mapping block 5361, and an output buffer 5371. Control logic (not shown) controls the operation of the GDAC (to perform functions such as enabling various blocks using enable signals such as EN, providing control signals to the multiplexer, and other control functions).

[0226] The DAC5351 receives a high reference voltage VREFH and a low reference voltage VREFL. The DAC5351 includes a voltage ladder of multiple resistors used to generate a voltage range between VREFL and VREFH according to an optional linear or logarithmic function. For example, the top node of the top resistor in the voltage ladder has voltage VREFH, the bottom of the resistor has a lower voltage due to the voltage drop across the top resistor, and the bottom node of the bottom resistor has voltage VREFL. Thus, the voltage ladder generates multiple voltage levels (L0, ..., Lk) (e.g., k may be 4095), and these voltage levels are needed when it is desired to supply voltage to the VMM array to operate the VMM array's non-volatile memory cells in linear or subthreshold mode.

[0227] The digital-to-analog converter 5351 receives a digital input DIN[n:0], which is used to select one of m+1 voltages via subblock 5363 in mapping block 5361, where (m+1)=2^(n+1). For example, if (n+1)=8, then (m+1)=256. Mapping block 5361 contains (m+1) trim blocks 5362 and (m+1) multiplexers 5363. Mapping block 5361 converts the k+1 voltage levels from DAC 5351 into their respective analog outputs corresponding to DIN[n:0]. This is achieved using local trimming for each level (represented by trim blocks L0_trm, ...Lm_trm), which may be useful, for example, when non-volatile memory cells in an array are operating in a subthreshold region. This is desirable to achieve an optimal IV gradient for non-volatile memory cells in the VMM array with respect to temperature in the subthreshold or linear region.

[0228] The k+1 level is similarly adjusted by adjusting the reference voltages VREFL and VREFH. This is, for example, to match the output range of this input block to the input range of the memory cell. This is also for temperature compensation by adjusting the reference levels VREFL and VREFH to match the reference level of the memory cell's gate bias over temperature (shifting lower at high temperatures and higher at low temperatures, etc.). Further individual level adjustments and temperature compensation are performed by the level trimming circuit of mapping block 5361. Conversion (mapping) and temperature compensation are assisted, for example, by the calibration circuits shown in Figures 59 to 64.

[0229] Figure 54 shows an example of a global digital-to-analog converter and row decoder 5480 similar to that in Figure 53, with the addition of an intermediate reference level VREFMx. The adjustment and temperature behavior of the VREFMx reference level are controlled in the same way as those of the VREFH and VREFL reference levels. It includes an additional buffer 5482 for imposing the intermediate reference level on a resistor ladder to further adjust the IV slope match between the GDAC 5480 and the memory array inputs.

[0230] Figures 79 to 81 show additional details regarding optional implementation configurations of the global digital-to-analog converter and row decoder 5350 and 5480 shown in Figures 53 and 54.

[0231] Figure 79 shows the GDAC input level to output level selection method 7900. In this example, there are 4096 different level inputs (k=4095), 4 trim bits (m=3) TRIM[3:0] per output level, and 256 possible output levels (L0..Ln).

[0232] Figure 80 shows the GDAC input level to output level selection method 8000. In this example, there are 4096 level inputs (k=4095), 4 trim bits (m=3) TRIM[3:0] per output level, and 256 possible output levels (L0..Ln). Block 8001 is group selection. As shown, there are four groups. Block 8002 is a trim selection block that adjusts the 1024 possible outputs from group selection block 8001. Block 8003 is an output selection block with 64:1 multiplexing. As shown, fewer trim block circuits are required compared to Figure 79.

[0233] Figure 81 shows a GDAC input level to output level selection method 8100. In this example, there are 4096 level inputs (k=4095), 4 trim bits (m=3) TRIM[3:0] per output level, and 256 output levels (L0..Ln). Block 8101 is group selection. As shown, there are four groups. Blocks 8102 and 8103 are trim selection blocks that adjust the 1024 possible outputs from group selection block 8101. Blocks 8104 and 8105 are output selection blocks with 64:1 multiplexing. As shown, fewer trim block circuits are required compared to Figure 79. To reduce latency, a ping-pong method can be performed between blocks 8102 and 8104 on the one hand, and between blocks 8103 and 8105 on the other. For example, while block 8102 performs a trim operation on a first set of input levels, a second group of input levels is used in block 8103 to set the trim bits, and vice versa.

[0234] Figure 55 shows illustrative waveforms 5500 illustrating the linear voltage levels for sample-and-hold operation by row sample-and-hold buffers 4305, 4405, 4505, 4605, and 4705, respectively, as shown in Figures 43 to 47. The GDAC output can take several different values. Two examples of sampling values ​​that can be output by row sample-and-hold buffers 4305, 4405, 4505, 4605, and 4705 are shown: a first sampling value and a second sampling value. Such values ​​are suitable for memory cells in VMM arrays operating in the linear domain where digital values ​​are converted to analog values ​​according to a linear function.

[0235] Figure 56 shows an illustrative waveform 5600 illustrating the logarithmic voltage level of the sample-and-hold operation illustrated by the row sample-and-hold buffers 4305, 4405, 4505, 4605, and 4705, respectively, as shown in Figures 43 to 47. The GDAC output can take several different values. Two examples of sampling values ​​that can be output by the row sample-and-hold buffers 4305, 4405, 4505, 4605, and 4705 are shown: a first sampling value and a second sampling value. Such values ​​are suitable for memory cells operating in a subthreshold region where digital values ​​are converted to analog values ​​according to a logarithmic function.

[0236] Alternatively, the global DAC voltage waveform can be used for memory cells operating in the saturation region.

[0237] Figure 57 shows two exemplary linear digital-to-analog outputs 5700 for 8-bit resolution (256 levels), with the two outputs generated at different operating temperatures.

[0238] Figure 58 shows an exemplary digital-to-analog output 5800 with segmented output. Each digital input corresponds to the same analog voltage output as in Figure 57, but the inputs are grouped into subgroups, each corresponding to a different voltage curve. For example, inputs L0-L63 correspond to voltage curve V1, inputs L64-L127 correspond to voltage curve V2, inputs L128-L191 correspond to voltage curve V3, and inputs L192-L255 correspond to voltage curve V4. This can be achieved, for example, by using the two most significant bits to determine which voltage curve V1, V2, V3, or V4 to apply, and then converting the remaining six bits to the appropriate voltage for the selected voltage curve. In this example, since one-quarter of the number of digital inputs need to be converted by the global DAC, the global DAC sampling time is reduced to one-quarter. Instead of four segments, other numbers of segments such as two, eight, or sixteen can be used.

[0239] Figure 59 shows an exemplary row-bias (IV cell / array) calibration circuit 5900, which comprises a current digital-to-analog converter 5901, an operational amplifier (op-amp) 5902, a transistor 5903 illustrated as a FET, and a memory cell 5904. The current digital-to-analog converter 5901 receives a digital input DIN[0:n] and outputs an analog current, where DIN[0:n] provides a range of digital values ​​corresponding to the possible currents drawn by the memory cell 5904. The op-amp 5902, with a cascode transistor 5903, applies a bias reference voltage VREF to the bit line of the memory cell 5904. The voltage from the control gate terminal of the memory cell 5904 is output as CGbias. As the current from the IDAC 5901 changes, the voltage from the control gate terminal changes accordingly.

[0240] Calibration circuit 5900 can be used to generate voltage CGbias for a current range of 1 to 128 nA in 0.5 nA steps for 256 levels in subthreshold operation. Thus, there are 256 levels for voltage CGbias, each level reflecting one of 256 current levels, each having 0.5 nA per current step. These CGbias values ​​can be applied to rows of memory cells in the VMM array to compensate for variations in the DAC and GDAC circuits shown in Figures 43 to 47, so that a given digital input has the same effect on memory cells in the VMM array, regardless of which DAC circuit the row containing the memory cells is attached to.

[0241] The calibration circuit 5900 can also be used to generate an equivalent voltage for a given current, such as the neuron current (bit line current). For example, for a neuron current of 10 μA, there is a corresponding CG voltage. In this case, the memory cell 5904 would contain multiple cells (operating in subthreshold mode) each having several mixed current patterns to represent the data patterns in the neural memory array. The CG bias voltage obtained when multiple cells are used is applied to the array during read operations so that the neuron current and array current do not change with temperature.

[0242] The memory cells 5904, 6004, 6134, and 6254 (described below) in Figures 59 and 60-62 can be part of a main VMM array such as the VMM array 3401 in Figure 34, or they can be a separate reference sector or an external miniarray.

[0243] Figure 60 shows a row bias calibration circuit 6000 comprising a current digital-to-analog converter (IDAC) 6001, an operational amplifier 6002, a comparator 6006, a FET 6003, and a memory cell 6004. The FET 6003 performs a cascading function. The current digital-to-analog converter 6001 receives a digital input DIN[0:n] and outputs an analog current, where DIN[0:n] provides a range of digital values ​​corresponding to the possible currents drawn by the memory cell 6004. The operational amplifier 6002, having a cascode FET 6003, applies a bias reference voltage VREF to the bit line BL (first terminal) of the memory cell 6004. The comparator 6006 receives a second reference voltage VREF2 at its inverting input and generates a control signal 6007 at its output. The voltage at the control gate (second terminal) of memory cell 6004, i.e., CGbias, is swept until comparator 6006 switches polarity, which means that control signal 6007 changes value when the first terminal of cascode FET 6003 exceeds VREF2. The change in control signal 6007 is used to sample and hold the control gate bias CGbias, which is then used as a bias voltage applied to the control gate terminal of the cell row in the VMM array. The source line (third terminal) of memory cell 6004 may be connected to ground.

[0244] The application of calibration circuit 6000 is the same as that of calibration circuit 5900 shown in Figure 59.

[0245] Figure 61 shows an exemplary row-bias calibration circuit 6130 comprising a current DAC 6131, an operational amplifier 6132, and a memory cell 6134. The operational amplifier 6132 outputs a voltage to terminal CG (second terminal) of the memory cell 6134 so that the current in the memory cell 6134 is the same as the current in the IDAC 6131. ​​The application of the calibration circuit 6100 is the same as that of the application in Figure 59. VREF is a voltage used to adjust the exact voltage of the bit line BL (first terminal of the memory cell 6134) to reduce inaccuracies due to bit line voltage variations. For example, VREF may be 0.6V, which means that the voltage bit line during this operation is 0.6V. The source line (third terminal) of the memory cell 6134 may be connected to ground.

[0246] Figure 62 shows an exemplary row bias calibration circuit 6250 comprising a current DAC 6251, a bias control circuit 6252, and a memory cell 6254. The current DAC 6251 is connected to the bit line (first terminal) of the memory cell 6254. The bias control circuit 6252 outputs voltages to the CG and EG terminals (both can be called the second or fourth terminals) of the memory cell 6254, respectively, so that the current in the memory cell 6254 is the same as the current in the IDAC 6251. VREF is a voltage used to adjust the voltage of the bit line BL (the first terminal of the memory cell 6254). The application of circuit 6250 is the same as the application in Figure 59. The source line (third terminal) of the memory cell 6254 may be connected to ground. The voltages of both the CG and EG terminals may be set until the bit line voltage exceeds VREF, at which point the CG and EG voltages can be applied to the VMM array as bias voltages.

[0247] Figure 63 shows an exemplary bias control circuit 6352. It comprises an operational amplifier 6362 (first operational amplifier) ​​having an inverting terminal for receiving a voltage from a first terminal (BL) of a non-volatile memory cell, a non-inverting terminal for receiving a reference voltage, and a first output, and a gain circuit consisting of an operational amplifier 6363 (second operational amplifier) ​​and input resistor R1 6367 and feedback resistor R2 6368. The gain is set by the ratio of R2 / R1, which can be, for example, about 1.9. Thus, EGBIAS, which is the output of operational amplifier 6363, is about 1.9 times CGbias. Other ratios are also possible. CGbias may be provided as a function of EGbias in other examples.

[0248] Figure 64 shows an exemplary calibration circuit 6470 comprising a current DAC 6471, an operational amplifier 6472, and a memory cell 6473. The output of the current DAC 6471 is connected to the bit line (first terminal) of the memory cell 6473. The operational amplifier 6472 outputs a voltage to the EG terminal (second terminal) of the memory cell 6473 so that the current in the memory cell 6473 is the same as the current of the IDAC 6471. VREF is a voltage used to adjust the voltage on the bit line BL (first terminal of the memory cell 6473). Optionally, the operational amplifier 6472 can be replaced with a bias control EGCG_CTL circuit 6452 as shown in Figure 63, where the bias control circuit 6452 outputs voltages on terminals CG and EG so that the current in the memory cell 6473 is the same as the current of the IDAC 6471. The source line (third terminal) of the memory cell 6473 is connected to ground.

[0249] Figure 65 shows an input block 6500 comprising a multiplexer 6501, a capacitor bank 6502, and a buffer 6503. The multiplexer 6501 receives m+1 digital bits [m:0] as a selection signal and also receives voltages from n+1 capacitors (L0, ...Ln), and in response to the received digital bits, provides a selected voltage to the buffer 6503, which outputs the selected voltage as a bias voltage. This is another method for generating the DAC output (instead of the method illustrated in Figures 43-47). In one example, an 8-bit DAC (m=7) thus comprises 256 capacitors (n=255) to hold 256 voltage levels. These voltage levels are generated, for example, by a linear or logarithmic function based on the digital bit input by the row bias calibration circuit in Figures 59-64.

[0250] Figure 66 shows an exemplary row input circuit 6600. The row input circuit 6600 comprises switches 6601, 6602, 6603, 6604, and 6605, capacitors 6606 and 6607, and a comparator 6608. The row input circuit 6600 provides buffer and offset calibration functions. The offset capacitor 6606 samples the offset voltage of the operational amplifier 6608 when switches 6603 (second switch) and 6602 (third switch) are closed and switches 6601 (first switch) and 6605 are opened. Next, capacitor 6606 is reconnected in reverse order, with switch 6601 (first switch) closed and switches 6603 (second switch) and 6602 (third switch) open, so that the offset voltage of capacitor 6606 cancels out the offset of op-amp 56098.

[0251] Figure 67 shows an exemplary global input generator 6700 comprising a global digital-to-analog converter 6701, a global digital-to-analog converter 6702, and switches 6703 and 6704. The global input generator 6700 enables real-time calibration without delaying normal operation. For example, the global digital-to-analog converter 6701 may be used to calibrate an array, and the global digital-to-analog converter 6702 may be used for readout neural operation, and vice versa.

[0252] Calibration can also be performed during the manufacturing process using calibration systems such as those shown in Figures 68 to 70 below.

[0253] Figure 68 shows a manufacturing calibration system 6800 comprising an array 6801, a neuron current comparison circuit 6802, and a bias controller 6803. Array 6801 is part of the VMM system being calibrated and is ultimately sent into the field for use. The neuron current comparison circuit 6802 and bias controller 6803 may be within the same VMM system for use during the manufacturing process, or they may be part of an external test apparatus used only during manufacturing. Array 6801 is programmed to store a predetermined set of weights. Neuron output currents are then generated, sampled, and compared by the neuron current comparison circuit 6802 to a target neuron current for that predetermined set of weights. Based on the comparison, the bias controller 6803 modifies the bias voltage applied to the CG or EG terminal of a selected cell until the neuron current comparison circuit 6802 indicates that the neuron output is equal to or within an acceptable threshold for the target neuron current. This may be performed on an entire neural network (which may include multiple layers), a single layer, or a portion of a single layer, but is not limited to this. Therefore, the neuron current comparison circuit 6802 is a sampling neuron circuit that receives current from multiple bit lines and generates an analog output from sampling of current from multiple bit lines.

[0254] Figure 69 shows a manufacturing calibration system 6900 comprising array 6801 (first array), reference array 6901 (second array), neuron current comparator circuit 6802, and bias controller 6803. Each bit line is coupled to a column in array 6801 and a column in reference array 6901. Manufacturing calibration system 6900 is similar to manufacturing calibration system 6800, except that the operation is performed on the embedded reference array 6901 rather than on array 6801. Array 6801 is used for normal vector matrix multiplication operations.

[0255] Figure 70 shows a manufacturing calibration system 7000 comprising a reference array 7001, a neuron current comparison circuit 6802, and a bias controller 6803. The manufacturing calibration system 7000 is similar to the manufacturing calibration system 6900, except that the reference array 7001 is separate and not integrated into the same device as the main VMM array.

[0256] The neuron current sampling in Figures 68 to 70 may represent the average value of the weight distribution of the neural layer or network.

[0257] Whenever the circuit optionally utilizes a reference current Iref, the reference current can be generated using the reference array 6901 or 7001 shown in Figures 69 and 70. This is useful because any changes to the reference array 6901 or 7001 (such as those due to temperature changes or corrections made through calibration) propagate to the generation of the reference current.

[0258] Figure 71 shows an array calibrator 7100 comprising an array 7101, a current source 7102, and a bias control circuit 7103. The current source 7102 supplies a target current. Array 7101 provides a sampling neuron current output. Array 7101 can be calibrated by changing a control gate bias or erase gate bias signal (which is a calibration parameter) applied to part or all of the array by the bias control circuit 7103 during a readout operation. When the current supplied by array 7101 is equal to that supplied by the current source 7102, the output switches polarity, indicating that the applied control gate bias or erase gate bias is appropriate. Optionally, the calibration parameters, along with the operating temperature and values ​​stored in the array, can be stored in a lookup table.

[0259] Figure 72 shows an exemplary current-to-voltage converter 7200 comprising an array 7201, a resistor 7202, and a bias control circuit 7203. The resistor 7202 supplies the output voltage. Array 7201 provides the sampling neuron current output. The sampling neuron current output from array 7201 can be varied by changing the control gate bias or erase gate bias signal applied to the array by the bias control circuit 7203 during readout operation. The desired configuration for the control gate bias or erase gate bias is achieved when the output voltage is equal to the desired target voltage. This can be used, for example, in conjunction with Figures 68 to 70.

[0260] Figure 73 shows an exemplary calibration method 7300. The method begins (operation 7301). The next operation is to calibrate the array of nonvolatile memory cells (operation 7302). The characteristics of the array (here, the voltage at the control gate terminal or erase gate terminal) are measured and compared to a target, such as a target voltage (or current) (operation 7303). If the measured voltage is equal to the target voltage or deviates by an acceptable margin (which is a predetermined range), operation 7303 is repeated periodically to determine whether calibration is needed, if so, which may occur, for example, when the operating temperature changes. If the measured voltage is neither equal to the target voltage nor deviates by an acceptable margin (which is a predetermined range), calibration operation 7302 is repeated.

[0261] Figure 74 shows an exemplary calibration method 7400. The method begins (operation 7401). The next operation is to calibrate the array of nonvolatile memory cells (operation 7402). The temperature sensor measures a characteristic (in this case, temperature) and compares it to the target temperature (operation 7403). If the measured temperature is equal to the target temperature or deviates by an acceptable margin (a predetermined range), operation 7403 is repeated periodically to determine whether calibration is needed, if so, which may occur when the operating temperature changes. If the measured temperature is neither equal to the target temperature nor deviates by an acceptable margin (a predetermined range), calibration operation 7402 is repeated.

[0262] Figure 75 shows an exemplary calibration method 7500. The method begins (operation 7501). The next operation is to calibrate the array of nonvolatile memory cells (operation 7502). A temperature sensor measures a characteristic (here, temperature) and compares it to the target temperature (operation 7503). If the measured temperature is equal to the target temperature or differs by an acceptable margin (a predetermined range), operation 7503 is repeated periodically. If the measured temperature is not equal to the target temperature and does not deviate by an acceptable margin (a predetermined range), the method proceeds to operation 7504, where the array characteristic (voltage or current, here, the voltage at the control gate terminal or erase gate terminal) is compared to the target voltage. If the measured array characteristic (e.g., voltage) is equal to the target or differs by an acceptable margin (a predetermined range), the method returns to operation 7303. If the measured characteristic is not equal to the target characteristic and does not deviate by an acceptable margin (a predetermined range), the method returns to operation 7502 and repeats the calibration. The advantage of calibration method 7500 is that the calibration procedure is repeated only if the measured array characteristic is actually different from the target. For example, if the measured temperature may differ from the target temperature, but the measured array characteristic may still be within an acceptable margin (a predetermined range) compared to the target, the calibration is not repeated.

[0263] Figure 76 shows an exemplary calibration method 7600. The method begins (operation 7601). The next operation is to calibrate the array of nonvolatile memory cells (operation 7602). A time sensor measures the time of an event and compares it to a target time, where time may be related to a thermal conductivity, such as the time it takes for a 1-degree increase to be detected at a distance of X (thermal conductivity) (operation 7603). If they are equal or differ by only an acceptable margin (a predetermined range), operation 7603 is repeated periodically to determine whether calibration is necessary. If they are not equal and do not differ by only an acceptable margin (a predetermined range), method 7400 triggers calibration operation 7402.

[0264] Figure 77 illustrates the calibration method 7700 for the global digital-to-analog converter and row decoder 5350 or 5480 in Figures 53 and 54. The method begins (operation 7801). Calibration is performed by adjusting the global reference levels VREFL, VREFH, and / or VREFM in Figure 53 or 54 (operation 7802), which adjusts the output DAC_OUT, which will then be used to generate bias voltages for multiple rows in input blocks 4300, 4400, 4500, 4600, and 4700 in Figures 43-47. The method ends (operation 7803).

[0265] Figure 78 shows an exemplary calibration method 7800 used for the global DAC 4707 and local DAC 4704 in Figure 47. The method starts (operation 7801). Calibration is performed on the global DAC and line decoder 5350 or 5480 (Figures 53 and 54) used for the GDAC 4707 in Figure 47 (operation 7802), by adjusting the global reference levels VREFL, VREFH, and / or VREFM in Figures 53 and 54, which adjusts the output DAC_OUT. The local digital-to-analog converter 4704 in Figure 47 is then calibrated in Figure 47 (operation 7803). The method ends (operation 7804).

[0266] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is a system, A digital-to-analog converter for receiving kbit input and generating a first analog output, A mapping scalar for converting the first analog output to a second analog output, A system comprising: an analog-to-digital converter for generating an n-bit output from the second analog output, wherein n is a value different from k.

2. The system according to claim 1, wherein the digital-to-analog converter performs a linear function.

3. The system according to claim 1, wherein the digital-to-analog converter performs a logarithmic function.

4. It is a system, Reference array and A bias generator for generating one or more bias voltages based on the aforementioned reference array, A system comprising a digital input and a digital-to-analog converter for generating an analog signal to be applied to a non-volatile memory array in response to one or more generated bias voltages.

5. The system according to claim 4, wherein the digital-to-analog converter performs a linear function.

6. The system according to claim 4, wherein the digital-to-analog converter performs a logarithmic function.

7. It is a system, A digital-to-analog converter for generating voltages for linear or subthreshold operation of non-volatile memory cells in an array, A system comprising: a mapping block for converting the voltage generated from the digital-to-analog converter into an analog output.

8. The system according to claim 7, further comprising an output buffer for providing the analog output as the output of the system.

9. The system according to claim 7, wherein the digital-to-analog converter performs a linear function.

10. The system according to claim 7, wherein the digital-to-analog converter performs a logarithmic function.

11. The system according to claim 7, wherein the non-volatile memory cell in the array is a split-gate flash memory cell.

12. The system according to claim 7, wherein the non-volatile memory cell in the array is a stacked gate flash memory cell.

13. It is a system, A capacitor bank comprising multiple capacitors, wherein each of the multiple capacitors stores a different voltage, A multiplexer for outputting the voltage of one of the plurality of capacitors in response to a digital input, A system comprising: a buffer for receiving the output voltage from the multiplexer and generating a bias voltage.

14. The system according to claim 13, wherein the bias voltage is based on a linear function using the value of the digital input.

15. The system according to claim 13, wherein the bias voltage is based on a logarithmic function using the value of the digital input.

16. It is a system, An operational amplifier including an inverting input, a non-inverting input, and an output, An offset capacitor having a first terminal and a second terminal, wherein the second terminal is connected to the inverting input, The first switch, The second switch, A third switch is provided, In the first mode, the first switch is open, the second switch is closed to connect the output of the operational amplifier to the inverting input, and the third switch is closed to connect the first terminal of the offset capacitor to the non-inverting input. In the second mode, the first switch is closed to connect the output of the operational amplifier to the first terminal of the capacitor, the second switch is open, and the third switch is open, in the system.

17. It is a system, The first global digital-to-analog generator, A system comprising a second global digital-to-analog generator.

18. A first switch between the output of the first global digital-to-analog generator and the output node, The system according to claim 17, further comprising a second switch between the output of the second global digital-to-analog generator and the output node.

19. The system according to claim 18, wherein the first global digital-to-analog generator is used to calibrate the memory array, and the second global digital-to-analog generator is used for readout neural operations.

20. It is a system, A first array of multiple non-volatile memory cells arranged in multiple rows and multiple columns, Multiple bit lines, each bit line being connected to each column in the first array, A system comprising: a sampling neuron circuit for receiving current from a plurality of bit lines and generating an analog output from sampling of the current from the plurality of bit lines, wherein the analog output includes neuron currents in a neural network.

21. The system according to claim 20, wherein the plurality of non-volatile memory cells in the first array are split-gate flash memory cells.

22. The system according to claim 20, wherein the plurality of non-volatile memory cells in the first array are stacked gate flash memory cells.

23. The system according to claim 20, wherein the first array is a reference array.

24. The system according to claim 23, comprising a second array of multiple nonvolatile memory cells arranged in multiple rows and multiple columns.

25. The system according to claim 24, wherein each bit line is coupled to a column in the second array.

26. The system according to claim 24, wherein the plurality of non-volatile memory cells in the second array are split-gate flash memory cells.

27. The system according to claim 22, wherein the plurality of non-volatile memory cells in the second array are stacked gate flash memory cells.

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