System and method for adaptive power multiplexing using a first type power multiplexer and a second type power multiplexer

Abstract

This invention provides circuits and methods for more efficiently utilizing routing space and chip area in power distribution networks (PDNs). [Solution] A system-on-a-chip (SOC) includes a PDN having two different types of power multiplexers. A first power multiplexer of the first type includes low-resistance switching logic, and a second power multiplexer of the second type includes high-resistance switching logic and digital logic that provides an enable signal to the first type power multiplexer. A given first type power multiplexer has a number of second type power multiplexers in a loop, the loop includes a communication path for the enable signal, and the enable signal is fed back to the enable input of the first type power multiplexer.

Description

Technical Field

[0001] Cross - reference to Related Applications

[0001] This application claims priority and the benefit of U.S. Patent Application No. 17 / 662,460, filed on May 9, 2022. Its disclosure is incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002]

[0002] This application generally relates to power multiplexing, and more specifically, to using a first type of power multiplexer and a second type of power multiplexer to provide adaptive power multiplexing.

Background Art

[0003]

[0003] Conventional computing devices (e.g., smartphones, tablet computers, etc.) may include a system - on - chip (SOC) having a processor and other arithmetic circuits. The SOC can receive its power from a battery, and thus, conventional designs can balance SOC performance and power usage to provide a desirable user experience while requiring as little battery charging as possible.

[0004]

[0004] Power multiplexing is a technique that can be used to conserve power in some cases. One way in which some systems may use power multiplexing to conserve power is to allow power collapse to some parts of the processing core (using a first power multiplexer and a first power domain) while supplying power to other parts of the processing core (using a second power multiplexer and a second power domain). Another way in which some conventional systems may use power multiplexing is to switch from a first power supply to a second power supply to power the central processing unit (CPU) memory and adjust the second power supply to overdrive the CPU memory. This technique can conserve power by allowing the SOC to selectively increase the voltage in some components while not increasing the voltage in other components. [Overview of the Initiative]

[0005]

[0005] Various implementation configurations provide circuits and techniques for more efficiently using routing space and chip area in a power distribution network (PDN). Some implementation configurations may use a first type of power multiplexer (e.g., having high-resistance switches) and a second type of power multiplexer (e.g., having low-resistance switches) to distribute power multiplexing functionality within a semiconductor chip. For example, a first type of power multiplexer may provide an enable signal to a second type of power multiplexer, which may be distributed across the chip in a daisy-chain or other configuration. Both the first and second type of power multiplexers may be implemented to conserve routing space within the chip, thereby providing a PDN that has less impact on routing and uses semiconductor area more efficiently than other implementation configurations.

[0006]

[0006] According to one implementation configuration, the system-on-chip (SOC) includes a first power multiplexer of a first type coupled to a first power supply and a second power supply, the first power multiplexer including a first switching logic disposed between the first power supply, the second power supply and the load, and a second power multiplexer of a second type coupled to the first power supply and the second power supply, the second power multiplexer including a second switching logic between the first power supply and the second power supply and the load, the second switching logic including an enable input coupled to the first power multiplexer.

[0007]

[0007] According to one implementation, the method includes transmitting an enable signal from a first power multiplexer of a first type to a second power multiplexer of a second type, and switching a first load from a first power source to a second power source by the first power multiplexer and the second power multiplexer, wherein the second power multiplexer switches the first load in response to the enable signal, and the first power multiplexer receives the enable signal.

[0008]

[0008] According to one implementation configuration, the semiconductor chip is a first power multiplexer of a first type and a second power multiplexer of a first type, the first power multiplexer and the second power multiplexer being arranged in a daisy chain with a controller, the daisy chain passing control signals from the controller to the first power multiplexer, then to the second power multiplexer, and then feeding the control signals back to the controller, the first power multiplexer and the second power multiplexer and the third and fourth power multiplexers of a second type being arranged in a first loop from the first power multiplexer, the first The loop includes a third and fourth power multiplexer, which pass a first enable signal from a first power multiplexer to a third and fourth power multiplexer and back to the first power multiplexer; and a fifth and sixth power multiplexer of a second type, which are arranged in a second loop from a second power multiplexer, the second loop including a fifth and sixth power multiplexer, which pass a second enable signal from a second power multiplexer to a fifth and sixth power multiplexer and back to the second power multiplexer.

[0009]

[0009] In yet another implementation, a power distribution network (PDN) on a semiconductor chip, the PDN comprising a first means for multiplexing between a first power source and a second power source, and a second means for multiplexing between the first power source and the second power source, the second means configured to receive an enable signal from the first means, the enable signal causing the second means to select between the first power source, the second power source, and a power collapse, wherein the first means comprises a first type of power multiplexer, the second means comprises a second type of power multiplexer different from the first type of power multiplexer, and further, the second means comprises a plurality of second type power multiplexers arranged in a loop to feed back the enable signal to the first means. [Brief explanation of the drawing]

[0010] [Figure 1]

[0010] This is a simplified diagram showing an exemplary power multiplexer in one implementation configuration. [Figure 2]

[0011] This is a diagram illustrating an exemplary multiplexed circuit configuration that includes two different types of switching logic in a single implementation. [Figure 3]

[0012] This shows an example of the switching logic of a power multiplexer in one implementation configuration. [Figure 4]

[0013] This is a diagram illustrating an example of a switching voltage generator in one implementation configuration. [Figure 5]

[0014] This is a diagram illustrating an example of a power multiplexing circuit in one implementation configuration. [Figure 6]

[0015] This is a diagram illustrating an example of a power multiplexing circuit in one implementation configuration. [Figure 7]

[0016] This is a diagram illustrating an example power distribution network (PDN) using multiple types of power multiplexers in a single implementation configuration. [Figure 8]

[0017] This figure shows an example PDN in one implementation configuration. [Figure 9] This figure shows an example PDN in one implementation configuration. [Figure 10] This figure shows an example PDN in one implementation configuration. [Figure 11]

[0018] This figure shows an exemplary application example of PDN applied to a memory device in one implementation configuration. [Figure 12]

[0019] This is a diagram illustrating an exemplary method adapted to one implementation configuration. [Figure 13]

[0020] This is a diagram of an exemplary chip having power multiplexing according to the principle described herein, in a single mounting configuration. [Modes for carrying out the invention]

[0011]

[0021] Some power multiplexing architectures allow numerous power multiplexing components, such as high-resistance switches, low-resistance switches, and enable logic, to be included in a single power multiplexing circuit. However, these power multiplexing circuits may use an undesirable amount of routing space within the system-on-chip (SOC) or processing unit. In this art, there is a need for more efficient use of routing space in power distribution networks (PDNs).

[0012]

[0022] The various implementations provided herein include systems and methods for providing power multiplexing using first-type and second-type power multiplexers. For example, the first-type power multiplexer may include digital logic and a first switching logic disposed between a first power supply, a second power supply, and a load. The second-type power multiplexer may be coupled to the first and second power supplies and may include a second switching logic disposed between the first power supply, the second power supply, and a load. The second switching logic may include an enable input coupled to the digital logic of the first-type power multiplexer. Thus, in some examples, the first-type power multiplexer may provide control signals for the second-type power multiplexer.

[0013]

[0023] Continuing with the example, the first switching logic can be implemented to have a higher resistance than that of the second switching logic. In one example, the first switching logic may be referred to as a "minority switch", and the second switching logic may be referred to as a "standby switch", but these terms are used for convenience rather than to define the switching logic. In one implementation, the first switching logic can be turned on to create a conductive path with a high resistance during a first period of the voltage switching operation, and the second switching logic can be turned on to create another conductive path with a low resistance while the first switching logic is off during a second time period of the voltage switching operation. Thus, when the voltage is switched from one voltage source to another, there can be a time period during which the high resistance is applied with the help of the minority switch to avoid current inrush or protrusion.

[0014]

[0024] As described above, the first type of power multiplexer can provide an enable signal to the second type of power multiplexer. For example, the second type of power multiplexer may be arranged in series with other similar power multiplexers with respect to the enable signal, whereby the enable signal generated from the first type of power multiplexer is transmitted on a conductive path through the second type of power multiplexer and returned to the enable input in the first type of power multiplexer. In fact, some implementations may include a number of first type of power multiplexers arranged in a daisy chain (e.g., sometimes referred to as a "main chain"), and each of the first type of power multiplexers may have a second type of power multiplexer arranged in its respective chain (e.g., sometimes referred to as a "secondary chain").

[0015]

[0025] Each of the power multiplexers can service a load. For example, a block of memory cells can be serviced by a number of secondary chains. Each power multiplexer within a secondary chain can switch between a first power source, a second power source, and a power breakdown.

[0016]

[0026] Continuing with this example, the power domain of the chip may include a main chain and one or more secondary chains. The chip may include a number of power domains, and the second power domain may include a second main chain having one or more secondary chains of its own.

[0017]

[0027] In one example, the transistors of the minority switches and the standby switches can be controlled using a switching voltage that is generated to be above the highest voltage of two different power supplies. The purpose of the switching voltage can be to have a gate-source voltage that is 0 or greater during the off period of the transistor to ensure that the transistor is turned off. The voltage generator can be implemented in any suitable part of the power multiplexer architecture. For example, the voltage generator may be implemented within a first type of power multiplexer, a second type of power multiplexer, or may be a stand-alone structure. Any suitable method can be used to supply a voltage from the switching voltage generator to the gates of the transistors of the first switching logic and the second switching logic.

[0018]

[0028] The placement of the switching voltage generator can affect the overall architecture of the power distribution network (PDN). For example, in an example where a second type of power multiplexer is implemented with the switching voltage generator, it may result in a larger structure of individual second type of power multiplexers, but can reduce the amount of switching voltage routing. On the other hand, other implementations may include the switching voltage generator in some but not all of the second type of power multiplexers, or may use a stand-alone switching voltage generator. Such implementations can reduce the size of the second type of power multiplexer (at least the power multiplexer without the switching voltage generator) at the expense of an increase in switching voltage routing.

[0019]

[0029] Various implementation forms may offer advantages over other systems. One advantage may include increased space savings. For example, each of the second type of power multiplexer may contain a number of transistors in parallel to provide the desired resistance, and lower resistances may correspond to more transistors in parallel. As a result, the second type of power multiplexer (sleep switch) may utilize on-chip routing resources across a number of metal layers. When paired with the first type of power multiplexer (minority switch), the resulting structure may use an undesirable number of metal layers within the chip structure.

[0020]

[0030] The various implementations of this disclosure move the quiescent switches into their own multiplexing structures and out of structures containing minority switches. As a result, fewer routing resources and fewer metal layers can be used, even with the same number of transistors. In other words, routing congestion can be reduced by moving the quiescent switches away from the minority switches, and fewer metal layers can be used for routing. For example, the implementations of this disclosure may use a total of six metal layers, while structures with both minority switches and quiescent switches may use nine or more metal layers. Of course, the scope of implementation is not limited to any number of metal layers, and this comparison is given for the sake of clarity. Furthermore, the reduction in routing congestion may allow other components to be moved closer to the power multiplexer within the chip design, thereby enabling more efficient use of semiconductor area.

[0021]

[0031] Figure 1 is a conceptual diagram of an example of an adaptive power multiplexing circuit configuration in one implementation form. Figure 1 shows a simplified block for illustrating the power multiplexer 110 and the enable logic circuit configuration block 124. The enable logic circuit configuration block 124 includes a forward path that can communicate with power management software, such as within the operating system kernel running on the processor core of the SOC. The forward path may include signals from the power management software that instruct the enable logic circuit configuration block 124 to select one or the other power supply Vdd1, Vdd2. A switching signal "sel" is provided from the enable logic circuit configuration block 124 to the multiplexer 110, and an assert or deasser selects one or the other power supply Vdd1, Vdd2. Although not further described herein, the enable logic circuit configuration block 124 may have further control signal outputs to other components (not shown) and may receive control signal inputs from them or other components (not shown) on a feedback path. Furthermore, the enable logic circuit configuration block 124 may also provide control signal feedback to the power management software.

[0022]

[0032] The output (Vdd_apm) of the power multiplexer 110 is supplied to a load (not shown), such as a memory block, a processing block, or other components on the chip. The power multiplexer 110 is a 2:1 multiplexer that selects between two power supplies Vdd1 and Vdd2 and drives the load output at the voltage Vdd_apm. The circuit in Figure 1 is adaptive in that it is configured to select a specific power rail in response to an external reference, such as passing through a control signal input in the forward path and a control signal output in the feedback path. The switching signal (sel) in this example is at a voltage level (Vdd_aon) greater than or equal to the larger of Vdd1 and Vdd2. The switching voltage level Vdd_aon ensures that the transistors in the multiplexer 110 turn off when Vdd_aon is applied to the control input (e.g., base) of those transistors.

[0023]

[0033] The power management logic within the chip may select Vdd1 or Vdd2 at a given time according to the operating mode. As described above, the exemplary operating system kernel may include power management software that can control power usage within the chip. For example, the power management software may decide to put one or more central processing unit (CPU) cores into turbo mode and increase the voltage in one or more memory blocks to support CPU turbo mode. Similarly, the power management software may decide to put one or more CPU cores into a low operating mode that matches power saving during normal operation. In such a case, the power management software may decrease the voltage in one or more memory blocks. Furthermore, in this example, either increasing or decreasing the operating voltage in the memory blocks may include controlling the power multiplexer 110 to select either the higher or lower power supply in accordance with the operating mode.

[0024]

[0034] Figure 2 shows an exemplary power multiplexing architecture 200 in one implementation configuration. In this example, there are two power supplies, namely a CX power supply and an MX power supply, which may have different voltage levels (e.g., Vdd1 and Vdd2 in Figure 1, respectively). The power multiplexing architecture 200 supplies a power output Vdd_apm to the load 230 by selecting either the power rail associated with the CX power supply or the power rail associated with the MX power supply. Furthermore, the power multiplexing architecture 200 can be used to power collapse the load 230, in which case both switches 211 and 212 will be turned off, thereby disconnecting the load 230 from both power rails.

[0025]

[0035] The power multiplexing architecture 200 includes two different switch types. Switch 211 is a first type switch, and switch 212 is a second type switch. In one implementation, switch 211 may have a low resistance (e.g., 1 ohm), while switch 212 may have a high resistance (e.g., 50 ohms). Of course, these values ​​are illustrative, and the implementation range is not limited to these resistance values.

[0026]

[0036] Continuing this example, switch 212 may be used during a first time period of voltage switching operation to prevent inrush or surge current from load 230. For example, when transitioning from collapsed power to CX power level, from collapsed power to MX power level, from MX power level to CX power level, or vice versa, switch 212 may be turned on (e.g., closed) while switch 211 is turned off (e.g., open). Current then flows through the high-resistance switch 212 between the selected power rail and the load. After a certain time (e.g., microseconds), both switches 212 may be turned off, but the corresponding switch 211 may be turned on, thereby providing current through the low-resistance switch for the duration of steady-state operation.

[0027]

[0037] For example, consider a scenario where the power multiplexing architecture 200 switches from a power collapse to a voltage level associated with a power source CX. During the power collapse, both switches 211 and 212 are off. In the first part of the voltage switching operation, the architecture 200 turns on switch 212a, which allows current to flow between the power rail of power source CX and the load 230 at a high resistance associated with switch 212a. After some time has elapsed, the architecture 200 turns on switch 211a and off switch 212a, thereby allowing current to flow through a low resistance associated with switch 211a.

[0028]

[0038] Although switches 211 and 212 are shown as single switches, various implementations may implement each of them as a group of switches. For example, the low-resistance switch 211 may be designed to include a number of individual transistors in parallel to achieve low resistance. In addition, the transistor sizes may be selected to achieve the desired resistance. The high-resistance switch 212 may also be selected according to the number and size to achieve the desired resistance.

[0029]

[0039] The power multiplexing architecture 200 provides the same functionality as described above with respect to the implementation shown in Figure 1, but additionally uses two different types of switches 211 and 212 to prevent inrush and spikes during switching operations. These two different types of switches 211 and 212 are sometimes referred to as a dormant switch (211) and a minority switch (212) in some examples. The various implementations described herein can separate the minority switch and dormant switch into a first type of power multiplexer and a second type of power multiplexer, as will be described in more detail below with respect to Figure 5. Furthermore, switch 212 is independent of switch 211. Rather, power multiplexer control will be described in more detail with respect to Figures 3 and 7.

[0030]

[0040] Figure 3 shows an exemplary idle switch 300 in one implementation configuration. For example, the p-type metal oxide semiconductor (PMOS) transistor 301 may correspond to switch 211b in Figure 2, and the PMOS transistor 302 may correspond to switch 211a.

[0031]

[0041] The hibernation switch 300 makes a selection between two power supplies, Vdd_mx and Vdd_cx. In one example, Vdd_mx represents the power supply used as the default for the memory block, and Vdd_cx represents the variable power supply used by the processor. Continuing this example, during turbo operation mode, Vdd_cx may be increased and supplied to the memory block by the power multiplexer using the hibernation switch 300. During non-turbo operation mode, the power multiplexer may use the hibernation switch 300 to select the Vdd_mx power supply for the memory block.

[0032]

[0042] The implementation shown in Figure 3 includes two enable signals, En_1 and En_2, and two P-type metal-oxide-semiconductor (PMOS) transistors 301 and 302. PMOS transistors 301 and 302 are off when the gate-source voltage is greater than or equal to 0, and on when the gate-source voltage is negative. Therefore, when En_1 is high and En_2 is low, transistor 301 is on, and the power multiplexer selects Vdd_mx to output as Vdd_apm. On the other hand, when En_1 is low and En_2 is high, transistor 302 is on, and the power multiplexer selects Vdd_cx.

[0033]

[0043] Inverter buffers 311, 312 and 313, 314 represent drivers for PMOS transistors 301 and 302. For example, inverter buffers 311 and 312 are powered by Vdd_aon, thereby applying Vdd_aon to the gate of transistor 301 when the output of inverter buffer 312 is high voltage (digital 1). Similarly, inverter buffers 313 and 314 are powered by Vdd_aon, thereby applying Vdd_aon to the gate of transistor 302 when the output of inverter buffer 314 is digital 1.

[0034]

[0044] Furthermore, the enable signals En_1 and En_2 are used so that only one of them is turned on at a given time, thereby preventing scenarios where Vdd_mx and Vdd_cx are short-circuited. Nevertheless, both En_1 and En_2 may be low, thereby neither power supply being selected.

[0035]

[0045] When transistor 301 is on and transistor 302 is off, the voltage Vdd_cx is applied to the gate of transistor 302. Vdd_aon is the switching voltage, selected to be the higher of Vdd_mx and Vdd_cx, thereby ensuring that the gate-source voltage remains greater than or equal to 0 even if the voltage level of Vdd_cx changes. Similarly, when transistor 301 is turned off, Vdd_aon is applied to its gate, thereby ensuring that the gate-source voltage remains greater than or equal to 0 while it is off.

[0036]

[0046] Vdd_aon may be provided by one or more voltage generators separate from or included within the power multiplexer, which includes one or more quiescent switches. The enable signal, representing a specific implementation of the switching signal (sel) in Figure 1, may be supplied by an enable logic circuit configuration block. Exemplary techniques for supplying Vdd_aon are described in more detail below with respect to Figure 4.

[0037]

[0047] Figure 4 shows an exemplary voltage generator 400 for a switching voltage Vdd_aon in one implementation configuration. As described above, the switching voltage Vdd_aon can be applied to transistors in a quiescent switch, such as transistors 301 and 302 in Figure 3.

[0038]

[0048] The control signals Sel_mx and Sel_cx may be supplied by a controller such as the controller 701 in Figure 7, which will be explained in more detail below. Only one of the control signals Sel_mx and Sel_cx will be high (digital 1) at any given time, and the control signals Sel_mx and Sel_cx cause the voltage generator 400 to select either the voltage associated with the MX power supply (Vdd_mx) or the voltage associated with the CX power supply (Vdd_cx) as the switching voltage Vdd_aon.

[0039]

[0049] Although not shown in Figure 4, the control signals Sel_mx and Sel_cx may be generated by a comparator that receives both Vdd_mx and Vdd_cx and outputs the control signals Sel_mx and Sel_cx based on a comparison of the voltage levels associated with Vdd_mx and Vdd_cx. For example, if Vdd_mx is higher than Vdd_cx, the comparator may output Sel_mx as a high voltage and Sel_cx as a low voltage. The reverse may also be true; therefore, if Vdd_cx is higher, Sel_mx may be output as a low voltage and Sel_cx as a high voltage.

[0040]

[0050] In the first example, the control signal Sel_mx is high and the control signal Sel_cx is low. As a result, a high voltage is applied to the gates of PMOS transistor P3 and N-type metal-oxide-semiconductor (NMOS) transistor N1. Similarly, a low voltage (digital 0) is applied to the gates of transistors P4 and N2. Transistors P3 and N2 are turned off, and transistors N1 and P4 are turned on, which applies a low voltage to the gates of transistors P2 and P6 and a high voltage to the gates of transistors P1 and P5. As a result, transistors P2 and P6 are turned on, and transistors P1 and P5 are turned off. Thus, the voltage Vdd_aon is Vdd_mx.

[0041]

[0051] In the second example, Vdd_cx is selected. The control signal Sel_mx is low, and the control signal Sel_cx is high. As a result, a low voltage is applied to the gates of PMOS transistor P3 and NMOS transistor N1. A high voltage (digital 1) is applied to the gates of transistors P4 and N2. Transistors P3 and N2 turn on, and transistors N1 and P4 turn off, which applies a high voltage to the gates of transistors P2 and P6 and a low voltage to the gates of transistors P1 and P5. As a result, transistors P2 and P6 turn off, and transistors P1 and P5 turn on. Therefore, the voltage Vdd_aon becomes Vdd_cx.

[0042]

[0052] Figure 5 shows exemplary power multiplexers 510, 520, and 530 in several implementation configurations. Specifically, Figure 5 is provided to illustrate a comparison between an exemplary power multiplexer 510, which includes both minority switches and quiescent switches, and an implementation configuration in which the minority switches are separated into a first type of power multiplexer and the quiescent switches into a second type of power multiplexer.

[0043]

[0053] First, looking at the power multiplexer 510, it includes a minority switch 511 and a quiescent switch 512. As mentioned above, in some implementations, combining the minority switch 511 and the quiescent switch 512 into a single power multiplexer unit such as a tile can result in routing congestion. Examples of the minority switch 511 and the quiescent switch 512 are provided in Figures 2 and 3 above. The power multiplexer 510 also includes an AON generator 515, which may conform to a circuit structure similar to or identical to that described above with respect to Figure 4. A comparator 513 may be used to provide selection signals to the AON generator. For example, as mentioned above in Figure 4, the switching voltage generator 400 receives enable signals Sel_mx and Sel_cx, and in some implementations, the comparator 513 may provide the same or similar signals to the AON generator 515. Digital block 514 may include digital logic that provides other enable signals to the minority switch 511 and the quiescent switch 512, causing switches 511 and 512 to select either the MX or CX power supply (or to power collapse the load). An example of such an enable signal is a 2-bit signal provided from the main tile 520 to the micro APM tile 530 in Figure 7 (described in more detail below).

[0044]

[0054] In contrast, various implementations use two different types of power multiplexers, shown here as power multiplexer 520 and power multiplexer 530. Power multiplexer 520 is sometimes referred to as the first type of power multiplexer, and sometimes as the main tile (Figure 7). Power multiplexer 520 includes a minority switch 521, which may be the same as or similar to minority switch 511. In some implementations, the size of minority switch 521 may be increased to the maximum size that still allows the circuit to achieve the desired resistance. Comparator 522 may be the same as or similar to comparator 513 and may apply a selection signal to AON generator 515. Digital block 523 may be the same as or similar to digital block 514 and may generate an enable signal that causes the minority switch 521 and the dormant switch of the micro APM tile 530 to select one or the other of the power supply (or neither).

[0045]

[0055] The second type of power multiplexer is shown as a micro APM (micro adaptive power multiplexer) tile 530, which includes a quiescent switch, such as one or more of the quiescent switches shown in Figure 3. In this example, the quiescent switch of the micro APM 530 is driven by Vdd_aon from the AON generator 515 and controlled by an enable signal from the digital logic block 523. As described above, the advantages of the implementations using the first and second types of power multiplexers include reduced routing congestion and more efficient use of semiconductor area compared to the power multiplexer 510 design.

[0046]

[0056] In some examples, there are an integer (xM) of micro APM tiles 530 that receive an enable signal from a single power multiplexer 520. The number xM can be chosen such that the combined resistance of the number of micro APM tiles 530 is greater than or equal to the combined resistance of xN instances of the power multiplexer 510.

[0047]

[0057] Figure 6 shows different configurations that may be used for the micro APM power tile 530 of Figure 5, in one implementation configuration. Configuration 650 provides a switching voltage generator 515 within the power multiplexer, along with a quiescent switch 611, which may be the same as or similar to the quiescent switch in Figure 3. Configuration 650 also includes a driver 612, which may be the same as or similar to the one implemented by the inverter buffers 311-314 in Figure 3. Configuration 650 is constructed to have the larger vertical dimension. In contrast, configuration 652 is similar to configuration 650, but instead is implemented within a horizontal channel, which has the larger horizontal dimension.

[0048]

[0058] Now, looking at configuration 654, it is similar to configuration 650, but does not include the switching voltage generator 515. As a result, configuration 654 is smaller than configuration 650. Configuration 656 is similar to configuration 654, but it is implemented so that its larger dimension is the horizontal dimension rather than the vertical dimension.

[0049]

[0059] The implementation in Figure 6 illustrates a second type of power multiplexer, for example, the concept that the micro-APM tile 530 in Figure 5 may or may not include the switching voltage generator 515. If the switching voltage generator 515 is not included in the micro-APM tile, it may be included elsewhere on the chip, but this comes at the cost of switching voltage routing between different micro-APM tiles. This concept is further explained with respect to Figures 8 to 11.

[0050]

[0060] Figure 7 shows an exemplary power multiplexing architecture 700 in one implementation configuration. The power multiplexing architecture 700 includes a main tile 520, a micro APM tile 530, and a controller 701. The main tile 520 includes a minority switch as the switching logic as described above with respect to Figure 5. Specifically, the main tile 520 in Figure 7 may be implemented the same as or similar to the first type of power multiplexer 520 in Figure 5.

[0051]

[0061] The micro APM tile 530 may be the same as or similar to the second type of power multiplexer 530 in Figures 5 and 6. The controller 701 may include a processing unit that controls the main tile 520 using a control signal 704 to select a power rail or to power collapse a load (not shown). For example, the main tile 520 may decode the control signal 704 to generate a control signal 703. The main tiles 520 are arranged in a daisy-chain with respect to each other and to the controller 701. In one implementation, the controller 701 controls the main tile 520a to select a power rail MX. The main tile 520a then controls the micro APM tiles 530a~d to select a power rail MX. For example, the main tile 520a may use the control signal 703 corresponding to the enable signals En_1 and En_2 in Figure 3 to control the micro APM tiles 530a~d. The micro APM tiles 530a to 530d are also arranged in a loop such that micro APM tile 530a first receives the control signal 703, which is then passed to micro APM tiles 530b to 530d, and then returned to the main tile 520a.

[0052]

[0062] When main tile 520a receives control signal 703 from micro APM tile 530D, main tile 530a passes control signal 704 to main tile 520b, which performs the same or similar power multiplexing as main tile 520a. For example, main tile 520b may also have a loop of micro APM tiles 530e~h, causing the micro APM tiles 530e~h to perform power multiplexing, and when main tile 520b receives control signal 703 from micro APM tile 530h, main tile 520b may transmit control signal 704 to main tile 520c. Of course, the range of implementation forms is not limited to the specific number of main tiles 520 or micro APM tiles 530 shown in Figure 7. Rather, the architecture 700 can be scaled to suit a given application.

[0053]

[0063] The micro APM tiles 530a to d are arranged in a loop, allowing either the main tile 520a or the controller 701 to check for faults. The same applies to loops containing micro APM tiles 530e to h. The daisy-chain arrangement of main tiles 520a to 520c allows the controller 701 to check for faults in the main tile 520 in a similar manner. Furthermore, in the example in Figure 7, there are fewer main tiles 520 than micro APM tiles 530, which means that the minority switches within the main tile 520 may draw a larger current than would be expected for the idle switches within the micro APM tiles 530. Therefore, the size of the minority switches within the main tile 520 can be sized appropriately for the expected current.

[0054]

[0064] In the example in Figure 7, the micro-APM tiles 530a to 530d include switching voltage generators such as the switching voltage generator 515 in Figures 5 and 6. Accordingly, the controller 701 may include a comparator that passes a control signal 702 to each of the micro-APM tiles 530a to 530d. The control signal 702 may correspond to Sel_mx and Sel_cx in Figure 4. In some implementations, the main tiles 520a and 520b may also include switching voltage generators and receive the control signal 702 in the same manner.

[0055]

[0065] Although not shown in Figure 7, each of the main tiles 520 and each of the micro-APM tiles 530 can be coupled to a load, as schematically shown above in Figure 2. For example, each of the micro-APM tiles 530a to d powers a different load, such as a different memory block or different processing circuit within a memory unit, and the main tile 520a powers each of those different loads associated with each of the micro-APM tiles 530a to d. As described above, the main tile 520 includes a small number of switches for high resistance, and the micro-APM tile 530 includes a pause switch for low resistance.

[0056]

[0066] Architecture 700 provides a PDN for a given power domain within the chip. Thus, each of the main tile 520 and the micro APM tile 530 is expected to select the same voltage (e.g., either MX or CX) or power collapse at a given time. In other words, the PDN provided by Architecture 700 does not involve mixing and matching voltage levels. Insofar as the chip may have other power domains operating independently, the chip may implement one or more other PDNs having the same or similar structure as shown in Figure 7. An example of an exemplary chip 1300 including power domains 0-3 is shown in Figure 13. Each of the different power domains includes a PDN by Architecture 700. The exemplary chip 1300 may include a central processing unit (CPU), graphics processing unit (GPU), memory, modem, etc., within a system-on-a-chip (SOC). However, the scope of implementation is not limited to an SOC, as the power multiplexing described herein can be applied to any chip having memory and / or processing.

[0057]

[0067] Figures 8 to 10 show different arrangements of PDNs in various implementation configurations. For example, the basic building blocks of the main tile and micro-APM can be mixed and matched to implement an adaptive power multiplexing system with different trade-offs such as voltage drop, semiconductor area, and routing congestion. As mentioned above, since the dormant switches of the micro-APM are separated from the minority switches of the main tile, the pitch of different tiles can be increased or decreased as appropriate.

[0058]

[0068] For example, the selection of tile pitch can take into account various factors such as the drop in the Vdd_aon rail during multiplexer switching, which can be a function of minority switch strength, load leakage, and parasitic capacitance on the Vdd_aon rail. In some implementations, stronger minority switches may lead to lower drop, load leakage may lead to higher drop, and longer Vdd_aon rails may lead to increased parasitic capacitance. In the case of Vdd_aon rails, the length may be influenced by the placement of switching voltage generators within the PDN. In a scenario where each micro-APM includes a switching voltage generator, Vdd_aon (switching voltage) routing may be minimal. In contrast, implementations that include standalone switching voltage generators or place switching voltage generators in only a few micro-APMs may show increased switching voltage routing, including longer Vdd_aon rails.

[0059]

[0069] However, engineering trade-offs can apply to each of these situations. For example, a switching voltage generator within each micro-APM minimizes the drop in the Vdd_aon rail while resulting in a larger micro-APM, but moving the Vdd_aon generator to only a few micro-APMs or to a standalone circuit may allow for simpler micro-APMs, but at the cost of increased voltage routing.

[0060]

[0070] Referring first to Figure 8, which shows an exemplary PDN800 in one implementation configuration, the micro-APM tile is exemplified by the micro-APM tile 811. The micro-APM tile 811 is contained within loop 810, and the other loops 820, 830, and 840 are implemented in the same or similar manner as loop 810. Loop 810 includes a main tile 814, which may be the same as or similar to the main tile 520 in Figures 5 and 7, and the main tile 814 may communicate with the micro-APM via a communication path 812 that carries enable signals such as the control signal 703 in Figure 7.

[0061]

[0071] Main tiles 814-817 may be arranged in a daisy-chain loop, as shown in Figure 7. Communication path 813 carries control signals, such as control signal 704 in Figure 7.

[0062]

[0072] What is noteworthy in Figure 8 is that each micro-APM tile (e.g., micro-APM tile 811) includes a quiescent switch as switching logic and a switching voltage generator. In other words, each micro-APM tile generates its own switching voltage (Vdd_aon), thereby reducing or eliminating any need to route switching voltages between micro-APM tiles. Thus, the implementation in Figure 8 reduces switching voltage routing at the cost of larger and more complex micro-APM tiles.

[0063]

[0073] Figure 9 shows an exemplary PDN900 in one implementation configuration. Since communication paths 812 and 813 are the same, main tiles 814-817 are arranged in the same daisy chain, and loops 910, 920, 930, and 940 have the same shape as loops 810, 820, 830, and 840, the PDN900 is similar to the PDN800.

[0064]

[0074] The difference between the PDN900 and the PDN800 is that the PDN900 contains only two micro-APM tiles with integrated switching voltage generators per loop. Taking loop 910 as an example, it contains micro-APM tiles 811 and 912, which have integrated switching voltage generators. The remaining micro-APM tiles in loop 910 (exemplified by micro-APM tile 911) contain idle switches but do not contain integrated switching voltage generators. In other words, micro-APM tile 911 may be the same as or similar to items 654 and 656 in Figure 6, and micro-APM tiles 811 and 912 may be the same as or similar to items 650 and 652 in Figure 6. As a result, the PDN900 uses switching voltage routing to supply switching voltage to the micro-APM tiles that do not have integrated switching voltage generators. Switching voltage routing uses horizontal routing, as exemplified by power rail 925, and vertical routing, as exemplified by power rail 926.

[0065]

[0075] Micro-APM tiles such as micro-APM tile 911 are smaller and less complex than micro-APM tiles 811 and 912 because they do not include an integrated switching voltage generator. Smaller micro-APM tiles such as micro-APM tile 911 can allow for a finer-grained arrangement for switching logic, thereby allowing such micro-APM tiles to be placed closer to each other and shortening the communication path 812. However, the overhead of switching voltage distribution is higher than that in the PDN800, and the switching voltage distribution section is generally expected to become more complex as the ratio of micro-APM tiles 911 to micro-APM tiles 811 increases.

[0066]

[0076] Figure 10 shows an exemplary PDN1000 in one implementation configuration. The PDN1000 differs from the PDN800 and PDN900 in that none of the micro-APM tiles include integrated switching voltage generation. Rather, each of the loops 1010, 1020, 1030, and 1040 is constructed using smaller micro-APM tiles, such as micro-APM tile 911. Switching voltage generation is provided by standalone switching voltage generation units 1011 and 1012 within loop 1010. The other loops 1020, 1030, and 1040 are configured similarly to loop 1010.

[0067]

[0077] The use of standalone switching voltage generation units 1011 and 1012 involves a more complex voltage routing structure than that seen in either the PDN800 or PDN900. The switching voltage distribution section is exemplified by horizontal power rails 1025, 1026, and 1027 (in the case of loop 1020) and vertical power rails 1031-1036 serving loops 1010, 1020, 1030, and 1040, respectively. The PDN1000 represents a further trade-off between the use of smaller micro APM tiles 911, which may allow for finer placement of idle switches, and more complex switching voltage routing.

[0068]

[0078] Naturally, the examples in Figures 8-10 are merely illustrative. The number of micro-APM tiles in the loop, the number of loops, the number of main tiles, and the number of switching voltage rails can be adjusted to suit a given application. In other words, the specific structure of the implementations in Figures 8-10 can be modified as appropriate to supply the desired voltage to a given number of loads in the application.

[0069]

[0079] Figure 11 shows an exemplary PDN 1100 applied to a memory device 1110 in one implementation configuration. The memory device 1110 can be any suitable memory device, such as a group of static random-access memory (SRAM) memory blocks. Power multiplexing functionality is located in columns 1120 and 1130. Power multiplexing functionality is provided by main tiles 1113-1119, and micro-APM tiles are exemplified by micro-APM tile 112 with an integrated switching voltage generator and micro-APM tile 1111 without an integrated switching voltage generator. The micro-APM tiles can be arranged in a loop, as shown in Figures 8-10. For example, exemplary loops are shown as items 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192.

[0070]

[0080] Figure 11 is provided to illustrate that power multiplexing hardware may be physically arranged on the chip in any suitable manner. Specifically, in Figure 11, the power multiplexing hardware is arranged in opposing columns 1120, 1130 on both sides of the memory device 1110. Although not shown in Figure 11, the main tiles 1113-1119 may be arranged in a daisy-chain configuration as shown in Figures 7-10, and the micro APM tiles may be arranged in loops 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192 as described above with respect to Figures 7-10.

[0071]

[0081] Furthermore, each of loops 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192 may serve individual memory blocks within the memory device 1110 in any suitable manner. For example, each of loops 1140, 1150, 1160, 1170, 1180, 1190, 1191, and 1192 may serve the physically nearest memory block, reaching the center from each side, so that each block within the memory device 110 is served by at least one power multiplexing loop.

[0072]

[0082] Naturally, the range of implementation configurations is not limited to the physical arrangement shown in Figure 11. Rather, other implementation configurations may involve distributing micro APM tiles around the chip as needed.

[0073]

[0083] The implementation configurations described in Figures 5 to 11 offer advantages over other designs that use only a single type of power multiplexer combining both minority switches and quiescent switches. As mentioned above, designs that combine minority switches and quiescent switches into a single physical power multiplexing structure can, at least partially, incur routing costs for the numerous transistors that make up the switching logic (minority switches and quiescent switches). Specifically, routing costs may include using an undesirable number of metal layers within the chip. Metal routing within a chip can be of a nature where the horizontal use of routing space can increase as the vertical use of metal layers by the components increases. Thus, not only can routing become more complex, but in addition, routing may use an undesirable amount of silicon area.

[0074]

[0084] In contrast, the various implementations described herein may utilize at least two types of power multiplexers. A first type of power multiplexer (e.g., main tile 520) may include high-resistance switching logic (e.g., minority switches), and a second type of power multiplexer (e.g., micro-APM tile 530) may include low-resistance switching logic (e.g., quiescent switches). The first type of power multiplexer is physically isolated from the second type of power multiplexer, and the implementation may include a communication path for providing enable signals from the first type of power multiplexer, through the loop of the second type of power multiplexer, and back to the first type of power multiplexer. The physical isolation of the two different types of power multiplexers can reduce the number of metal layers used for routing, and therefore reduce the overall silicon area used for the same power multiplexing functionality. Reduced routing complexity and the use of less semiconductor area can lead to lower manufacturing costs.

[0075]

[0085] A flowchart of an exemplary method 1200 for multiplexing across multiple power supplies is shown in Figure 12. In one example, method 1200 is performed by the circuitry shown in Figures 1 to 11. The circuitry may operate under the control of a power management unit which may include hardware and / or software functionality in the processor (e.g., CPU) of a computing device contained within an SOC (not shown) or other structure. For example, controller 701 in Figure 7 may represent a standalone controller or hardware and / or software functionality in another processing device such as a CPU or another processor. In some examples, the power management unit includes a processing circuit configuration which executes computer-readable instructions to select one power supply or another power supply as the operating voltage for one or more memory blocks.

[0076]

[0086] In action 1210, the system transmits an enable signal from the first power multiplexer of the first type to the second power multiplexer of the second type. An example of the main tile 520a transmitting control signals 703 to micro APM tiles 530a-d is shown in Figure 7. In this example, control signals 703 may include enable signals such as En_1 and En_2 in Figure 3.

[0077]

[0087] In action 1220, the system switches the first load from the first power supply to the second power supply by the first power multiplexer and the second power multiplexer. In the example in Figure 7, the main tile 520a switches the load from the first power supply to the second power supply (for example, from CX to MX, or vice versa) and causes the micro APM tiles 530 to switch each of those loads from the first power supply to the second power supply. The first power multiplexer may be made to switch from the first power supply to the second power supply in response to a signal from the controller, and the second power multiplexer may be made to switch from the first power supply to the second power supply by an enable signal. Each of the individual micro APM tiles 530a to d serves its respective load, but the main tile 520a serves each of these different loads and switches the power supply for each of these different loads.

[0078]

[0088] Furthermore, each of the first and second power multiplexers may receive a switching voltage equal to or greater than the highest voltage level of the first and second power supplies. An example of a switching voltage generator 400 generating Vdd_aon is shown with respect to Figure 4.

[0079]

[0089] In action 1230, the first power multiplexer receives an enable signal. For example, in the implementation shown in Figure 7, the micro APM tile 530 is in the loop, and the control signal 703 is fed back to the main tile 520a. In some examples, the feeding back of the control signal 703 to the main tile 520a allows the main tile 520a to confirm the operational status of the micro APM tile 530 in the loop.

[0080]

[0090] In action 1240, the first power multiplexer can transmit a control signal to a third power multiplexer of the first type. Figure 7 shows an example in which a main tile 520a can transmit a control signal 704 to the main tile 520b after receiving a control signal 703 from the micro APM tile 530b. The main tile 520b may also have a loop of micro APM tiles 530, which can transmit the same control signal 703 to an additional main tile 520c after passing the control signal 704 back to the main tile 520b. This action can be performed successively for each main tile 520 in the daisy chain until the control signal 704 is fed back to the controller 701. As a result, each of the main tiles 520 and their respective loops of micro APM tiles 530 can switch their respective loads from the first power supply to the second power supply.

[0081]

[0091] The scope of implementations is not limited to the actions shown in Figure 12; rather, other implementations may add, omit, rearrange, or modify one or more actions. In another example, instead of switching from the first power supply to the second power supply, the main tile 520 and the micro APM tile 530 may switch from the second power supply to the first power supply, or their loads may be completely power-collapsed. Furthermore, some implementations may include repeating actions 1210-1240 multiple times during normal operation when the processor on the chip transitions from one power mode to another.

[0082]

[0092] Various implementation forms will be further explained with respect to the following clauses. Article 1. A first power multiplexer of a first type coupled to a first power supply and a second power supply, wherein the first power multiplexer includes a first switching logic disposed between the first power supply, the second power supply and the load, A second power multiplexer of a second type coupled to a first power supply and a second power supply, the second power multiplexer comprising a second switching logic between the first power supply and the second power supply and a load, the second switching logic including an enable input coupled to the first power multiplexer, System-on-a-chip (SOC). Clause 2. The SOC described in Clause 1, wherein the first switching logic comprises a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors, and the second switching logic comprises a second plurality of PMOS transistors, further wherein the first plurality of PMOS transistors are smaller in size than the second plurality of PMOS transistors. Clause 3. The SOC as described in Clause 1, wherein the first switching logic comprises a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors, the second switching logic comprises a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors have a collective resistance smaller than the collective resistance of the second plurality of PMOS transistors. Article 4. A third power multiplexer of a second type coupled to a first power supply and a second power supply, the third power multiplexer further comprising a third switching logic, the third switching logic comprising an additional enable input coupled to the first power multiplexer, between the first power supply and the second power supply and another load, the third power multiplexer further comprising a third switching logic, the third switching logic comprising an additional enable input coupled to the first power multiplexer. The second power multiplexer and the third power multiplexer are coupled in a loop with the first power multiplexer. An SOC as defined in any one of clauses 1 through 3. Clause 5. The SOC described in Clause 4, wherein the loop comprises a first path from a first power multiplexer to the enable input of a second switching logic, a second path from the enable input of the second switching logic to an additional enable input, and a third path from the additional enable input to the first power multiplexer. Clause 6. The SOC as described in Clause 4, wherein a second power multiplexer includes a first voltage generator configured to provide a switching voltage to a second switching logic, and a third power multiplexer includes a second voltage generator configured to provide a switching voltage to a third switching logic. Clause 7. The SOC as described in Clause 4, wherein the second power multiplexer includes a first voltage generator configured to provide switching voltages to the second switching logic and to the third switching logic. Clause 8. The SOC according to Clause 4, further comprising a first voltage generator physically separated from a first power multiplexer and a second power multiplexer, wherein the first voltage generator is configured to provide switching voltages to a second switching logic and a third switching logic. Article 9. A second type of fourth power multiplexer coupled to a first power supply and a second power supply, wherein the fourth power multiplexer includes a fourth switching logic between the first power supply and the second power supply and another load, the fourth switching logic including an additional enable input coupled to the first power multiplexer, The system further comprises a control circuit coupled to a plurality of voltage generators associated with each of the first, second, and fourth power multiplexers. The SOC as described in Clause 1. Clause 10. The SOC as described in Clause 9, wherein the control circuit includes a comparator coupled to a first power supply and a second power supply, and the output of the comparator is coupled to a plurality of voltage generators. Article 11. A second type of fifth power multiplexer coupled to a first power supply and a second power supply, wherein the fifth power multiplexer includes a fifth switching logic between the first power supply and the second power supply and another load, the fifth switching logic including an additional enable input coupled to the first power multiplexer, It further comprises multiple memory bit cells arranged in multiple rows and multiple columns, The first power multiplexer, the second power multiplexer, and the fifth power multiplexer are arranged in a column parallel to the first column among a plurality of columns. The second power multiplexer includes a first voltage generator configured to provide a switching voltage to a second switching logic and a fifth switching logic. The SOC as described in Clause 1. Article 12. Transmitting an enable signal from a first power multiplexer of the first type to a second power multiplexer of the second type, Switching a first load from a first power source to a second power source using a first power multiplexer and a second power multiplexer, wherein the second power multiplexer switches the first load in response to an enable signal. The first power multiplexer receives an enable signal, method. Clause 13. A second power multiplexer is arranged in a loop with a third power multiplexer of the first type and a fourth power multiplexer of the first type, and the fourth power multiplexer is coupled to the first power multiplexer. The enable signal is received by the first power multiplexer from the fourth power multiplexer via the communication path. The first power multiplexer and the third power multiplexer switch the second load from the first power source to the second power source. The method described in Article 12. Clause 14. The method according to Clause 13, wherein the first power multiplexer and the fourth power multiplexer switch the third load from the first power source to the second power source. Article 15. The first power multiplexer, after receiving an enable signal, further includes transmitting a control signal from the first power multiplexer to a fifth power multiplexer of a first type, instructing the fifth power multiplexer to switch the fourth load from the first power source to the second power source. The method described in Article 12. Clause 16. The method according to Clause 15, wherein the first and fifth power multiplexers are arranged in a daisy-chain with a controller that provides control signals. Clause 17. A power distribution network (PDN) on a semiconductor chip, where the PDN is A first means for performing redundancy between a first power supply and a second power supply, A second means for multiplexing between a first power supply and a second power supply, wherein the second means is configured to receive an enable signal from the first means, and the enable signal causes the second means to select between the first power supply, the second power supply, and a power collapse, the second means includes A PDN comprising a first means comprising a first type of power multiplexer, a second means comprising a second type of power multiplexer different from the first type of power multiplexer, and further comprising a plurality of second type power multiplexers arranged in a loop to feed back an enable signal to the first means. Article 18. A daisy-chain of a first type of power multiplexer including a first means, further comprising a daisy-chain configured to pass control signals between the daisy-chains of power multiplexers. PDN as specified in Clause 17. Clause 19. A power multiplexer of the first type includes a first switching logic having lower resistance than the second switching logic of the second type of power multiplexer, as described in either Clause 17 or 18. Clause 20. Each of the second type of power multiplexer includes the respective means for generating a switching voltage, as described in either Clause 17 or 18. Clause 21. A PDN as described in either Clause 17 or 18, wherein some but not all of the second type power multiplexers include means for generating switching voltages, and the PDN further comprises means for distributing switching voltages among the second type power multiplexers. Clause 22. A PDN according to either Clause 17 or 18, further comprising means for generating a switching voltage, wherein the means for generating the switching voltage is physically separated from each of the first and second means, and the PDN further comprises means for distributing the switching voltage among the second type of power multiplexers. Clause 23. A PDN as described in either Clause 17 or 18, which is physically positioned along both opposing sides of the memory device. Article 24. A first power multiplexer of a first type and a second power multiplexer of a first type, wherein the first power multiplexer and the second power multiplexer are daisy-chained with a controller, and the daisy-chain transmits control signals from the controller to the first power multiplexer, then to the second power multiplexer, and feeds the control signals back to the controller, A third and fourth power multiplexer of a second type, arranged in a first loop from a first power multiplexer, wherein the first loop passes a first enable signal from the first power multiplexer to the third and fourth power multiplexers and back to the first power multiplexer, A second type of fifth and sixth power multiplexers arranged in a second loop from a second power multiplexer, wherein the second loop passes a second enable signal from the second power multiplexer to the fifth and sixth power multiplexers and back to the second power multiplexer, the fifth and sixth power multiplexers, Semiconductor chip. Clause 25. A semiconductor chip as described in Clause 24, wherein the first type includes a first switching logic, and the second type includes a second switching logic, and the first switching logic has a higher resistance than the second switching logic. Clause 26. The semiconductor chip described in Clause 24, wherein each of the third and fourth power multiplexers includes an integrated switching voltage generation circuit configuration. Clause 27. The semiconductor chip according to Clause 24, wherein the third power multiplexer includes an integrated switching voltage generation circuit configuration not contained within the fourth power multiplexer, and the semiconductor chip further includes a voltage distribution unit configured to provide a switching voltage from the third power multiplexer to the fourth power multiplexer. Clause 28. The semiconductor chip according to Clause 24, further comprising a switching voltage generation circuit configuration physically separated from a third power multiplexer and a fourth power multiplexer, wherein the semiconductor chip further comprises a voltage distribution unit configured to provide switching voltages to the third power multiplexer and the fourth power multiplexer. Herein, as will be understood by those skilled in the art, and depending on the specific applications present, many modifications, substitutions, and variations may be made to and from the materials, apparatus, configurations, and methods of use of the Disclosure without departing from the spirit and scope of the Disclosure. In light of this, since the specific embodiments described and illustrated herein are merely some examples, the scope of the Disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the claims and their functional equivalents appended thereto.

Claims

1. A first power multiplexer of a first type coupled to a first power supply and a second power supply, wherein the first power multiplexer includes a first switching logic disposed between the first power supply, the second power supply and the load, A second power multiplexer of a second type coupled to the first power supply and the second power supply, the second power multiplexer comprising a second switching logic between the first power supply and the second power supply and the load, the second switching logic including an enable input coupled to the first power multiplexer, System-on-a-chip (SOC).

2. The SOC according to claim 1, wherein the first switching logic includes a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors, the second switching logic includes a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors are smaller in size than the second plurality of PMOS transistors.

3. The SOC according to claim 1, wherein the first switching logic includes a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors, the second switching logic includes a second plurality of PMOS transistors, and further, the first plurality of PMOS transistors have a collective resistance smaller than the collective resistance of the second plurality of PMOS transistors.

4. A third power multiplexer of the second type coupled to the first power supply and the second power supply, the third power multiplexer further comprising a third switching logic between the first power supply and the second power supply and another load, the third switching logic including an additional enable input coupled to the first power multiplexer, The second power multiplexer and the third power multiplexer are coupled in a loop with the first power multiplexer. The SOC according to claim 1.

5. The SOC according to claim 4, wherein the loop comprises a first path from the first power multiplexer to the enable input of the second switching logic, a second path from the enable input of the second switching logic to the additional enable input, and a third path from the additional enable input to the first power multiplexer.

6. The SOC according to claim 4, wherein the second power multiplexer includes a first voltage generator configured to provide a switching voltage to the second switching logic, and the third power multiplexer further includes a second voltage generator configured to provide the switching voltage to the third switching logic.

7. The SOC according to claim 4, wherein the second power multiplexer includes a first voltage generator configured to provide switching voltages to the second and third switching logics.

8. The SOC according to claim 4, further comprising a first voltage generator physically separated from the first power multiplexer and the second power multiplexer, wherein the first voltage generator is configured to provide switching voltages to the second switching logic and the third switching logic.

9. A fourth power multiplexer of a second type coupled to the first power supply and the second power supply, wherein the fourth power multiplexer includes a fourth switching logic between the first power supply and the second power supply and another load, the fourth switching logic including an additional enable input coupled to the first power multiplexer, The system further comprises control circuits coupled to a plurality of voltage generators associated with each of the first power multiplexer, the second power multiplexer, and the fourth power multiplexer. The SOC according to claim 1.

10. The SOC according to claim 9, wherein the control circuit includes a comparator coupled to the first power supply and the second power supply, and the output of the comparator is coupled to the plurality of voltage generators.

11. A fifth power multiplexer of a second type coupled to the first power supply and the second power supply, wherein the fifth power multiplexer includes a fifth switching logic between the first power supply and the second power supply and another load, the fifth switching logic including an additional enable input coupled to the first power multiplexer, It further comprises multiple memory bit cells arranged in multiple rows and multiple columns, The first power multiplexer, the second power multiplexer, and the fifth power multiplexer are arranged in a row parallel to the first row among the plurality of rows. The second power multiplexer includes a first voltage generator configured to provide a switching voltage to the second switching logic and to the fifth switching logic. The SOC according to claim 1.

12. Transmitting an enable signal from a first power multiplexer of the first type to a second power multiplexer of the second type, The first power multiplexer and the second power multiplexer switch the first load from the first power source to the second power source, wherein the second power multiplexer switches the first load in response to the enable signal. The first power multiplexer includes receiving the enable signal, method.

13. The second power multiplexer is arranged in a loop with the third power multiplexer of the first type and the fourth power multiplexer of the first type, and the fourth power multiplexer is coupled to the first power multiplexer. The enable signal is received by the first power multiplexer from the fourth power multiplexer via the communication path. The first power multiplexer and the third power multiplexer switch the second load from the first power source to the second power source. The method according to claim 12.

14. The method according to claim 13, wherein the first power multiplexer and the fourth power multiplexer switch the third load from the first power source to the second power source.

15. The first power multiplexer, after receiving the enable signal, further includes transmitting a control signal from the first power multiplexer to a fifth power multiplexer of the first type, instructing the fifth power multiplexer to switch the fourth load from the first power source to the second power source. The method according to claim 12.

16. The method according to claim 15, wherein the first power multiplexer and the fifth power multiplexer are arranged in a daisy-chain with the controller that provides the control signals.

17. A power distribution network (PDN) on a semiconductor chip, wherein the PDN is A first means for performing redundancy between a first power supply and a second power supply, A second means for performing multiplexing between the first power supply and the second power supply, wherein the second means is configured to receive an enable signal from the first means, and the enable signal causes the second means to select between the first power supply, the second power supply, and a power collapse, A PDN comprising a first means comprising a first type of power multiplexer, a second means comprising a second type of power multiplexer different from the first type of power multiplexer, and further comprising a plurality of the second type of power multiplexers arranged in a loop to feed back the enable signal to the first means.

18. A daisy-chain of the first type of power multiplexer including the first means, further comprising a daisy-chain configured to pass control signals between the daisy-chains of power multiplexers, The PDN according to claim 17.

19. The PDN according to claim 17, wherein the first type of power multiplexer includes a first switching logic having lower resistance than the second switching logic of the second type of power multiplexer.

20. The PDN according to claim 17, wherein each of the second type of power multiplexer includes means for generating a switching voltage.

21. The PDN according to claim 17, wherein some but not all of the second type of power multiplexers each include means for generating a switching voltage, and the PDN further comprises means for distributing the switching voltage among the second type of power multiplexers.

22. The PDN according to claim 17, further comprising means for generating a switching voltage, wherein the means for generating the switching voltage is physically separated from each of the first and second means, and the PDN further comprises means for distributing the switching voltage among the second type of power multiplexer.

23. The PDN according to claim 17, wherein the PDN is physically arranged along both opposing sides of the memory device.

24. A first power multiplexer of a first type and a second power multiplexer of the first type, wherein the first power multiplexer and the second power multiplexer are daisy-chained with a controller, and the daisy-chain transmits control signals from the controller to the first power multiplexer, then to the second power multiplexer, and feeds the control signals back to the controller, A third and fourth power multiplexer of a second type, arranged in a first loop from the first power multiplexer, wherein the first loop passes a first enable signal from the first power multiplexer to the third and fourth power multiplexers and back to the first power multiplexer, A fifth and sixth power multiplexer of the second type, arranged in a second loop from the second power multiplexer, wherein the second loop passes a second enable signal from the second power multiplexer to the fifth and sixth power multiplexers and back to the second power multiplexer. Semiconductor chip.

25. The semiconductor chip according to claim 24, wherein the first type includes a first switching logic, and the second type includes a second switching logic, wherein the first switching logic has a higher resistance than the second switching logic.

26. The semiconductor chip according to claim 24, wherein each of the third power multiplexer and the fourth power multiplexer includes an integrated switching voltage generation circuit configuration.

27. The semiconductor chip according to claim 24, wherein the third power multiplexer includes an integrated switching voltage generation circuit configuration not included in the fourth power multiplexer, and the semiconductor chip further includes a voltage distribution unit configured to provide a switching voltage from the third power multiplexer to the fourth power multiplexer.

28. The semiconductor chip according to claim 24, further comprising a switching voltage generation circuit configuration physically separated from the third power multiplexer and the fourth power multiplexer, wherein the semiconductor chip further comprises a voltage distribution unit configured to provide switching voltages to the third power multiplexer and the fourth power multiplexer.

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