Light-emitting element, electronic device, and method for manufacturing a light-emitting element

Abstract

In a light-emitting element having nanocolumns, the degradation of the quality of the light-emitting layer of the nanocolumns is suppressed. [Solution] The light-emitting element of the embodiment comprises a first semiconductor layer having a first surface, a second semiconductor layer having a different conductivity than the first semiconductor layer, a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and a buffer layer disposed between the light-emitting layer and the first semiconductor layer. The light-emitting layer has a laminate in which InGaN layers and GaN layers are alternately stacked and has a second surface which is a facet. The composition ratio of In in the InGaN layer, which has the highest In composition in the light-emitting layer, is 30% or more. The buffer layer has a third surface which is a facet. The composition ratio of In in the buffer layer is 20% or more.

Description

Technical Field

[0001] The present invention relates to a light-emitting element, an electronic device, and a method for manufacturing a light-emitting element.

Background Art

[0002] Conventionally, as a light-emitting element including a plurality of nanostructures, a light-emitting element including a semiconductor substrate, a plurality of columnar nanostructures disposed on the semiconductor substrate, and an active layer disposed on the plurality of nanostructures is known. The columnar nanostructures are also called nanocolumns, nanopillars, nanowires, etc. The semiconductor material of the nanostructure is selected according to the wavelength band of the color light to be emitted as the light-emitting element. For example, a nitride-based compound is used for the nanostructures of a light-emitting element that emits color light having a green wavelength band.

[0003] For example, in Patent Document 1, a semiconductor light-emitting element including an active layer made of a nitride-based compound semiconductor, an upper light confinement layer and a lower light confinement layer made of a nitride-based compound semiconductor including a superlattice structure sandwiching the active layer, an upper cladding layer disposed above the upper light confinement layer, and a lower cladding layer disposed below the lower light confinement layer is disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor light-emitting device disclosed in Patent Document 1, a light-confining layer consisting of a superlattice of indium gallium nitride (InGaN) and gallium nitride (GaN) is arranged above and below the active layer. Generally, increasing the composition ratio of indium (In) in the InGaN stacked on GaN lengthens the wavelength range of the colored light emitted from the semiconductor light-emitting device, specifically enabling the emission of green light, red light, or infrared wavelength light. On the other hand, increasing the composition ratio of In in InGaN increases the difference in lattice constants between InGaN and GaN, causing threading dislocations, which degrades crystal quality and worsens the light-emitting characteristics of the semiconductor light-emitting device.

[0006] In the semiconductor light-emitting element disclosed in Patent Document 1, phase separation of the active layer is prevented by arranging the aforementioned light-confinement layers above and below the active layer, thereby improving crystal quality and enhancing luminescence characteristics. However, when emitting colored light with relatively long wavelengths, such as green or red light, from the semiconductor light-emitting element disclosed in Patent Document 1, it is difficult to avoid the occurrence of crystal defects if the thickness of the light-confinement layer is to be ensured, which can lead to a decrease in the crystal quality of the light-confinement layer and a high probability of deterioration in the luminescence characteristics of the semiconductor light-emitting element. Therefore, measures are desired to achieve both sufficient thickness of the light-confinement layer and suppression of the occurrence of crystal defects. [Means for solving the problem]

[0007] A light-emitting element according to one aspect of the present disclosure comprises a first semiconductor layer having a first surface, a second semiconductor layer having a different conductivity than the first semiconductor layer, a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and a buffer layer disposed between the light-emitting layer and the first semiconductor layer. The light-emitting layer has a laminate in which indium gallium nitride (InGaN) layers and gallium nitride (GaN) layers are alternately stacked, and has a second surface which is a facet. The In composition ratio of the InGaN layer with the highest In composition in the light-emitting layer is 30% or more. The buffer layer has a third surface which is a facet. The In composition ratio in the buffer layer is 20% or more. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram of the projector according to the embodiment. [Figure 2] Figure 1 is a plan view of the light-emitting element of the projector. [Figure 3] Figure 2 is a cross-sectional view of the light-emitting element. [Figure 4] Figure 2 is a cross-sectional view illustrating the manufacturing method of the light-emitting element. [Figure 5] Figure 2 is a cross-sectional view illustrating the manufacturing method of the light-emitting element. [Figure 6] Figure 2 is a cross-sectional view illustrating the manufacturing method of the light-emitting element. [Figure 7] This is a HAADF-STEM image of the nanocolumn of the first prototype light-emitting element. [Figure 8] This is a HAADF-STEM image of the nanocolumn of the first prototype light-emitting element, and is a magnified view of a portion of Figure 7. [Figure 9] This is a graph showing the composition ratio of the nanocolumns in the first prototype light-emitting element. [Figure 10] This is a HAADF-STEM image of the nanocolumn of the second prototype light-emitting element. [Figure 11] This is a graph showing the composition ratio of the nanocolumns in the second prototype light-emitting element. [Modes for carrying out the invention]

[0009] Hereinafter, a light-emitting element, an electronic device, and a method for manufacturing the light-emitting element according to the embodiment will be described with reference to the drawings. In the following drawings, the dimensions and scale of each part may differ from those of the actual device as appropriate. Unless otherwise stated in the following description to limit the scope of this disclosure, the scope of this disclosure is not limited to the embodiments described below.

[0010] <Electronic equipment> First, a projector 10 according to one embodiment of the present invention will be described. Figure 1 is a schematic diagram of the projector 10. As shown in Figure 1, the projector 10 is a projection-type image display device that includes a light-emitting device 12, a diffuser plate 19, a light modulation device 13, and a projection optical system 14, and projects an image onto a screen SCR. The projector 10 corresponds to the electronic equipment described later and the electronic equipment described in the claims.

[0011] In the following explanation, a Cartesian coordinate system consisting of the X, Y, and Z axes is used to describe each component. The Z axis is an axis parallel to the optical axis AX of the light LC emitted from the light-emitting device 12 described below, and corresponds to, for example, the thickness direction or the vertical direction. One side of the Z axis is referred to as the -Z side, and the other side of the Z axis is referred to as the +Z side. The X and Y axes are perpendicular to the Z axis and are perpendicular to each other. The X axis is, for example, parallel to the horizontal plane and corresponds to the left-right direction. One side of the X axis is referred to as the -X side, and the other side of the X axis is referred to as the +X side. The Y axis is, for example, parallel to the horizontal plane and corresponds to the depth direction. One side of the Y axis is referred to as the -Y side, and the other side of the Y axis is referred to as the +Y side.

[0012] The light-emitting device 12 emits optical light LC, which is colored light for projecting an image, along an optical axis AX parallel to the Z-axis towards the +Z side. The light-emitting device 12 includes a light-emitting element 20 and a heat sink 21.

[0013] The light-emitting element 20 has two end faces 20a and 20b and emits optical light (LC). End face 20a is located on the +Z side of the two end faces and may have irregularities with respect to the XY plane including the X and Y axes, or it may be a flat surface parallel to the XY plane, for example, having irregularities with respect to the XY plane. When viewed along the Z axis, the shape of the end faces 20a and 20b of the light-emitting element 20, and the shape of the light-emitting region R22 on end face 20a are rectangular. End face 20b is located on the -Z side of end face 20a and is a flat surface parallel to the XY plane. The detailed configuration of the light-emitting element 20 will be described later.

[0014] The light LC is emitted from the end face 20a of the light-emitting element 20 along the optical axis AX to the +Z side. If the projector 10 is a device capable of displaying a full-color image, the light LC is, for example, white light including red light, green light, and blue light. If the projector 10 is a device capable of displaying a monochromatic image, the light LC is light of the same color as the monochromatic image, for example, light of any one of red light, green light, and blue light.

[0015] The heat sink 21 is disposed on the end face 20b of the light-emitting element 20 and releases the heat generated by the light-emitting element 20.

[0016] The diffuser plate 19 is disposed on the optical path of the light LC emitted from the light-emitting device 12. The diffuser plate 19 diffuses the incident light LC in the XY plane and equalizes the illuminance of the light LC in the XY plane. The diffuser plate 19 may be omitted.

[0017] The light modulation device 13 is disposed on the optical path of the light LC emitted from the light-emitting device 12 and passing through the diffuser plate 19. The light modulation device 13 receives an electrical signal input from an external input device or an image forming device (not shown) via a control device (not shown) and is driven to modulate the incident light LC according to the image information included in the electrical signal, thereby generating image light LM including a projected image.

[0018] The light modulation device 13 includes an incident-side polarizing element 16, a liquid crystal element 17, and an emission-side polarizing element 18.

[0019] The incident-side polarizing element 16 is disposed on the optical path of the light LC emitted from the light-emitting device 12 and passing through the diffuser plate 19. The incident-side polarizing element 16, for example, contacts the liquid crystal element 17 from the -Z side, but may be disposed at an appropriate interval from the liquid crystal element 17 on the Z axis. The incident-side polarizing element 16 has a polarization plane parallel to the XY plane and emits a predetermined polarization of the incident light LC along the +Z side along the Z axis. The aforementioned predetermined polarization is, for example, P polarization.

[0020] The liquid crystal element 17 is positioned on the optical path of light LC of a predetermined polarization emitted from the incident polarizing element 16. The modulation plane of the liquid crystal element 17, including the image forming region R26, is parallel to the XY plane. When viewed along the Z axis, the shape of the image forming region R26 of the liquid crystal element 17 is rectangular and is approximately similar to the shape of the light-emitting region R22 of the light-emitting element 20. The area of ​​the image forming region R26 of the liquid crystal element 17 is the same as the area of ​​the light-emitting region R22 of the light-emitting element 20, or slightly smaller than the area of ​​the light-emitting region R22 of the light-emitting element 20.

[0021] The liquid crystal element 17 is, for example, a transmissive liquid crystal panel. In the liquid crystal panel constituting the liquid crystal element 17, a plurality of pixels (not shown) are formed in the region corresponding to the image formation region R26 of the liquid crystal element 17. The plurality of pixels are arranged along the X and Y axes. Each pixel is equipped with a switching element. The switching element is, for example, a polysilicon thin-film transistor (TFT). The liquid crystal element 17 emits the image light LM generated in the liquid crystal panel along the Z axis towards the +Z side.

[0022] An electrical signal corresponding to the brightness of the color light at the relative position of each pixel in the image projected by the projector 10 is supplied to the switching element of each pixel of the liquid crystal panel from an external input device or image forming apparatus. Each pixel of the liquid crystal panel modulates the vibration direction of the light LC emitted from the incident polarizing element 16 by the operation of the switching element in accordance with the aforementioned electrical signal, thereby generating image light LM having an illuminance distribution of each color light in accordance with the aforementioned electrical signal.

[0023] The ejection-side polarizing element 18 is positioned on the optical path of the image light LM emitted from the liquid crystal element 17. The ejection-side polarizing element 18 is, for example, in contact with the liquid crystal element 17 from the +Z side, but may also be positioned at an appropriate distance from the liquid crystal element 17 along the Z axis. The ejection-side polarizing element 18 has a polarization plane parallel to the XY plane and emits a predetermined polarization of the incident image light LM along the Z axis towards the +Z side. The aforementioned predetermined polarization is, for example, P polarization.

[0024] The incident polarizing element 16 and the exit polarizing element 18 are, for example, reflective polarizers or absorbing polarizers. If it is desirable to suppress the generation of stray light inside the projector 10 and the return of light to the light-emitting device 12, it is desirable to use an absorbing polarizer as the incident polarizing element 16. If it is desirable to suppress the generation of stray light inside the projector 10 and the return of light to the liquid crystal element 17, it is desirable to use an absorbing polarizer as the exit polarizing element 18.

[0025] The projection optical system 14 is positioned on the optical path of the image light LM emitted from the optical modulator 13. The projection optical system 14 projects the incident image light LM onto the screen SCR located on the +Z side, and displays the image transmitted and output from the image forming apparatus to the liquid crystal element 17 of the optical modulator 13 on the screen SCR in an enlarged view.

[0026] <hibi> Next, a light-emitting element 20 of one embodiment of the present invention will be described. Figure 2 is a plan view of the light-emitting element 20, and corresponds to a view of the light-emitting element 20 along the Z axis from the +Z side.

[0027] As shown in Figure 2, the end face 20a of the light-emitting element 20 is divided into a light-emitting region R22 including the center and a peripheral region R24 on the outer periphery of the light-emitting region R22 when viewed along the Z axis. Multiple nanocolumns 57 are formed around the entire area of ​​the light-emitting region R22 and spaced apart from each other along the X and Y axes, but in Figure 2 only some of the nanocolumns 57 are shown, and the remaining nanocolumns 57 are omitted.

[0028] As shown in Figure 2, the distance Px between the centers of two adjacent nanocolumns 57 in the X-axis and the distance Py between the centers of two adjacent nanocolumns 57 in the Y-axis are, for example, between 1 nm and 500 nm. For example, if the distances Px and Py are equal, the multiple nanocolumns 57 are arranged periodically with intervals along the X and Y axes. In addition to being arranged in a square lattice pattern when viewed from the +Z side along the Z-axis, as illustrated in Figure 2, the multiple nanocolumns 57 may also be arranged in a rectangular lattice pattern, a triangular lattice pattern, a honeycomb lattice pattern, a kagome lattice pattern, or a maple leaf lattice pattern, for example, in a plane parallel to the XY plane.

[0029] The distance Dx between nanocolumns 57, 57 located at both ends of multiple nanocolumns 57 arranged along the X-axis, and the distance Dy between nanocolumns 57, 57 located at both ends of multiple nanocolumns 57 arranged along the Y-axis, are appropriately set according to the size of the light-emitting region R22 in the X-axis and Y-axis.

[0030] Figure 3 is a cross-sectional view of the light-emitting element 20, viewed along the line III-III shown in Figure 2. As shown in Figure 3, the light-emitting element 20 includes a substrate 50, a semiconductor layer 55, a mask layer 56, a plurality of nanocolumns 57, and conductive layers 52, 53.

[0031] The substrate 50 constitutes the base of the light-emitting element 20 and has a front surface 50a and a back surface 50b parallel to the XY plane. The substrate 50 is, for example, a silicon (Si) substrate, a GaN substrate, a sapphire substrate, etc.

[0032] In this embodiment, a sapphire substrate with a C-plane orientation is used as the substrate 50. Because the substrate 50 is the aforementioned sapphire substrate, when the semiconductor material of the semiconductor layer 55 formed on the +Z side surface 50a of the substrate 50 is GaN, the crystal quality of the GaN semiconductor layer 55 is high, and a uniform crystal is formed on the surface 50a. As a result, the current flows uniformly through the semiconductor layer 67 of the nanocolumn 57, and the luminescence efficiency of the light-emitting element 20 is improved.

[0033] The semiconductor layer 55 is formed on the +Z-side surface 50a of the substrate 50. The semiconductor layer 55 is composed of, for example, an n-type GaN layer doped with Si.

[0034] The bottom surface of the semiconductor layer 55 on the -Z side is in contact with the surface 50a of the substrate 50. In the semiconductor layer 55, the semiconductor layer 55A of the light-emitting region R22, where multiple nanocolumns 57 are formed on the +Z side in the XY plane as will be explained later, protrudes to the +Z side more than the semiconductor layer 55B of the peripheral region R24. The surface 50a of the semiconductor layer 55A is located to the +Z side more than the back surface 50b of the semiconductor layer 55B.

[0035] The mask layer 56 is formed on the +Z side surface of the semiconductor layer 55A. The mask layer 56 is composed of a layer containing, for example, titanium (Ti). The dimension of the mask layer 56 in the Z axis, i.e., the thickness of the mask layer 56, is, for example, about 5 nm. Multiple through holes are formed in the mask layer 56, corresponding to the positions where multiple nanocolumns 57 are formed. The multiple through holes act as openings, and the nanocolumns 57 grow from the through holes toward the +Z side, as will be explained later. The mask layer 56 is a mask layer for forming nanocolumns 57 in multiple selective small regions of the surface 55a of the semiconductor layer 55A that are exposed toward the +Z side by the multiple through holes.

[0036] Multiple nanocolumns 57 are formed in multiple small regions of the surface 55a of the semiconductor layer 55A that are exposed and not covered by the mask layer 56. Each nanocolumn 57 is a columnar crystalline structure and nanostructure that extends from the semiconductor layer 55A along the Z axis toward the +Z side. Light emitted from the semiconductor layer 67, which is the light-emitting layer, is emitted not only along the Z axis toward the +Z side, but also in directions parallel to the XY plane and toward the -Z side. Therefore, mirrors may be provided on the side or back of the nanocolumn 57, and reflective structures may be provided to increase the amount of light emitted toward the +Z side.

[0037] The shape of the nanocolumn 57 when viewed along the Z-axis, i.e., the planar shape of the nanocolumn 57, can be, for example, a polygon or a circle. If the semiconductor material of the nanocolumn 57 contains GaN, the planar shape of the nanocolumn 57 is hexagonal. The maximum width of the nanocolumn 57 when viewed along the Z-axis, i.e., the diameter of the nanocolumn 57, is on the order of nanometers, for example, between 100 nm and 300 nm. If the planar shape of the nanocolumn 57 is polygonal, the diameter of the nanocolumn 57 means the diameter of the smallest circle that contains the polygon. If the planar shape of the nanocolumn 57 is elliptical, the diameter of the nanocolumn 57 means the diameter of the smallest circle that contains the ellipse.

[0038] If the planar shape of the nanocolumn 57 is a circle, then the center of the nanocolumn 57 is the center of the circle. If the planar shape of the nanocolumn 57 is a polygon, then the center of the nanocolumn 57 is the center of the smallest circle that contains the polygon. If the planar shape of the nanocolumn 57 is an ellipse, then the center of the nanocolumn 57 is the center of the smallest circle that contains the ellipse.

[0039] The nanocolumn 57 has semiconductor layers 65, 66, 67, and 68. The semiconductor layers 65, 66, 67, and 68 are stacked sequentially along the Z axis from the -Z side to the +Z side. The semiconductor layers 66, 67, and 68 are formed by epitaxial growth, as will be described later.

[0040] The semiconductor layer 65 is positioned on the -Z side of the nanocolumn 57 and is formed in a small region on the surface 55a of semiconductor layer 55A in the light-emitting region R22 of semiconductor layer 55 that is not covered by the mask layer 56, and extends from semiconductor layer 55A along the Z axis toward the +Z side. Semiconductor layer 65 corresponds to the first semiconductor layer described later and the first semiconductor layer described in the claims. Semiconductor layer 65 is formed of the same semiconductor material as semiconductor layer 55, and is composed of, for example, a Si-doped n-type GaN layer.

[0041] The +Z-side surface 65a of the semiconductor layer 65 is inclined with respect to the XY plane and, when viewed along the Z axis, moves towards the +Z side as it approaches the center from the outer edge. The +Z-side surface 65a of the semiconductor layer 65 is formed by the epitaxial growth of n-type GaN during the formation of the semiconductor layer 65 and narrows towards the +Z side towards the center when viewed along the Z axis. The surface 65a of the semiconductor layer 65 corresponds to the first surface described later and the first surface described in the claims.

[0042] The semiconductor layer 66 is positioned on the +Z side of the semiconductor layer 65 and is stacked on the +Z side of the semiconductor layer 65. The semiconductor layer 66 corresponds to the buffer layer described later and the buffer layer described in the claims.

[0043] The bottom surface of the semiconductor layer 66 on the -Z side is in contact with the surface 65a of the semiconductor layer 65 from the +Z side, and is tilted with respect to the XY plane at the same angle as the surface 65a of the semiconductor layer 65. When viewed along the Z axis, it moves towards the +Z side as it approaches the center from the outer edge.

[0044] The +Z-side surface 66a of the semiconductor layer 66 is tilted at a larger angle with respect to the XY plane than the -Z-side bottom surface of the semiconductor layer 66, and as viewed along the Z-axis, it moves towards the +Z side as it approaches the center from the outer edge. The distance along the Z-axis between the outer edge and the center of the surface 66a of the semiconductor layer 66 is greater than the distance along the Z-axis between the outer edge and the center of the -Z-side bottom surface of the semiconductor layer 66. The dimension of the semiconductor layer 66 along the Z-axis, i.e., the thickness of the semiconductor layer 66, increases as it approaches the center from the outer edge.

[0045] The semiconductor layer 66 is composed of a superlattice (SL) of InGaN and GaN. The layer composed of the InGaN and GaN superlattice is a laminate in which InGaN layers and GaN layers are alternately stacked along the Z axis. The dimension of the InGaN layer in the InGaN and GaN superlattice along the Z axis, i.e., the thickness of the InGaN layer, is, for example, about 5 nm. The dimension of the GaN layer in the InGaN and GaN superlattice along the Z axis, i.e., the thickness of the GaN layer, is about the same as the thickness of the InGaN layer, for example, about 5 nm.

[0046] The +Z-side surface 66a of the semiconductor layer 66 corresponds to the third surface described later and the third surface described in the claims, and is a facet, for example, the (10-11) surface of a layer consisting of an InGaN and GaN superlattice.

[0047] The dimension of the semiconductor layer 66 in the Z-axis at its outer edge, i.e., the thickness of the semiconductor layer 66 at its outer edge, is, for example, 100 nm to 400 nm. The average composition ratio of In in the semiconductor layer 66 is adjusted by the thickness of the semiconductor layer 66. The semiconductor layer 66 acts as a pseudo-mixed crystal of InGaN, in which the average composition ratio of In is adjusted by the thickness. In the light-emitting element 20 of this embodiment, the average composition ratio of In in the semiconductor layer 66 is at least 18%, preferably 20% or more, and more preferably 25% or more and less than 30%.

[0048] When the average composition ratio of In in semiconductor layer 66 is approximately 22%, the angle that the surface 66a of semiconductor layer 66 makes with respect to the XY plane is approximately 60°, and the angle that the -Z side surface of semiconductor layer 66 and the surface 65a of semiconductor layer 65 make with respect to the XY plane is approximately 30°.

[0049] The semiconductor layer 67 is positioned on the +Z side of the semiconductor layer 66 and is stacked on the +Z side of the semiconductor layer 66. The semiconductor layer 67 corresponds to the active layer and corresponds to the light-emitting layer described later and the light-emitting layer described in the claims.

[0050] The bottom surface of the semiconductor layer 67 on the -Z side is in contact with the surface 66a of the semiconductor layer 66 from the +Z side, and is inclined with respect to the XY plane at the same angle as the surface 66a of the semiconductor layer 66, and moves towards the +Z side as it approaches the center from the outer edge when viewed along the Z axis. The surface 67a on the +Z side of the semiconductor layer 67 is inclined with respect to the XY plane at the same angle as the surface 66a of the semiconductor layer 66 and the bottom surface of the -Z side of the semiconductor layer 67, and moves towards the +Z side as it approaches the center from the outer edge when viewed along the Z axis. The dimensions of the semiconductor layer 67 along the Z axis, i.e., the thickness of the semiconductor layer 67, are substantially uniform in the XY plane from the outer edge to the center.

[0051] The surface 67a of the semiconductor layer 67 corresponds to the second surface described later and the second surface described in the claims, and is a facet, for example, the (10-11) surface of a layer consisting of a multi quantum well (MQW) structure of InGaN and GaN.

[0052] The semiconductor layer 67 is composed of a laminated structure of InGaN layers and GaN layers and has MQW. The laminated structure of InGaN layers and GaN layers is a laminate in which InGaN layers and GaN layers are stacked alternately along the Z axis.

[0053] The dimension of the semiconductor layer 67 in the Z-axis, i.e., the thickness of the semiconductor layer 67, is, for example, 20 nm to 200 nm. The average composition ratio of In in the semiconductor layer 67 is adjusted by the thickness of the semiconductor layer 67, similar to the semiconductor layer 66. In the light-emitting element 20 of this embodiment, the composition ratio of In in the InGaN layer, which has the highest In composition in the semiconductor layer 67, is at least higher than the average composition ratio of In in the semiconductor layer 66, and is 30% or more, for example, 33% to 35%. It is desirable that the average composition ratio of In in the semiconductor layer 67 be 30% or more.

[0054] For example, if the average composition ratio of In in semiconductor layer 66 is approximately 22% and the average composition ratio of In in semiconductor layer 67 is approximately 33%, then the angle that the surface 67a of semiconductor layer 67 makes with respect to the XY plane is approximately 60°.

[0055] The band gap of InGaN contained in semiconductor layers 66 and 67 is relatively narrow compared to other semiconductor materials. In the light-emitting element 20 of this embodiment, semiconductor layer 66, in which the average composition ratio of In is lower than that of semiconductor layer 67, is arranged as a buffer layer on the -Z side of semiconductor layer 67, i.e., below semiconductor layer 67, which is the active layer. By arranging semiconductor layer 66 between semiconductor layer 65 and semiconductor layer 67, the difference in lattice constants between semiconductor layer 65 containing n-type GaN and semiconductor layer 67 containing InGaN is mitigated.

[0056] Because the average composition ratio of In in the semiconductor layer 66 is higher than that of the semiconductor layer of conventional light-emitting devices, the semiconductor layer 66 is arranged on the +Z side of the center of the nanocolumn 57 in the direction along the Z axis, i.e., on the upper part of the nanocolumn 57, as a hexagonal pyramidal structure with (10-11) facets, with a surface 66a and consisting of a superlattice of InGaN and GaN.

[0057] In this embodiment, the average composition ratio of In in the semiconductor layer 66 of the light-emitting element 20 is at least less than 18%. However, as will be explained later, it has been confirmed that even if the average composition ratio of In in the semiconductor layer 66 is around 16%, the (10-11) plane appears well on the surface 66a. If the average composition ratio of In in the semiconductor layer 66 is excessively low, for example less than 15%, then in addition to the (10-11) plane, (10-12) planes or (10-13) planes may be present on the surface 66a of the semiconductor layer 66. In that case, the crystal quality and characteristics of the semiconductor layer 67 growing from the surface 66a of the semiconductor layer 66 towards the +Z side may become non-uniform in planes parallel to the XY plane, potentially leading to the occurrence of through-dislocations and defects in the semiconductor layer 67 and a decrease in the luminous efficiency of the light-emitting element 20.

[0058] If the average composition ratio of In in the semiconductor layer 66 is 20% or more, then when a semiconductor layer 67 with an even higher average composition ratio of In is grown from the surface 66a of the semiconductor layer 66, In will smoothly enter the semiconductor layer 67. By arranging the semiconductor layer 66, even when the temperature of the environment in which the light-emitting element 20 is manufactured is relatively high, a desired semiconductor layer 67 with a high average composition ratio of In, 30% or more, can be obtained, improving the luminous efficiency of the light-emitting element 20.

[0059] When current is injected into the light-emitting element 20, carriers are recombined effectively, and the brightness of the optical LC emitted from the light-emitting element 20 is improved. In the semiconductor layer 67, the In composition ratio of the InGaN layer, which has the highest In composition, is 30% or more. For example, the average composition ratio of In is 30% or more, which is relatively high, so the wavelength band of the optical LC can easily be in the long red wavelength band of the visible wavelength range.

[0060] The semiconductor layer 68 is located on the +Z side of the semiconductor layer 67 and is stacked on the +Z side of the semiconductor layer 67. The semiconductor layer 68 corresponds to the second semiconductor layer described later and the second semiconductor layer described in the claims. The semiconductor layer 68 is formed of a semiconductor material having a different conductivity than the semiconductor layer 55, and is composed of, for example, a p-type GaN layer doped with magnesium (Mg).

[0061] The -Z-side surface of semiconductor layer 68 is tilted with respect to the XY plane at the same angle as the surface 67a of semiconductor layer 67, and when viewed along the Z axis, it moves towards the +Z side as it approaches the center from the outer edge.

[0062] An insulating layer, not shown, may be formed on the +Z-side surface of the mask layer 56. The +Z-side surface of the insulating layer, not shown, is located at the same position on the Z-axis as the +Z-side surface of the semiconductor layer 68 of the multiple nanocolumns 57, and forms substantially the same plane as the +Z-side surface of the semiconductor layer 68. The refractive index of the insulating layer, not shown, is lower than the effective refractive index of the semiconductor layer 67 of the nanocolumn 57. The insulating layer, not shown, is composed of, for example, a silicon oxide (SiO2) layer or an aluminum oxide (Al2O3) layer.

[0063] The conductive layer 52 is positioned laterally to the multiple nanocolumns 57 in the XY plane and is formed on the surface 55a of the semiconductor layer 55B in the peripheral region R24 of the semiconductor layer 55. The conductive layer 52 is electrically connected to the semiconductor layer 67 of the nanocolumn 57 via the semiconductor layer 55 and the semiconductor layers 65 and 66 of the nanocolumn 57. The conductive layer 52 corresponds to the first electrode of the light-emitting element 20 and is one of the electrodes for injecting current into the semiconductor layer 67 of the nanocolumn 57.

[0064] The conductive layer 52 is composed of layers made of a conductive material, and may be composed of, for example, an aluminum (Al) layer or a gold (Au) layer, or it may be composed of a laminate in which a Ti layer, an Al layer and an Au layer are stacked in this order on the +Z side.

[0065] The conductive layer 53 is positioned on the +Z side, i.e., above, the multiple nanocolumns 57 and is formed across the +Z side surface of the multiple semiconductor layers 68. The conductive layer 53 is electrically connected to the semiconductor layers 67 via the semiconductor layers 68 of the nanocolumns 57. The conductive layer 53 corresponds to the second electrode of the light-emitting element 20 and is the other electrode for injecting current into the semiconductor layers 67 of the nanocolumns 57.

[0066] The conductive layer 53 is composed of a layer made of a conductive material, for example, ITO (Indium Tin Oxide), and may be composed of an Al layer or an Au layer.

[0067] In the light-emitting element 20, a PIN diode is formed by a p-type semiconductor layer 68 of the nanocolumn 57, an undoped semiconductor layer 67, and an n-type semiconductor layer 65. The band gap between semiconductor layers 65 and 68 is larger than the band gap in semiconductor layer 67. When a forward bias voltage corresponding to the PIN diode is applied between the conductive layers 52 and 53 and current is injected, recombination of electrons and holes occurs in semiconductor layer 67, generating light.

[0068] <Method for manufacturing luminescent elements> Next, a method for manufacturing the light-emitting element 20 of one embodiment of the present invention will be described. Figures 4 to 6 are cross-sectional views illustrating the manufacturing method of the light-emitting element 20, and correspond to the view taken along the line III-III shown in Figure 2.

[0069] First, a semiconductor layer 55 is formed on the surface 50a of a substrate 50, such as a sapphire substrate, by stacking a substrate 155 made of n-type GaN crystal or the like on the +Z side of the surface 50a of the substrate 50. However, the semiconductor layer 55 may also be formed by epitaxially growing an n-type GaN layer on the surface 50a of the substrate 50 using a metal-organic vapor deposition method or the like.

[0070] Next, as shown in Figure 4, a mask layer 56 made of a Ti layer or the like with a thickness of about 5 nm is formed on the surface 55a of the semiconductor layer 55. Then, as shown in Figure 5, the mask layer 56 is patterned according to the arrangement of the multiple nanocolumns 57 in the XY plane, and a small region of the surface 55a of the semiconductor layer 55 is formed to expose. For the formation of the mask layer 56 over the entire surface 55a of the semiconductor layer 55, for example, a deposition method may be used. For the patterning of the mask layer 56, electron beam (EB) lithography and dry etching may be used. By patterning the mask layer 56, multiple openings are formed in the mask layer 56 according to the relative arrangement of the multiple nanocolumns 57, and the surface 55a of the small region of the surface 55a of the semiconductor layer 55 where the multiple nanocolumns 57 are formed is exposed.

[0071] Next, as shown in Figure 5, a step is performed to form nanocolumns 57 in a small region of the semiconductor layer 55 that is not covered by the mask layer 56 from the +Z side. Molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) may be used to form the nanocolumns 57. By using appropriate growth conditions for each of the semiconductor layers 65, 66, 67, and 68, the mask layer 56 acts as a selective growth mask, and columnar semiconductor layers 65, 66, 67, and 68 grow in the openings of the mask layer 56, extending along the Z axis towards the +Z side.

[0072] In the process of growing the nanocolumn 57 along the Z-axis towards the +Z side, the amount of semiconductor material irradiated onto the columnar semiconductor layer 65, 66, 67, and 68 from the +Z side and the outer periphery in the XY plane, i.e., from obliquely above, is appropriately adjusted at each growth stage of the columnar semiconductor layer 65, 66, 67, and 68. The irradiation rate of the semiconductor material for each semiconductor layer is included in the appropriate growth conditions for each of the semiconductor layers 65, 66, 67, and 68.

[0073] Although not shown in the diagram, after the formation of multiple nanocolumns 57, a conductive layer 53 is formed over the semiconductor layer 68 of the multiple nanocolumns 57 in the light-emitting region R22 corresponding to the display area using electrode patterning or the like. The mask layer 56 of the peripheral region R24 is removed, and the +Z side portion of the semiconductor layer 55 of the peripheral region R24 is removed using dry etching or the like, and a conductive layer 52 is formed on the surface 55a of the semiconductor layer 55B using electrode patterning or the like.

[0074] By performing the steps described above, the light-emitting element 20 shown in Figure 3 can be manufactured.

[0075] <Prototype Example> Next, a prototype example of the light-emitting element 20 of this embodiment will be described. The element of the prototype example was manufactured based on the configuration and manufacturing method of the light-emitting element 20 described above.

[0076] Figure 7 shows HAADF-STEM (High-Angle Annular Dark Field Scanning Transmission Electron Microscopy) images of multiple nanocolumns 57 of the first prototype light-emitting element 20. Figure 8 is a magnified view of a portion of the HAADF-STEM image in Figure 7. In the first prototype, the average composition ratio of In in the semiconductor layer 66 was assumed to be 25%, and the average composition ratio of In in the semiconductor layer 67 was assumed to be 33%. From Figures 7 and 8, it can be confirmed that high-quality semiconductor layers 66 and 67 with almost no crystal defects are formed in the columnar nanocolumns 57.

[0077] As shown in Figure 8, a semiconductor layer 67A, which can act as a barrier layer consisting of a superlattice of InGaN and GaN, is formed on the -Z side of the semiconductor layer 67. A semiconductor layer 67B, which acts as an MQW of InGaN and GaN, is formed on the +Z side of the semiconductor layer 67.

[0078] Figure 9 is a graph showing the average composition ratios of In and Ga in the range of the IX-IX line in Figure 8. As shown in Figure 9, the average composition ratio of In in semiconductor layer 66 was approximately 25%, as expected, and the average composition ratio of In in semiconductor layer 67 was approximately 33%, as expected.

[0079] Figure 10 shows HAADF-STEM images of the semiconductor layers 65 and 66 of multiple nanocolumns 57 in the second prototype light-emitting element 20. In the second prototype, the average composition ratio of In in the semiconductor layer 66 was assumed to be 16%. From Figure 10, it can be confirmed that high-quality semiconductor layers 66 with almost no crystal defects are formed in the columnar nanocolumns 57.

[0080] Figure 11 is a graph showing the average composition ratio of In and Ga in the XI-XI line range of Figure 10. As shown in Figure 11, the average composition ratio of In in semiconductor layer 66 was approximately 16%, as expected.

[0081] The light-emitting element 20 of this embodiment described above includes a semiconductor layer (first semiconductor layer) 65, a semiconductor layer (second semiconductor layer) 68, a semiconductor layer (light-emitting layer) 67, and a semiconductor layer (buffer layer) 66. The semiconductor layer 65 has a surface (first surface) 65a on the +Z side. The semiconductor layer 68 has a different conductivity than the semiconductor layer 65. In this embodiment, the semiconductor layer 65 has n-type conductivity, while the semiconductor layer 68 has p-type conductivity. The semiconductor layer 67 is located between the semiconductor layers 65 and 68 on the Z axis. The semiconductor layer 66 is located between the semiconductor layers 65 and 68 on the Z axis. In the light-emitting element 20 of this embodiment, the semiconductor layer 67 has a laminate in which InGaN layers and GaN layers are alternately stacked on the Z axis, and has a faceted surface (second surface) 67a. In the semiconductor layer 67, the In composition ratio of the InGaN layer, which has the highest In composition, is 30% or more. The semiconductor layer 66 has a faceted surface (third surface) 66a. The composition ratio of In in the semiconductor layer 66 is at least 18%, preferably 20% or more.

[0082] In the light-emitting element 20 of this embodiment, the light-emitting element has a nanocolumn 57, and the nanocolumn 57 has a buffer layer, which is a semiconductor layer 66 containing InGaN and GaN, between a semiconductor layer 65 containing n-type GaN and a light-emitting layer, which is a semiconductor layer 67 containing InGaN and GaN. In the semiconductor layer 67, the In composition ratio of the InGaN layer, which has the highest In composition, is high, at 30% or more, whereas the average composition ratio (composition ratio) of In in the semiconductor layer 66 is lower than the In composition ratio of the InGaN layer, which has the highest In ratio in the semiconductor layer 67, being 20% ​​or more and less than 30%. In the light-emitting element 20 of this embodiment, the difference in lattice constants between the semiconductor layers 65 and 67 is mitigated by the semiconductor layer 66, so that the occurrence of crystal defects in the semiconductor layer 67 is suppressed, a high-quality semiconductor layer 67 is formed, and optical LC in the red wavelength band on the longer wavelength side of the visible wavelength band can be emitted from the semiconductor layer 67. In other words, it is possible to achieve both sufficient thickness of semiconductor layers 66 and 67 for light confinement in the nanocolumn 57 and suppression of the occurrence of crystal defects in the semiconductor layer 67.

[0083] In the light-emitting element 20 of this embodiment, the surface 65a of the semiconductor layer 65 is faceted.

[0084] According to the light-emitting element 20 of this embodiment, since a (10-11) facet is formed on the surface 65a of the semiconductor layer 65, the (10-11) facet can be realized on the surface 66a without excessively increasing the thickness of the semiconductor layer 66 grown on the +Z side of the surface 65a. This simplifies the manufacturing process of the light-emitting element 20 of this embodiment and allows for miniaturization of the light-emitting element 20.

[0085] In the light-emitting element 20 of this embodiment, the semiconductor layer 66 is a superlattice layer in which InGaN layers and GaN layers are stacked alternately along the Z axis.

[0086] According to the light-emitting element 20 of this embodiment, since the semiconductor layer 66 is composed of a superlattice of InGaN and GaN, the difference in lattice constants between the semiconductor layers 65 and 67 is more smoothly mitigated, and the illuminance distribution and light quantity of the optical LC emitted from the light-emitting element 20 can be stabilized.

[0087] The projector 10 of this embodiment includes a light-emitting device 12 having the light-emitting element 20 of this embodiment.

[0088] According to the projector 10 of this embodiment, since it has a high-quality light-emitting element 20, it is possible to improve the characteristics of the image light LM based on the light LC emitted from the light-emitting element 20, and to improve the display quality of the projected image.

[0089] In addition to projectors, other examples of electronic devices having the light-emitting element 20 of this embodiment include head-mounted displays (HMDs) and printers.

[0090] The method for manufacturing a light-emitting element of this embodiment is a method for manufacturing a light-emitting element 20, comprising the step of sequentially forming semiconductor layers 65, 66, 67, and 68 on the surface 50a of a substrate 50 via a semiconductor layer 55, along a direction parallel to the Z-axis intersecting the surface 50a. In the above step, a (10-11) facet (third facet) is made to appear on the +Z side surface 66a of the semiconductor layer 66, and a (10-11) facet (second facet) is made to appear on the +Z side surface 67a of the semiconductor layer 67.

[0091] According to the manufacturing method of the light-emitting element of this embodiment, the above-mentioned high-quality light-emitting element 20 can be manufactured.

[0092] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims.

[0093] [Summary of this disclosure] A summary of this disclosure is provided below. (Note 1) A light-emitting element comprising: a first semiconductor layer having a first surface; a second semiconductor layer having conductivity different from that of the first semiconductor layer; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and a buffer layer disposed between the light-emitting layer and the first semiconductor layer, wherein the light-emitting layer has a laminate in which indium gallium nitride (InGaN) layers and gallium nitride (GaN) layers are alternately stacked, and has a second surface which is a facet, and the In composition ratio of the InGaN layer having the highest In composition in the light-emitting layer is 30% or more, and the buffer layer has a third surface which is a facet, and the In composition ratio of the buffer layer is 20% or more.

[0094] In the configuration described in Appendix 1, the buffer layer mitigates the difference in lattice constants between the first semiconductor layer and the light-emitting layer, suppressing the generation of crystal defects in the light-emitting layer, thus enabling the formation of a high-quality light-emitting layer. The configuration described in Appendix 1 makes it possible to achieve both sufficient thickness of the buffer layer and light-emitting layer for light confinement in the nanocolumn of the light-emitting element and suppression of the generation of crystal defects in the light-emitting layer.

[0095] (Note 2) The first surface is a facet, the light-emitting element of Note 1.

[0096] The configuration described in Appendix 2 allows the third surface to be realized as a facet without excessively increasing the thickness of the buffer layer grown on the first surface.

[0097] (Note 3) The light-emitting element according to Note 1 or Note 2, wherein the buffer layer is a superlattice layer which is a laminate in which InGaN layers and GaN layers are stacked alternately.

[0098] The configuration described in Appendix 3 allows for a smoother reduction of the difference in lattice constants between the first semiconductor layer and the light-emitting layer, thereby stabilizing the illuminance distribution and light intensity of the light emitted from the light-emitting element.

[0099] (Note 4) An electronic device equipped with a light-emitting element as described in any of Notes 1 to 3.

[0100] The configuration described in Appendix 4 makes it possible to improve the characteristics of the image light based on the light emitted from the light-emitting element, and to improve the display quality of the image displayed by the image light.

[0101] (Note 5) A method for manufacturing a light-emitting element as described in any of Notes 1 to 3, comprising the step of sequentially forming the first semiconductor layer, the buffer layer, the light-emitting layer, and the second semiconductor layer on the surface of a substrate in a direction intersecting the surface, wherein in the step, a second surface which is a facet of the light-emitting layer is revealed, and a third surface which is a facet of the buffer layer is revealed.

[0102] The configuration described in Appendix 5 allows for the provision of high-quality light-emitting elements as described above. [Explanation of Symbols]

[0103] 10...Projector (electronic device), 20...Light-emitting element, 65...Semiconductor layer (first semiconductor layer), 66...Semiconductor layer (buffer layer), 67...Semiconductor layer (light-emitting layer), 68...Semiconductor layer (second semiconductor layer).

Claims

1. A first semiconductor layer having a first surface, A second semiconductor layer having a different conductivity from the first semiconductor layer, A light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, A buffer layer disposed between the light-emitting layer and the first semiconductor layer, Equipped with, The light-emitting layer has a laminate in which indium gallium nitride (InGaN) layers and gallium nitride (GaN) layers are alternately stacked, and has a second facet surface. In the aforementioned light-emitting layer, the In composition ratio of the InGaN layer, which has the highest indium (In) composition, is 30% or more. The buffer layer has a third facet, The composition ratio of In in the buffer layer is 20% or more. Light-emitting element.

2. The first surface is a facet. The light-emitting element according to claim 1.

3. The buffer layer is a superlattice layer, which is a laminate in which InGaN layers and GaN layers are stacked alternately. The light-emitting element according to claim 1.

4. A light-emitting element according to any one of claims 1 to 3, electronic equipment.

5. A method for manufacturing an light-emitting element as described in claim 1, The process includes sequentially forming the first semiconductor layer, the buffer layer, the light-emitting layer, and the second semiconductor layer on the surface of the substrate along a direction intersecting the surface, In the above process, The second surface, which is a facet of the aforementioned light-emitting layer, is revealed. To bring forth the third surface, which is a facet of the buffer layer, A method for manufacturing a light-emitting element.

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