Integrated circuit device

Abstract

The present invention provides an integrated circuit device equipped with a transistor including a multi-gate MOSFET with improved operating characteristics. [Solution] The invention comprises one or more first semiconductor patterns extending in a first horizontal direction, a first source / drain region connected to the first horizontal end of one or more first semiconductor patterns, one or more second semiconductor patterns spaced apart from one or more first semiconductor patterns in a second horizontal direction intersecting the first horizontal direction and extending in the first horizontal direction, a second source / drain region connected to the first horizontal end of one or more second semiconductor patterns, and an insulating wall extending in a first horizontal direction between one or more first semiconductor patterns and one or more second semiconductor patterns and between the first source / drain region and the second source / drain region and disposed within an insulating wall opening, wherein the insulating wall includes an insulating wall liner disposed on the inner wall of the insulating wall opening, an embedded insulating layer disposed on the insulating wall liner, and an insulating wall capping layer disposed within the insulating wall opening and on the upper surface of the insulating wall liner and the upper surface of the embedded insulating layer.

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device including a field-effect transistor. [Background technology]

[0002] The demand for miniaturization, multi-functionality, and high performance in electronic products has led to a need for high-capacity integrated circuit devices, and to provide such devices, an increased degree of integration is required. For example, in order to improve the performance of a device, it is necessary to explore new methods through structural changes of the device, and proposing integrated circuit devices equipped with transistors of new structures is a daily challenge. [Overview of the project] [Problems that the invention aims to solve]

[0003] The present invention has been made in view of the problems in the above-mentioned conventional integrated circuit devices, and the object of the present invention is to provide an integrated circuit device equipped with a transistor including a multi-gate MOSFET with improved operating characteristics. [Means for solving the problem]

[0004] To achieve the above objective, an integrated circuit device according to the present invention comprises: at least one first semiconductor pattern extending in a first horizontal direction; a first source / drain region connected to the first horizontal end of the at least one first semiconductor pattern; at least one second semiconductor pattern spaced apart from the at least one first semiconductor pattern in a second horizontal direction intersecting the first horizontal direction and extending in the first horizontal direction; a second source / drain region connected to the first horizontal end of the at least one second semiconductor pattern; and an insulating wall extending in the first horizontal direction and disposed within an insulating wall opening between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and between the first source / drain region and the second source / drain region, wherein the insulating wall comprises an insulating wall liner disposed on the inner wall of the insulating wall opening; an embedded insulating layer disposed on the insulating wall liner; and an insulating wall capping layer disposed within the insulating wall opening and on the upper surface of the insulating wall liner and the upper surface of the embedded insulating layer.

[0005] Furthermore, an integrated circuit device according to an embodiment of the present invention includes a first active region and a second active region extending in a first horizontal direction, an insulating wall extending in the first horizontal direction between the first active region and the second active region, at least one first semiconductor pattern disposed on the first active region and extending in the first horizontal direction, a first source / drain region disposed on the first active region and connected to the at least one first semiconductor pattern, at least one second semiconductor pattern disposed on the second active region and extending in the first horizontal direction, and a second source / drain region disposed on the second active region and connected to the at least one second semiconductor pattern, wherein the insulating wall includes an embedded insulating layer extending in the first horizontal direction between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and between the first source / drain region and the second source / drain region, an insulating wall liner disposed on the side wall of the embedded insulating layer, and an insulating wall capping layer disposed on the upper surface of the insulating wall liner and the upper surface of the embedded insulating layer.

[0006] Furthermore, an integrated circuit device according to an embodiment of the present invention includes a substrate including a first active region and a second active region extending in a first horizontal direction; at least one first semiconductor pattern and at least one second semiconductor pattern disposed on the first active region and spaced apart in the vertical direction; a first source / drain region and a second source / drain region disposed on the first active region and the second active region, respectively, and connected to the at least one first semiconductor pattern and the at least one second semiconductor pattern; and an insulating wall between the first active region and the second active region, and between the at least one first semiconductor pattern and the at least one second semiconductor pattern, wherein the insulating wall includes an embedded insulating layer, an insulating wall liner disposed on the side wall of the embedded insulating layer, and an insulating wall capping layer disposed on the upper surface of the insulating wall liner and the upper surface of the embedded insulating layer. [Effects of the Invention]

[0007] According to the integrated circuit apparatus of the present invention, by forming an insulating wall including an insulating wall liner, an embedded insulating layer, and an insulating wall capping layer, the insulating wall liner contains a low dielectric constant material, thereby preventing coupling effects and improving the threshold voltage regulation characteristics of the integrated circuit apparatus. Furthermore, since the insulating wall capping layer covers the upper surface of the insulating wall liner, it is possible to prevent loss or damage to the insulating wall that may occur when the upper surface of the insulating wall liner is exposed during the element isolation film formation process. [Brief explanation of the drawing]

[0008] [Figure 1] This is a layout diagram showing the schematic configuration of an integrated circuit device according to an embodiment of the present invention. [Figure 2] Figure 1 is a perspective view showing the schematic configuration of an integrated circuit device. [Figure 3A] This is a cross-sectional view taken along the line A-A' in Figure 1. [Figure 3B] This is a cross-sectional view taken along the line B-B' in Figure 1. [Figure 3C] This is a cross-sectional view taken along the line C-C' in Figure 1. [Figure 4A] This is an enlarged view of the CX1 portion in Figure 3B. [Figure 4B] This is an enlarged view of the CX2 portion in Figure 3C. [Figure 5A] This is a cross-sectional view showing a schematic configuration of an integrated circuit device according to an embodiment of the present invention. [Figure 5B] This is a cross-sectional view showing a schematic configuration of an integrated circuit device according to an embodiment of the present invention. [Figure 5C] This is a cross-sectional view showing a schematic configuration of an integrated circuit device according to an embodiment of the present invention. [Figure 6A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7A]A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7B] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7C] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 8A] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 8B] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 9A] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 9B] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 10] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 11] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12A] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12B] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 13A] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 13B] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 13C] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 14A] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 14B] A cross-sectional view for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 14C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 15A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 15B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 15C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 16A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 16B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 16C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 17A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 17B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 17C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 18A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 18B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 18C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 19A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 19B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 19C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 20A] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 20B] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 20C] This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0009] Next, specific examples of embodiments for implementing the integrated circuit device according to the present invention will be described with reference to the drawings.

[0010] Figure 1 is a layout diagram showing the schematic configuration of an integrated circuit device 100 according to an embodiment of the present invention; Figure 2 is a perspective view showing the schematic configuration of the integrated circuit device 100 of Figure 1; Figure 3A is a cross-sectional view taken along the line A-A' in Figure 1; Figure 3B is a cross-sectional view taken along the line B-B' in Figure 1; Figure 3C is a cross-sectional view taken along the line C-C' in Figure 1; Figure 4A is an enlarged view of the CX1 portion of Figure 3B; and Figure 4B is an enlarged view of the CX2 portion of Figure 3C.

[0011] Referring to Figures 1, 2, 3A, 3B, 3C, 4A, and 4B, the integrated circuit device 100 includes a plurality of cell transistors CTR arranged at a first vertical level, and a front wiring structure FS arranged at a second vertical level higher than the first vertical level and electrically connected to the plurality of cell transistors CTR. Multiple cell transistors (CTRs) each constitute various types of logic cells included in a logic circuit. In an embodiment of the present invention, the integrated circuit device 100 constitutes a logic cell including a multibridge channel FET (MBCFET) element.

[0012] The integrated circuit device 100 includes a first active region RX1 and a second active region RX2 that protrude from the upper surface of the substrate 110 and extend along a first horizontal direction X, respectively. In this embodiment, the first active region RX1 and the second active region RX2 protrude vertically Z from the upper surface of the substrate 110 and extend along the first horizontal direction X. An element isolation film 112 is placed in an element isolation trench 112T that extends within the substrate 110, and at least a portion of the side walls of the first active region RX1 and the second active region RX2 are in contact with the element isolation film 112. In this embodiment, the first active region RX1 and the second active region RX2 are either PMOS transistor regions or NMOS transistor regions. In this embodiment, the multiple cell transistors CTR arranged within the first active region RX1 and the second active region RX2 may include PMOS transistors. In this embodiment, the multiple cell transistors CTR arranged within the first active region RX1 and the second active region RX2 may include NMOS transistors. In other embodiments, the plurality of cell transistors CTR located within the first active region RX1 may include PMOS transistors, and the plurality of cell transistors CTR located within the second active region RX2 may include NMOS transistors.

[0013] In this embodiment, an insulating wall DW extending in the first horizontal direction X is placed between the first active region RX1 and the second active region RX2. The insulating wall DW is located within an insulating wall opening DWH that extends into the substrate 110 between the first active region RX1 and the second active region RX2. The bottom surface of the insulating wall opening DWH is positioned at the same vertical level as the bottom surface level LV0 of the element isolation trench 112T. The insulating wall DW includes an insulating wall liner D10 positioned on the inner wall of the insulating wall opening DWH, an embedded insulating layer D20 filling the insulating wall opening DWH on the insulating wall liner D10, and an insulating wall capping layer D30 positioned on the embedded insulating layer D20 and the insulating wall liner D10.

[0014] In one embodiment, the insulating wall liner D10 includes a low dielectric constant film (for example, a film having a dielectric constant in the range of 2.0 to 3.0). For example, the insulating wall liner D10 may contain at least one of silicon carbon oxide, silicon carbon nitride, or silicon carbon oxynitride. In the embodiment, the embedded insulating layer D20 may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In the embodiment, the insulating wall capping layer D30 may include at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0015] In this embodiment, the insulating wall DW includes a first portion DWU1 and a second portion DWU2, which have different heights in the vertical direction Z. For example, the first portion DWU1 of the insulating wall DW has an upper surface positioned at a first vertical level LV1, and the second portion DWU2 of the insulating wall DW has an upper surface positioned at a second vertical level LV2 which is lower than the first vertical level LV1. For example, when using the level LV0 at the bottom of the element isolation trench 112T as a reference, the second vertical level LV2 is even lower than the first vertical level LV1. In one embodiment, a portion of the upper part of the insulating wall DW is removed by a recessing process, for example, lowering the upper surface level of the second portion DWU2 of the insulating wall DW. During the recessing process, the portion of the insulating wall capping layer D30 contained within the second portion DWU2 of the insulating wall DW is removed. As a result, the insulating wall capping layer D30 remains only in the first portion DWU1 of the insulating wall DW and not in the second portion DWU2 of the insulating wall DW. For example, the upper surface of the insulating wall capping layer D30 within the first portion DWU1 of the insulating wall DW is located at the first vertical level LV1, and the upper surface of the second portion DWU2 of the insulating wall DW, i.e., the upper surface of the embedded insulating layer D20, is located at the second vertical level LV2.

[0016] Multiple cell transistors CTR are arranged on the first active region RX1 and the second active region RX2, spaced apart along the first horizontal direction X and the second horizontal direction Y. A plurality of cell transistors CTR include a plurality of semiconductor patterns NS arranged spaced apart in the vertical direction Z, a plurality of gate structures GS surrounding the plurality of semiconductor patterns NS and extending in the second horizontal direction Y, and a plurality of source / drain regions SD located on both sides of the plurality of gate structures GS. In the embodiment, each of the plurality of semiconductor patterns NS may include a group IV semiconductor such as Si or Ge, a group IV-IV compound semiconductor such as SiGe or SiC, or a group III-V compound semiconductor such as GaAs, InAs, or InP.

[0017] In this embodiment, each of the multiple semiconductor patterns NS is arranged on the side wall of the insulating wall DW and is spaced apart in the vertical direction Z on the side wall of the insulating wall DW. In this embodiment, a plurality of semiconductor patterns NS (here, the plurality of semiconductor patterns NS arranged on the first active region RX1 are referred to as the first semiconductor pattern NS1) are arranged on the first side wall DWS1 of the insulating wall DW in contact with the first side wall DWS1. In this embodiment, a plurality of semiconductor patterns NS (here, the plurality of semiconductor patterns NS arranged on the second active region RX2 are referred to as the second semiconductor pattern NS2) are arranged on the second active region RX2 (or in a position that vertically overlaps with the second active region RX2) in contact with the second side wall DWS2 opposite to the first side wall DWS1 of the insulating wall DW, and are positioned on the second side wall DWS2.

[0018] In this embodiment, the end of the first semiconductor pattern NS1 in the second horizontal direction Y is in contact with the first side wall DWS1 of the insulating wall DW, and the end of the second semiconductor pattern NS2 in the second horizontal direction Y is in contact with the second side wall DWS2 of the insulating wall DW. In this embodiment, the first semiconductor pattern NS1 and the second semiconductor pattern NS2 are arranged separated in the second horizontal direction Y with an insulating wall DW in between, and the first semiconductor pattern NS1 and the second semiconductor pattern NS2 are in contact with the side wall of the insulating wall liner D10. In this embodiment, the upper surface of the insulating wall liner D10 contained within the first portion DWU1 of the insulating wall DW is positioned at a vertical level higher than the upper surface of the uppermost semiconductor pattern NS among the plurality of semiconductor patterns NS. The upper surface of the insulating wall liner D10 contained within the first portion DWU1 of the insulating wall DW is positioned at a lower vertical level than the upper surface of the insulating wall capping layer D30 contained within the first portion DWU1 of the insulating wall DW. As a result, the insulating wall liner D10 is not exposed to the etching atmosphere during the insulating layer formation process for forming the element isolation film 112 and / or the subsequent etch-back process.

[0019] In this embodiment, the multiple gate structures GS extend in the second horizontal direction Y so as to surround the multiple semiconductor patterns NS on the first sidewall DWS1 and second sidewall DWS2 of the insulating wall DW, and are spaced apart along the first horizontal direction X. In this embodiment, each of the multiple gate structures GS includes a gate electrode 122 and a gate insulating layer 124. For example, the gate electrode 122 is extended in the second horizontal direction Y so as to surround multiple semiconductor patterns NS, and a gate insulating layer 124 is placed between the gate electrode 122 and each of the semiconductor patterns NS. In this embodiment, the gate insulating layer 124 is arranged on the top surface, side walls, and bottom surface of a plurality of semiconductor patterns NS and conformally extends onto the first side wall DWS1 and the second side wall DWS2 of the insulating wall DW. In one embodiment, a portion of the gate insulating layer 124 is placed on the upper surface of the first portion DWU1 of the insulating wall DW (for example, the upper surface of the insulating wall capping layer D30), and the other portion of the gate insulating layer 124 is placed on the upper surface of the first active region RX1, the upper surface of the second active region RX2, and the upper surface of the element isolation film 112.

[0020] In embodiments, the gate electrode 122 may include doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or a combination thereof. For example, the gate electrode 122 can be made of Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof, but is not limited thereto. In an embodiment, the gate electrode 122 includes a work function metal-containing layer and a gap-fill metal film. The work function metal-containing layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The gap-fill metal film is made of a W film or an Al film.

[0021] In an embodiment, the gate electrode 122 may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W, but is not limited thereto. In an embodiment, the gate insulating layer 124 may be made of a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high-k dielectric film may be made of a metal oxide or a metal oxynitride. For example, the high-k dielectric film that can be used as the gate insulating layer 124 may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0022] In an embodiment, on the upper surface of the gate electrode 122, a capping layer 126 extends in the second horizontal direction Y. In an embodiment, the capping layer 126 is silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon carbonitride (SiC x N y ), silicon oxycarbonitride (SiO x C y N z) or a combination thereof. In this embodiment, spacers 128 are further positioned on the side walls of a portion of the gate structure GS, which is located at a higher level than the uppermost semiconductor pattern NS. The spacer 128 extends in the second horizontal direction Y to both side walls of the gate electrode 122 (or on the side walls of the gate insulating layer 124, which is located at a level higher than the uppermost semiconductor pattern NS), and the capping layer 126 is positioned on the upper surface of the spacer 128. In another embodiment, the spacer 128 may extend from the side walls of the gate electrode 122 onto the side walls of the capping layer 126.

[0023] In this embodiment, the upper surface of the gate structure GS is positioned at a vertical level higher than the bottom surface of the insulating wall capping layer D30 of the insulating wall DW. The upper surface of the first portion DWU1 of the insulating wall DW, surrounded by the gate electrode 122, is located at the first vertical level LV1, and the upper surface of the first portion DWU1 of the insulating wall DW has a substantially flat profile. Source / drain regions SD are formed on both sides of the gate structure GS. The source / drain region SD is located on recesses RS formed in the first active region RX1 and the second active region RX2, and connects to both ends of multiple semiconductor patterns NS. The source / drain region SD may have an upper surface that is identical to or located at a higher level than the uppermost semiconductor pattern NS.

[0024] In the embodiment, the source / drain region SD may, but is not limited to, a doped SiGe film, a doped Ge film, a doped SiC film, or a doped InGaAs film. In one embodiment, the source / drain region SD consists of multiple semiconductor layers with different compositions. For example, the source / drain region (SD) includes sequentially stacked lower semiconductor layers, upper semiconductor layers, and capping semiconductor layers. For example, the lower semiconductor layer, the upper semiconductor layer, and the capping semiconductor layer each contain SiC, but with different Si and C content.

[0025] In this embodiment, a second portion DWU2 of the insulating wall DW is positioned between a source / drain region SD (hereinafter referred to as the first source / drain region SD1) located on the first active region RX1 and a source / drain region SD (hereinafter referred to as the second source / drain region SD2) located on the second active region RX2. In one embodiment, a portion of the second portion DWU2 of the insulating wall DW located between the first source / drain region SD1 and the second source / drain region SD2 is removed by a recessing process, thereby giving the second portion DWU2 a rounded top surface. In this embodiment, the first source / drain region SD1 and the second source / drain region SD2 have upper surfaces that are positioned at a vertical level higher than the upper surface of the second portion DWU2 of the insulating wall DW located between them. Furthermore, the upper parts of the first source / drain region SD1 and the second source / drain region SD2 are positioned at a relatively small separation distance w2 (see Figure 16B) from each other at a vertical level higher than the upper surface of the second portion DWU2 of the insulating wall DW.

[0026] In one embodiment, the source / drain region SD includes a lower sidewall (SD_L) that contacts a second portion DWU2 of the insulating wall DW, and an upper sidewall (SD_U) that is positioned at a vertical level higher than the lower sidewall (SD_L) and does not contact the second portion DWU2 of the insulating wall DW. In one embodiment, as shown in Figure 4A, the upper sidewall (SD_U) of the source / drain region SD protrudes outward relative to the lower sidewall (SD_L) of the source / drain region SD. For example, the upper sidewall (SD_U) of the source / drain region SD is separated from the lower sidewall (SD_L) of the source / drain region SD by a first distance d1 in the second horizontal direction Y (from the lower sidewall (SD_L)). In the embodiment, the first distance d1 has a range of 0.1 to 5 nm. In one embodiment, the insulating wall DW has a first width w1 in the second horizontal direction Y, and the first width w1 is in the range of 15 to 25 nm. Therefore, the first source / drain region SD1 and the second source / drain region SD2 are arranged at a distance from each other, with the insulating wall DW in between.

[0027] A cell transistor (CTR) is either an NMOS transistor or a PMOS transistor, depending on the conductivity type of the semiconductor pattern NS and / or the conductivity type of the source / drain region SD. An etching stop film 142 is placed between the gate structures GS to cover the upper surface of the source / drain region SD, and an inter-gate insulating layer 144 is formed on the etching stop film 142 to fill the space between the gate structures GS. The etching stop film 142 contains silicon oxide or silicon oxynitride, and the intergate insulating layer 144 contains silicon oxide or silicon oxynitride. The etching stop film 142 is also conformally positioned on the upper surface of the second portion DWU2 of the insulating wall DW, which is located between the first source / drain region SD1 and the second source / drain region SD2.

[0028] The gate cut insulating layer GCI is positioned on the side wall of the gate structure GS in the second horizontal direction Y. Gate cut insulating layer The GCI fills the interior of the gate cut region GCIH, which is formed by removing a portion of the gate structure GS, the etching stop film 142, and the inter-gate insulating layer 144. In the embodiment, the bottom of the gate-cut insulating layer GCI extends to a level lower than the bottom surface of the gate electrode 122 and has a downward tapered shape. The bottom of the gate-cut insulating layer GCI is surrounded by the element isolation film 112. The upper surface of the gate-cut insulating layer GCI is positioned coplanar with the upper surface of the capping layer 126. An upper insulating layer 146 is placed on the gate cut insulating layer GCI and the inter-gate insulating layer 144. The upper insulating layer 146 contains silicon oxide or silicon oxynitride.

[0029] The first contact 152 and the first via 154 are positioned on the source / drain region SD, penetrating the upper insulating layer 146 and the inter-gate insulating layer 144, while the second contact 156 and the second via 158 are positioned on the gate electrode 122, penetrating the upper insulating layer 146 and the capping layer 126. In this embodiment, the first contact 152 and the first via 154 are stacked in a stacked structure so that the first contact 152 is electrically connected to the source / drain region SD and the first via 154 is positioned on the first contact 152, and the second contact 156 and the second via 158 are stacked in a stacked structure so that the second contact 156 is electrically connected to the gate electrode 122 and the second via 158 is positioned on the second contact 156. In other embodiments, the second via 158 may be omitted, and the upper surface of the first via 154 may be coplanar with the upper surface of the second contact 156 and the upper surface of the upper insulating layer 146. In other embodiments, the first via 154 and the second via 158 may be omitted, the first contact 152 may penetrate the upper insulating layer 146, and the upper surface of the first contact 152 may be coplanar with the upper surface of the second contact 156 and the upper surface of the upper insulating layer 146.

[0030] On the upper insulating layer 146, a front wiring structure FS is placed that is electrically connected to the cell transistor CTR. The front wiring structure FS includes the front via FSV, the front wiring layer FSW, and the front insulation layer FSI. In this embodiment, the front wiring layer FSW is a wiring pattern arranged on one vertical level, or it is a wiring pattern arranged on two or more vertical levels. In embodiments, the front insulating layer FSI may consist of an oxide film, a nitride film, a low dielectric constant film having a dielectric constant of about 2.2 to 2.4, or a combination thereof. The front wiring layer FSW is electrically connected to the first via 154 and the second via 158. The front via FSV is electrically connected to the front wiring layer FSW, and the front wiring layer FSW and the side walls of the front via FSV are surrounded by the front insulation layer FSI.

[0031] As the scaling down of integrated circuit devices progressed, an integrated circuit device was proposed in which semiconductor patterns were arranged with an insulating wall in between. When forming an insulating wall first and then forming a semiconductor pattern, there is a problem in that residual material from the semiconductor pattern is not completely removed, which degrades the characteristics of the device. To solve this problem, a method has been proposed in which semiconductor patterns are formed first, and then insulating walls are formed between the semiconductor patterns. However, this method has the problem of increasing the width deviation of the semiconductor patterns and degrading the device characteristics.

[0032] However, according to an integrated circuit device according to an embodiment of the present invention, an insulating wall DW is formed including an insulating wall liner D10, an embedded insulating layer D20, and an insulating wall capping layer D30, a recess process is performed on the upper side of the insulating wall DW to reduce the height of the insulating wall DW, and then the source / drain region SD is grown. The insulating wall liner D10 contains a low dielectric constant material, which prevents coupling effects and improves the threshold voltage regulation characteristics of the integrated circuit device 100. Furthermore, since the insulating wall capping layer D30 covers the upper surface of the insulating wall liner D10, it prevents loss or damage to the insulating wall DW that may occur if the upper surface of the insulating wall liner D10 is exposed during the process of forming the element isolation film 112. Therefore, the integrated circuit device 100 according to the present invention has excellent electrical performance. The structure and material of the insulating wall DW within the integrated circuit device 100 can solve the aforementioned technical problems related to wall formation with only a single insulating wall DW, thus eliminating the need to form a second wall.

[0033] Figures 5A, 5B, and 5C are cross-sectional views showing a schematic configuration of an integrated circuit device 100a according to an embodiment of the present invention. Referring to Figures 5A, 5B, and 5C, the integrated circuit device 100a includes a plurality of cell transistors CTR arranged at a first vertical level, a front wiring structure FS arranged at a second vertical level higher than the first vertical level and electrically connected to the plurality of cell transistors CTR, and a rear wiring structure BS arranged at a third vertical level lower than the first vertical level and electrically connected to the plurality of cell transistors CTR. The rear wiring structure BS includes a power delivery network for applying power supply voltage and ground voltage to the cell transistor CTR. The rear wiring structure BS includes a rear via BSV, a rear wiring layer BSW, and a rear insulation layer BSI.

[0034] The substrate 110 (see Figure 3A) is removed from the integrated circuit device 100a, and the base insulating layer 116 is placed in the position where the substrate 110 was removed. A rear contact 160 is positioned that penetrates the base insulating layer 116 and is electrically connected to the bottom surface of the source / drain region SD. The rear wiring structure BS is positioned on the bottom surface of the base insulating layer 116 and the element isolation film 112, and is arranged so that the rear via BSV or rear wiring layer BSW is electrically connected to the rear contact 160. In one embodiment, a place holder may be further positioned between the bottom surface of the source / drain region SD and the back contact 160, but the technical idea of ​​the present invention is not limited thereto.

[0035] Figures 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10, 11, 12A, 12B, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, and 20C are cross-sectional views illustrating a method for manufacturing an integrated circuit device 100 according to an embodiment of the present invention. Specifically, Figures 6A, 7A, 9A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A are cross-sectional views obtained by cutting along the line A-A' in Figure 1; Figures 6B, 7B, 8B, 8A, 9B, 10, 11, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are cross-sectional views obtained by cutting along the line B-B' in Figure 1; and Figures 6C, 7B, 8B, 13C, 14C, 15C, 16C, 17C, 18C, 19C, and 20C are cross-sectional views obtained by cutting along the line C-C' in Figure 1.

[0036] Referring to Figures 6A to 6C, a semiconductor layer stack NSS is formed on the upper surface of the substrate 110 by alternately and sequentially forming a sacrificial layer 210 and a semiconductor layer NSL. Subsequently, a mask pattern M10 is formed on the semiconductor layer stack NSS, and a portion of the semiconductor layer stack NSS and a portion of the substrate 110 are removed to form an element isolation trench 112T and an insulating wall opening DWH that extend into the interior of the substrate 110. In this embodiment, the element isolation trenches 112T and insulating wall openings DWH are arranged alternately and extend in the first horizontal direction X.

[0037] In embodiments of the present invention, the insulating wall opening DWH has a first width w01 in the second horizontal direction Y in the range of approximately 15 to 25 nm. A portion of the substrate 110 positioned on the first side of the insulating wall opening DWH is referred to as the first active region RX1, and a portion of the substrate 110 positioned on the second side of the insulating wall opening DWH is referred to as the second active region RX2. As a result, the first active region RX1 and the second active region RX2 are extended and positioned in the first horizontal direction X, with the insulating wall opening DWH in between. In one embodiment, the sacrificial layer 210 and the semiconductor layer NSL are formed by an epitaxy process. In this embodiment, the sacrificial layer 210 and the semiconductor layer NSL are made of materials having an etching selectivity ratio with respect to each other. For example, the sacrificial layer 210 and the semiconductor layer NSL are each made of single crystal layers of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor, and the sacrificial layer 210 and the semiconductor layer NSL are made of different materials. In one embodiment, the sacrificial layer 210 is made of SiGe, and the semiconductor layer NSL is made of single-crystal silicon.

[0038] In embodiments, the epitaxy process may be a vapor-phase epitaxy (VPE), a CVD process such as ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, or a combination thereof. In the epitaxy process, a liquid or gaseous precursor is used as the precursor necessary for forming the sacrificial layer 210 and the semiconductor layer NSL.

[0039] Referring to Figures 7A to 7C, an insulating wall liner layer D10L is formed on the inner wall of the element isolation trench 112T and the insulating wall opening DWH. The insulating wall liner layer D10L is conformally positioned on the surface of the relatively thin semiconductor layer stack NSS. In this embodiment, the insulating wall liner layer D10L is formed by a chemical vapor deposition process or an atomic layer lamination process using a low dielectric constant dielectric material. For example, the insulating wall liner layer D10L is formed using at least one of silicon carbon oxide, silicon carbon nitride, or silicon carbon oxynitride.

[0040] Referring to Figures 8A to 8B, an embedded insulating layer D20 is formed on the inner wall of the insulating wall opening DWH. In this embodiment, the embedded insulating layer D20 is formed on the insulating wall liner layer D10L so as to fill the interior of the insulating wall opening DWH. An etch-back process is performed on the upper side of the embedded insulating layer D20 to position the upper surface of the embedded insulating layer D20 at a lower level than the upper surface of the semiconductor layer stack NSS. In the embodiment, the embedded insulating layer D20 is formed by a chemical vapor deposition process or an atomic layer lamination process using at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0041] Referring to Figures 9A and 9B, the etch-back process is performed until the upper surface of the embedded insulating layer D20 is exposed, leaving a portion of the insulating wall liner layer D10L inside the insulating wall opening DWH, and exposing the surface of the semiconductor layer stack NSS again. A portion of the insulating wall liner layer D10 L that remains inside the insulating wall opening DWH is referred to as insulating wall liner D10. The insulating wall liner D10 has an upper surface that is positioned at the same level as the upper surface of the embedded insulating layer D20. After the etch-back process, the upper surface of the insulating wall liner D10 and the upper surface of the embedded insulating layer D20 are positioned higher than the uppermost semiconductor layer NSL and lower than the uppermost sacrificial layer 210. In one embodiment, after the etch-back process, the upper surface of the insulating wall liner D10 and the upper surface of the embedded insulating layer D20 may be positioned at the same level as the uppermost semiconductor layer NSL.

[0042] Referring to Figure 10, a capping layer D30L is formed to cover the semiconductor layer stack NSS. The capping layer D30L is positioned above the insulating wall opening DWH, covering the upper surface of the insulating wall liner D10 and the embedded insulating layer D20. In the embodiment, the capping layer D30L may contain at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0043] Referring to Figure 11, an etch-back process is performed on the capping layer D30L, leaving only a portion of the capping layer D30L above the insulating wall opening DWH, and exposing the surface of the semiconductor layer stack NSS again. Here, a portion of the capping layer D30L remaining on the upper side of the insulating wall opening DWH is referred to as the insulating wall capping layer D30. The insulating wall liner D10, embedded insulating layer D20, and insulating wall capping layer D30, positioned within the insulating wall opening DWH, form an integrated wall structure, which is collectively referred to as the insulating wall DW. In this embodiment, the interior of the insulating wall opening DWH is filled with insulating wall DW, while the element isolation trench 112T is not filled.

[0044] Referring to Figures 12A and 12B, an element isolation film 112 is formed within the element isolation trench 112T. In one embodiment, an insulating layer is formed on the inner wall of the element isolation trench 112T and on the semiconductor layer stack NSS, and the upper side of the insulating layer is etched back to leave the element isolation film 112 on the inner wall of the element isolation trench 112T. In the process of forming an insulating layer on a semiconductor layer stack NSS and / or etching back the insulating layer, the upper surface of the insulating wall liner D10 is covered by the insulating wall capping layer D30 and is not exposed to the outside or the etching atmosphere. This prevents the insulating wall liner D10 from being damaged or lost during the insulating layer formation process and / or the insulating layer etch-back process.

[0045] Referring to Figures 13A to 13C, the mask pattern M10 (see Figure 12A) is removed. In the process of removing the mask pattern M10, or after the process of removing the mask pattern M10, a portion of the upper part of the insulating wall capping layer D30 is removed, thereby placing the upper surface of the insulating wall capping layer D30 at the same level as the upper surface of the semiconductor layer stack NSS (or the upper surface of the topmost sacrificial layer 210). Subsequently, a semiconductor layer stack NSS is placed on the substrate 110, forming a sacrificial gate structure 230 that extends in the second horizontal direction Y. The sacrificial gate structure 230 includes a sacrificial gate insulating layer 232, a sacrificial gate electrode 234, and a sacrificial capping layer 236. In one embodiment, the sacrificial gate electrode 234 is formed using polysilicon. The sacrificial capping layer 236 is formed using silicon nitride. In the embodiment, the sacrificial gate insulating layer 232 includes silicon oxide obtained by performing a thermal oxidation process on the surface of the semiconductor layer stack NSS. In other embodiments, the sacrificial gate insulating layer 232 may include silicon oxide formed on the surface of the semiconductor layer stack NSS by performing a chemical vapor deposition process or an atomic layer stacking process. In one embodiment, after forming a sacrificial gate structure 230 on the semiconductor layer stack NSS, the sacrificial gate structure 230 is used as an etching mask to remove the uppermost sacrificial layer 210 and expose the upper surface of the uppermost semiconductor layer NSL.

[0046] Referring to Figures 14A to 14C, spacers 128 are formed on the upper surface and side walls of the sacrificial gate structure 230. Spacer 128 is formed using silicon nitride.

[0047] Referring to Figures 15A to 15C, a recess process is performed on a portion of the insulating wall DW that is positioned at a vertical level higher than the uppermost semiconductor layer NSL and protrudes above the uppermost semiconductor layer NSL, thereby lowering the height of the upper part of the insulating wall DW. In the embodiment, the insulating wall capping layer D30 on the upper side of the insulating wall DW is removed during the recessing process, and the height of the upper surface of the insulating wall DW is reduced. As a result of the recession process, the portion of the insulating wall DW whose height has been reduced is referred to as the second portion DWU2, and the portion of the insulating wall DW that is covered by the sacrificial gate structure 230 and not subjected to the recession process, and whose height is maintained at the same level, is referred to as the first portion DWU1. The upper surface of the second part DWU2 is positioned at a lower level than the upper surface of the first part DWU1. For example, the upper surface of the first part DWU1, which is covered by the sacrificial gate structure 230, is located at the first vertical level LV1, and the upper surface of the second part DWU2 is located at the second vertical level LV2, which is lower than the first vertical level LV1.

[0048] Subsequently, a portion of the semiconductor layer stack NSS between the sacrificial gate structures 230 is removed to form a recess RS. The recess RS extends into a portion of the first active region RX1 and the second active region RX2. In the process of removing a portion of the semiconductor layer stack NSS, the upper part of the insulating wall DW, for example, the upper part of the second portion DWU2, is also removed. As a result of this process, the second part DWU2 includes a rounded top surface, and the top surface of the second part DWU2 is positioned at a lower level than the top surface of the first part DWU1. For example, the upper surface of the first part DWU1, which is covered by the sacrificial gate structure 230, is located at the first vertical level LV1, and the upper surface of the second part DWU2 is located at the second vertical level LV2, which is lower than the first vertical level LV1. According to the embodiment, in the step of removing a portion of the semiconductor layer stack NSS, the second portion DWU2 of the insulating wall DW has a relatively low height, which allows for precise control of the step of removing a portion of the semiconductor layer stack NSS within the recess RS.

[0049] Referring to Figures 16A to 16C, source / drain regions SD that fill the inside of the recess RS are formed on the upper surface of the substrate 110 exposed on both sides of the sacrificial gate structure 230. In one embodiment, the source / drain region SD is formed by epitaxially growing semiconductor material from the surface of the sacrificial layer 210, the semiconductor layer NSL, and the substrate 110. The source / drain region SD may include at least one of the following: an epitaxially grown Si layer, an epitaxially grown SiC layer, an epitaxially grown SiGe layer, or an epitaxially grown SiP layer. In this embodiment, the source / drain region SD (hereinafter referred to as the first source / drain region SD1) located on the first active region RX1 and the source / drain region SD (hereinafter referred to as the second source / drain region SD2) located on the second active region RX2 are separated in the second horizontal direction Y, with the second portion DWU2 of the insulating wall DW in between. The upper parts of the first source / drain region SD1 and the second source / drain region SD2 are positioned at a vertical level higher than the upper surface of the second portion DWU2 of the insulating wall DW, and are separated from each other by a relatively small separation distance w2.

[0050] In one embodiment, the source / drain region SD includes a lower sidewall (SD_L) that contacts a second portion DWU2 of the insulating wall DW, and an upper sidewall (SD_U) that is positioned at a vertical level higher than the lower sidewall (SD_L) and does not contact the second portion DWU2 of the insulating wall DW. In one embodiment, the upper sidewall (SD_U) of the source / drain region SD protrudes outward relative to the lower sidewall (SD_L) of the source / drain region SD. For example, the upper sidewall (SD_U) of the source / drain region SD is separated from the lower sidewall (SD_L) of the source / drain region SD by a first distance d1 in the second horizontal direction Y (from the lower sidewall (SD_L)). In the embodiment, the first distance d1 has a range of 0.1 to 5 nm. In one embodiment, the insulating wall DW has a first width w1 in the second horizontal direction Y, and the first width w1 is in the range of 15 to 25 nm. Because the upper sidewall (SD_U) of the source / drain region SD protrudes outward by a relatively small first distance d1 relative to the lower sidewall (SD_L) (or grows laterally), the first source / drain region SD1 and the second source / drain region SD2 are not merged with each other during the epitaxial growth process.

[0051] Referring to Figures 17A to 17C, an etching stop film 142 and an intergate insulating layer 144 are formed to cover the source / drain region SD. The etching stop film 142 conformally covers the first source / drain region SD1 and the second source / drain region SD2, and a portion of the etching stop film 142 is positioned on the upper surface of the second portion DWU2 of the insulating wall DW. In the process of forming the intergate insulating layer 144, or after forming the intergate insulating layer 144, an insulating structure IB is formed to cover the end of the semiconductor layer stack NSS in the first horizontal direction X.

[0052] Referring to Figures 18A to 18C, the sacrificial gate structure 230 is removed to form the gate space GSS. The sacrificial layer 210 exposed in the gate space GSS is removed to expose the top and bottom surfaces of the semiconductor layer NSL. The removal process for the sacrificial layer 210 is a wet etching process using the etching selectivity ratio between the sacrificial layer 210 and the semiconductor layer NSL. In this embodiment, the semiconductor layer NSL exposed after the sacrificial layer 210 has been removed is referred to as the semiconductor pattern NS. The semiconductor layer NSL included in the first horizontal X-direction end of the semiconductor layer stack NSS is referred to as the edge semiconductor pattern (NS_E). The edge semiconductor pattern (NS_E) is positioned adjacent to the insulating structure IB.

[0053] Referring to Figures 19A to 19C, the gate insulating layer 124 and gate electrode 122 are formed in the space where the sacrificial gate structure 230 has been removed (gate space GSS shown in Figure 18A). The gate electrode 122, gate insulating layer 124, and capping layer 126 are referred to as the gate structure GS, which surrounds a plurality of semiconductor patterns NS separated in the vertical direction Z and extends in the second horizontal direction Y. By placing the spacer 128 on the uppermost semiconductor pattern NS, a portion of the gate electrode 122 positioned at a higher level than the uppermost semiconductor pattern NS has a narrower width (e.g., width in the first horizontal direction X) than a portion of the gate electrode 122 positioned between two adjacent semiconductor patterns NS. Subsequently, a capping layer 126 is formed on the upper surface of the gate electrode 122. In one embodiment, the capping layer 126 is positioned to be in contact with the sidewall of the intergate insulating layer 144.

[0054] Referring to Figures 20A to 20C, a portion of the gate structure GS is removed to form a gate cut region GCIH, and an insulating material is used to form a gate cut insulating layer GCI inside the gate cut region GCIH. The bottom of the gate-cut insulating layer GCI protrudes toward the element isolation film 112 and comes into contact with the element isolation film 112. A first contact 152 is formed that penetrates the intergate insulating layer 144 and the etching stop film 142 and is electrically connected to the source / drain region SD, and a second contact 156 is formed that penetrates the capping layer 126 and is electrically connected to the gate electrode 122. Subsequently, an upper insulating layer 146 is formed on the gate structure GS, the gate cut insulating layer GCI, and the inter-gate insulating layer 144. A first via 154 is formed that penetrates the upper insulating layer 146 and is electrically connected to the first contact 152, and a second via 158 is formed that penetrates the upper insulating layer 146 and is electrically connected to the second contact 156.

[0055] Referring again to Figures 3A to 3C, the front wiring layer FSW, the front via FSV, and the front insulation layer FSI are formed on the upper insulating layer 146. This completes the front wiring structure FS.

[0056] Generally, to form an integrated circuit device with a forksheet structure, where semiconductor patterns are arranged with an insulating wall in between, the insulating wall is formed first, and then the semiconductor patterns are formed. However, there is a problem in that residual material on the semiconductor pattern is not completely removed, which degrades the characteristics of the device. Conversely, a method has been proposed in which semiconductor patterns are formed first, and then insulating walls are formed by etching between the semiconductor patterns. However, this method has the problem that the etching process increases the width deviation of the semiconductor patterns, degrading the device characteristics.

[0057] However, according to an integrated circuit device according to an embodiment of the present invention, an insulating wall DW is formed including an insulating wall liner D10, an embedded insulating layer D20, and an insulating wall capping layer D30, a recess process is performed on the upper side of the insulating wall DW to reduce the height of the insulating wall DW, and then the source / drain region SD is grown. The insulating wall liner D10 contains a low dielectric constant material, which prevents coupling effects and improves the threshold voltage regulation characteristics of the integrated circuit device 100. Furthermore, since the insulating wall capping layer D30 covers the upper surface of the insulating wall liner D10, it is possible to prevent loss or damage to the insulating wall DW that may occur when the upper surface of the insulating wall liner D10 is exposed during the formation of the element isolation film 112 and / or the etch-back process. Therefore, the integrated circuit device 100 can have excellent electrical performance. According to the integrated circuit apparatus of the present invention, an insulating wall is formed including an insulating wall liner, an embedded insulating layer, and an insulating wall capping layer, a recess process is performed on the upper side of the insulating wall to reduce the height of the insulating wall, and then the source / drain region is grown. The insulating wall liner, by containing a low dielectric constant material, prevents coupling effects and improves the threshold voltage regulation characteristics of the integrated circuit device. Furthermore, since the insulating wall capping layer covers the upper surface of the insulating wall liner, it prevents loss or damage to the insulating wall that may occur when the upper surface of the insulating wall liner is exposed during the element isolation film formation process. Therefore, integrated circuit devices can have excellent electrical performance.

[0058] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0059] 100 Integrated Circuit Device 110 circuit boards 112 Element Separation Membrane 112T element isolation trench 122 Gates 124 Gate Insulation Layer 126 Capping Layers 128 Spacers 142 Etching stop film 144 Gate-to-gate insulating layer 146 Upper insulating layer 152 First Contact 154 First Beer 156 Second Contact 158 Second Beer D10 Insulating Wall Liner D20 Embedded Insulation Layer D30 Insulating Wall Capping Layer DW Insulation Wall DWH Insulation Wall Opening FS front wiring structure FSI Front Insulation Layer FSV Front Via FSW front wiring layer GCI gate cut insulating layer GCIH Gate Cut Region GS Gate Structure IB Insulating Structure LV0 Bottom level LV1 First Vertical Level LV2 Second Vertical Level NS semiconductor pattern NS1 First semiconductor pattern NS2 Second semiconductor pattern NS_E edge semiconductor pattern RS recess RX1 1st active region RX2 2nd active region SD Source / Drain Area SD1 First Source / Drain Region SD2 Second Source / Drain Region

Claims

1. A first semiconductor pattern extending in a first horizontal direction, A first source / drain region connected to the first horizontal end of the at least one first semiconductor pattern, At least one second semiconductor pattern is spaced apart from the at least one first semiconductor pattern in a second horizontal direction intersecting the first horizontal direction, and is arranged to extend in the first horizontal direction, A second source / drain region connected to the first horizontal end of the at least one second semiconductor pattern, The device has an insulating wall that extends horizontally and is positioned within the insulating wall opening between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and between the first source / drain region and the second source / drain region. The aforementioned insulating wall is An insulating wall liner is placed on the inner wall of the insulating wall opening, An embedded insulating layer placed on the insulating wall liner, An integrated circuit apparatus characterized by including an insulating wall capping layer disposed within the insulating wall opening and on the upper surface of the insulating wall liner and the upper surface of the embedded insulating layer.

2. The aforementioned insulating wall is A first portion disposed between the at least one first semiconductor pattern and the at least one second semiconductor pattern, A second portion disposed between the first source / drain region and the second source / drain region, The integrated circuit apparatus according to claim 1, characterized in that the upper surface of the second portion is positioned at a lower level vertically than the upper surface of the first portion.

3. The integrated circuit apparatus according to claim 2, characterized in that the upper surface of the second portion of the insulating wall is positioned at a lower level vertically than the upper surface of the first source / drain region and the upper surface of the second source / drain region.

4. The integrated circuit apparatus according to claim 2, characterized in that the upper part of the first source / drain region and the upper part of the second source / drain region are arranged to be separated in the second horizontal direction.

5. The insulating wall capping layer is disposed within the first portion of the insulating wall. The integrated circuit apparatus according to claim 2, characterized in that the insulating wall capping layer is disposed outside the second portion of the insulating wall.

6. The second horizontal end of the at least one first semiconductor pattern is in contact with the first side wall of the insulating wall. The integrated circuit apparatus according to claim 2, characterized in that the second horizontal end of at least one second semiconductor pattern is in contact with the second side wall of the insulating wall opposite to the first side wall.

7. The integrated circuit apparatus according to claim 6, characterized in that the second horizontal end of the at least one first semiconductor pattern and the second horizontal end of the at least one second semiconductor pattern are in contact with the insulating wall liner.

8. A gate electrode that surrounds the at least one first semiconductor pattern and the at least one second semiconductor pattern and extends horizontally in the second direction, The present invention further comprises a gate insulating layer disposed between the at least one first semiconductor pattern and the gate electrode, and between the at least one second semiconductor pattern and the gate electrode. The integrated circuit apparatus according to claim 2, characterized in that the gate insulating layer extends onto the upper surface of the first portion of the insulating wall.

9. The integrated circuit apparatus according to claim 8, characterized in that the gate insulating layer is disposed within the first portion of the insulating wall and on the upper surface of the insulating wall capping layer.

10. The integrated circuit device according to claim 2, characterized in that the insulating wall has a width of 15 nm to 25 nm in the second horizontal direction.

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